Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a plurality of word line trenches and a plurality of word line structures. The substrate comprises an isolation structure and an active region. The active region comprises a first active structure and a second active structure. The isolation structure comprises a first isolation part and a second isolation part. The plurality of word line trenches are located in the substrate and comprise a first word line trench and a second word line trench. The first word line trench passes through the active region and the first isolation part in a second direction, and the second word line trench passes through the active region and the second isolation part in the second direction. The depth of the second word line trench is smaller than that of the first word line trench. The plurality of word line structures comprise a first word line and a second word line. The first word line is located in the first word line trench, and the second word line is located in the second word line trench and is composed of insulating material. The surface of the second word line can be made flat, so that the subsequent process of the word line structure is facilitated, and the product yield can be improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In the fabrication of memory devices, when forming an embedded word line structure, word line trenches are typically formed first. Then, a gate dielectric layer is formed on the inner wall of the word line trench, and a gate conductive layer is filled in the bottom region of the word line trench. Finally, an insulating capping layer covering the gate conductive layer is formed in the remaining region of the word line trench.

[0003] In actual manufacturing processes, uneven surface often occurs after the character line structure is formed, which is detrimental to subsequent processes. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem of uneven surface after word line structure formation in existing technologies.

[0005] A semiconductor structure, comprising:

[0006] A substrate includes an isolation structure and an active region defined by the isolation structure; the active region includes a first active structure and a second active structure, the first active structures extending along a third direction and spaced apart, the second active structures being located outside the first active structures; the isolation structure includes a first isolation portion and a second isolation portion, the first isolation portion being located between adjacent first active structures along a third direction, the second isolation portion being located between adjacent first active region structures and second active structures along a third direction, and in a first direction, the width of the second isolation portion is greater than the width of the first isolation portion;

[0007] Multiple word line trenches are located within the substrate and are spaced apart along a first direction, including a first word line trench and a second word line trench. The first word line trench passes through the active region and the first isolation portion in a second direction, and the second word line trench passes through the active region and the second isolation portion in a second direction. The second direction intersects the first direction, and the depth of the second word line trench is less than the depth of the first word line trench.

[0008] The structure includes a first word line and a second word line, wherein the first word line is located in a first word line groove and the second word line is located in a second word line groove, and the second word line is made of insulating material.

[0009] In one embodiment, the semiconductor structure includes:

[0010] The first gate dielectric layer includes a first portion located on the inner wall of the first word line trench and a second portion located on the inner wall of the second word line trench;

[0011] The first gate conductive layer is located on the surface of the first gate dielectric layer of the first word line trench;

[0012] An insulating capping layer includes a first portion located in a first word line trench and a second portion located in a second word line trench, wherein the first portion of the insulating capping layer is in direct contact with the top surface of the first gate conductive layer, and the second portion of the insulating capping layer is in direct contact with the second portion of the first gate dielectric layer.

[0013] The first word line is formed by the first gate dielectric layer, the first gate conductive layer and the insulating capping layer in the first word line trench, and the second word line is formed by the first gate dielectric layer and the insulating capping layer in the second word line trench.

[0014] In one embodiment, the width of the insulating cover layer of the second word line in the first direction is smaller than the width of the insulating cover layer of the first word line in the first direction.

[0015] In one embodiment, the first word line further includes a conductive protective layer located between the first gate conductive layer and the insulating capping layer.

[0016] In one embodiment, both the first isolation portion and the second isolation portion include a first oxide layer and a nitride layer, wherein the first oxide layer covers the sidewalls and bottom of the nitride layer.

[0017] Below the first letter line opposite to the first isolation portion are the nitride layer and the first oxide layer.

[0018] A nitride layer is provided below the second word line opposite to the second isolation portion, and the first oxide layer is provided on the sidewalls of the second word line and the nitride layer below it.

[0019] In one embodiment, the isolation structure includes a third isolation portion located on the side of the second isolation portion away from the first isolation portion.

[0020] The third isolation layer includes a first oxide layer, a nitride layer, and a second oxide layer. The first oxide layer covers the sidewalls and bottom of the nitride layer, and the nitride layer covers the sidewalls and bottom of the second oxide layer.

[0021] In one embodiment, the width of the first word line in the first direction is greater than the width of the adjacent active region in the first direction.

[0022] A method for fabricating a semiconductor structure, the semiconductor structure having a storage region and a peripheral region surrounding the storage region, the method comprising:

[0023] A substrate is provided; the substrate includes an initial isolation structure and a first active structure defined by the initial isolation structure, the first active structures extending along a third direction and spaced apart; the initial isolation structure includes a first initial isolation portion and a third initial isolation portion, the first initial isolation portion being located between adjacent first active structures, the third initial isolation portion being located outside all first active structures, and in a first direction, the width of the third initial isolation portion being greater than the width of the first initial isolation portion.

[0024] The substrate is etched to form a plurality of word line trenches spaced apart along a first direction; after etching, the remaining initial isolation structure forms an isolation structure, wherein the remaining first initial isolation portion forms a first isolation portion, and the remaining third initial isolation portion forms a third isolation portion; the plurality of word line trenches include a first word line trench and a second word line trench, the first word line trench passes through the first active structure and the first isolation portion in a second direction, the second word line trench passes through the third isolation portion in a second direction, the second direction intersects the first direction, and the depth of the second word line trench is less than the depth of the first word line trench;

[0025] A first character line is formed in the first character line groove, and a second character line is formed in the second character line groove, the second character line being made of insulating material.

[0026] A semiconductor structure, comprising:

[0027] The substrate includes an isolation structure and a first active structure defined by the isolation structure, the first active structures extending along a third direction and spaced apart; the isolation structure includes a first isolation portion and a third isolation portion, the first isolation portion being located between adjacent first active structures along the third direction, the third isolation portion being located outside all first active structures, and in a first direction, the width of the third isolation portion being greater than the width of the first isolation portion.

[0028] Multiple word line trenches are located within the substrate and are spaced apart along a first direction, including a first word line trench and a second word line trench. The first word line trench passes through the first isolation portion and the first active structure in a second direction, and the second word line trench passes through the third isolation portion in a second direction. The second direction intersects the first direction, and the depth of the second word line trench is less than the depth of the first word line trench.

[0029] The structure includes multiple word lines, including a first word line and a second word line; the first word line is located in a first word line groove, the second word line is located in a second word line groove, and the second word line is made of insulating material.

[0030] In one embodiment, the semiconductor structure includes:

[0031] The first gate dielectric layer includes a first portion located on the inner wall of the first word line trench and a second portion located on the inner wall of the second word line trench;

[0032] The first gate conductive layer is located on the surface of the first gate dielectric layer of the first word line trench;

[0033] An insulating capping layer includes a first portion located in a first word line trench and a second portion located in a second word line trench, wherein the first portion of the insulating capping layer is in direct contact with the top surface of the first gate conductive layer, and the second portion of the insulating capping layer is in direct contact with the second portion of the first gate dielectric layer.

[0034] The first word line is formed by the first gate dielectric layer, the first gate conductive layer and the insulating capping layer in the first word line trench, and the second word line is formed by the first gate dielectric layer and the insulating capping layer in the second word line trench.

[0035] In one embodiment, the width of the insulating cover layer of the second word line in the first direction is smaller than the width of the insulating cover layer of the first word line in the first direction.

[0036] A semiconductor structure, comprising:

[0037] The substrate includes an isolation structure and an active region defined by the isolation structure;

[0038] Multiple word line trenches are located within the substrate, spaced apart along a first direction, passing through the active region and the isolation structure, and include a first word line trench and a second word line trench.

[0039] The first gate dielectric layer includes a first portion located on the inner wall of the first word line trench and a second portion located on the inner wall of the second word line trench;

[0040] The first gate conductive layer is located on the surface of the first gate dielectric layer of the first word line trench;

[0041] An insulating capping layer includes a first portion located in a first word line trench and a second portion located in a second word line trench, wherein the first portion of the insulating capping layer is in direct contact with the top surface of the first gate conductive layer, and the second portion of the insulating capping layer is in direct contact with the second portion of the first gate dielectric layer.

[0042] In one embodiment, the semiconductor structure further includes:

[0043] An insulating isolation post extends into the groove of the second letter and is in direct contact with the insulating cover layer.

[0044] A semiconductor structure, comprising:

[0045] The substrate includes an isolation structure and an active region defined by the isolation structure;

[0046] Multiple word line trenches are located within the substrate, spaced apart along a first direction, passing through the active region and the isolation structure, and include a first word line trench and a second word line trench.

[0047] The first gate dielectric layer includes a first portion that is in direct contact with the inner wall of the first word line trench and a second portion that is in direct contact with the inner wall of the second word line trench.

[0048] The first gate conductive layer is located on the surface of the first gate dielectric layer of the first word line trench;

[0049] An insulating capping layer is located only within the first word line groove and covers the first gate conductive layer.

[0050] The aforementioned semiconductor structure and its fabrication method include multiple word line trenches, comprising a first word line trench and a second word line trench. The depth of the second word line trench is less than the depth of the first word line trench. A second word line (dummy word line) is disposed within the second word line trench, and the second word line is composed of an insulating material. During the fabrication of the first and second word lines, because the second word line trench is shallower, even if gaps occur due to unevenness in the trench during the deposition of the insulating material within the second word line trench, these gaps easily move upwards above the second word line trench. Therefore, after removing the insulating material outside the second word line trench using a chemical mechanical polishing (CMP) process to form the second word line, a smooth second word line surface can be obtained. In subsequent processes, processing can be performed based on the smooth surface of the second word line within the area where it is located, thereby improving product yield. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in one embodiment;

[0053] Figure 2 Corresponding to the semiconductor structure provided in one embodiment Figure 1 A schematic diagram of the cross-sectional structure along the A-A' direction;

[0054] Figures 3 to 7 This is a diagram showing the corresponding steps in the fabrication process of the semiconductor structure provided in one embodiment. Figure 1 A schematic diagram of the cross-sectional structure along the A-A' direction;

[0055] Figure 8 Corresponding to the semiconductor structure provided in one embodiment Figure 1 A schematic diagram of the cross-sectional structure of the section in the B-B' direction;

[0056] Figure 9 This is a top view of a semiconductor structure provided in another embodiment;

[0057] Figure 10 Corresponding to the semiconductor structure provided in one embodiment Figure 9 A schematic diagram of the cross-sectional structure along the C-C' direction;

[0058] Figure 11 Corresponding to the semiconductor structure provided in yet another embodiment Figure 1 Schematic diagram of the cross-sectional structure of the section in the B-B' direction;

[0059] Figure 12 For the semiconductor structure provided in another embodiment Figure 1 A schematic diagram of the cross-sectional structure of the section in the B-B' direction;

[0060] Figure 13 For yet another embodiment of the semiconductor structure provided Figure 1 Schematic diagram of the cross-sectional structure of the section in the B-B' direction;

[0061] Figures 14 to 16 This is a schematic diagram of a cross-sectional structure during the fabrication process of a semiconductor structure provided in another embodiment.

[0062] The "correspondence" mentioned above can be understood. Figure 1 "Schematic diagram of the cross-sectional structure of the section in the A-A' direction", "corresponding to Figure 1 "Schematic diagram of the cross-sectional structure of the section in the A-A' direction", "corresponding to Figure 1 The "diagram of the cross-sectional structure in the A-A' direction" can be from other different embodiments. Figure 1 The example shown corresponds to a schematic diagram, while other different embodiments are... Figure 1 The illustrated embodiments may differ. Similarly, Figure 10 Corresponding to the semiconductor structure provided in one embodiment Figure 9 A schematic diagram of the cross-sectional structure along the C-C' direction. Figure 10 The illustrated embodiments and Figure 9 The embodiments shown may differ.

[0063] Explanation of reference numerals in the attached figures:

[0064] 100 - Substrate, 110 - Active region, 111 - First active structure, 112 - Second active structure, 1121 - First structure, L11 - First outer contour, L111 - First arcuate protrusion, L12 - First inner contour, L121 - First arcuate groove, 1122 - Second structure, L21 - Second outer contour, L211 - Second arcuate protrusion, L22 - Second inner contour, L221 - Second arcuate groove, 113 - Logic active structure, 120 - Isolation structure, 121 - First oxide layer, 122 - Nitride layer, 123 - Second oxide layer, 1201 - First isolation portion, 1202 - Second isolation portion, 1203 - Third isolation portion, 120a - Initial isolation structure, 121a - First initial oxide layer, 122a - Initial nitride layer, 123 a-Second initial oxide layer, 1201a-First initial isolation portion, 1202a-Second initial isolation portion, 1203a-Third initial isolation portion, 410-First gate dielectric layer, 410a-First gate dielectric material layer, 420-First gate conductive layer, 420a-First gate conductive material layer, 430-Insulating cap layer, 430a-Insulating cap material layer, 440-Conductive protective layer, 401-First word line, 402-Second word line, 500-Bit line, 600-Bit line contact plug structure, 710-Insulating isolation pillar, 720-Insulating fill pillar, 800-Node contact structure, 810-Contact layer, 820-Metal layer, 900-Gate structure, 910-Second gate dielectric layer, 920-Second gate conductive layer, 11-First word line trench, 12-Second word line trench. Detailed Implementation

[0065] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0067] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0068] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0069] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0070] In one embodiment, see Figure 1 as well as Figure 2 A semiconductor structure is provided, including a substrate 100, a plurality of word line trenches, and a plurality of word line structures.

[0071] The substrate 100 includes an isolation structure 120 and an active region 110 defined by the isolation structure 120. The active region 110 includes a first active structure 111 and a second active structure 112.

[0072] The first active structure 111 extends along a third direction and is arranged at intervals. The second active structure 112 is located outside the first active structure 111.

[0073] Each first active structure 111 can extend along a third direction. Simultaneously, multiple first active structures 111 can be arranged in a row at intervals along the third direction. The lengths of different rows of first active structures 111 can be different, and the number of first active structures 111 contained in different rows of first active structures 111 can be different. For example, multiple rows of first active structures 111 can be arranged within a square region. A second active structure 112 can surround the outside of this square region.

[0074] The second active structure 112 may include two first structures 1121 and two second structures 1122 arranged opposite each other in the second direction. The two first structures 1121 and the two second structures 1122 are connected to form a ring-shaped closed structure (second active structure 112). The plurality of first active structures 111 are located within the area enclosed by the ring-shaped second active structure 112.

[0075] The first structure 1121 includes a first outer contour L11 and a first inner contour L12. In a second direction, the first outer contour L11 is located on the side of the first inner contour L12 away from the first active structure 111. The first outer contour L11 includes a plurality of first arcuate protrusions L111 arranged sequentially along a first direction. The first arcuate protrusions L111 protrude along the second direction toward the side away from the first active structure 111. The first inner contour L12 includes a plurality of first arcuate grooves L121 arranged sequentially along the first direction. The first arcuate grooves are recessed along the second direction toward the side away from the first active structure 111. The first arcuate grooves L121 and the first arcuate protrusions L111 are arranged alternately along the first direction.

[0076] The second structure 1122 includes a second outer contour L21 and a second inner contour L22. In a first direction, the second outer contour L21 is located on the side of the second inner contour L22 away from the first active structure 111. The second outer contour L21 includes a plurality of second arcuate protrusions L211 arranged sequentially along a second direction. The second arcuate protrusions L211 protrude along the first direction toward the side away from the first active structure 111. The second inner contour L22 includes a plurality of second arcuate grooves L221 arranged sequentially along the second direction. The second arcuate grooves L221 are recessed along the first direction toward the side away from the first active structure 111. The second arcuate grooves L221 and the second arcuate protrusions L211 are arranged alternately along the second direction.

[0077] The maximum width of the first arc-shaped protrusion L111 in the first direction is D1. The maximum width of the second arc-shaped protrusion L211 in the second direction is D2. D1 is greater than D2.

[0078] The isolation structure 120 includes a first isolation portion 1201 and a second isolation portion 1202. The first isolation portion 1201 is located between adjacent first active structures 111 along a third direction, and the second isolation portion 1202 is located between adjacent first active region 110 structures and second active structures 112 along a third direction. In a first direction, the width of the second isolation portion 1202 is greater than the width of the first isolation portion 1201.

[0079] Multiple word line trenches are located within the substrate 100. Furthermore, the multiple word line trenches are spaced apart along a first direction.

[0080] The plurality of word line grooves includes a first word line groove 11 and a second word line groove 12. The first word line groove 11 passes through the active region 110 and the first isolation portion 1201 in a second direction. The second word line groove 12 passes through the active region 110 and the second isolation portion 1202 in a second direction. The second word line groove 12 is located outside the structure of the first word line groove 11. The second direction intersects with the first direction. Exemplarily, the second direction is perpendicular to the first direction.

[0081] The depth of the second character line groove 12 is less than the depth of the first character line groove 11.

[0082] The multiple character line structure includes a first character line 401 and a second character line 402. The first character line 401 is located within a first character line groove 11. The second character line 402 is located within a second character line groove 12. The second character line 402 is located outside the first character line 401.

[0083] The first word line 401 is a normal word line that provides word line signals to memory cells. The second word line 402 does not provide word line signals to memory cells; it is a dummy word line.

[0084] The second digit 402 is made of insulating material.

[0085] In this embodiment, the plurality of word line grooves include a first word line groove 11 and a second word line groove 12. The depth of the second word line groove 12 is less than the depth of the first word line groove 11. A second word line 402 (dummy word line) is provided in the second word line groove 12, and the second word line 402 is made of insulating material. At this time, during the preparation of the first word line 401 and the second word line 402, since the second word line groove 12 is shallow, even if gaps occur due to unevenness of the groove during the deposition of insulating material in the second word line groove 12, the gaps are easy to move upward above the second word line groove 12. Therefore, after removing the insulating material outside the second word line groove 12 by chemical mechanical polishing (CMP) to form the second word line 402, a smooth surface of the second word line 402 can be obtained. At this time, in subsequent processes, processing can be carried out based on the smooth surface of the second word line 402 in the area where the second word line 402 is located, thereby improving the product yield. For example, in subsequent processes, other components can be formed above the second word line 402. Since the surface of the second word line 402 is flat, this effectively prevents these components from tilting or even collapsing. In this embodiment, the second word line 402 is located outside the first word line 401. In the memory structure, the word line structure is located in the memory area, and there is also an outer perimeter area outside the word line structure. Therefore, the second word line 402 is located between the memory area and the outer perimeter area. The memory area has a dense distribution of devices, while the outer perimeter area is relatively sparse, creating a structural difference between the two. The flat top of the second word line 402 between these two areas prevents further exacerbation of this difference.

[0086] In one embodiment, see Figure 2 The semiconductor structure includes a first gate dielectric layer 410, a first gate conductive layer 420, and an insulating capping layer 430.

[0087] The first gate dielectric layer 410 includes a first portion located on the inner wall of the first word line trench 11 and a second portion located on the inner wall of the second word line trench 12. A first gate conductive layer 420 is located on the surface of the first gate dielectric layer 410 in the first word line trench 11. An insulating capping layer 430 includes a first portion located in the first word line trench 11 and a second portion located in the second word line trench 12. The first portion of the insulating capping layer 430 is in direct contact with the top surface of the first gate conductive layer 420. The second portion of the insulating capping layer 430 is in direct contact with the second portion of the first gate dielectric layer 410.

[0088] That is, within the first word line trench 11, a first portion of the first gate dielectric layer 410 is located on the inner wall of the first word line trench 11, the first gate conductive layer 420 is located on the surface of the first gate dielectric layer 410, and a first portion of the insulating capping layer 430 is located on the top surface of the first gate conductive layer 420. Within the second word line trench 12, a second portion of the first gate dielectric layer 410 is located on the inner wall of the second word line trench 12, and a second portion of the insulating capping layer 430 is located on the surface of the second portion of the first gate dielectric layer 410. Based on this, the first gate dielectric layer 410, the first gate conductive layer 420, and the insulating capping layer 430 within the first word line trench 11 form the first word line 401, and the first gate dielectric layer 410 and the insulating capping layer 430 within the second word line trench 12 form the second word line 402.

[0089] In this embodiment, please refer to Figures 3 to 7 During the fabrication of the semiconductor structure, when the insulating capping layer 430 is formed (see [link to semiconductor fabrication process]), Figure 7 First, an insulating cap material layer 430a can be deposited. Then, the insulating cap material layer 430a is chemically and mechanically polished to remove the insulating cap material layer 430a located outside the word line grooves. The insulating cap material layer 430a remaining within the word line grooves forms the insulating cap layer 430 (see [link to documentation]). Figure 2 The portion of the insulating cap layer 430 located within the first letter groove 11 is its first portion. The portion of the insulating cap layer 430 located within the second letter groove 12 is its second portion. The second letter groove 12 is shallower, so that even if gaps occur due to unevenness in the groove during the deposition of the insulating cap material layer 430a, these gaps can easily move upwards above the second letter groove 12 (see [reference]). Figure 7 This allows it to be removed during subsequent chemical mechanical polishing. Therefore, it is possible to effectively ensure that the top of the portion of the insulating capping layer 430 located within the second letter groove 12 (the second portion) has no gaps (see [link]). Figure 2 This allows the top surface of the second character line 402 to be flat.

[0090] In one embodiment, see Figure 2 The bottom of the second portion of the insulating cover layer 430 is higher than the bottom of the first portion of the insulating cover layer 430. At this time, even if the top of the first portion of the insulating cover layer 430 located in the first letter groove 11 has a gap, it can be ensured that the top of the second portion of the insulating cover layer 430 located in the second letter groove 12 is flat and seamless.

[0091] In one embodiment, see Figure 1 The width of the insulating cover layer 430 of the second character line 402 in the first direction is smaller than the width of the insulating cover layer 430 of the first character line 401 in the first direction.

[0092] Please refer to the process of semiconductor structure fabrication. Figure 5 Before forming the insulating capping layer 430, a first gate dielectric material layer 410a can be formed first on the structural surface after the word line trenches are formed. Then, a first gate conductive material layer 420a is deposited on the surface of the first gate dielectric material layer 410a. See then... Figure 6 The first gate conductive material layer 420a is etched to remove the first gate conductive material layer 420a in the second word line trench 12, while retaining a portion of the first gate conductive material layer 420a located in the first word line trench 11, thereby forming the first gate conductive layer 420.

[0093] At this time, the width of the remaining space of the second character line groove 12 in the third direction can be smaller than the width of the remaining space of the first character line groove 11 in the third direction. Simultaneously, the width of the character line groove in the first direction is proportional to its width in the third direction.

[0094] Therefore, the width of the remaining space in the second alphanumeric groove 12 in the first direction can be smaller than the width of the remaining space in the first alphanumeric groove 11 in the first direction. That is, the remaining space in the second alphanumeric groove 12 is narrower. Therefore, when the insulating cap material layer 430a is subsequently deposited to form the insulating cap layer 430, the insulating material that gradually thickens along the two sidewalls of the second alphanumeric groove 12 can easily connect with each other, thereby making it easier to make the top of the insulating cap layer 430 in the second alphanumeric groove 12 seamless. For example, after the insulating cap material layer 430a is subsequently removed by chemical mechanical polishing, the first gate dielectric material layer 410a outside the alphanumeric groove can be removed, thereby forming the first gate dielectric layer 410.

[0095] In one embodiment, see Figure 8 The first word line 401 also includes a conductive protective layer 440. The conductive protective layer 440 is located between the first gate conductive layer 420 and the insulating capping layer 430.

[0096] For example, the material of the conductive protective layer 440 may include, but is not limited to, polycrystalline silicon.

[0097] In other embodiments, the first word line 401 may also exclude the conductive protective layer 440, which can be set according to actual needs.

[0098] In one embodiment, see Figure 2 Both the first isolation section 1201 and the second isolation section 1202 include a first oxide layer 121 and a nitride layer 122. The first oxide layer 121 covers the sidewalls and bottom of the nitride layer 122.

[0099] Below the first letter line 401, which is opposite to the first isolation portion 1201, there is a nitride layer 122 and a first oxide layer 121. Below the second letter line 402, which is opposite to the second isolation portion 1202, there is a nitride layer 122, and the second letter line 402 and the sidewalls of the nitride layer 122 below it are both covered with a first oxide layer 121.

[0100] At this point, during the fabrication of the semiconductor structure, substrate 100 can be provided first. (See also...) Figure 3 The substrate 100 includes an initial isolation structure 120a and an active region 110. The active region 110 is defined by the initial isolation structure 120a. The initial isolation structure 120a includes a first initial isolation portion 1201a and a second initial isolation portion 1202a. The first initial isolation portion 1201a is located between adjacent first active structures 111 along a third direction. The second initial isolation portion 1202a is located between adjacent first active region 110 structures and second active structures 112 along a third direction. Both the first initial isolation portion 1201a and the second initial isolation portion 1202a include a first initial oxide layer 121a and an initial nitride layer 122a.

[0101] Then, please see Figure 4 The substrate 100 is etched to form a plurality of word line trenches spaced apart along a first direction. The plurality of word line trenches include a first word line trench 11 and a second word line trench 12. After etching, the remaining initial isolation structure 120a forms an isolation structure 120. Specifically, the remaining first initial isolation portion 1201a forms a first isolation portion 1201, and the remaining second initial isolation portion 1202a forms a second isolation portion 1202. More specifically, the remaining first initial oxide layer 121a forms a first oxide layer 121, and the remaining initial nitride layer 122a forms a nitride layer 122.

[0102] During the formation of the word line trench, both the first initial oxide layer 121a and the initial nitride layer 122a of the first initial isolation portion 1201a can be etched, thereby exposing the active region 110 on the sidewall of the formed first word line trench 11. Simultaneously, the initial nitride layer 122a of the second initial isolation portion 1202a can be etched, while the first initial oxide layer 121a of the second initial isolation portion 1202a is not etched or is etched only minimally, thereby ensuring that the sidewall of the formed second word line trench 12 has the first oxide layer 121.

[0103] Based on this, when the width of the second isolation portion 1202 is greater than the width of the first isolation portion 1201, the width of the second alphanumeric groove 12 can be made smaller than the width of the first alphanumeric groove 11. This facilitates the realization that the width of the insulating cover layer 430 in the first alphanumeric groove 11 is smaller than the width of the insulating cover layer 430 in the second alphanumeric groove 12, which means that the width of the insulating cover layer 430 of the second alphanumeric line 402 in the first direction is smaller than the width of the insulating cover layer 430 of the first alphanumeric line 401 in the first direction.

[0104] In one embodiment, see Figure 4 The isolation structure 120 also includes a third isolation section 1203. The third isolation section 1203 is located on the side of the second isolation section 1202 that is away from the first isolation section 1201.

[0105] For example, the first isolation section 1201 and the second isolation section 1202 may be located in the storage area, and the third isolation section 1203 may be located in the peripheral area.

[0106] The size of the third isolation section 1203 can be larger than the size of the first isolation section 1201 and the size of the second isolation section 1202.

[0107] The third isolation section 1203 includes a first oxide layer 121, a nitride layer 122 and a second oxide layer 123. The first oxide layer 121 covers the sidewalls and bottom of the nitride layer 122, and the nitride layer 122 covers the sidewalls and bottom of the second oxide layer 123.

[0108] Please refer to the process of semiconductor structure fabrication. Figure 3 When forming the initial isolation structure 120a, isolation trenches can be formed first. The isolation trenches may include a first trench portion, a second trench portion, and a third trench portion. The first and second trench portions may be located in the storage area, and the third trench portion may be located in the peripheral area.

[0109] Then, a first oxide material, a nitride material, and a second oxide material can be sequentially deposited on the structural surface after the isolation trenches are formed. During this process, the larger first and second trench portions can be filled after the nitride material is deposited. The larger third trench portion is filled only after the second oxide material is deposited. Afterward, the second oxide material, nitride material, and first oxide material can be chemically mechanically ground to remove the second oxide material, nitride material, and first oxide material located outside the isolation trenches. The remaining second oxide material, nitride material, and first oxide material form a second initial oxide layer 123a, an initial nitride layer 122a, and a first initial oxide layer 121a, respectively, thereby forming an initial isolation structure 120a. At this time, the initial nitride layer 122a and the first initial oxide layer 121a retained in the first trench portion form the first initial isolation portion 1201a, the initial nitride layer 122a and the first initial oxide layer 121a retained in the second trench portion form the second initial isolation portion 1202a, and the second initial oxide layer 123a, the initial nitride layer and the first initial oxide layer 121a retained in the third trench portion form the third initial isolation portion 1203a. Then, after etching the substrate 100 to form a plurality of word line trenches, the remaining first initial isolation portion 1201a forms the first isolation portion 1201, and the remaining second initial isolation portion 1202a forms the second isolation portion 1202.

[0110] In one embodiment, the width of the first word line 401 in the first direction is greater than the width of the adjacent active region 110 in the first direction, thereby effectively improving the word line structure density.

[0111] In one embodiment, see Figure 9 as well as Figure 10 The semiconductor structure also includes bit lines 500 and bit line contact plug structures 600. Bit lines 500 may extend along a first direction and may contact the active region 110 on one side of the word line structure, thereby connecting to either the source or drain of the transistor in the memory cell. Multiple bit lines 500 may be arranged along a second direction. Bit line contact plug structures 600 may be located on the side of the bit lines 500 away from the substrate 100, thereby leading out the signals from the bit lines 500.

[0112] In one embodiment, see Figure 11 A semiconductor structure is provided, comprising a substrate 100, a plurality of word line trenches, and a plurality of word line structures. It is understood that, although this embodiment is different from... Figure 1 The semiconductor structures of the illustrated embodiments are not exactly the same, but can be referenced. Figure 1The first active structure 111, the first isolation section 1201, and the third isolation section 1203 in this embodiment are understood from the top view shown and the following text.

[0113] Substrate 100 includes an isolation structure 120 and first active structures 111 defined by the isolation structure 120. The first active structures 111 extend along a third direction and are spaced apart. The isolation structure 120 includes a first isolation portion 1201 and a third isolation portion 1203. The first isolation portion 1201 is located between adjacent first active structures 111 along a third direction. The third isolation portion 1203 is located outside all first active structures 111. In a first direction, the width of the third isolation portion 1203 is greater than the width of the first isolation portion 1201.

[0114] Multiple word line trenches are located within the substrate 100 and are spaced apart along a first direction. The multiple word line trenches include a first word line trench 11 and a second word line trench 12. The first word line trench 11 passes through a first isolation portion 1201 and a first active structure 111 in a second direction. The second word line trench 12 passes through a third isolation portion 1203 in the second direction. The second direction intersects the first direction. The depth of the second word line trench 12 is less than the depth of the first word line trench 11.

[0115] The multiple character line structure includes a first character line 401 and a second character line 402. The first character line 401 is located within a first character line groove 11. The second character line 402 is located within a second character line groove 12. The second character line 402 is made of insulating material.

[0116] In this embodiment, during the fabrication of the first letter line 401 and the second letter line 402, because the second letter line groove 12 is relatively shallow, a smooth surface can be obtained within the second letter line groove 12. In subsequent processes, processing can be performed based on the smooth surface of the second letter line 402 within the area where it is located, thereby improving product yield. This also prevents the third isolation portion 1203 in the outer area from being uneven due to its large size, which could affect subsequent processes performed on the third isolation portion 1203.

[0117] In one embodiment, see Figure 11 The semiconductor structure includes a first gate dielectric layer 410, a first gate conductive layer 420, and an insulating capping layer 430.

[0118] The first gate dielectric layer 410 includes a first portion located on the inner wall of the first word line trench 11 and a second portion located on the inner wall of the second word line trench 12. A first gate conductive layer 420 is located on the surface of the first gate dielectric layer 410 in the first word line trench 11. An insulating capping layer 430 includes a first portion located in the first word line trench 11 and a second portion located in the second word line trench 12. The first portion of the insulating capping layer 430 is in direct contact with the top surface of the first gate conductive layer 420, and the second portion of the insulating capping layer 430 is in direct contact with the second portion of the first gate dielectric layer 410.

[0119] In one embodiment, see Figure 11 The width of the insulating cover layer 430 of the second character line 402 in the first direction is smaller than the width of the insulating cover layer 430 of the first character line 401 in the first direction.

[0120] In one embodiment, see Figure 11 The semiconductor structure may also include a gate structure 900. The gate structure 900 may include a second gate dielectric layer 910 and a second gate conductive layer 920.

[0121] Specifically, in the outer area, on the side of the third isolation section 1203 away from the storage area, a logical active structure 113 may be provided (see [link to relevant documentation]). Figure 9 The gate structure 900 can be formed on the logic active structure 113 to form a logic device located in the peripheral region.

[0122] In one embodiment, see Figure 2 as well as Figure 1 A semiconductor structure is provided, which includes a substrate 100, a first gate dielectric layer 410, a first gate conductive layer 420, an insulating capping layer 430, and a plurality of word line trenches.

[0123] The substrate 100 includes an isolation structure 120 and an active region 110 defined by the isolation structure 120. A plurality of word line trenches are located within the substrate 100 and spaced apart along a first direction. Each word line trench passes through the active region 110 and the isolation structure 120. The plurality of word line trenches include a first word line trench 11 and a second word line trench 12.

[0124] The first gate dielectric layer 410 includes a first portion located on the inner wall of the first word line trench 11 and a second portion located on the inner wall of the second word line trench 12. A first gate conductive layer 420 is located on the surface of the first gate dielectric layer 410 in the first word line trench 11. An insulating capping layer 430 includes a first portion located in the first word line trench 11 and a second portion located in the second word line trench 12. The first portion of the insulating capping layer 430 is in direct contact with the top surface of the first gate conductive layer 420, and the second portion of the insulating capping layer 430 is in direct contact with the second portion of the first gate dielectric layer 410.

[0125] In this embodiment, the positions of the first alphanumeric groove 11 and the second alphanumeric groove 12 are not limited and can be set according to actual needs. For example, the depth of the second alphanumeric groove 12 can be less than the depth of the first alphanumeric groove 11. In this case, the shallower depth of the second alphanumeric groove 12 effectively ensures that the top of the portion of the insulating cover layer 430 located within the second alphanumeric groove 12 (the second portion) will not have gaps. In this case, in subsequent processes, processing can be performed on a flat surface within the area where the second alphanumeric groove 12 is located, thereby improving product yield.

[0126] In one embodiment, see Figure 12 The semiconductor structure also includes an insulating isolation pillar 710. The insulating isolation pillar 710 extends into the second word line trench 12 and is in direct contact with the insulating capping layer 430.

[0127] At this point, the semiconductor structure may also include a node contact structure 800. The node contact structure 800 may contact the active region 110 on one side of the word line structure, connecting to the source or drain of the transistor in the memory cell, thereby leading its signal upward to the capacitor. The node contact structure 800 may include a contact layer 810 and a metal layer 820 stacked together.

[0128] The insulating isolation column 710 can effectively isolate the nodes between the contact structures 800.

[0129] For example, the insulating isolation posts 710 may also be located in the peripheral area. And in the peripheral area, insulating filler posts 720 may be provided between the insulating isolation posts 710.

[0130] In one embodiment, see Figure 13 The semiconductor structure includes a substrate 100, a first gate dielectric layer 410, a first gate conductive layer 420, an insulating capping layer 430, and multiple word line trenches. It is understood that, although this embodiment is different from... Figure 1 The semiconductor structures of the illustrated embodiments are not exactly the same, but can be referenced. Figure 1 The isolation structure 120, active area 110, first word line groove 11 and second word line groove 12 in this embodiment are explained by the top view shown and the following text.

[0131] The substrate 100 includes an isolation structure 120 and an active region 110 defined by the isolation structure 120. A plurality of word line trenches are located within the substrate 100 and spaced apart along a first direction. Each word line trench passes through the active region 110 and the isolation structure 120. The plurality of word line trenches include a first word line trench 11 and a second word line trench 12. Exemplarily, the depth of the second word line trench 12 may be less than the depth of the first word line trench 11. Exemplarily, the width of the second word line trench 12 in the first direction may be less than the width of the first word line trench 11 in the first direction.

[0132] The first gate dielectric layer 410 includes a first portion that is in direct contact with the inner wall of the first word line groove 11 and a second portion that is in direct contact with the inner wall of the second word line groove 12.

[0133] The first gate conductive layer 420 is located on the surface of the first gate dielectric layer 410 in the first word line trench 11;

[0134] The insulating capping layer 430 is located only within the first word line groove 11, covering the first gate conductive layer 420. Exemplarily, the insulating capping layer 430 may be configured to directly contact the top surface of the first gate conductive layer 420. Exemplarily, a conductive protective layer 440 may also be provided between the insulating capping layer 430 and the first gate conductive layer 420.

[0135] In this embodiment, only the first gate dielectric layer 410 is provided in the second word line trench 12, without the first gate conductive layer 420 and the insulating capping layer 430. At this time, after the word line trench is formed, when the first gate dielectric material layer 410a is deposited, the first gate dielectric material layer 410a fills the second word line trench 12. After removing the first gate dielectric material layer 410a outside the word line trench, the remaining first gate dielectric material layer 410a forms the first gate dielectric layer 410. At this time, the upper surface of the first gate dielectric layer 410 filling the second word line trench 12 is flat, thus facilitating subsequent processes.

[0136] In one embodiment, a method for fabricating a semiconductor structure is provided, comprising the following steps:

[0137] Step S10, please refer to Figure 14 A substrate 100 is provided; the substrate 100 includes an initial isolation structure 120a and first active structures 111 defined by the initial isolation structure 120a, the first active structures 111 extending along a third direction and spaced apart; the initial isolation structure 120a includes a first initial isolation portion 1201a and a third initial isolation portion 1203a, the first initial isolation portion 1201a being located between adjacent first active structures 111, the third initial isolation portion 1203a being located outside all first active structures 111, and in a first direction, the width of the third initial isolation portion 1203a being greater than the width of the first initial isolation portion 1201a;

[0138] For step S20, please refer to... Figure 15 The substrate 100 is etched to form a plurality of word line trenches spaced apart along a first direction. After etching, the remaining initial isolation structure 120a forms an isolation structure 120, wherein the remaining first initial isolation portion 1201a forms a first isolation portion 1201, and the remaining third initial isolation portion 1203a forms a third isolation portion 1203. The plurality of word line trenches include a first word line trench 11 and a second word line trench 12. The first word line trench 11 passes through the first active structure 111 and the first isolation portion 1201 in a second direction, and the second word line trench 12 passes through the third isolation portion 1203 in a second direction. The second direction intersects the first direction, and the depth of the second word line trench 12 is less than the depth of the first word line trench 11.

[0139] For step S30, please refer to... Figure 16 A first character line 401 is formed in the first character line groove 11, and a second character line 402 is formed in the second character line groove 12. The second character line 402 is made of insulating material.

[0140] In step S10, an initial isolation structure 120a may be formed within the substrate 100. The initial isolation structure 120a defines a plurality of first active structures 111 within the substrate 100.

[0141] The initial isolation structure 120a includes a first initial isolation section 1201a and a third initial isolation section 1203a. The first initial isolation section 1201a may be located in the storage area. The third initial isolation section 1203a may be located in the peripheral area.

[0142] In step S20, etching can be performed simultaneously on the substrate 100 of the storage region and the peripheral region to form a first word line trench 11 in the storage region and a second word line trench 12 in the peripheral region. The second word line trench 12 in the peripheral region passes through the third isolation portion 1203 and has a shallow depth.

[0143] In step S30, processing can be performed simultaneously in the first character line groove 11 and the second character line groove 12 to simultaneously form the first character line 401 and the second character line 402. Furthermore, since the depths of the first character line groove 11 and the second character line groove 12 are different, the second character line 402 formed in the second character line groove 12 can be made of insulating material.

[0144] In this embodiment, during the fabrication of the first letter 401 and the second letter 402, since the second letter groove 12 is relatively shallow, even if gaps occur due to unevenness in the groove during the deposition of insulating material within the second letter groove 12, these gaps tend to rise above the second letter groove 12. Therefore, after removing the insulating material outside the second letter groove 12 using a chemical mechanical polishing (CMP) process to form the second letter 402, a smooth surface of the second letter 402 can be obtained. In subsequent processes, processing can be performed based on the smooth surface of the second letter 402 within the area where it is located, thereby improving product yield. This also prevents the third isolation portion 1203 in the outer area from being uneven due to its large size, which could affect subsequent processes performed on the third isolation portion 1203.

[0145] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0146] In the description of this specification, references to terms such as "one embodiment," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0147] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0148] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes an isolation structure and an active region defined by the isolation structure; The active region includes a first active structure and a second active structure. The first active structure extends along a third direction and is arranged at intervals. The second active structure is located outside the first active structure. The isolation structure includes a first isolation portion and a second isolation portion. The first isolation portion is located between adjacent first active structures along a third direction. The second isolation portion is located between adjacent first active region structures and second active structures along a third direction. In a first direction, the width of the second isolation portion is greater than the width of the first isolation portion. Multiple word line trenches are located within the substrate and are spaced apart along a first direction, including a first word line trench and a second word line trench. The first word line trench passes through the active region and the first isolation portion in a second direction, and the second word line trench passes through the active region and the second isolation portion in a second direction. The second direction intersects the first direction, and the depth of the second word line trench is less than the depth of the first word line trench. The structure includes a first word line and a second word line, wherein the first word line is located in a first word line groove and the second word line is located in a second word line groove, and the second word line is made of insulating material.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes: The first gate dielectric layer includes a first portion located on the inner wall of the first word line trench and a second portion located on the inner wall of the second word line trench; The first gate conductive layer is located on the surface of the first gate dielectric layer of the first word line trench; An insulating capping layer includes a first portion located in a first word line trench and a second portion located in a second word line trench, wherein the first portion of the insulating capping layer is in direct contact with the top surface of the first gate conductive layer, and the second portion of the insulating capping layer is in direct contact with the second portion of the first gate dielectric layer. The first word line is formed by the first gate dielectric layer, the first gate conductive layer and the insulating capping layer in the first word line trench, and the second word line is formed by the first gate dielectric layer and the insulating capping layer in the second word line trench.

3. The semiconductor structure according to claim 2, characterized in that, The width of the insulating cover layer of the second character line in the first direction is smaller than the width of the insulating cover layer of the first character line in the first direction.

4. The semiconductor structure according to claim 2, characterized in that, The first word line also includes a conductive protective layer, which is located between the first gate conductive layer and the insulating capping layer.

5. The semiconductor structure according to claim 1, characterized in that, Both the first isolation portion and the second isolation portion include a first oxide layer and a nitride layer, wherein the first oxide layer covers the sidewalls and bottom of the nitride layer. Below the first letter line opposite to the first isolation portion are the nitride layer and the first oxide layer. A nitride layer is provided below the second word line opposite to the second isolation portion, and the first oxide layer is provided on the sidewalls of the second word line and the nitride layer below it.

6. The semiconductor structure according to claim 5, characterized in that, The isolation structure includes a third isolation portion, which is located on the side of the second isolation portion away from the first isolation portion. The third isolation layer includes a first oxide layer, a nitride layer, and a second oxide layer. The first oxide layer covers the sidewalls and bottom of the nitride layer, and the nitride layer covers the sidewalls and bottom of the second oxide layer.

7. The semiconductor structure according to claim 1, characterized in that, The width of the first character line in the first direction is greater than the width of the adjacent active region in the first direction.

8. A method for fabricating a semiconductor structure, characterized in that, The semiconductor structure has a storage region and a peripheral region surrounding the storage region, and the method for fabricating the semiconductor structure includes: A substrate is provided; the substrate includes an initial isolation structure and a first active structure defined by the initial isolation structure, the first active structures extending along a third direction and spaced apart; the initial isolation structure includes a first initial isolation portion and a third initial isolation portion, the first initial isolation portion being located between adjacent first active structures, the third initial isolation portion being located outside all first active structures, and in a first direction, the width of the third initial isolation portion being greater than the width of the first initial isolation portion. The substrate is etched to form a plurality of word line trenches spaced apart along a first direction; after etching, the remaining initial isolation structure forms an isolation structure, wherein the remaining first initial isolation portion forms a first isolation portion, and the remaining third initial isolation portion forms a third isolation portion; the plurality of word line trenches include a first word line trench and a second word line trench, the first word line trench passes through the first active structure and the first isolation portion in a second direction, the second word line trench passes through the third isolation portion in a second direction, the second direction intersects the first direction, and the depth of the second word line trench is less than the depth of the first word line trench; A first character line is formed in the first character line groove, and a second character line is formed in the second character line groove, the second character line being made of insulating material.

9. A semiconductor structure, characterized in that, include: The substrate includes an isolation structure and a first active structure defined by the isolation structure, the first active structure extending along a third direction and spaced apart. The isolation structure includes a first isolation portion and a third isolation portion. The first isolation portion is located between adjacent first active structures along a third direction. The third isolation portion is located outside all the first active structures. In a first direction, the width of the third isolation portion is greater than the width of the first isolation portion. Multiple word line trenches are located within the substrate and are spaced apart along a first direction, including a first word line trench and a second word line trench. The first word line trench passes through the first isolation portion and the first active structure in a second direction, and the second word line trench passes through the third isolation portion in a second direction. The second direction intersects the first direction, and the depth of the second word line trench is less than the depth of the first word line trench. Multiple character line structure, including the first character line and the second character line; The first character line is located in the first character line groove, the second character line is located in the second character line groove, and the second character line is made of insulating material.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure includes: The first gate dielectric layer includes a first portion located on the inner wall of the first word line trench and a second portion located on the inner wall of the second word line trench; The first gate conductive layer is located on the surface of the first gate dielectric layer of the first word line trench; An insulating capping layer includes a first portion located in a first word line trench and a second portion located in a second word line trench, wherein the first portion of the insulating capping layer is in direct contact with the top surface of the first gate conductive layer, and the second portion of the insulating capping layer is in direct contact with the second portion of the first gate dielectric layer. The first word line is formed by the first gate dielectric layer, the first gate conductive layer and the insulating capping layer in the first word line trench, and the second word line is formed by the first gate dielectric layer and the insulating capping layer in the second word line trench.

11. The semiconductor structure according to claim 10, characterized in that, The width of the insulating cover layer of the second character line in the first direction is smaller than the width of the insulating cover layer of the first character line in the first direction.

12. A semiconductor structure, characterized in that, include: The substrate includes an isolation structure and an active region defined by the isolation structure; Multiple word line trenches are located within the substrate, spaced apart along a first direction, passing through the active region and the isolation structure, and include a first word line trench and a second word line trench. The first gate dielectric layer includes a first portion located on the inner wall of the first word line trench and a second portion located on the inner wall of the second word line trench; The first gate conductive layer is located on the surface of the first gate dielectric layer of the first word line trench; An insulating capping layer includes a first portion located in a first word line groove and a second portion located in a second word line groove, wherein the first portion of the insulating capping layer is in direct contact with the top surface of the first gate conductive layer, and the second portion of the insulating capping layer is in direct contact with the second portion of the first gate dielectric layer.

13. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure also includes: An insulating isolation post extends into the groove of the second letter and is in direct contact with the insulating cover layer.

14. A semiconductor structure, characterized in that, include: The substrate includes an isolation structure and an active region defined by the isolation structure; Multiple word line trenches are located within the substrate, spaced apart along a first direction, passing through the active region and the isolation structure, and include a first word line trench and a second word line trench. The first gate dielectric layer includes a first portion that is in direct contact with the inner wall of the first word line trench and a second portion that is in direct contact with the inner wall of the second word line trench. The first gate conductive layer is located on the surface of the first gate dielectric layer of the first word line trench; An insulating capping layer is located only within the first word line groove and covers the first gate conductive layer.

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