Integrated circuit and method of forming the same

Abstract

Methods for forming a transistor include depositing a first gate metal layer on a high-K gate dielectric layer; and depositing a work function gate metal layer on the first gate metal layer. The first gate metal layer has a lower resistivity than the work function metal layer. The work function gate metal layer is formed in situ with the first gate metal layer without breaking vacuum. This helps ensure that the first gate metal is not oxidized at all during deposition of the work function metal. Metal atoms from the work function gate metal layer effectively diffuse into the first gate metal layer and migrate laterally and vertically. Embodiments of the present application also relate to integrated circuits and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuits and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have yielded multiple generations of integrated circuits, each featuring smaller and more complex circuits than the previous generation. Throughout the development of integrated circuits, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization process typically provides benefits through increased production efficiency and reduced associated costs. However, such miniaturization also increases the complexity of handling and manufacturing integrated circuits. Summary of the Invention

[0003] Some embodiments of this application provide a method for forming an integrated circuit, comprising: forming a first region including a first active region and a first fin substrate region; forming a second region including a second active region and a second fin substrate region; depositing an isolation structure between the first fin substrate region and the second fin substrate region, wherein the isolation structure is adjacent to the sidewalls of the first fin substrate region and the sidewalls of the second fin substrate region; defining a plurality of stacked first channels of a first transistor extending in a first lateral direction by forming source / drain trenches in the first active region; growing a first source / drain region of the first transistor in the source / drain trenches, the first source / drain region being coupled to the first channel. The channel has a width greater than the channel in the second lateral direction, such that a portion of the first source / drain region is suspended above the isolation structure; an etch stop layer is deposited over the source / drain region and the isolation structure; an interlayer dielectric layer is deposited on the etch stop layer; an interface gate dielectric layer is formed on the channel; a high-k gate dielectric layer is formed on the interface gate dielectric layer; a first gate metal layer of the gate electrode is deposited on the high-k gate dielectric layer; and a second gate metal layer is deposited in situ on the first gate metal layer between the first channels, the second gate metal layer having a higher resistivity than the first gate metal layer and corresponding to the work function gate metal of the transistor.

[0004] Other embodiments of this application provide a method for forming an integrated circuit, comprising: forming a semiconductor fin extending in a first direction; forming an isolation structure adjacent to the semiconductor fin; depositing a gate spacer layer over the semiconductor fin and the isolation structure; defining a plurality of stacked channels of transistors below the gate spacer layer by forming source / drain trenches in the semiconductor fin; growing source / drain regions in the source / drain trenches; depositing a gate dielectric layer on the channels, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer layer; and depositing the gate dielectric layer between the channels. A first gate metal layer is deposited on the gate dielectric layer; a second gate metal layer is formed on the first gate metal layer between the channels, wherein the aluminum concentration in the first gate metal layer is higher after the formation of the second gate metal layer than before the formation of the second gate metal layer; an interlayer dielectric layer is deposited over the source / drain regions; and a source / drain contact is formed extending through the interlayer dielectric layer to be electrically coupled to the source / drain regions, wherein the source / drain contact is spaced apart from the source / drain regions by a metal-containing layer having a composition different from that of the source / drain contact.

[0005] Some embodiments of this application provide an integrated circuit, including: an N-type transistor comprising: a plurality of stacked first channels; an interface gate dielectric layer located on the stacked first channels; a high-k gate dielectric layer located on the interface gate dielectric layer; a source / drain region coupled to the channels; a gate electrode comprising: a first gate metal located on the high-k gate dielectric between the first channels, and a second gate metal located on the first gate metal layer between the channels, wherein the first gate metal has a gradient aluminum concentration that increases with distance from the high-k gate dielectric layer; a gate spacer layer adjacent to the gate electrode; and a first etch. A stop layer is disposed above the source / drain region; a first interlayer dielectric layer is disposed above the first etch stop layer; a source / drain contact extends through the first interlayer dielectric layer to be electrically coupled to the source / drain region, wherein the conductivity of the source / drain contact is greater than the conductivity of the source / drain region, wherein the source / drain contact is separated from the gate spacer layer by the first etch stop layer; a second etch stop layer is located above the gate spacer layer; and a second interlayer dielectric layer is located above the second etch stop layer, wherein the source / drain contact is spaced from the gate metal by the gate spacer layer and the first etch stop layer. Attached Figure Description

[0006] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1 to 28 These are cross-sectional views, top views, and perspective views of an integrated circuit at various processing stages according to some embodiments.

[0008] Figure 29 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments.

[0009] Figure 30 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0012] Terms indicating relative degree, such as “about” or “basically”, should be interpreted as those skilled in the art would take into account current technical specifications.

[0013] This disclosure generally relates to semiconductor devices, and more particularly to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured devices. Examples of nanostructured devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and the like. In advanced technology nodes, the active region spacing between nanostructured devices is typically uniform, the source / drain epitaxial structure is symmetrical, and a metal gate surrounds all four sides of the nanostructure (e.g., a nanosheet).

[0014] GAA transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with pitches, for example, smaller than those achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0015] Embodiments of this disclosure provide a method for forming a transistor with low gate resistance and low threshold voltage. The gate electrode of the transistor includes depositing a function metal after depositing a first metal layer having a resistivity lower than that of the function metal. The function gate metal layer is formed in situ with the formation of the first gate metal layer without breaking the vacuum. This helps ensure that the first gate metal is not oxidized during the deposition of the function metal. Nucleation of metal atoms from the function gate metal layer is better on the first gate metal layer than on the gate dielectric layer, and metal atoms can efficiently diffuse into the first gate metal layer and migrate laterally and vertically. The in-situ formation of the function metal with the first gate metal layer provides a gate electrode with lower resistance, thereby reducing the overall gate resistance and improving electrical performance. The threshold voltage is low and there are no undesirable variations. Because the first gate metal layer suffers little or no oxidation, a uniform function metal can be formed even within the limited spacing between channels. All of these result in transistors with improved electrical characteristics, integrated circuits in which transistors are formed with better functionality, and improved wafer yield.

[0016] While the accompanying drawings and description focus primarily on examples of nanostructured transistors including channel stacks, the principles of this disclosure extend to other types of transistors. These principles extend to MOS transistors, FinFETs, and other types of transistors.

[0017] Figures 1 to 16BThese are cross-sectional views, top views, and perspective views of an integrated circuit 100 manufactured according to some embodiments of the present disclosure. The manufacturing process produces a plurality of transistors 101, as will be described in further detail below.

[0018] Figure 1 This is a cross-sectional view of integrated circuit 100 during an intermediate processing stage. Integrated circuit 100 includes a substrate 102. Substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., having P-type or N-type dopants) or undoped. The semiconductor material of substrate 102 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium arsenide phosphide indium; or combinations thereof. Other substrates, such as single-layer, multilayer, or gradient substrates, may be used.

[0019] Integrated circuit 100 includes a semiconductor stack 103, which includes a plurality of alternating semiconductor layers 104 and sacrificial semiconductor layers 106. Figure 1 In one example, the stack 103 includes three semiconductor layers 104 and four sacrificial semiconductor layers 106. However, in practice, different numbers of semiconductor layers 104 and sacrificial semiconductor layers 106 may be used without departing from the scope of embodiments of this disclosure.

[0020] As will be explained in further detail below, the patterned semiconductor layer 104 is used to form a stacked channel for multiple transistors. As will be explained in more detail below, the sacrificial semiconductor layer 106 will eventually be completely removed and used to enable the formation of gate metal and other structures around the channel.

[0021] In some embodiments, the semiconductor layer 104 is formed of a first semiconductor material, such as silicon, silicon carbide, etc. The sacrificial semiconductor layer 106 is formed of a second semiconductor material, such as silicon germanium, etc. According to some embodiments, each layer of the multilayer stack 103 is epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0022] Due to the high etch selectivity between the materials of semiconductor layer 104 and sacrificial semiconductor layer 106, the sacrificial semiconductor layer 106 of the second semiconductor material can be removed without significantly etching the semiconductor layer 104 of the first semiconductor material, thereby allowing the semiconductor layer 104 to be released to form the stacked channel region of the transistor, as will be explained in more detail below.

[0023] In one example, semiconductor layer 104 is silicon, and sacrificial semiconductor layer 106 is silicon-germanium. In some embodiments, sacrificial semiconductor layer 106 has a germanium concentration between 10% and 50%, but other concentrations may be used without departing from the scope of embodiments of this disclosure. This makes sacrificial semiconductor layer 106 selectively etchable relative to semiconductor layer 104. Other materials and concentrations may be used without departing from the scope of embodiments of this disclosure.

[0024] Figure 2A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 2B The integrated circuit 100 according to some embodiments is in Figure 2A A top view of the processing stage shown. Figure 2A The cross-sectional view is from Figure 2B Cut along cutting line 2A.

[0025] exist Figure 2A In this context, multiple semiconductor fins 108a-108c have been formed by stacked components 103. In the following discussion, some reference numerals include the suffixes "a", "b", or "c". The suffixes may be omitted when the reference is not specific to a particular single structure. For example, when the reference applies to each semiconductor fin, semiconductor fins 108a-108c may be simply referred to as semiconductor fin 108.

[0026] Semiconductor fins 108 are formed by forming trenches 110 in the stack 103 and the substrate 102. Although Figure 1 Not shown, but a hard mask layer is first formed and patterned on the stack 103. Trench 110 is formed using an anisotropic etching process, which etches in the downward direction in the presence of the patterned hard mask. The etching process defines semiconductor fins 108 by forming trench 110 through the sacrificial semiconductor layer 106, semiconductor layer 104, and substrate 102. Semiconductor fins 108 extend in the X direction and are spaced apart from each other in the Y direction by the trench 110.

[0027] Semiconductor fins 108a-108c each correspond to an active region or active area A1-A3 of integrated circuit 100. Each active area corresponds to the location of the source / drain and channel regions forming a transistor. Semiconductor fin 108a corresponds to a first active region. Semiconductor fin 108b corresponds to a second active region. Semiconductor fin 108c corresponds to a third active region. In some embodiments, the substrate 102 of each semiconductor fin corresponds to a doped well region. In other words, the first region includes the first active region A1 and the first semiconductor fin 108a. The second region includes the second active region A2 and the second semiconductor fin 108b. The third region includes the third active region A3 and the third semiconductor fin 108c.

[0028] exist Figure 2A and Figure 2B In this process, an isolation structure 112 has been formed by depositing dielectric material in the grooves 110 between the fins 108. Figure 2A The isolation structure 112 is shown as a single dielectric material layer. However, in practice, multiple dielectric layers can be used to form the isolation structure 112. The dielectric layers can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. In an exemplary embodiment, the dielectric material of the isolation structure 112 includes silicon oxide. However, without departing from the scope of embodiments of this disclosure, the dielectric material may include SiN, SiCN, SiOC, SiOCN, or other dielectric materials. Each semiconductor fin 108 has a fin substrate region 109. The isolation structure is adjacent to the fin substrate portions of two adjacent semiconductor fins 108.

[0029] After depositing the dielectric material of the isolation structure 112, an etch-back process has been performed to recess the top of the isolation structure 112 below the bottommost sacrificial semiconductor layer 106. This results in the isolation structure 112 having a top surface below the bottom surface of the bottommost sacrificial semiconductor layer 106 of each fin. Other processes may be used to form the isolation structure 112 without departing from the scope of embodiments of this disclosure. Each isolation structure 112 extends in the X direction beside and between two adjacent semiconductor fins 108.

[0030] In some embodiments, the isolation structure 112 comprises SiO2 or other suitable dielectric material. In some embodiments, the isolation structure 112 has a depth between 50 nm and 100 nm.

[0031] In some embodiments, semiconductor fins 108a-108c correspond to active regions for N-type transistors. As will be described in more detail below, in some embodiments, tensile strain is provided to the channel of the N-type transistor using sacrificial source / drain regions of a first semiconductor material. In some embodiments, the sacrificial source / drain regions are replaced with source / drain regions of a second semiconductor material that promote low resistance in the source / drain regions.

[0032] Figure 3A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 3B It is integrated circuit 100 in Figure 3A A top view of the processing stage shown. Figure 3A The cross-sectional view is from Figure 3B Cut along cutting line 3A.

[0033] exist Figure 3A and Figure 3BIn this configuration, a sacrificial gate structure 114 has been formed above the fin 108. Each sacrificial gate structure 114 extends in the Y direction across the semiconductor fin 108 and the isolation structure 112. The layout of the sacrificial gate structure 114 corresponds to the layout of the gate metal or gate structure of the transistor. In particular, the sacrificial gate structure 114 will eventually be replaced with gate metal. The sacrificial gate structure 114 corresponds to the corresponding gate metal layout positions G1-G3.

[0034] The sacrificial gate structure 114 includes a dielectric layer 116. In an exemplary embodiment, the dielectric layer 116 comprises silicon oxide. However, alternatively, without departing from the scope of embodiments of this disclosure, the dielectric layer 116 may comprise SiN, SiCN, SiOC, SiOCN, or other dielectric materials. In some embodiments, the dielectric layer 116 has a low-k dielectric material. The dielectric layer 116 may be deposited by CVD, ALD, or PVD.

[0035] The sacrificial gate structure includes a sacrificial gate layer 118 on dielectric layer 116. The sacrificial gate layer 118 may include a material with high etch selectivity relative to isolation structure 112. In an exemplary embodiment, the sacrificial gate layer 118 includes polysilicon. However, the sacrificial gate layer 118 may be a conductive, semi-conductive, or non-conductive material, and may be or include amorphous silicon, polysilicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 118 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques used for depositing the selected material.

[0036] In some embodiments, the sacrificial gate structure 114 includes a dielectric layer on the sacrificial gate layer 118. In an exemplary embodiment, the dielectric layer includes SiN. However, alternatively, without departing from the scope of embodiments of this disclosure, the dielectric layer may include SiO, SiCN, SiOC, SiOCN, or other dielectric materials. The dielectric layer may be deposited by CVD, ALD, or PVD.

[0037] exist Figure 3A and Figure 3BIn this embodiment, a gate spacer layer 120 has been formed on the sidewalls of the sacrificial gate structure 114. Specifically, the gate spacer layer 120 is formed on the sidewalls of the dielectric layer 116 and the sacrificial gate layer 118. The gate spacer layer 120 is also formed on the top surface of the sacrificial gate structure 114, the top semiconductor layer 104 of each semiconductor fin 108, and other exposed surfaces. The gate spacer layer 120 can be formed by PVD, CVD, ALD, or other suitable deposition processes. In a specific example shown herein, the gate spacer layer 120 comprises SiOCN. Alternatively, the gate spacer layer 120 may comprise one or more of SiO, SiN, SiON, SiCN, SiOC, or other suitable dielectric materials. In some embodiments, the gate spacer layer 120 has a width between 2 nm and 8 nm, but other thicknesses may be utilized without departing from the scope of embodiments of this disclosure. Figure 3A A single gate spacer layer 120 is shown. However, in some embodiments, the gate spacer structure includes a second gate spacer layer.

[0038] exist Figure 3A and Figure 3B In this process, an etching process has been performed to pattern the gate spacer layer 120. The etching process includes an anisotropic etching process that etches in the downward direction. The anisotropic etching process removes the gate spacer layer 120 from the horizontal surface of the gate spacer 120, which has a smaller vertical thickness. After the gate spacer layer is patterned, the vertically thicker portion of the gate spacer layer 120 remains on the sidewall of the sacrificial gate structure 114.

[0039] As in Figure 3B As can be seen in the top view, after the patterned gate spacer layer 120, the dielectric structure 121 remains on the top surface of the isolation structure 112 as the remainder of the gate spacer layer 120. Although not shown in the figure, the dielectric structure 121 will suppress the lateral growth of the lower portion of the source / drain region.

[0040] exist Figure 3A and Figure 3B In this process, the CMP process has been implemented. The CMP process reduces the height of the sacrificial gate layer 118 and the gate spacer layer 120.

[0041] Figure 4 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 4In some embodiments, source / drain trenches 124 have been formed. After patterning the gate spacer layer 120, one or more etching processes are performed to form the source / drain trenches 124 in the fins 108. Forming the source / drain trenches 124 includes etching through each of the semiconductor layers 104, each of the sacrificial semiconductor layers 106, and portions of the substrate 102. Therefore, the removal operations include suitable etching operations for removing material from the semiconductor layers 104, the sacrificial semiconductor layers 106, and the substrate 102. The etching processes may include reactive ion etching (RIE), neutral beam etching (NBE), atomic layer etching (ALE), etc.

[0042] The formation of the source / drain trench 124 results in the formation of a stack 126 of channel 105. Specifically, the remaining portion of the semiconductor layer 104, after the formation of the source / drain trench 124, now corresponds to a stacked channel 105 of the transistor. The formation of the source / drain trench 124 results in the formation of a plurality of sacrificial semiconductor nanostructures 107 from the sacrificial semiconductor layer 106. A substrate 102 is exposed at the bottom of each source / drain trench 124. Each stack 126 of channel 105 corresponds to a stacked channel of an individual transistor, as will be explained in more detail below.

[0043] Figure 5 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 5 Internal spacers 130 have been formed. The formation of internal spacers 130 begins with a selective etching process to recess the exposed end portions of the sacrificial semiconductor nanostructure 107 without substantially etching the channel 105. More specifically, grooves are formed in the end portions of the sacrificial semiconductor nanostructure 107 relative to the adjacent channel 105. The grooves can be formed by performing an etching process that selectively etches the material of the sacrificial semiconductor nanostructure 107 relative to the materials of the channel 105 and the substrate 102.

[0044] The internal spacer 130 is formed by depositing a dielectric layer on the exposed surfaces of the channel 105, the gate spacer layer 120, and the sacrificial semiconductor nanostructure 107, and on the substrate 102, in a conformal deposition process. Most notably, the dielectric layer fills the trenches. The dielectric layer may include SiCN, SiOCN, SiON, SiN, or other suitable dielectric materials. The dielectric layer can be formed using suitable deposition methods, such as CVD, ALD, PVD, or other deposition processes.

[0045] The internal spacer 130 is formed by performing an anisotropic etching process in the downward direction. During the anisotropic etching process, the gate spacer layer 120 and the sacrificial gate structure 114 are used as a mask. The dielectric layer is removed from all locations exposed by the mask. As a result, the dielectric layer is removed from the trench 124. The portion of the dielectric layer retained in the recess of the sacrificial semiconductor nanostructure 107 corresponds to the internal spacer 130. The internal spacer 130 contacts the end of the sacrificial semiconductor nanostructure 107 and contacts the channel 105. As will be further explained in detail below, the internal spacer 130 separates the gate metal from the source / drain regions.

[0046] Figure 6 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 6 In this embodiment, an intervening component, such as a bottom semiconductor layer 132, has been formed on the substrate 102 at the bottom of each source / drain trench 124. In some embodiments, the bottom semiconductor layer 132 comprises an intrinsic (undoped) semiconductor material. In some embodiments, the semiconductor material of the semiconductor layer 132 is the same as the semiconductor material of the substrate 102. In some embodiments, the substrate 102 located below the source / drain trenches and channels 105 is a doped well region, and the bottom semiconductor layer 132 is undoped.

[0047] exist Figure 6 In each source / drain trench 124, an intervening component, such as a bottom dielectric structure 134, has been formed on the bottom semiconductor layer 132. The bottom dielectric structure 134 may include SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The bottom dielectric structure 134 may be formed by ALD, CVD, or PVD followed by a selected patterning process. The bottom dielectric structure 134 can help prevent leakage current from flowing between the source / drain regions and the bottom semiconductor layer 132. In some embodiments, the bottom dielectric structure 134 has a thickness between 2 nm and 8 nm.

[0048] Figure 7A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 7A In some embodiments, source / drain regions 136 have been formed in the source / drain trench 124. The source / drain regions 136 are epitaxially grown from the channel 105. Each channel 105 extends between adjacent source / drain regions 136.

[0049] In some embodiments, channel 105 is a silicon channel of an N-type transistor, and the semiconductor material of the source / drain region 136 is silicon; however, other semiconductor materials may be used without departing from the scope of embodiments of this disclosure. In some embodiments, the source / drain region 136 is phosphorus-doped silicon or arsenic-doped silicon. In some embodiments, the source / drain region 136 has a dopant concentration between 1E21 and 3E21. In some embodiments, the source / drain region 136 is epitaxially grown from the ends of channel 105 using a low-temperature CVD epitaxial growth process. In some embodiments, the temperature during the epitaxial growth process is between 300°C and 500°C. Other materials, dopants, dopant concentrations, and temperatures may be used in forming the source / drain region 136 without departing from the scope of embodiments of this disclosure.

[0050] Figure 7B It is based on some embodiments corresponding to Figure 7A A cross-sectional view of a variant of integrated circuit 100. Figure 7B In this embodiment, the source / drain region 136 includes a first source / drain layer 136a and a second source / drain layer 136b. In some embodiments, the first source / drain layer 136a is grown from the end of the channel 105 using a first epitaxial growth process. In some embodiments, the second source / drain layer 136b is grown using a second epitaxial growth process. In some embodiments, the first source / drain layer 136a and the second source / drain layer 136b are in-situ doped during the epitaxial growth process. In some embodiments, the first source / drain layer 136a is doped with a first dopant material, while the second source / drain layer 136b is doped with a second dopant material different from the first dopant material. In some embodiments, the first dopant material is arsenic, and the second dopant material is phosphorus. In some embodiments, the first source / drain layer has a different dopant concentration than the second source / drain layer. In some embodiments, the first source / drain layer is substantially undoped, while the second source / drain layer is doped with the dopant concentration described above. Other combinations of epitaxial growth processes and doping processes may be used without departing from the scope of embodiments of this disclosure.

[0051] Figure 8 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 8 In some embodiments, a contact etch stop layer (CESL) 140 and an interlayer dielectric (ILD) layer 142 have been formed. In some embodiments, CESL 140 is a thin dielectric layer conformally deposited on the exposed surfaces of the source / drain region 136 and the exposed surfaces of the gate spacer layer 120.

[0052] In some embodiments, CESL 140 comprises SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. CESL 140 can be deposited by CVD, ALD, PVD, or other suitable deposition processes. In a particular example, CESL 140 comprises silicon nitride. In some embodiments, CESL 140 has a thickness between 3 nm and 6 nm, but other thicknesses may be utilized without departing from the scope of embodiments of this disclosure.

[0053] Interlayer dielectric layer 142 covers CESL 140. Interlayer dielectric layer 142 fills the remaining space between adjacent sacrificial gate structures 114. Interlayer dielectric layer 142 may correspond to the bottommost interlayer dielectric layer of integrated circuit 100. In some embodiments, interlayer dielectric layer 142 may be referred to as ILD0. Interlayer dielectric layer 142 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. Interlayer dielectric layer 142 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0054] In some embodiments, a CMP process is performed after the interlayer dielectric layer 142 is deposited. The result of the CMP process is that the top surfaces of the interlayer dielectric layer 142, CESL 140, gate spacer layer 120, and sacrificial gate layer 118 are coplanar. The CMP process can also reduce the height of the sacrificial gate structure 114 and the gate spacer layer 120.

[0055] Figure 9A This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 9B According to some embodiments Figure 9A The cross-sectional view of integrated circuit 100 taken by the cutting line "X cut". Figure 9C According to some embodiments Figure 9A The term "Y-cut" refers to a cross-sectional view of integrated circuit 100 taken by a cutting line. Subsequently, the term "X-cut" refers to a cross-sectional view with the vertical direction being the Z-axis and the horizontal direction being the X-axis. The term "Y-cut" refers to a cross-sectional view with the vertical direction being the Z-axis and the horizontal direction being the Y-axis.

[0056] Figures 9A to 9C The integrated circuit 100 has relative to Figures 1 to 8 The structure shown is a slightly modified version of the original structure. Figures 1 to 8 Stack 103 is shown (see Figure 1 The top layer is the semiconductor layer 104. This results in a structure where there is no internal spacer 130 between the top channel 105 and the gate spacer layer 120. However, Figures 9A to 9C(And subsequent figures) show the case where an internal spacer 130 exists between the top channel 105 and the gate spacer layer 120. This structure can be produced when starting with a stack 103 containing a sacrificial semiconductor layer 106 on top of the highest semiconductor layer 104. Used to form Figures 9A to 9C The process of the structure shown is basically similar to Figures 1 to 8 The process shown is slightly modified due to the presence of a sacrificial semiconductor layer 106 above the highest semiconductor layer 104.

[0057] exist Figures 9A to 9C In some embodiments, the sacrificial gate layer 118 and the dielectric layer 116 have been removed. The sacrificial gate layer 118 can be removed by an etching process that selectively etches the material of the sacrificial gate layer 118 relative to adjacent materials, such as the gate spacer layer 120. The removal of the sacrificial gate layer 118 creates a gap 143 between the gate spacer layers 120.

[0058] exist Figures 9A to 9C In some embodiments, an etching process has been performed to remove the sacrificial semiconductor nanostructure 107. The sacrificial semiconductor nanostructure 107 can be removed by a selective etching process using an etchant selective to the material of the channel 105, thereby removing the sacrificial semiconductor nanostructure 107 without substantially etching the channel 105. The removal of the sacrificial semiconductor nanostructure 107 is referred to as “releasing” the channel 105. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, combinations thereof, etc. In some embodiments, the etching process reduces the thickness of the central portion of each channel 105, such that the end portions of the channel 105 are perpendicularly thicker than the central portions of the channel 105. The etching process also causes the gap 143 to extend between the channels 105.

[0059] like Figure 9A As can be seen, the source / drain region 136 extends laterally in the Y direction above the isolation structure 112 on either side of the fin 108. Furthermore, the source / drain region 136 has a hexagonal structure. Therefore, the source / drain region 136 has a wider width in the Y direction than the channel 105, causing a portion of the first source / drain region to hang above the isolation structure 112. Figure 9A In this configuration, adjacent source / drain regions 136 are already grown together. However, in some embodiments, the source / drain regions 136 are not connected together. In some embodiments, an isolation structure (not shown) is formed to physically separate adjacent source / drain regions 136.

[0060] Figure 10AThis is a cross-sectional view of an integrated circuit 100 corresponding to an X-cut according to some embodiments. Figure 10B This is a cross-sectional view of an integrated circuit 100 corresponding to a Y-cut according to some embodiments.

[0061] exist Figure 10A and Figure 10B In some embodiments, a gate dielectric has been formed. The gate dielectric includes an interface gate dielectric layer 146 and a high-k gate dielectric layer 148. In some embodiments, the interface gate dielectric layer 146 has been deposited on an exposed portion of the channel 105. The interface gate dielectric layer 146 is formed directly on the exposed portion of the channel 105. The high-k gate dielectric layer 148 is formed on the interface gate dielectric layer 146 and on other exposed surfaces, such as the exposed sidewalls of the gate spacer layer 120 and the internal spacer 130.

[0062] Interface gate dielectric layer 146 surrounds channel 105. Interface gate dielectric layer 146 may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric materials. Interface gate dielectric layer 146 may include a relatively low-k dielectric relative to a high-k dielectric (such as hafnium oxide or other high-k dielectric materials that can be used in the gate dielectric of a transistor). High-k dielectrics may include dielectric materials having a dielectric constant higher than that of silicon oxide. Interface gate dielectric layer 146 may be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. Interface gate dielectric layer 146 may have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for interface gate dielectric layer 146 without departing from the scope of embodiments of this disclosure.

[0063] A high-k gate dielectric layer 148 is deposited in a conformal deposition process. The conformal deposition process deposits the high-k gate dielectric layer 148 on the interface gate dielectric layer 146, the substrate 102, the gate spacer layer 120, and the internal spacer 130. The high-k gate dielectric layer 148 surrounds the channel 105. The high-k gate dielectric layer 148 has a thickness between 1 nm and 3 nm. The high-k gate dielectric layer 148 includes one or more dielectric material layers, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The high-k gate dielectric layer 148 can be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials may be used for the high-k gate dielectric layer 148 without departing from the scope of embodiments of this disclosure. The high-k gate dielectric layer 148 has a higher dielectric constant than the gate spacer layer 120. The high-k gate dielectric layer 148 is formed on the interface gate dielectric layer 146.

[0064] Figure 11A This is a cross-sectional view of an integrated circuit 100 corresponding to an X-cut according to some embodiments. Figure 11B This is a cross-sectional view of an integrated circuit 100 corresponding to a Y-cut according to some embodiments.

[0065] In some embodiments, Figure 11A The channel 105 is the channel of the NFET. A high-k gate dielectric is now formed around the channel 105, which will form the gate electrode. By applying a selected voltage to the source / drain regions and the gate electrode, the transistor is either "turned on" (allowing current to flow through the channel from one source / drain region to another) or "turned off" (preventing current from flowing through the channel). In an NFET, the transistor is turned on by applying a voltage equal to or greater than the threshold voltage to the gate electrode. The threshold voltage of the transistor is partly based on the semiconductor material of the channel and the material of the gate electrode. As scaling down continues, in many cases, NFETs with lower threshold voltages are advantageous.

[0066] In some embodiments, the threshold voltage is partly based on the work function of the channel and the work function of the gate metal. In a broader sense, the threshold voltage is partly based on the difference between the work function of the gate electrode and the work function of the semiconductor material in the channel. The work function of the gate metal is the energy required to move an electron from the metal to a vacuum. The semiconductor work function is related to its electron affinity and band gap. If the work function of the gate metal is closer to the conduction band of the semiconductor, the threshold voltage is lower, which is advantageous for NFETs in some cases. If the work function of the gate metal is closer to the valence band of the semiconductor material in the channel, the threshold voltage is higher, which is advantageous for PFETs in some cases.

[0067] In some embodiments, the gate electrode of the NFET will have multiple gate metal layers. One of the gate metal layers is a function gate metal layer. The function gate metal layer is selected for adjusting the threshold voltage of the NFET, as described above. In some embodiments, the semiconductor material of the channel is silicon, and the function gate metal layer is an aluminum-containing metal, such as TaAl or TiAl, but other materials may be used without departing from the scope of embodiments of this disclosure.

[0068] According to some embodiments, one possible solution is to deposit an aluminum-containing work-function gate metal layer directly on the high-k gate dielectric layer 148 as the first gate metal layer of the gate electrode in the gate stack. However, this solution has some drawbacks. For example, the aluminum-containing work-function gate metal layer has relatively high resistivity compared to other metals. For example, the resistivity of TiAl can be between 2000 µΩ-cm and 4000 µΩ-cm, which may adversely affect the electrical performance of NFETs with larger channel lengths. Furthermore, there are difficulties associated with forming the aluminum-containing work-function gate metal layer directly on the high-k gate dielectric layer 148. For example, depositing TiAl using an ALD process may result in poor Al nucleation on the high-k gate dielectric layer 148, thereby affecting film quality, uniformity, adhesion, and deposition rate.

[0069] According to some embodiments, another solution is to deposit a first gate metal layer having a lower resistivity than the high-K gate dielectric layer 148 before depositing the function gate metal layer. In some embodiments, the function gate metal layer is then deposited in situ on the first gate metal layer in the same deposition chamber without breaking the vacuum. The integrated circuit 100 is part of the wafer during processing (and is later diced from the wafer after wafer processing is complete). The wafer is placed in a thin-film deposition chamber, and the vacuum chamber is under vacuum conditions to effectively eliminate or significantly reduce the amount of oxygen present during the thin-film deposition process. The first gate metal layer is then deposited using a thin-film deposition process. After depositing the first gate metal layer, the function gate metal layer is then deposited on the first gate metal layer in the same thin-film deposition chamber without breaking the vacuum. This provides several benefits, which will be described in more detail below. In some embodiments, forming a function gate metal layer "in situ" on the first gate metal layer includes: forming the first gate metal layer on the wafer in the deposition chamber; and forming the function gate metal layer in the same deposition chamber without removing the wafer from the deposition chamber and exposing the wafer to external conditions. In some embodiments, this includes not disrupting the vacuum conditions between the deposition of the first gate metal layer and the power function gate metal layer.

[0070] exist Figure 11A and Figure 11B In some embodiments, a first gate metal layer 150 is deposited on a high-k gate dielectric layer 148. In some embodiments, the first gate metal layer 150 is deposited in a thin-film deposition chamber under vacuum conditions, as described above. In some embodiments, the first gate metal layer 150 has a resistivity lower than that of a work-function gate metal layer. In some embodiments, the first gate metal layer 150 is titanium nitride having a resistivity between 300 µΩ-cm and 500 µΩ-cm.

[0071] In some embodiments, the first gate metal layer 150 is deposited using an ALD process. In some embodiments where the first gate metal layer 150 is titanium nitride, the ratio of titanium to nitrogen is about 1:1 or between 0.9 and 1.1. In some embodiments, the conditions in the ALD process include temperatures between 300°C and 400°C and a temperature of 10... -3 Up to 10 -7 The pressure between the trolleys. In some embodiments, the titanium source includes TiCl4 and the nitrogen source includes NH3, but other sources may be used for the ALD process without departing from the scope of embodiments of this disclosure.

[0072] In some embodiments, the first gate metal layer 150 has a thickness between 0.3 nm and 4 nm. The thickness of the first gate metal layer 150 is partially selected based on the vertical spacing between high-k gate dielectric layers 148 on adjacent channels 105. In some embodiments, the spacing between the high-k gate dielectric layers 148 on adjacent channels 105 is between 2 nm and 10 nm. The thickness of the first gate metal layer 150 is selected to ensure that a gap remains between adjacent channels 105 after the deposition of the first gate metal layer 150, such that a subsequently deposited power-function gate metal layer is formed between the channels 105. In some embodiments, the thickness of the first gate metal layer 150 is selected to ensure a gap of at least 0.3 nm and 3 nm. Other thicknesses, deposition processes, and materials may be selected for the first gate metal layer 150 without departing from the scope of embodiments of this disclosure.

[0073] Figure 12A This is a cross-sectional view of an integrated circuit 100 corresponding to an X-cut according to some embodiments. Figure 12B This is a cross-sectional view of an integrated circuit 100 corresponding to a Y-cut according to some embodiments.

[0074] exist Figure 12A and Figure 12B In some embodiments, a function gate metal layer 152 has been deposited on the first gate metal layer 150. In some embodiments, the function gate metal layer 152 is an aluminum-containing gate metal function gate metal layer. In some embodiments, the function gate metal layer is TiAl or TaAl, but other materials may be used without departing from the scope of embodiments of this disclosure. In some embodiments, tantalum aluminum has a resistivity between 1000 µΩ-cm and 5000 µΩ-cm.

[0075] As previously described, in some embodiments, the power-function gate metal layer 152 is deposited on the first gate metal layer 150 in the same deposition chamber as the first gate metal layer 150 without breaking the vacuum. In other words, after the deposition process for the first gate metal layer 150 is completed, the wafer of the integrated circuit 100 remains in the deposition chamber. The power-function gate metal layer 152 is then deposited in the deposition chamber without breaking the vacuum. In some embodiments, the power-function gate metal layer 152 is deposited using an ALD process, but other processes may be used without departing from the scope of embodiments of this disclosure. Thus, in some embodiments, the first ALD process deposits the first gate metal layer 150 without breaking the vacuum, and the second ALD process deposits the power-function gate metal layer 152.

[0076] Forming the functional gate metal layer 152 in situ without disrupting the vacuum offers several advantages. The first advantage is minimal or no oxidation of the first gate metal layer, as the wafer is not exposed to oxygen between the formation of the first gate metal layer 150 and the functional gate metal layer 152. Therefore, in some embodiments, the oxygen content is less than 0.1%. Furthermore, the first gate metal layer 150 remains fully or mostly oxidized, and aluminum nucleation on the first gate metal layer 150 is highly efficient during the ALD process for the functional gate metal layer 152 compared to nucleation on the high-k gate dielectric layer 148 or an oxidized gate metal layer. The result is a high-quality aluminum-containing functional gate metal layer 152 deposited on the first gate metal layer 150, filling the gaps between adjacent channels 105. Additionally, aluminum atoms can diffuse efficiently into the first gate metal layer 150 and can migrate laterally and vertically. This can help ensure a low threshold voltage for the transistor. Furthermore, for the forked transistor (as will be further described below with reference to the following figures), the titanium nitride of the first gate metal layer 150 serves as an effective etch stop layer for the formation of the gate contacts and also protects the power-function gate metal layer 152 from oxidation.

[0077] In some embodiments, because Al can migrate vertically in the first gate metal layer 150 toward the high-k gate dielectric layer 148, the threshold voltage of the NFET device is reduced, and the variation in threshold voltage is reduced, making the threshold voltage distribution of the NFET more concentrated, which improves stability and device yield. In some embodiments, the integrated circuit 100 includes an SRAM array comprising an NFET utilizing a first gate metal layer 150 and a work-function gate metal layer 152 as described herein. The dosage (atomic %) of aluminum within the first gate metal layer 150 is between 5% and 50%, and decreases further toward the high-k gate dielectric layer 148 (i.e., the Al concentration decreases with distance from the work-function gate metal layer 152). This helps to provide a gate electrode with lower resistance, thereby reducing overall gate resistance and improving electrical performance. The threshold voltage is low and there is no undesirable variation. Because the first gate metal layer suffers little or no oxidation, a uniform work-function metal can be formed even within the limited spacing between channels.

[0078] As previously explained, the lower resistivity of the first gate metal layer 150 compared to the resistivity of the power function gate metal layer 152 provides a lower overall resistance of the gate electrode, which offers better electrical performance, including higher switching speeds and lower power consumption. Because the first gate metal layer 150 remains unoxidized, a uniform layer of the aluminum-containing power function gate metal layer 152 can be formed even within the limited spacing between channels. For fork-type devices, the aluminum-containing power function gate metal layer is well protected from oxidation by the first gate metal layer 150, thereby preventing any shift in the threshold voltage.

[0079] In some embodiments, the thickness of the function gate metal layer 152 is between 0.3 nm and 3 nm. In some embodiments, the spacing between the first gate metal layers 150 on adjacent channels 105 is between 0.5 nm and 1 nm. The function gate metal layer 152 is grown from each adjacent first gate metal layer 150 and completely fills the remaining spacing between channels 105. In some embodiments, the thickness ratio of the first gate metal layer 150 to the function gate metal layer 152 is between 0.1 and 2, but other ratios may be used without departing from the scope of embodiments of this disclosure.

[0080] In some embodiments, the power function gate metal layer 152 comprises carbon. In some embodiments, the power function gate metal layer 152 is tantalum aluminum, comprising between 5% and 50% aluminum, between 20% and 50% titanium, and between 10% and 40% carbon. In some embodiments, the power function gate metal layer is tantalum aluminum, comprising between 5% and 50% aluminum, between 20% and 50% titanium, and between 10% and 40% carbon. Other combinations of concentrations may be used without departing from the scope of embodiments of this disclosure. Although Figure 12A and Figure 12B The remaining gaps between channels 105 are shown to be completely filled by the functional gate metal layer 152, but in some embodiments, small gaps still exist between channels 105 after the functional gate metal layer 152 is formed.

[0081] Figure 12C This is an enlarged cross-sectional view of portions of the high-k gate dielectric layer 148 and the first gate metal layer 150 during the deposition of the power-function gate metal layer, according to some embodiments. Figure 12C In one example, the first gate metal layer 150 is titanium nitride, and the work function gate metal layer 152 is titanium aluminum. As previously explained, other materials may be used for the gate metal layer 150 and the work function gate metal layer 152 without departing from the scope of the prior disclosure.

[0082] In some embodiments, the process for depositing the power function gate metal layer 152 is an ALD process, wherein the source for titanium includes TiCl4, and the source for aluminum includes trimethylaluminum (TMA) or triethylaluminum (TEA). In some embodiments, the formation conditions include a temperature between 300°C and 400°C, and 10 -3 To and 10 -7 The pressure between the trays and the flow rates of the titanium and aluminum sources are between 5 and 500 sccm, but other process conditions may be used without departing from the scope of embodiments of this disclosure.

[0083] Figure 12C Note 1 indicates that aluminum has a higher nucleation rate on the gate metal layer 150 compared to the case where there is high oxidation in the gate metal layer. Figure 12C Note 2: Aluminum atoms diffuse into the gate metal layer 150 and migrate vertically and laterally, thereby conformally doping the gate metal layer 150 with Al atoms. Figure 12C The formation of C2H5 molecules during the ALD process is also shown according to some embodiments.

[0084] In some embodiments, because the bottom gate metal layer 150 and the function gate metal layer 152 are deposited in situ, the diffusion barrier for Al atoms from the function gate metal layer to the gate metal layer 150 is lower due to the Al concentration gradient. In some embodiments, Al atoms can diffuse into the bottom TiN layer without an additional thermal annealing process. As explained above, in some embodiments, the gate metal layer 150 and the function gate metal layer 152 are formed in situ, such that the gate metal layer 150 is deposited on the wafer in the deposition chamber, and the function gate metal layer 152 is deposited on the wafer in the same deposition chamber without removing the wafer from the deposition chamber and exposing the wafer to external conditions. In some embodiments, this includes not breaking the vacuum conditions between the deposition of the first gate metal layer and the function gate metal layer. In some embodiments, a thermal annealing process is performed to allow Al atoms to diffuse further into the gate metal layer 150. Therefore, in some embodiments, a thermal annealing process is performed after the deposition of the function gate metal layer 152.

[0085] In some embodiments, a hybrid layer of gate metal layer 150 and power function gate metal layer 152 is formed between gate metal layer 150 and power function gate metal layer 152. In examples where gate metal layer 150 comprises titanium nitride and power function gate metal layer 152 comprises titanium aluminum, the hybrid layer is a TiAlN layer, but other materials may be used without departing from the scope of embodiments of this disclosure.

[0086] Figure 12D In completing about Figure 12C Enlarged cross-sectional view of portions of the high-k gate dielectric layer 148, gate metal layer 150, and power-function gate metal layer 152 after the ALD process. Figure 12D The diffusion of aluminum atoms within the gate metal layer 150 is shown. As previously explained, other materials may be used for the gate metal layer 150 and the power function gate metal layer 152 without departing from the scope of embodiments of this disclosure.

[0087] Figure 13A This is a cross-sectional view of an integrated circuit 100 corresponding to an X-cut according to some embodiments. Figure 13B This is a cross-sectional view of an integrated circuit 100 corresponding to a Y-cut according to some embodiments.

[0088] exist Figure 13A and Figure 13BIn some embodiments, a gate metal layer 154 has been deposited on the power function gate metal layer 152. In some embodiments, the gate metal layer 154 is a shielding layer for the power function gate metal layer 152. In some embodiments, the gate metal layer 154 comprises titanium nitride, tungsten nitride, tantalum nitride, or other suitable materials. In some embodiments, the gate metal layer 154 is made of the same material as the gate metal layer 150. In some embodiments, both the gate metal layer 154 and the gate metal layer 150 comprise titanium nitride. In some embodiments, the gate metal layer 154 has a thickness between 0.2 nm and 1.5 nm. In some embodiments, the gate metal layer 154 is titanium nitride having a Ti:N ratio between 0.9 and 1.1. Other thicknesses and atomic ratios may be utilized without departing from the scope of embodiments of this disclosure.

[0089] exist Figure 13A and Figure 13B In this process, a capping layer 156 has been formed on the gate metal layer 154. In some embodiments, a vacuum destruction step is performed between the deposition of the gate metal layer 154 and the deposition of the capping layer 156. In some embodiments, this results in oxidation of the gate metal layer 154. In some embodiments, the atomic percentage of oxygen in the gate metal layer 154 is less than 10% and greater than the oxygen concentration in the gate metal layer 150. In some embodiments, some aluminum from the gate metal layer 152 diffuses into the gate metal layer 154. In some embodiments, the atomic percentage of aluminum in the gate metal layer 154 is between 5% and 20%. The aluminum concentration in the gate metal layer 154 decreases in the direction from the gate metal layer 152 toward the capping layer 156.

[0090] In some embodiments, capping layer 156 comprises a thin layer of semiconductor material positioned on gate metal layer 154. In some embodiments, capping layer 156 may comprise silicon, silicon germanium, or other suitable semiconductor materials. In some embodiments, capping layer comprises SiTi or another suitable material. In the specific examples given herein, capping layer 156 is initially a silicon layer. Capping layer 156 may be deposited by ALD, CVD, PVD, or other suitable deposition processes. The thickness of capping layer 156 is between 0.5 nm and 2 nm, but other thicknesses may be utilized without departing from the scope of embodiments of this disclosure. In some embodiments, capping layer 156 ensures that aluminum from the functional gate metal layer 152 does not diffuse into subsequently deposited layers of the gate electrode.

[0091] In some embodiments, a mixture may exist between the capping layer 156 and the gate metal layer 154. In instances where the gate metal layer 154 is titanium nitride and the capping layer is silicon, a thin layer of SiTiN may be formed. Therefore, in some embodiments, a mixed layer of SiTiN exists between the gate metal layer 154 and the capping layer 156.

[0092] exist Figure 13A and Figure 13B In some embodiments, an adhesive layer 158 has been deposited on the capping layer 156. In some embodiments, the adhesive layer 158 is a gate metal layer comprising Ti, TiN, or another suitable conductive material. In some embodiments, the adhesive layer 158 comprises TiSiN. In some embodiments, the adhesive layer has a thickness between 4 nm and 10 nm. The adhesive layer can be deposited by ALD, CVD, or PVD. Other materials, thicknesses, and deposition processes may be utilized without departing from the scope of embodiments of this disclosure.

[0093] Figure 14A This is a cross-sectional view of an integrated circuit 100 corresponding to an X-cut according to some embodiments. Figure 14B This is a cross-sectional view of an integrated circuit 100 corresponding to a Y-cut according to some embodiments.

[0094] exist Figure 14A and Figure 14B In some embodiments, a gate metal layer 160 has been deposited on the adhesive layer 158. For example... Figure 14A As can be seen, the gate metal layer 160 fills the gaps between the gate spacer layers 120 above the channel 105. In some embodiments, the gate metal layer 160 is a gate fill material because it fills the remaining gaps between the gate spacer layers 120. In some embodiments, the gate metal layer 160 comprises tungsten. In some embodiments, the gate metal layer 160 comprises Cu, Ti, Au, Ru, Ta, or other suitable conductive materials. The gate metal layer 160 can be deposited by PVD, ALD, CVD, or another suitable deposition process.

[0095] Figure 15A This is a cross-sectional view of an integrated circuit 100 corresponding to an X-cut according to some embodiments. Figure 15B This is a cross-sectional view of an integrated circuit 100 corresponding to a Y-cut according to some embodiments.

[0096] exist Figure 15A and Figure 15B In this process, CMP technology has been implemented. After CMP technology is implemented, the top surface of the gate metal layer 160 is coplanar with the top surfaces of the adhesive layer 158, the capping layer 156, the gate metal layer 154, the gate metal layer 152, the gate metal layer 150, the gate spacer layer 120, the etch stop layer 140, and the interlayer dielectric layer 142.

[0097] exist Figure 15A and Figure 15BIn this process, the gate electrode 162 of transistor 101 is completed. The gate electrode 162 includes a gate metal layer 160, a binder layer 158, a capping layer 156, a gate metal layer 154, a gate metal layer 152, a gate metal layer 150, a gate spacer layer 120, an etch stop layer 140, and an interlayer dielectric layer 142.

[0098] Figure 16A This is a cross-sectional view of an integrated circuit 100 corresponding to an X-cut according to some embodiments. Figure 16B This is a cross-sectional view of an integrated circuit 100 corresponding to a Y-cut according to some embodiments.

[0099] exist Figure 16A and Figure 16B In some embodiments, an etching process has been performed to expose a portion of the top surface of the source / drain region 136. The etching process etches through portions of the interlayer dielectric layer 142 and the etch stop layer 140 to expose a portion of the top surface of the source / drain region 136. Although Figure 16A Not shown, but a recessed process is performed to recess the exposed portion of the top surface of the source / drain region 136. After the recessed process, a silicide layer 163 is formed in preparation for the formation of the source / drain contacts. The silicide layer 163 is a metal-containing layer. The formation of the silicide layer 163 may include: depositing a thin metal layer of Ti, Ni, Al, Ta, or other suitable metal; and performing a low-temperature thermal annealing process to form the silicide layer 163 from the metal layer. Therefore, the silicide layer 163 may include titanium silicide, nickel silicide, aluminum silicide, tantalum silicide, or other suitable silicides.

[0100] exist Figure 16A In this process, source / drain contacts 165 have been formed on the silicide layer 163. The source / drain contacts 165 are formed by depositing metal in trenches formed in the interlayer dielectric layer 142 and the etch stop layer 140. In some embodiments, the source / drain contacts 165 comprise tungsten. Optionally, the source / drain contacts 165 may comprise Ta, Ti, Al, Ru, Co, Au, or other suitable materials. In some embodiments, a pad layer of titanium nitride or tantalum nitride is formed on the silicide layer 163 and on the sidewalls of the trench before forming the source / drain contacts 165. The source / drain contacts 165 can be deposited using PVD, ALD, CVD, or other suitable deposition processes. After the source / drain contact 165 is formed, it is separated from the gate electrode 160 by an interlayer dielectric layer 142, an etch stop layer 140, a gate spacer layer 120, and a high-k gate dielectric layer 148. The source / drain contact 165 is separated from the gate spacer layer 120 by the first etch stop layer 140. After the source / drain contact 165 is formed, a CMP process is performed.

[0101] exist Figure 16A and Figure 16B In this embodiment, an etch stop layer 164 has been formed on the top surface of the interlayer dielectric layer 142, source / drain contact 165, gate spacer layer 120, etch stop layer 140, and gate electrode 162. According to some embodiments, an interlayer dielectric layer 166 has been formed on the etch stop layer 164. In some embodiments, the etch stop layer 164 comprises SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The etch stop layer 164 can be deposited by CVD, ALD, PVD, or other suitable deposition processes. In a particular example, the etch stop layer 164 comprises silicon nitride. In some embodiments, the etch stop layer 164 has a thickness between 3 nm and 6 nm, but other thicknesses may be used without departing from the scope of embodiments of this disclosure.

[0102] In some embodiments, the interlayer dielectric layer 166 may be referred to as ILD1. The interlayer dielectric layer 166 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The interlayer dielectric layer 166 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0103] exist Figure 16A and Figure 16B In the process, an etching process has been performed to expose the top surfaces of the source / drain contacts 165 and the gate electrode 162. The etching process forms trenches through the interlayer dielectric layer 166 and the etch stop layer 164 to expose the top surfaces of the source / drain contacts 165 and the gate electrode 162. After the etching process, conductive material is deposited to fill the trenches. The conductive material forms gate plugs or gate contacts 168 that contact and are electrically coupled to the gate metal layer 160 of the gate electrode 162. The conductive material forms conductive vias 169 that are electrically coupled to and contact the source / drain contacts 165. The conductive material may include Ta, Ti, Al, Ru, Co, Au, or other suitable materials. The conductive material may be deposited by PVD, CVD, ALD, or other suitable deposition processes. After forming the gate contact 168 and the conductive via 169, a CMP process is performed to planarize the top surface of the gate contact 168, the conductive via 169, and the interlayer dielectric layer 166. Figure 16A and Figure 16B In this process, the processing of transistor 101 is basically complete.

[0104] Although Figure 16A and Figure 16BNot shown, but in some embodiments, multiple interlayer dielectric layers are formed above interlayer dielectric layer 166. Multiple layers of metal lines and conductive vias are formed in the multiple interlayer dielectric layers to provide electrical contacts to the source / drain contacts 165 and gate contacts 168 of each transistor, and to enable a complex circuit arrangement consisting of multiple transistors 101.

[0105] Figure 17A This is a cross-sectional view of transistor 101 of integrated circuit 100 according to some embodiments. Figure 17A The substrate 102 and channel 105 are shown, as well as the interface gate dielectric layer 146 on the substrate 102 and channel 105 and the high-k gate dielectric layer 148 on the interface gate dielectric layer 146. Figure 17A Gate metal layers 150, 152, and 154, a capping layer 156, and an adhesive layer 158 are shown according to some embodiments. Dashed boxes marked 17B and 17C indicate... Figure 17B and Figure 17C The location of the enlarged cross-sectional view shown.

[0106] Figure 17B According to some embodiments Figure 17A An enlarged cross-sectional view of a portion of integrated circuit 100. Figure 17B An interface gate dielectric layer 146, a high-k gate dielectric layer 148, a gate metal layer 150, and a power-function gate metal layer 152 are shown according to some embodiments. Figure 17B This illustrates the migration of aluminum atoms from the work function gate metal layer 152 to the gate metal layer 150.

[0107] Figure 17C According to some embodiments Figure 17A An enlarged cross-sectional view of a portion of integrated circuit 100. Figure 17C The diagram illustrates an interface gate dielectric layer 146, a high-k gate dielectric layer 148, a gate metal layer 150, a power-function gate metal layer 152, a gate metal layer 154, a capping layer 156, and an adhesive layer 158, according to some embodiments. Figure 17C The diagram illustrates the migration of aluminum atoms from the power function gate metal layer 152 to the gate metal layer 150. As previously described, in some embodiments, aluminum atoms also migrate from the power function gate metal layer 152 to the gate metal layer 154. A shielding layer 156 inhibits the migration of aluminum atoms into the adhesive layer 158.

[0108] Figure 17D This is a cross-sectional view of transistor 101 of integrated circuit 100 according to some embodiments. Figure 17D The substrate 102 and channel 105 are shown, as well as the interface gate dielectric layer 146 on the substrate 102 and channel 105 and the high-k gate dielectric layer 148 on the interface gate dielectric layer 146. Figure 17DGate metal layers 150, 152, and 154, cover layer 156, and adhesive layer 158 are shown according to some embodiments. Figure 17D The top channel 105, according to some embodiments, has a width in the Y direction that is slightly smaller than that of the two lower channels 105.

[0109] Figure 17E This is a cross-sectional view of transistor 101 of integrated circuit 100 according to some embodiments. Figure 17E The substrate 102 and channel 105 are shown, as well as the interface gate dielectric layer 146 on the substrate 102 and channel 105 and the high-k gate dielectric layer 148 on the interface gate dielectric layer 146. Figure 17E Gate metal layers 150, 152, and 154, cover layer 156, and adhesive layer 158 are shown according to some embodiments. Figure 17D and Figure 17E The top surface of the top channel 105 is shown to be narrower in the Y direction than the top surfaces of the two lower channels. The sidewalls of the top channel 105 show a greater curvature than the sidewalls of the two lower channels.

[0110] Figure 17F According to some embodiments Figure 17E An enlarged cross-sectional view of a portion of integrated circuit 100. According to some embodiments, Figure 17F This includes numerical values ​​representing the combined thickness of gate metal layers 150, 152, and 154.

[0111] Figures 18 to 26B These are perspective and cross-sectional views illustrating the formation of transistors in a forked configuration according to some embodiments of an integrated circuit 100.

[0112] Figure 18 This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 18 The processing stages shown correspond in many ways to Figure 9A The processing stage shown has some variations. Channel 105 has already been formed over substrate 102. In the semiconductor stack (e.g., Figure 1 A gate protection layer 180 (corresponding to a mask layer) has been formed and patterned over the semiconductor stack 103 shown, such that a portion of the gate protection layer 180 is placed over the sacrificial semiconductor nanostructure (e.g., Figure 8 The sacrificial semiconductor nanostructure 107 shown is then located on top of the stacked material of the channel 105, as... Figure 18 As shown in the figure. In some embodiments, the gate protection layer 180 comprises a low-k dielectric material. In some embodiments, the gate protection layer 180 comprises SiOCN, SiCN, or another suitable dielectric material. The gate protection layer can be formed by an ALD process, but other deposition processes can be utilized without departing from the scope of embodiments of this disclosure. Figure 18 In this process, the sacrificial semiconductor nanostructure 107 has been removed. The use of the gate protection layer 180 can help reduce the capacitance of the transistor 101, and thus reduce the RC delay.

[0113] exist Figure 18 In Figure 18 An isolation wall structure 172 has been formed between the two stacks of the channel 105 shown. The wall structure 172 is formed above the isolation structure 112 between adjacent fins 108 before the removal of the sacrificial semiconductor nanostructure 107. The wall structure 172 includes a pad layer 174. The dielectric pad layer 174 is formed to be in direct contact with the sidewalls of the channel 105. In some embodiments, the pad layer 174 comprises silicon oxide, but other dielectric materials may be used without departing from the scope of embodiments of this disclosure. In some embodiments, the dielectric pad layer is formed using an ALD process, but other suitable deposition processes may be used without departing from the scope of embodiments of this disclosure.

[0114] According to some embodiments, the wall structure 172 includes a shell 176. The shell 176 is formed on the dielectric liner layer 174 and includes SiN, SiOCN, SICN, or another suitable dielectric material. The shell 176 can be formed by an ALD process, but other deposition processes can be used without departing from the scope of embodiments of this disclosure.

[0115] The wall structure 172 includes a core dielectric layer 178. The core dielectric layer 178 comprises SiN, SiOCN, SiCN, or another suitable dielectric material. The core dielectric layer 178 may be the same material as the dielectric shell 176 or a different material. In some embodiments, the core dielectric layer 178 is formed using an ALD process, but other deposition processes may be utilized without departing from the scope of embodiments of this disclosure.

[0116] In some embodiments, the wall structure 172 is formed after the gate metal is formed in the integrated circuit 100. A trench is formed through the gate metal.

[0117] Figure 19 This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 19In some embodiments, an etching process has been performed to trim the dielectric liner layer 174. In some embodiments, the etching process includes a wet etching process. After the etching process, residual dielectric structures 175 corresponding to the liner layer 174 exist between each channel 105 and the adjacent shells 176 of the wall structures 172. The dielectric structures have a wedge shape between the shells 176 and the channels 105. Specifically, the dielectric structures 175 are vertically thicker at locations adjacent to the shells 176 and vertically thinner at locations adjacent to the channels 105. In some embodiments, the exposed top and bottom surfaces of the dielectric structures 175 are curved.

[0118] Figure 19 A protective structure 184 is also shown above the trench isolation structure 112. The protective structure 184 includes dielectric layers 185 and 187. The isolation structure includes an additional dielectric layer 113, not shown in the previous figures. The additional dielectric layer 113 may include silicon oxide, silicon nitride, or other suitable dielectric materials. In some embodiments, dielectric layer 185 includes silicon oxide, but other materials may be used without departing from the scope of embodiments of this disclosure. In some embodiments, dielectric layer 187 includes SiN, SiOCN, SiON, SiCN, or other suitable dielectric materials. After a wet etching process, the top surface of dielectric layer 185 is recessed relative to the top surface of dielectric layer 187.

[0119] Figure 20 This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 20 In some embodiments, an interface gate dielectric layer 146 and a high-k gate dielectric layer 148 have been formed. The high-k gate dielectric layer may have the same composition as previously described. Figure 20 In the middle, the high-K gate dielectric layer 148 is lined with dielectric structure 175, sidewalls of wall structure 170 and gate protection layer 180.

[0120] Figure 21 The integrated circuit 100 according to some embodiments is in Figure 20 The cross-sectional view of the processing stage is shown. Figure 21 The location of a high-k gate dielectric layer 148, according to some embodiments, on the dielectric structure 175 and at least partially between the channel 105 and the wall structure 172 is also shown.

[0121] Figure 22 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 22In this process, gate metal layer 150 and power function gate metal layer 152 have been deposited using the materials and deposition processes previously described. Gate metals 150 and 152 are located between channels 105 due to the presence of dielectric structure 175. Gate metal 150 includes portions projecting downward and upward toward dielectric structure 175. According to some embodiments, gate metals 150 and 152 are formed around gate protective layer 180.

[0122] Figure 23 This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 23 In some embodiments, the gate metal layer 154, capping layer 156, adhesive layer 158, and gate metal layer 160 have been formed using the materials and processes previously described. A CMP process has been implemented.

[0123] Figure 23 The presence of dielectric layers 186, 188, 190, 194, and 195 according to some embodiments is also shown. According to some embodiments, dielectric layer 186 may include SiN, SiON, SiCN, SiOCN, SiOC, or other suitable dielectric materials. In some embodiments, dielectric layer 188 includes silicon oxide, but other materials may be used without departing from the scope of embodiments of this disclosure. In some embodiments, dielectric layer 190 includes SiN, SiCN, SiOCN, SiON, SiC, or other suitable dielectric materials. In some embodiments, dielectric layer 192 includes SiN, SiCN, SiOCN, SiON, SiC, or other suitable dielectric materials. In some embodiments, dielectric layer 194 includes silicon oxide, but other materials may be used without departing from the scope of embodiments of this disclosure. In some embodiments, dielectric layer 196 includes SiN, SiCN, SiOCN, SiON, SiC, or other suitable dielectric materials.

[0124] like Figure 23 As can be seen, the gate metal layer 160 fills the spacing between the stacks of the channel 105. Each stack of the channel 105 is defined on one side by a corresponding wall structure 172.

[0125] Figure 24 A cross-sectional view of a portion of an integrated circuit according to some embodiments is shown. Figure 24This more clearly illustrates why transistor 101 is described as having a fork configuration. The gate electrode 162, and specifically the gate metals 150 and 152, extend towards the wall structure 172 between channels 105 like the teeth of a fork without enclosing the other side of the channel 105. As previously described, the disadvantages associated with forming a functional gate metal layer directly on the high-k gate dielectric layer 152 are exacerbated in the fork configuration because the gate metal does not completely enclose the channel. Therefore, the beneficial reduction in resistivity provided by forming the gate metal layer 150 before forming the functional gate metal layer 152 is enhanced in the fork configuration.

[0126] Figure 25 This is an enlarged cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 25 In the middle, an interlayer dielectric layer 166 has already formed. Although Figure 25 Not shown, but according to some embodiments, the etch stop layer 164 is deposited before the interlayer dielectric layer 166. An etching process has been performed to expose the top surface of the gate metal layer 150 above the highest channel 105 and below the gate guard layer 180. The etching process forms a trench on the bottom surface of the gate guard layer 180 that extends through the interlayer dielectric layer 166, the etch stop layer (not shown), the gate guard layer 180, and the high-k gate dielectric layer 148. The gate metal layer 150 serves as an etch stop layer for the etching process. A gate contact 168 is formed in the trench, electrically coupled to and in contact with the gate metal layer 150. The gate contact 160 extends through the interlayer dielectric layer 166, the etch stop layer 164 (not shown), the gate guard layer 180, and the high-k gate dielectric layer 148 to contact the gate metal layer 150. According to some embodiments, the trench does not expose the function gate metal layer 152, and the gate contact 168 does not directly contact the function gate metal layer 152. Because the function gate metal layer 152 is not exposed during the formation of the gate contact 168, the function gate metal layer is not oxidized. This prevents or reduces threshold voltage shift.

[0127] Figure 26A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 26A The integrated circuit 100 includes a fork configuration substantially as previously described. A gate contact 168 contacts a gate metal layer 150. Current flows from the gate contact 168 through the top fork teeth and into the lower fork teeth. Due to the construction of the gate metal layers 150 and 152, the overall resistance of the gate electrode 162 is significantly reduced.

[0128] Figure 26B According to some embodiments Figure 26A An enlarged cross-sectional view of the portion of the integrated circuit 100 corresponding to the X-cut section. Figure 26BA portion of the top channel 105, interface gate dielectric layer 146, high-k gate dielectric layer 148, internal spacer 130, gate metal layer 150, gate metal layer 152, gate guard layer 180, and gate contact 168 are shown. According to some embodiments, the gate contact 168 extends through the gate guard layer 180 and the high-k gate dielectric layer 148 to contact the gate metal layer 150.

[0129] Figure 27A This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 27B According to some embodiments Figure 27B A cross-sectional view of integrated circuit 100. Figure 27C According to some embodiments Figure 27B An enlarged cross-sectional view of a portion of integrated circuit 100. Figure 27A and Figure 27B A FinFET utilizing gate metal 150 and power function gate metal 152 as previously described is shown.

[0130] Figure 27A The substrate 102, trench isolation structure 112, and semiconductor fin 108 are shown. Figure 27A The source / drain region 136, epitaxially grown from fin 108, is shown. Although Figure 27A Not shown in the diagram, but in some embodiments, the fin 108 is first recessed, and the source / drain region 136 is grown in the recess. An etch stop layer 140 and an interlayer dielectric layer 142 have been formed, as previously described. The gate spacer layer 120, the high-k gate dielectric layer 148, and the gate electrode 162 are... Figure 27A The diagram is shown in three-dimensional form. Each of these structures can be formed in a substantially similar manner and includes similar materials as previously described, but in a FinFET structure rather than in a full-ring gate or fork structure.

[0131] Figure 27B The cross-sectional view shows the channel region 105 of the FinFET in the upper portion of the fin 108. Figure 27B Also shown are an interface gate dielectric layer 146 on the surface of fin 108, a high-k gate dielectric layer 148 on the interface gate dielectric layer 146, a gate metal layer 150 on the surface of the high-k gate dielectric layer 148, a power-function gate metal layer 152 on the surface of the gate metal layer 150, a gate metal layer 154 on the gate metal layer 152, a capping layer 156 on the gate metal layer 154, an adhesive layer 158 on the capping layer 156, and a gate metal layer 160 on the adhesive layer 158. The formation of the gate metal layer 150 and gate metal layer 152 as previously described provides the previously described benefits for FinFET.

[0132] Forming the functional gate metal layer 152 in situ with the gate metal layer 150 without disrupting the vacuum provides several benefits for FinFETs. The first benefit is minimal or no oxidation of the first gate metal layer, as the wafer is not exposed to oxygen between the formation of the first gate metal layer 150 and the functional gate metal layer 152. Aluminum nucleation on the first gate metal layer 150 is highly efficient during the ALD process used for the functional gate metal layer 152. Aluminum atoms can efficiently diffuse into both the first gate metal layer 150 and the gate metal layer 154, migrating laterally and vertically. This helps ensure a low threshold voltage for the transistor. Furthermore, the reduced threshold voltage and its variation result in a more concentrated threshold voltage distribution in the NFET, improving stability and device yield. The resistivity of the first gate metal layer 150, compared to the resistivity of the functional gate metal layer 152, provides a lower overall resistance of the gate electrode, resulting in better electrical performance, including higher switching speeds and lower power consumption.

[0133] Figure 27C Enlarged views of the high-k gate dielectric layer 148, gate metal layer 150, work-function gate metal layer 152, and gate metal layer 154 are shown. Aluminum atoms can migrate or diffuse from gate metal layer 152 into gate metal layers 150 and 154.

[0134] Figure 28 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. The integrated circuit 100 shows a first transistor 101a and a second transistor 101b. In some embodiments, the first transistor 101a is an NFET including a channel 105a, and the second transistor 101b is a PFET including a channel 105b. Transistors 101a / 101b include an interface gate dielectric layer 146a / 146b and a high-k gate dielectric layer 148a / 148b. The high-k gate dielectric layer 148a / 148b is formed in the same deposition step.

[0135] In some embodiments, transistor 101a corresponds to Figure 16A and Figure 16B The transistor 101a includes a first gate metal layer 150, a power function gate metal layer 152, a gate metal layer 154, a capping layer 156, a binder layer 158, and a gate fill layer 160, as previously described.

[0136] In some embodiments, transistor 101 includes a gate metal layer 151. In some embodiments, gate metal layer 151 is a work-function gate metal layer for PFET 101b. Gate metal layer 151 comprises titanium nitride, but other suitable materials may be used without departing from the scope of embodiments of this disclosure. In some embodiments, gate metal layer 151 is the same material as gate metal layer 150, except that it contains no aluminum or a very small amount of aluminum. Therefore, gate metal layer 150 has a higher aluminum concentration than gate metal layer 151 (in some embodiments, gate metal layer 151 contains no aluminum at all). While aluminum is advantageous as a work-function gate metal layer for NFETs, it is not advantageous for PFETs in some embodiments. Therefore, in some embodiments, processing steps are selected to ensure that the gate electrode 162b of PFET 101b contains very little or no aluminum.

[0137] In some embodiments, the gate metal layer 150 and the power function gate metal layer 152 are initially formed on channels 105a and 105b in the same process step. After the formation of the gate metal layer 150 and the power function gate metal layer 152, a mask is formed and patterned such that the mask covers transistor 101a and exposes transistor 101b. An etching process is then performed in the presence of the mask to remove the gate metal layer 150 and the power function gate metal layer 152 from transistor 101b. This exposes the high-k gate dielectric layer 148b. In some embodiments, a gate metal layer 151 is subsequently deposited on the high-k gate dielectric layer 148b.

[0138] In some embodiments, gate metal layer 151 is made of the same material as gate metal layer 154. In some embodiments, gate metal layer 151 is formed in the same deposition process as gate metal layer 154. Therefore, in some embodiments, after removing gate metal layer 150 and power function gate metal layer 152 from transistor 101b, the mask described above is then removed from transistor 101a. Then, gate metal layer 154 is deposited on power function gate metal layer 152 at transistor 101a and on high-k gate dielectric layer 148b at transistor 101b, serving as gate metal layer 151.

[0139] In some embodiments, layer 153 is formed on gate metal layer 151 at transistor 101b. In some embodiments, layer 153 is the same material as capping layer 156 and is formed in the same deposition process as capping layer 156. In some embodiments, layer 153 is a different material from capping layer 156. In some embodiments, layer 153 includes one or more of TiN, TaN, W, Co, or other suitable materials.

[0140] In some embodiments, layer 155 is formed on layer 153 at transistor 101b. In some embodiments, layer 155 is the same material as adhesive layer 158 and is formed in the same deposition process as adhesive layer 158. In some embodiments, layer 155 is a different material from adhesive layer 158. In some embodiments, layer 155 includes one or more of TiN, TaN, W, Co, or other suitable materials.

[0141] In some embodiments, a gate fill layer 159 is formed on layer 155 at transistor 101b. In some embodiments, layer 159 is the same material as gate fill layer 160 and is formed in the same deposition process as gate fill layer 160. In some embodiments, layer 159 is a different material from gate fill layer 160. In some embodiments, layer 159 includes one or more of W, TiN, TaN, Co, Ru, or other suitable materials.

[0142] In some embodiments, a patterned mask is formed and patterned prior to the deposition of gate metal 150. The patterned mask covers transistor 101b and exposes transistor 101a. Then, gate metal layer 150 and power-function gate metal layer 152 are deposited at transistor 101a, as previously described. Due to the presence of the mask, gate metal layers 150 and 152 are not formed around the channel 105b of transistor 101b. Subsequently, the mask is removed, and gate metal layer 151 is formed around the channel 105b. In some embodiments, gate metal layer 151 is formed in the same deposition step as gate metal layer 154.

[0143] In some embodiments, transistor 101b has a similarity to... Figure 28 The different gate layer combinations shown are illustrated. According to some embodiments, transistor 101b may include […]. Figure 28 The diagram shows a comparison of more gate layers, fewer gate layers, or different combinations of gate layers.

[0144] Figure 29 This is a flowchart of a method 2900 for forming an integrated circuit according to some embodiments. Method 2900 can utilize information regarding... Figures 1 to 28 The described structure, process, and system. In 2902, method 2900 includes: forming a first region including a first active region and a first fin base region. In 2904, method 2900 includes: forming a second region including a second active region and a second fin base region. An example of the first active region and the second active region is... Figure 2A The active regions A1 and A2. An example of the fin base region is... Figure 2AThe fin base region 109. In 2906, method 2900 includes: depositing an isolation structure between the first fin base region and the second fin base region, wherein the isolation structure is boundaryd with the sidewalls of the first fin base region and the sidewalls of the second fin base region. An example of the isolation structure is... Figure 2A The isolation structure 112. In 2908, method 2900 includes defining a plurality of stacked first channels of a first transistor extending in a first lateral direction by forming source / drain trenches in a first active region. An example of the first channel is... Figure 4 The channel 105. In 2910, method 2900 includes: growing a first source / drain region of a first transistor in a source / drain trench, the first source / drain region being coupled to a first channel and having a width larger than the channel in a second lateral direction, such that a portion of the first source / drain region is suspended above an isolation structure. An example of the first source / drain region is... Figure 7A The source / drain region 136. In 2912, method 2900 includes: depositing an etch stop layer over the source / drain region and the isolation structure. An example of an etch stop layer is... Figure 8 The etch stop layer 140. In 2914, method 2900 includes: depositing an interlayer dielectric layer on the etch stop layer. An example of an interlayer dielectric layer is... Figure 8 Interlayer dielectric layer 142. In 2916, method 2900 includes: forming an interface gate dielectric layer on the channel. In 2918, method 2900 includes: forming a high-k gate dielectric layer on the interface gate dielectric layer. An example of an interface gate dielectric layer is... Figure 10A The interface gate dielectric layer is 146. An example of a high-k gate dielectric layer is... Figure 10A A high-k gate dielectric layer 146. In 2920, method 2900 includes: depositing a first gate metal layer for the gate electrode on the high-k gate dielectric layer. An example of the first gate metal layer is... Figure 11A The gate metal layer 150. In 2922, method 2900 includes: depositing a second gate metal layer in situ on the first gate metal layer between the first channels, the second gate metal layer having a higher resistivity than the first gate metal layer and corresponding to the work function gate metal of the transistor. An example of the second gate metal layer is... Figure 12A The gate metal layer 152.

[0145] Figure 30 This is a flowchart of a method 3000 for forming an integrated circuit according to some embodiments. Method 3000 can utilize... Figures 1 to 28The described structures, processes, and systems. In method 3002, method 3000 includes forming a semiconductor fin extending in a first direction. In method 3004, method 3000 includes forming an isolation structure adjacent to the semiconductor fin. An example of a semiconductor fin is... Figure 2A The semiconductor fin 108. An example of an isolation structure is... Figure 2A The isolation structure 112. In 3006, method 3000 includes: depositing a gate spacer layer over the semiconductor fin and the isolation structure. An example of the gate spacer layer is... Figure 3A The gate spacer layer 120. In 3008, method 3000 includes defining a plurality of stacked channels of transistors beneath the gate spacer layer by forming source / drain trenches in semiconductor fins. An example of a source / drain trench is... Figure 4 The source / drain trench is 124. An example of a channel is... Figure 4 The channel 105. In 3010, method 3000 includes: forming a plurality of internal spacers intersecting with the channel. An example of the internal spacers is... Figure 5 The internal spacer 130. In 3012, method 3000 includes: after forming the internal spacer, growing a source / drain region in the source / drain trench. An example of the source / drain region is... Figure 6 The source / drain region 136. In 3014, method 3000 includes: depositing a gate dielectric layer on the channel, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer layer. An example of a gate dielectric layer is... Figure 10A A high-k gate dielectric layer 148. In 3016, method 3000 includes: depositing a first gate metal layer on the gate dielectric layer between channels. An example of the first gate metal layer is... Figure 11A The gate metal layer 150. In 3018, method 3000 includes: forming a second gate metal layer on the first gate metal layer, wherein the aluminum concentration in the first gate metal layer is higher after the formation of the second gate metal layer than before the formation of the second gate metal layer. An example of the second gate metal layer is... Figure 12A The gate metal layer 152. In 3020, method 3000 includes: depositing an interlayer dielectric layer over the source / drain regions. An example of an interlayer dielectric layer is... Figure 8 The interlayer dielectric layer 142. In 3022, method 3000 includes: forming a source / drain contact extending through the interlayer dielectric layer to be electrically coupled to a source / drain region, wherein the source / drain contact is spaced apart from the source / drain region by a metal-containing layer having a composition different from that of the source / drain contact. An example of the source / drain contact is... Figure 16A The source / drain contact 165. An example containing a metal layer is... Figure 16A The silicide layer 163.

[0146] Embodiments of this disclosure provide a method for forming a transistor with low gate resistance and low threshold voltage. The gate electrode of the transistor includes depositing a function metal after depositing a first metal layer having a resistivity lower than that of the function metal. The function gate metal layer is formed in situ with the formation of the first gate metal layer without breaking the vacuum. This helps ensure that the first gate metal is not oxidized during the deposition of the function metal. Nucleation of metal atoms from the function gate metal layer is better on the first gate metal layer than on the gate dielectric layer, and metal atoms can efficiently diffuse into the first gate metal layer and migrate laterally and vertically. The in-situ formation of the function metal with the first gate metal layer provides a gate electrode with lower resistance, thereby reducing the overall gate resistance and improving electrical performance. The threshold voltage is low and there are no undesirable variations. Because the first gate metal layer suffers little or no oxidation, a uniform function metal can be formed even within the limited spacing between channels. All of these result in transistors with improved electrical characteristics, integrated circuits in which transistors are formed with better functionality, and improved wafer yield.

[0147] In some embodiments, the method includes: forming a first region including a first active region and a first fin substrate region; forming a second region including a second active region and a second fin substrate region; and depositing an isolation structure between the first fin substrate region and the second fin substrate region. The isolation structure is adjacent to the sidewalls of the first fin substrate region and the sidewalls of the second fin substrate region. The method includes: defining a plurality of stacked first channels of a first transistor extending in a first lateral direction by forming source / drain trenches in the first active region; and growing a first source / drain region of the first transistor in the source / drain trenches, the first source / drain region being coupled to the first channel and having a width larger than the channel in a second lateral direction, such that a portion of the first source / drain region is suspended above the isolation structure. The method includes: depositing an etch stop layer over the source / drain region and the isolation structure; depositing an interlayer dielectric layer on the etch stop layer; forming an interface gate dielectric layer on the channel; and forming a high-k gate dielectric layer on the interface gate dielectric layer. The method includes: depositing a first gate metal layer of a gate electrode on a high-k gate dielectric layer; and depositing a second gate metal layer in situ on the first gate metal layer between first channels, the second gate metal layer having a higher resistivity than the first gate metal layer and corresponding to the power function gate metal of the transistor.

[0148] In some embodiments, the method includes: forming a semiconductor fin extending in a first direction; forming an isolation structure adjacent to the semiconductor fin; and depositing a gate spacer layer over the semiconductor fin and the isolation structure. The method includes: defining a plurality of stacked channels of a transistor below the gate spacer layer by forming source / drain trenches in the semiconductor fin; forming a plurality of internal spacers interleaved with the channels; and growing source / drain regions in the source / drain trenches after forming the internal spacers. The method includes: depositing a gate dielectric layer on the channels. The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer layer. The method includes: depositing a first gate metal layer on the gate dielectric layer between the channels; and forming a second gate metal layer on the first gate metal layer between the channels. The aluminum concentration in the first gate metal layer is higher after the formation of the second gate metal layer than before the formation of the second gate metal layer. The method includes: depositing an interlayer dielectric layer over the source / drain regions; and forming source / drain contacts extending through the interlayer dielectric layer to be electrically coupled to the source / drain regions. The source / drain contacts are separated from the source / drain regions by a metal-containing layer having a composition different from that of the source / drain contacts.

[0149] In some embodiments, the integrated circuit includes an N-type transistor, the N-type transistor including: a plurality of stacked first channels; an interface gate dielectric layer on the stacked first channels; and a high-k gate dielectric layer on the interface gate dielectric layer. The transistor includes source / drain regions coupled to the channels and a gate electrode. The gate electrode includes: a first gate metal on a high-k gate dielectric between the first channels; and a second gate metal on a first gate metal layer between the channels. The first gate metal has a gradient aluminum concentration that increases with distance from the high-k gate dielectric layer. The integrated circuit includes: a gate spacer layer adjacent to the gate electrode; a first etch stop layer disposed above the source / drain regions; a first interlayer dielectric layer disposed above the first etch stop layer; and source / drain contacts extending through the first interlayer dielectric layer to be electrically coupled to the source / drain regions. The conductivity of the source / drain contacts is greater than the conductivity of the source / drain regions. The source / drain contacts are separated from the gate spacer layer by the first etch stop layer. The integrated circuit includes: a second etch stop layer located above the gate spacer layer; and a second interlayer dielectric layer located above the second etch stop layer, wherein the source / drain contacts are spaced apart from the gate metal through the gate spacer layer and the first etch stop layer.

[0150] Some embodiments of this application provide a method for forming an integrated circuit, comprising: forming a first region including a first active region and a first fin substrate region; forming a second region including a second active region and a second fin substrate region; depositing an isolation structure between the first fin substrate region and the second fin substrate region, wherein the isolation structure is adjacent to the sidewalls of the first fin substrate region and the sidewalls of the second fin substrate region; defining a plurality of stacked first channels of a first transistor extending in a first lateral direction by forming source / drain trenches in the first active region; growing a first source / drain region of the first transistor in the source / drain trenches, the first source / drain region being coupled to the first channel. The channel has a width greater than the channel in the second lateral direction, such that a portion of the first source / drain region is suspended above the isolation structure; an etch stop layer is deposited over the source / drain region and the isolation structure; an interlayer dielectric layer is deposited on the etch stop layer; an interface gate dielectric layer is formed on the channel; a high-k gate dielectric layer is formed on the interface gate dielectric layer; a first gate metal layer of the gate electrode is deposited on the high-k gate dielectric layer; and a second gate metal layer is deposited in situ on the first gate metal layer between the first channels, the second gate metal layer having a higher resistivity than the first gate metal layer and corresponding to the work function gate metal of the transistor.

[0151] In some embodiments, the first transistor is an NFET, and the second gate metal layer is one of titanium aluminum or tantalum aluminum. In some embodiments, the method further includes diffusing aluminum atoms into the first gate metal layer by depositing the second gate metal layer. In some embodiments, after depositing the second gate metal layer, the first gate metal layer has an aluminum atom percentage greater than 5%. In some embodiments, the aluminum concentration in the first gate metal layer increases with distance from the high-k gate dielectric layer. In some embodiments, the first gate metal layer is titanium nitride. In some embodiments, the method further includes: depositing the first gate metal layer using a first atomic layer deposition process; and depositing the second gate metal layer using a second atomic layer deposition process. In some embodiments, the method further includes forming a third gate metal layer having the same material as the first gate metal layer on the second gate metal layer. In some embodiments, the method further includes forming a semiconductor capping layer on the third gate metal layer. In some embodiments, the method further includes: forming a plurality of stacked second channels having a second transistor having a different conductivity type than the first transistor; forming an interface gate dielectric layer on the second channels; forming a high-k gate dielectric layer on the interface gate dielectric layer on the second channels; and depositing a third gate metal layer on the high-k gate dielectric layer on the second channels, wherein the third gate metal layer has the same material as the first gate metal layer, wherein the first gate metal layer has a higher aluminum concentration than the third gate metal layer. In some embodiments, the method further includes forming the third gate metal layer in a deposition step different from that of the first gate metal layer. In some embodiments, the method further includes forming the third gate metal layer on the second gate metal layer.

[0152] Other embodiments of this application provide a method for forming an integrated circuit, comprising: forming a semiconductor fin extending in a first direction; forming an isolation structure adjacent to the semiconductor fin; depositing a gate spacer layer over the semiconductor fin and the isolation structure; defining a plurality of stacked channels of transistors below the gate spacer layer by forming source / drain trenches in the semiconductor fin; growing source / drain regions in the source / drain trenches; depositing a gate dielectric layer on the channels, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer layer; and depositing the gate dielectric layer between the channels. A first gate metal layer is deposited on the gate dielectric layer; a second gate metal layer is formed on the first gate metal layer between the channels, wherein the aluminum concentration in the first gate metal layer is higher after the formation of the second gate metal layer than before the formation of the second gate metal layer; an interlayer dielectric layer is deposited over the source / drain regions; and a source / drain contact is formed extending through the interlayer dielectric layer to be electrically coupled to the source / drain regions, wherein the source / drain contact is spaced apart from the source / drain regions by a metal-containing layer having a composition different from that of the source / drain contact.

[0153] In some embodiments, the method further includes forming the second gate metal in situ with the first gate metal without breaking the vacuum. In some embodiments, the method further includes forming a gate contact extending through the second gate metal layer to contact the first gate metal layer, wherein the first gate metal layer is an etch stop layer, and wherein the transistor is a forklift transistor. In some embodiments, the method further includes: forming a plurality of internal spacers interleaved with the channel; and after forming the plurality of internal spacers, growing the source / drain regions in the source / drain trench. In some embodiments, the second gate metal includes aluminum, carbon, and any one of tantalum or titanium.

[0154] Some embodiments of this application provide an integrated circuit, including: an N-type transistor comprising: a plurality of stacked first channels; an interface gate dielectric layer located on the stacked first channels; a high-k gate dielectric layer located on the interface gate dielectric layer; a source / drain region coupled to the channels; a gate electrode comprising: a first gate metal located on the high-k gate dielectric between the first channels, and a second gate metal located on the first gate metal layer between the channels, wherein the first gate metal has a gradient aluminum concentration that increases with distance from the high-k gate dielectric layer; a gate spacer layer adjacent to the gate electrode; and a first etch. A stop layer is disposed above the source / drain region; a first interlayer dielectric layer is disposed above the first etch stop layer; a source / drain contact extends through the first interlayer dielectric layer to be electrically coupled to the source / drain region, wherein the conductivity of the source / drain contact is greater than the conductivity of the source / drain region, wherein the source / drain contact is separated from the gate spacer layer by the first etch stop layer; a second etch stop layer is located above the gate spacer layer; and a second interlayer dielectric layer is located above the second etch stop layer, wherein the source / drain contact is spaced from the gate metal by the gate spacer layer and the first etch stop layer.

[0155] In some embodiments, the integrated circuit further includes a P-type transistor comprising: a plurality of stacked second channels; a high-k gate dielectric layer; and a second gate electrode including a third gate metal layer on the high-k gate dielectric between the second channels, wherein the third gate metal layer and the first gate metal layer comprise titanium nitride, and wherein the aluminum concentration in the third gate metal is lower than the aluminum concentration in the first gate metal layer. In some embodiments, the integrated circuit further includes a gate contact extending through the second gate metal layer to contact the first gate metal layer.

[0156] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming an integrated circuit, comprising: A first region is formed, comprising a first active region and a first fin base region; A second region is formed, comprising a second active region and a second fin base region; An isolation structure is deposited between the first fin base region and the second fin base region, wherein the isolation structure is in contact with the sidewalls of the first fin base region and the sidewalls of the second fin base region; A plurality of stacked first channels of a first transistor extending in a first lateral direction are defined by forming source / drain trenches in the first active region; A first source / drain region of the first transistor is grown in the source / drain trench. The first source / drain region is coupled to the first channel and has a width greater than that of the channel in the second lateral direction, such that a portion of the first source / drain region is suspended above the isolation structure. An etch stop layer is deposited over the source / drain region and the isolation structure; An interlayer dielectric layer is deposited on the etch stop layer; An interface gate dielectric layer is formed on the channel; A high-k gate dielectric layer is formed on the interface gate dielectric layer; A first gate metal layer for the gate electrode is deposited on the high-k gate dielectric layer; and A second gate metal layer is deposited in situ on the first gate metal layer between the first channels, the second gate metal layer having a higher resistivity than the first gate metal layer and corresponding to the power function gate metal of the transistor.

2. The method according to claim 1, wherein, The first transistor is an NFET, and the second gate metal layer is either titanium aluminum or tantalum aluminum.

3. The method of claim 2, further comprising diffusing aluminum atoms into the first gate metal layer by depositing the second gate metal layer.

4. The method according to claim 3, wherein, After the second gate metal layer is deposited, the first gate metal layer has a greater than 5% percentage of aluminum atoms.

5. The method according to claim 3, wherein, The aluminum concentration in the first gate metal layer increases with the distance from the high-k gate dielectric layer.

6. The method according to claim 2, wherein, The first gate metal layer is titanium nitride.

7. The method according to claim 2, further comprising: The first gate metal layer is deposited using a first atomic layer deposition process; as well as The second gate metal is deposited using a second atomic layer deposition process.

8. The method of claim 7, further comprising forming a third gate metal layer having the same material as the first gate metal layer on the second gate metal layer.

9. A method for forming an integrated circuit, comprising: Semiconductor fins are formed extending in the first direction; An isolation structure is formed next to the semiconductor fin; A gate spacer layer is deposited over the semiconductor fin and the isolation structure; Multiple stacked channels of transistors are defined beneath the gate spacer layer by forming source / drain trenches in the semiconductor fins; Source / drain regions are grown in the source / drain trench; A gate dielectric layer is deposited on the channel, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer layer; A first gate metal layer is deposited on the gate dielectric layer between the channels; A second gate metal layer is formed on the first gate metal layer between the channels, wherein the aluminum concentration in the first gate metal layer is higher after the formation of the second gate metal layer than before the formation of the second gate metal layer; An interlayer dielectric layer is deposited above the source / drain regions; and A source / drain contact is formed extending through the interlayer dielectric layer to be electrically coupled to the source / drain region, wherein the source / drain contact is spaced apart from the source / drain region by a metal-containing layer having a composition different from that of the source / drain contact.

10. An integrated circuit, comprising: An N-type transistor includes: a plurality of stacked first channels; an interface gate dielectric layer located on the stacked first channels; a high-k gate dielectric layer located on the interface gate dielectric layer; source / drain regions coupled to the channels; and a gate electrode including: a first gate metal located on the high-k gate dielectric between the first channels, and a second gate metal located on the first gate metal layer between the channels, wherein the first gate metal has a gradient aluminum concentration that increases with distance from the high-k gate dielectric layer; and a gate spacer layer adjacent to the gate electrode. A first etch stop layer is disposed above the source / drain region; The first interlayer dielectric layer is disposed above the first etch stop layer; A source / drain contact extends through the first interlayer dielectric layer to be electrically coupled to the source / drain region, wherein the conductivity of the source / drain contact is greater than the conductivity of the source / drain region, and wherein the source / drain contact is separated from the gate spacer layer by the first etch stop layer. A second etch stop layer is located above the gate spacer layer; and The second interlayer dielectric layer is located above the second etch stop layer, wherein the source / drain contacts are spaced apart from the gate metal by the gate spacer layer and the first etch stop layer.

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