Gallium nitride device with local charge regulation type anti-single event burnout and preparation method thereof

Abstract

The application discloses a local charge regulation type anti-single-particle burnout gallium nitride device and a preparation method thereof. The device comprises, from bottom to top, a substrate layer, a nucleation layer, a buffer layer, a polar hole management layer, a spacer layer and a channel layer which are stacked in sequence; a barrier layer located in the middle region of the upper surface of the channel layer; a source electrode located on one side of the barrier layer and a drain electrode located on the other side; a gate cap layer and a gate electrode located above the barrier layer; a passivation layer covering the upper surface of the barrier layer; a source step field plate located above the passivation layer and the source electrode and electrically connected with the source electrode, wherein the field plate comprises two or more step edges; at least one step edge is aligned with the center position of at least one buried island in the source-drain direction; the polar hole management layer comprises a plurality of local polar hole regulation units arranged in segments in the source-drain direction; each unit comprises a buried island and a polarization cap layer arranged on the buried island, and the rapid capture and removal of radiation-induced holes in the whole range of the gate-drain drift region are realized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a locally charge-controlled gallium nitride device resistant to single-event burn-out and its fabrication method. Background Technology

[0002] p-GaN (gallium nitride) gate-enhanced AlGaN (aluminum gallium nitride) / GaN high electron mobility transistors (HEMTs) are widely used in aerospace power systems due to their normally-off characteristics, high breakdown voltage, and good thermal conductivity. However, these devices are susceptible to single-event burn-out (SEB) in the space radiation environment: high-energy heavy ions incident on the gate-drain drift region generate electron-hole pairs. Electrons are rapidly drawn away by the drain electric field, while holes, due to the low mobility in GaN (approximately 10-30 cm² / Vs) and the reverse bias of the p-GaN / AlGaN / GaN pin junction, accumulate below the gate-drain edge, leading to localized electric field enhancement, impact ionization avalanche, and ultimately thermal burn-out. Therefore, SEB-resistant design cannot only consider the static breakdown voltage; it must simultaneously address the electric field distribution and transient charge distribution.

[0003] The existing approaches can be divided into three directions: GaN HEMT anti-single-particle burn-off structure design, application of polarization-induced hole transport layer in GaN devices, and fundamental research on polarization-induced 2DHG (two-dimensional hole gas).

[0004] In the design of GaN HEMT structures resistant to single-event burn-out, the following existing solutions are included: (1) Segmented gate metal scheme with source connection: In this scheme, the p-GaN gate metal is segmented, and part of the metal finger disconnects the gate connection and is connected to the source through the field plate interconnect layer. The metal connected to the source directly contacts the AlGaN barrier layer, providing a channel for the accumulated holes generated by radiation to be discharged to the source through the p-GaN / AlGaN / GaN path. Experimental results show that the SEB threshold voltage is increased from 217V in the conventional structure to 558V (linear energy transfer of about 76 MeV·cm² / mg).

[0005] (2) Hybrid source deep trench scheme, in which a deep trench is etched in the source region, a second source metal is deposited deep into the semiconductor layer (through the barrier layer into the buffer layer), and a metal-semiconductor Schottky contact is formed on the sidewall and bottom. Holes generated by radiation are directly extracted by the source through this low-resistance path.

[0006] (3) Buffer layer PN junction scheme, which proposes to introduce a PN junction connected to the drain in the p-GaN gate HEMT buffer layer to block the vertical transport path of carriers generated by radiation.

[0007] (4) MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) Separated Gate and P-Well Buffer Layer Anti-SEB Scheme: This scheme proposes to improve the traditional polysilicon gate into a separated gate structure, introduce a P-well buffer layer below the P-well region, and introduce an N-type doped slowly varying region between the N+ substrate and the N- drift region. The P-well buffer layer accelerates the extraction of transient holes generated by radiated particles, suppressing parasitic transistor turn-on. This scheme is for Si (silicon)-based MOSFETs and is not applicable to GaN HEMT material systems.

[0008] (5) P-type polysilicon source MIS (metal-insulator-semiconductor structure) barrier anti-SEB scheme: This scheme introduces a P-type polysilicon source into the power device and applies an MIS barrier to the device surface to adjust the surface electric field, causing most of the holes to drift to the trench source surface and flow to the heavily doped P-type region, thus avoiding hole accumulation at the gate and inducing gate breakdown. This is also applicable to Si-based power devices.

[0009] (6) Dual-field plate SEB hardening scheme: This scheme proposes to improve the SEB threshold in enhancement-mode GaN HEMTs by using a dual-field plate (gate-connected field plate + source-connected field plate). The dual-field plate reduces the peak electric field at the gate edge by redistributing the electric field between the gate and drain, thereby reducing the collisional ionization rate after heavy ion incident. This scheme only reduces the amount of carriers generated by electric field modulation, and does not solve the problem of collecting and expelling the generated holes.

[0010] In the application of polarization-induced hole transport layers in GaN devices, the following existing solutions are included: (7) Radiation-resistant GaN logic circuit with AlGaN polarization-induced hole transport layer: This scheme proposes a radiation-resistant GaN logic circuit structure, comprising a substrate layer, an AlN nucleation layer, a GaN buffer layer, an AlGaN polarization-induced hole transport layer, a GaN channel layer, and a barrier layer. The device incorporates a deep trench electrode on the HEMT side and a deep trench electrode on the resistor side, which are bridged to prevent hole accumulation at the bottom of the active region, mitigating threshold drift and 2DEG (two-dimensional electron gas) resistance fluctuations caused by the back-gate effect. This scheme is the closest prior art to this invention.

[0011] (8) GaN / AlN (aluminum nitride) double heterojunction 2DEG and 2DHG dual-channel ultraviolet detector. This scheme utilizes the AlGaN / GaN double heterojunction to simultaneously form 2DEG and 2DHG channels, providing independent transport paths for photogenerated electrons and holes. The back gate's band tilt is controlled by the combined action of an applied electric field and a polarization field. This scheme is used in ultraviolet detectors and non-power device radiation-hardening applications.

[0012] Within the field of fundamental research on polarization-induced 2DHG, the following existing schemes are included: (9) The polarization-induced 2DHG scheme for GaN / AlN heterojunctions proposes to realize polarization-induced two-dimensional hole gas in undoped GaN / AlN quantum wells, with an areal density of 5×10¹³ cm⁻¹. - ², the hole mobility is approximately 26 cm² / Vs at room temperature (limited by interface scattering), and can reach several hundred cm² / Vs at low temperatures. Subsequently, in 2021, the conductivity of 2DHG was further improved by introducing an impurity blocking layer.

[0013] (10) In the single-event effect study of p-channel GaN / AlN HEMT, a single-event effect TCAD simulation study of the recess gate GaN / AlN p-channel HEMT was carried out. The results showed that the device is most sensitive to heavy ion incident in the gate-drain access region, and the transient leakage current increases with the linear energy transfer of LET. This study is the first to associate 2DHG channel devices with radiation effects, but its purpose is to evaluate the radiation vulnerability of p-channel HEMT itself, rather than to use 2DHG as a radiation hardening method.

[0014] However, existing single-event burn-off prevention schemes for enhanced GaN HEMTs cannot achieve rapid capture and removal of radiation-induced holes across the entire gate-drain drift region without changing the core device structure or increasing process complexity. Therefore, the risk of single-event burn-off still exists in high-voltage power applications. Summary of the Invention

[0015] To address the aforementioned problems in the prior art, this invention provides a locally charge-controlled gallium nitride device resistant to single-event burn-out and its fabrication method.

[0016] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a locally charge-controlled gallium nitride device resistant to single-event burn-out, the device comprising: The substrate layer, nucleation layer, buffer layer, polarized hole management layer, spacer layer, and channel layer are stacked sequentially from bottom to top. The polarized hole management layer includes multiple localized polarized hole control units arranged in segments along the source-drain direction; each localized polarized hole control unit includes a buried island and a polarization cap layer disposed on the buried island. A barrier layer located in the middle region of the upper surface of the channel layer; The source electrode is located on one side of the barrier layer and the drain electrode is located on the other side of the barrier layer; A gate cap layer and a gate are sequentially located above the barrier layer; A passivation layer covering the upper surface of the barrier layer; A source electrode stepped field plate is located above the passivation layer and the source electrode; the source electrode stepped field plate includes two or more stepped edges; at least one stepped edge is aligned with the center position of at least one buried island along the source-drain direction; the source electrode stepped field plate is electrically connected to the source electrode.

[0017] Secondly, the present invention provides a method for fabricating a locally charge-controlled gallium nitride device resistant to single-event burn-out, the method comprising: A core layer and a buffer layer are grown sequentially from bottom to top on the substrate. An initial embedded island layer and an initial polarization cap layer are epitaxially grown on the buffer layer; The initial buried island layer and the initial polarization cap layer are patterned into a segmented island structure arranged along the source-drain direction by photolithography and dry etching, and multiple local polarization hole control units are formed by etching downward; each local polarization hole control unit includes a buried island and a polarization cap layer disposed on the buried island. A spacer layer, a channel layer, and an initial barrier layer are sequentially grown in the buffer layer and the plurality of localized polarization hole control units. An epitaxial gate cap layer is grown on top of the initial barrier layer; A passivation layer is deposited on the surfaces of the initial barrier layer and the gate cap layer; The passivation layer is etched downwards from its upper surface to form a gate opening above the gate cap layer. Both sides of the initial barrier layer are etched away to obtain a barrier layer, and source and drain openings are formed on both sides of the barrier layer. A source is formed in the source opening, a drain is formed in the drain opening, and a gate is formed in the gate opening. A source electrode stepped field plate is fabricated on the passivation layer and the source electrode; the source electrode stepped field plate includes two or more stepped edges; at least one stepped edge is aligned with the center position of at least one buried island along the source-drain direction; the source electrode stepped field plate is electrically connected to the source electrode.

[0018] This invention provides a locally charged, charge-controlled, single-particle burn-off-resistant gallium nitride (GaN) device. The polarized hole management layer employs multiple locally polarized hole control units arranged in segments along the source-drain direction. Regardless of whether heavy ion incident at the gate edge or deep within the drift region, the generated holes can be captured by the nearest buried island, significantly shortening the hole drift distance. Furthermore, the polarized hole management layer is disposed on the upper surface of the buffer layer, completely decoupled from the gate cap layer and the gate, and does not affect the device's threshold voltage, transconductance, or switching characteristics. Simultaneously, the segmented buried island design allows for controllable depletion of the two-dimensional electron gas, avoiding the severe depletion of the two-dimensional electron gas in high-voltage power devices with continuous polarization layer structures. The increase in on-resistance is controllable, making it suitable for high-voltage power applications. Moreover, the fabrication of the polarized hole management layer does not require deep trench etching through the barrier layer, avoiding crystal damage introduced by this process.

[0019] The source stepped field plate disperses the peak electric field, which was originally concentrated at the edge of the gate-drain side, into multiple lower local field peaks, homogenizing the static electric field and reducing the probability of strong collisional ionization triggered by heavy ion incident from the source. At the same time, at least one stepped edge is aligned with the center of at least one buried island along the source-drain direction, so that the residual high field region after field plate modulation exactly matches the hole collection node position, realizing spatial coordination of electric field modulation and hole collection.

[0020] Therefore, without changing the core structure of the device or increasing the complexity of the process, this invention achieves rapid capture and removal of radiation-induced holes throughout the entire gate-drain drift region, avoiding the risk of single-particle burnout in high-voltage power applications.

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a locally charged, charge-controlled gallium nitride device resistant to single-event burn-out, provided by an embodiment of the present invention. Figure 2 This is a schematic flowchart of a method for fabricating a locally charged, charge-controlled gallium nitride device resistant to single-event burn-out, provided by an embodiment of the present invention. Figure 3 This is a schematic diagram illustrating the fabrication process of a locally charge-controlled gallium nitride device resistant to single-event burn-out, provided in an embodiment of the present invention. Figure 4 This is a schematic diagram comparing the single-particle burn-off threshold of the device structure provided in the embodiments of the present invention.

[0023] Reference numerals in the figures: 1. Substrate layer; 2. Nucleation layer; 3. Buffer layer; 4. Buried island; 5. Polarization cap layer; 6. Spacer layer; 7. Channel layer; 8. Barrier layer; 9. Gate cap layer; 10. Source; 11. Drain; 12. Gate; 13. Source stepped field plate. Detailed Implementation

[0024] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0025] To address the issue that existing single-event burn-off (SED) protection schemes for enhancement-mode GaN HEMTs cannot achieve rapid capture and removal of radiation-induced holes across the entire gate-drain drift region without altering the core device structure or increasing process complexity, and still pose a SED risk in high-voltage power applications, this invention provides a locally charge-controlled GaN device with SED protection. (See [link to relevant documentation]). Figure 1 , Figure 1This is a schematic diagram of a local charge-controlled gallium nitride device resistant to single-event burn-out provided by an embodiment of the present invention. The device includes a substrate layer 1, a nucleation layer 2, a buffer layer 3, a polarized hole management layer, a spacer layer 6, a channel layer 7, a barrier layer 8, a source 10, a drain 11, a gate cap layer 9, a gate 12, a passivation layer, and a source stepped field plate 13.

[0026] In this embodiment of the invention, the substrate layer 1, the nucleation layer 2, the buffer layer 3, the polarized hole management layer, the spacer layer 6, and the channel layer 7 are stacked sequentially from bottom to top.

[0027] The substrate layer 1 provides mechanical support and a heat dissipation path. The material of the substrate layer 1 can be SiC, GaN, Si, or sapphire, and its thickness can be greater than 100 μm.

[0028] Nucleation layer 2 is used to improve epitaxial quality. The material of nucleation layer 2 can be AlN, and its thickness can range from 100 to 300 nm.

[0029] The material of buffer layer 3 can be semi-insulating GaN or GaN:C (carbon-doped gallium nitride), and C (carbon) doping can be used, with a concentration range of [missing information]. The thickness ranges from 2 to 3 μm.

[0030] In this embodiment of the invention, the polarized hole management layer includes multiple locally polarized hole control units arranged in segments along the source-drain direction; each locally polarized hole control unit includes a buried island 4 and a polarization cap layer 5 disposed on the buried island 4. The buried island 4 and the polarization cap layer 5 together form a locally polarized hole control unit, used to modulate the local electric field, bind or redistribute radiation-induced holes, and suppress impact ionization positive feedback when heavy ions are incident. Each buried island 4 is provided with a polarization cap layer 5, which may be located on the upper surface or part of the upper surface of the buried island 4.

[0031] The number of local polarization hole control units is 2-10.

[0032] In this embodiment of the invention, the width of a single buried island 4 along the source-drain direction ranges from 0.3 to 3 μm, and the thickness ranges from 30 to 150 nm. The material of the buried island 4 is p-GaN, specifically Mg-doped p-GaN, wherein the Mg doping concentration can be [missing information]. .

[0033] In one implementation, multiple locally polarized hole control units are arranged in a non-uniform segmented manner along the source-drain direction.

[0034] The width of the buried island 4 in the local polarization hole control unit near the drain side edge of the gate 12 is smaller than the width of the buried island 4 in the local polarization hole control unit near the drain 11, so as to match the electric field distribution of the drift region.

[0035] In one implementation, the buried island 4 is in a floating or quasi-floating state. It is not directly connected to the source electrode 10 metal through source etching holes. This structure mainly suppresses SEB positive feedback through local confinement, recombination, potential clamping, and electric field redistribution.

[0036] In this context, the floating state means that the buried island 4 has no low-resistance electrical connection with any external electrodes, including the source 10, drain 11, gate 12, and substrate. At this time, the buried island 4 is completely electrically isolated by the depletion region of the surrounding reverse-biased PN junction.

[0037] The quasi-floating state refers to the formation of a controllable high-resistance or Schottky-type charge exchange path between the buried island 4 and the source 10 through processes such as etching contact holes and sputtering metal, rather than a direct low-resistance ohmic connection. In this state, the buried island 4 is not completely suspended, but has a controllable weak charge exchange path. The charge is not permanently bound and can be slowly exchanged with the outside. It is a compromise between "completely floating" and "directly connected to a fixed potential".

[0038] In another implementation, at least one buried island 4 is electrically connected to the source 10 through a conductive via, source opening, or local contact structure to further stabilize the potential of the buried island 4 and provide a path for some holes to be discharged to the source 10.

[0039] In this embodiment of the invention, the buried island 4 closest to the source electrode 10 can be extended. This extension design has the following two functions: Firstly, it provides process convenience for fabricating vertical vias (VIA) connecting the source electrode 10 and the buried island 4, allowing the via to be directly etched vertically downwards to the extended island without additional alignment or offset. Secondly, the extended buried island 4 is closer to the source electrode 10, which is conducive to guiding the holes generated by radiation to be transported along the buried island 4 towards the source electrode 10, thereby improving the hole collection efficiency.

[0040] In this embodiment of the invention, the buried island 4 may be located above the buffer layer 3, below the channel layer 7, below the barrier layer 8, or near the residual high field region below the source electrode stepped field plate 13.

[0041] In one implementation, the material of the buried island 4 can be replaced with a group III nitride material capable of providing local hole potential traps or local potential modulation, such as InGaN (indium gallium nitride) or a composite nitride layer containing Al / In (aluminum / indium).

[0042] In this embodiment of the invention, the polarization cap layer 5 can be AlN or AlGaN with an Al composition greater than 0.5%. The thickness of the polarization cap layer 5 can range from 0.5 to 10 nm, preferably 1 to 5 nm. For the AlN / GaN system, the formation and mobility of polarization-induced two-dimensional holes are affected by interface quality, impurity concentration, strain state, and regrowth conditions. Therefore, this invention does not require all embodiments to achieve a fixed areal density, but rather utilizes polarization charge, valence band shift, and p-GaN local potential to achieve hole manipulation.

[0043] In this embodiment of the invention, the segmented local polarization hole control unit covers the entire gate-drain drift region, shortening the hole drift distance to within 1 μm, and binding and recombinizing nearby, thereby suppressing avalanche positive feedback from the source.

[0044] In this embodiment of the invention, a continuous polarization cap layer can also be used to replace the segmented islands. A continuous polarization cap layer is laid in the entire gate drain drift region as an alternative structure. The process is simpler but the 2DEG depletion effect is stronger.

[0045] In one implementation, it can be used (3-5nm) as a substitute for pure AlN, the polarization discontinuity is slightly smaller, but the critical thickness and epitaxial process window may be wider.

[0046] Spacer layer 6 is used to isolate buried island 4 from channel layer 7. Its material can be UID (unintentionally doped)-GaN, and its thickness can be 300-600nm.

[0047] The region adjacent to the heterogeneous interface between the polarization cap layer 5 and the regenerated spacer layer 6 above it can induce two-dimensional hole gas, hole potential wells, or local hole enrichment regions, serving as a rapid transport channel for holes.

[0048] In one implementation, for high-voltage devices, such as >1200V high-voltage devices, two or more segmented polarization hole management units can be set in the buffer layer 3.

[0049] In this embodiment of the invention, the barrier layer 8 is located in the middle region of the upper surface of the channel layer 7. The barrier layer 8 is used to form a two-dimensional electron gas with the channel layer 7. The channel layer 7 is used to form the main channel.

[0050] The material of barrier layer 8 can be... x = 0.15-0.25; the thickness of barrier layer 8 can range from 10-20 nm. The material of channel layer 7 can be GaN, and the thickness can range from 100-300 nm.

[0051] In this embodiment of the invention, the source 10 and the drain 11 are located above the channel layer 7, the source 10 is located on one side of the barrier layer 8, and the drain 11 is located on the other side of the barrier layer 8.

[0052] The source electrode 10 and drain electrode 11 metal materials can be Ti / Al / Ni / Au (titanium / aluminum / nickel / gold) or other metal systems suitable for n-type contacts.

[0053] In this embodiment of the invention, the gate cap layer 9 and the gate 12 are sequentially located on the barrier layer 8.

[0054] The gate cap layer 9 can be made of p-GaN with a thickness ranging from 80 to 200 nm. The gate cap layer 9 is Mg-doped, with a Mg doping concentration ranging from [missing value]. .

[0055] Gate 12 is stacked on top of the gate cap. The metal of gate 12 can be Ni / Au, TiN (titanium nitride) / Al or other metal systems suitable for p-GaN gates.

[0056] In this embodiment of the invention, a passivation layer covers the barrier layer 8 to support the source stepped field plate 13 and reduce the influence of surface states. The material of the passivation layer can be Si3N4 (silicon nitride), and the thickness can be in the range of 100-300 nm.

[0057] In this embodiment of the invention, the source stepped field plate 13 is located above the passivation layer and the source electrode 10. The source stepped field plate 13 is electrically connected to the source electrode 10.

[0058] The source stepped field plate 13 includes two or more stepped edges. Further, the source stepped field plate 13 includes at least two stepped edges with different medium thicknesses or different lateral extension lengths.

[0059] Specifically, the source stepped field plate 13 includes a stepped dielectric layer and a field plate metal covering the stepped dielectric layer; the stepped dielectric layer has two or more stepped edges.

[0060] The number of steps can be 2-10.

[0061] In one implementation, the number of stepped edges of the source stepped field plate 13 is preferably the same as or similar to the number of localized polarization hole control units. Each edge of the stepped field plate corresponds to an electric field peak, and the localized polarization hole control units serve as internal electric field modulation nodes. When the number of both is matched, a one-to-one correspondence between the stepped edges and the localized polarization hole control units can be achieved, forming a coordinated electric field homogenization effect, thereby obtaining the optimal withstand voltage improvement.

[0062] In this embodiment of the invention, the total length of the source stepped field plate 13 can cover the gate-drain spacing, i.e., 30%-70% of the drift region length, to ensure a sufficiently uniform electric field. The dielectric thickness at the stepped edge near the gate side can be 100-300 nm, and the dielectric thickness at the stepped edge near the drain side can be 300-800 nm. The lateral deviation between the stepped edge and the corresponding buried island 4 is preferably less than 0.5 μm.

[0063] In this embodiment of the invention, two or more stepped edges are provided along the source-drain direction by the source stepped field plate 13, so that the high field originally concentrated near the gate edge is distributed into multiple lower local field peaks. At least one stepped edge is aligned with the center position of at least one buried island 4 along the source-drain direction, so that the residual high field region after field plate modulation matches the local polarization hole control unit.

[0064] In this embodiment of the invention, the working principle of SEB protection is as follows: When only the gate field plate is added, the initial peak electric field at the gate drain edge is reduced, and the SEB threshold reaches 360V. However, after heavy ion injection, the residual high field in the drift region will still drive electrons to move towards the drain 11, and holes and induced positive charges will change the local potential, and collisional ionization positive feedback may still be initiated.

[0065] The source stepped field plate 13 first changes the static electric field distribution in the gate-drain drift region. Compared with a single field plate, the stepped field plate disperses the high field that was originally concentrated near the edge of the gate-drain side into multiple lower local field peaks, making the electric field distribution before heavy ion incidence smoother, reducing the initial conditions for triggering strong collisional ionization after heavy ion incidence, and increasing the SEB threshold to 570V.

[0066] The buried island 4 in p-GaN provides a local p-type potential, and the polarization cap layer 5 forms a vertical polarization field and a hole-related potential well through polarization discontinuities. Holes generated by heavy ions are more easily trapped, recombine, or redistributed near the buried island 4 / polarization cap layer 5, no longer continuously pushing up the high-field region potential of the gate-drain. Impaction ionization positive feedback is thus suppressed, and the SEB threshold is increased to 710V. This mechanism does not require all holes to be discharged from the device through the metal channel. The key is to change the hole and local electric field distribution before the formation of SEB positive feedback, making it difficult for the high-field region to continuously reach the avalanche condition.

[0067] When a source VIA or local source contact is configured, the potential of the buried island 4 can be further clamped by the source 10. In this case, holes affected by the local electric field and concentration gradient can be discharged from the device through the local contact structure connected to the source 10. This source-connection structure can improve hole management capability, but it is not a necessary condition for achieving an improved SEB threshold.

[0068] In this embodiment of the invention, the polarized hole management layer employs multiple locally polarized hole control units arranged in segments along the source-drain direction. Regardless of whether the heavy ion incident position is at the edge of the gate 12 or deep in the drift region, the generated holes can be captured by the nearest buried island 4, significantly shortening the hole drift distance. Furthermore, the polarized hole management layer is disposed on the upper surface of the buffer layer 3, completely decoupled from the gate cap layer 9 and the gate 12, and does not affect the device's threshold voltage, transconductance, or switching characteristics. Simultaneously, the segmented buried island 4 design allows for controllable depletion of the two-dimensional electron gas, avoiding the problem of severe two-dimensional electron gas depletion in high-voltage power devices with continuous polarization layer structures. The increase in on-resistance is controllable, making it suitable for high-voltage power scenarios. Moreover, the fabrication of the polarized hole management layer does not require deep trench etching through the barrier layer 8, avoiding the crystal damage introduced by this process.

[0069] The source stepped field plate 13 disperses the peak electric field, which was originally concentrated at the edge of the gate drain side, into multiple lower local field peaks, homogenizing the static electric field and reducing the probability of strong collisional ionization triggered after heavy ion incident from the source. At the same time, at least one stepped edge is aligned with the center position of at least one buried island 4 along the source drain direction, so that the residual high field region after field plate modulation exactly matches the hole collection node position, realizing spatial coordination of electric field modulation and hole collection.

[0070] Therefore, without changing the core structure of the device or increasing the complexity of the process, this invention achieves rapid capture and removal of radiation-induced holes throughout the entire gate-drain drift region, avoiding the risk of single-particle burnout in high-voltage power applications.

[0071] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a locally charge-controlled gallium nitride device resistant to single-event burn-out, see [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic flowchart of a method for fabricating a locally charged, charge-controlled gallium nitride device resistant to single-event burn-out, according to an embodiment of the present invention. The fabrication method specifically includes the following steps: Step S201: A core layer 2 and a buffer layer 3 are grown sequentially from bottom to top on the substrate layer 1.

[0072] See Figure 3 , Figure 3 This is a schematic diagram illustrating the fabrication process of a locally charge-controlled gallium nitride device resistant to single-event burn-out, provided by an embodiment of the present invention. Figure 3Figure (a) shows a schematic diagram of the formation of nucleation layer 2 and buffer layer 3. First, a substrate layer 1 is selected. The material of substrate layer 1 can be SiC, GaN, Si, or sapphire, and its thickness can be greater than 100 μm. Then, nucleation layer 2 and buffer layer 3 are grown sequentially from bottom to top on substrate layer 1. The material of nucleation layer 2 can be AlN, and its thickness can range from 100-300 nm. The material of buffer layer 3 can be semi-insulating GaN or GaN:C, and C carbon doping can be used, with a concentration range of [missing information]. The thickness ranges from 2 to 3 μm.

[0073] Step S202: An initial buried island layer and an initial polarization cap layer are epitaxially grown on the buffer layer 3.

[0074] See Figure 3 (b) Figure 3 (b) shows a schematic diagram of the formation of the initial buried island layer and the initial polarization cap layer. The material of the initial buried island is p-GaN, specifically Mg-doped p-GaN, where the Mg doping concentration can be [missing information]. The initial polarization cap layer can be AlN or AlGaN with an Al content greater than 0.5.

[0075] In step S203, the initial buried island layer and the initial polarization cap layer are patterned into a segmented island structure arranged along the source-drain direction by photolithography and dry etching, and multiple local polarization hole control units are formed by downward etching; each local polarization hole control unit includes a buried island 4 and a polarization cap layer 5 disposed on at least the buried island 4.

[0076] In this embodiment of the invention, the initial buried island layer and the initial polarization cap layer are patterned into a segmented island structure by photolithography and dry etching. Etching downwards stops at the surface of buffer layer 3 or at a predetermined depth, forming multiple localized polarization hole control units. (See also...) Figure 3 (c) Figure 3 (c) in the diagram is a schematic diagram of the formation of a local polarization hole control unit. Each local polarization hole control unit includes a buried island 4 and a polarization cap layer 5 disposed on the buried island 4.

[0077] The number of localized polarization hole control units is 2-10, and the width of a single buried island 4 along the source-drain direction ranges from 0.3-3 μm, and the thickness ranges from 30-150 nm. The thickness of the polarization cap layer 5 can range from 0.5-10 nm, preferably 1-5 nm.

[0078] Then, the patterned surface is cleaned, annealed in an NH3 atmosphere, treated with N2 plasma, or subjected to other surface repair treatments to reduce the impact of etching damage on the regrowth interface.

[0079] In step S204, a spacer layer 6, a channel layer 7, and an initial barrier layer are sequentially grown in the buffer layer 3 and multiple localized polarization hole control units.

[0080] See Figure 3 (d) in Figure 3 Figure (d) shows a schematic diagram of the structure of spacer layer 6, channel layer 7, and initial barrier layer. Spacer layer 6, channel layer 7, and initial barrier layer are then regrowed on top of the patterned structure. Regrowth can be achieved using N2 (nitrogen) carrier gas MOCVD (metal-organic chemical vapor deposition), MBE (molecular beam epitaxy), or other low-hydrogen / hydrogen-free processes to reduce the impact of Mg-H complex formation on subsequent acceptor activation efficiency.

[0081] The spacer layer 6 isolates the buried island 4 from the channel layer 7. Its material can be UID (unintentionally doped)-GaN, and its thickness can range from 300nm to 600nm. The channel layer 7 forms the main channel. The channel layer 7 can also be made of GaN, and its thickness can range from 100nm to 300nm. The initial barrier layer can be made of... The thickness range is 10-20 nm, with x = 0.15-0.25.

[0082] Step S205: Epitaxially grow gate cap layer 9 on top of the initial barrier layer.

[0083] See Figure 3 In step (e), an initial gate cap layer is epitaxially grown on top of the initial barrier layer. The gate cap layer region is then defined using photolithography and selective etching, followed by Mesa isolation etching. If necessary, residual hydrogen release and Mg acceptor activity can be promoted during subsequent annealing to obtain gate cap layer 9. (See [reference]). Figure 3 (f) in the middle.

[0084] The gate cap layer 9 can be made of p-GaN with a thickness ranging from 80 to 200 nm. The gate cap layer 9 is Mg-doped, with a Mg doping concentration ranging from [missing value]. .

[0085] Step S206: Deposit a passivation layer on the surface of the initial barrier layer and the gate cap layer 9.

[0086] In this embodiment of the invention, a passivation layer is deposited on the surface of the initial barrier layer and the gate cap layer 9 using plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD). The passivation layer is used to support the source stepped field plate 13 and reduce the influence of surface states. The material of the passivation layer can be Si3N4, and the thickness can range from 100 to 300 nm.

[0087] In step S207, etching downwards from the upper surface of the passivation layer to form a gate opening above the gate cap layer 9, etching away both sides of the initial barrier layer to obtain the barrier layer 8, and forming source openings and drain openings on both sides of the barrier layer 8; fabricating a source 10 in the source opening, fabricating a drain 11 in the drain opening, and fabricating a gate 12 in the gate opening.

[0088] In this embodiment of the invention, the insulating passivation layer is patterned by photolithography, and RIE, ICP or wet etching is used to etch downward on the upper surface of the passivation layer in the preset window area to remove the passivation layer, forming a gate opening above the gate cap layer 9, etching away the two sides of the initial barrier layer to obtain the barrier layer 8, and forming source openings and drain openings on both sides of the barrier layer 8.

[0089] Then, see Figure 3 In (g), source electrode 10 is fabricated within the source aperture using processes such as electron beam evaporation (MBE), magnetron sputtering, and pulsed laser deposition (PLD), and drain electrode 11 is fabricated within the drain aperture. The ohmic contact metals for source electrode 10 and drain electrode 11 can be Ti / Al / Ni / Au or other metal systems suitable for n-type contacts.

[0090] See Figure 3 In (h), the gate 12 is fabricated in the gate opening using the same processes such as electron beam evaporation, magnetron sputtering, and pulsed laser deposition. The metal of the gate 12 can be Ni / Au, TiN / Al, or other metal systems suitable for p-GaN gates.

[0091] Step S208: A source stepped field plate 13 is fabricated on the passivation layer and the source electrode 10; the source stepped field plate 13 includes two or more stepped edges; at least one stepped edge is aligned with the center position of at least one buried island 4 along the source-drain direction; the source stepped field plate 13 is electrically connected to the source electrode 10.

[0092] In this embodiment of the invention, a stepped dielectric layer can be formed on the passivation layer and the source 10 through multiple dielectric depositions, photolithography, and etching. Then, a field plate metal is deposited on the surface of the stepped dielectric layer to form a source stepped field plate 13, which is connected to the source 10 via an interconnect structure. (See also...) Figure 3 (i) in the middle.

[0093] The source stepped field plate 13 includes two or more stepped edges; at least one stepped edge is aligned with the center of at least one buried island 4 along the source-drain direction.

[0094] In this embodiment of the invention, the total length of the source stepped field plate 13 can cover 30%-70% of the gate-drain spacing. The dielectric thickness of the stepped edge near the gate side can be 100-300 nm, and the dielectric thickness of the stepped edge near the drain side can be 300-800 nm. At least one stepped edge is aligned with the center position of at least one buried island 4 along the source-drain direction, and the lateral deviation is preferably less than 0.5 μm.

[0095] In this embodiment of the invention, it is preferred that the number of stepped edges of the source stepped field plate 13 is the same as or similar to the number of local polarization hole control units.

[0096] In this embodiment of the invention, the polarized hole management layer employs multiple locally polarized hole control units arranged in segments along the source-drain direction, distributed throughout the entire gate-drain drift region. Regardless of whether the heavy ion incident position is at the edge of the gate 12 or deep within the drift region, the generated holes can be captured by the nearest buried island 4, significantly shortening the hole drift distance. Furthermore, the polarized hole management layer is disposed on the upper surface of the buffer layer 3, completely decoupled from the gate cap layer 9 and the gate 12, and does not affect the device's threshold voltage, transconductance, or switching characteristics. Simultaneously, the segmented buried island 4 design allows for controllable depletion of the two-dimensional electron gas, avoiding the problem of severe depletion of the two-dimensional electron gas and increased on-resistance in high-voltage power devices caused by continuous polarization layer structures. Moreover, the fabrication of the polarized hole management layer does not require deep trench etching through the barrier layer 8, avoiding the crystal damage introduced by this process.

[0097] The source stepped field plate 13 disperses the peak electric field, which was originally concentrated at the edge of the gate drain side, into multiple lower local field peaks, reducing the probability of strong collisional ionization triggered after heavy ion incident from the source. At the same time, at least one stepped edge is aligned with the center position of at least one buried island 4 along the source drain direction, so that the residual high field region after field plate modulation exactly matches the hole collection node position, realizing spatial coordination of electric field modulation and hole collection.

[0098] Therefore, without changing the core structure of the device or increasing the complexity of the process, this invention achieves rapid capture and removal of radiation-induced holes throughout the entire gate-drain drift region, avoiding the risk of single-particle burnout in high-voltage power applications.

[0099] In this embodiment of the invention, the spontaneous polarization and piezoelectric polarization discontinuity of the AlN / GaN heterointerface are utilized to generate a high concentration of 2DHG (~) at the interface via a field ionization mechanism. This method is temperature-independent and effective even in low-temperature environments. Existing hole discharge paths are only effective directly below the gate or near the source. In this embodiment, the buried island 4+2DHG channel is distributed throughout the gate-drain drift region, allowing holes generated at any location within the drift region to be collected nearby (<1μm from the nearest collection node), significantly shortening the hole drift distance. The buried island 4+AlN cap layer also acts as a back barrier during normal operation, enhancing channel electron confinement and reducing leakage current in the buffer layer 3. Existing radiation hardening solutions lack this additional function. The source stepped field plate 13 reduces the peak electric field and decreases carrier generation, while the 2DHG rapidly collects generated holes. Both are spatially aligned, with the electric field modulation region of the source stepped field plate 13 matching the location of the 2DHG collection node. The polarized hole management layer is located inside the buffer layer 3, decoupled from the gate structure, and does not affect the threshold voltage, transconductance, or switching characteristics. The segmented island design (rather than a continuous layer) makes the depletion effect of 2DEG controllable and is suitable for high-voltage power HEMTs of 650V and above, while the continuous layer design is only suitable for low-voltage logic circuits.

[0100] Unlike existing deep trench hybrid source and deep trench electrode schemes, the buried island 4 in this embodiment of the invention is realized by standard epitaxy + photolithography. The entire fabrication method is highly compatible with existing GaN HEMT mass production processes, which helps to reduce production costs and improve yield.

[0101] In one implementation, a conductive via can be formed in the source region, allowing at least one buried island 4 to be electrically connected to the source 10 via a Ni / Au, Pd (palladium) / Au, or other metal system suitable for p-type GaN contacts, facilitating selection based on different voltage ratings and process capabilities.

[0102] In the TCAD (Computer-Aided Design for Semiconductor Processes and Devices) simulation, mobility models, carrier generation and recombination models, collisional ionization models, polarization models, and heavy ion models are introduced. Heavy ions with a linear energy transfer of 0.7 pC / μm are assumed to be incident from the edge of the field plate. See [link to TCAD simulation]. Figure 4 , Figure 4 This is a schematic diagram comparing the single-particle burn-off threshold of the device structure provided in an embodiment of the present invention. In a simulation embodiment, as shown... Figure 4 As shown in (a), the SEB threshold of a conventional gate field plate reference structure is approximately 360V; Figure 4 As shown in (b), the SEB threshold of the intermediate structure after adding the source stepped field plate 13 is increased to approximately 570V; after further adding the segmented p-GaN buried island 4 and the AlN cap layer, as shown in (b), the SEB threshold of the intermediate structure is increased to approximately 570V; Figure 4 As shown in (c), the SEB threshold is increased to approximately 710V. See Table 1, which is a comparison table of single-event burn-off thresholds for device structures.

[0103] Table 1 Comparison of Single-Particle Burn-Off Thresholds for Device Structures

[0104] Compared to a structure with only a gate field plate, the SEB threshold of this invention is improved by approximately 97.2%. The core effect of this invention does not depend on source vias. The latest simulation structure does not include source etched vias connecting to the buried island 4, yet still achieves an SEB threshold of 710V; therefore, source vias are an optional embodiment. The above values ​​correspond to specific device dimensions, bias conditions, and heavy ion models, and are used to illustrate structural improvement trends, not to limit the scope of protection of this invention.

[0105] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0106] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0107] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0108] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0109] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0110] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0111] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A locally charge-controlled gallium nitride device resistant to single-event burn-out, characterized in that, The device includes: The substrate layer, nucleation layer, buffer layer, polarized hole management layer, spacer layer, and channel layer are stacked sequentially from bottom to top. The polarized hole management layer includes multiple localized polarized hole control units arranged in segments along the source-drain direction; each localized polarized hole control unit includes a buried island and a polarization cap layer disposed on the buried island. A barrier layer located in the middle region of the upper surface of the channel layer; The source electrode is located on one side of the barrier layer and the drain electrode is located on the other side of the barrier layer; A gate cap layer and a gate are sequentially located above the barrier layer; A passivation layer covering the upper surface of the barrier layer; A source electrode stepped field plate is located above the passivation layer and the source electrode; the source electrode stepped field plate includes two or more stepped edges; at least one stepped edge is aligned with the center position of at least one buried island along the source-drain direction; the source electrode stepped field plate is electrically connected to the source electrode.

2. The locally charged, charge-controlled gallium nitride device resistant to single-event burn-out according to claim 1, characterized in that, The multiple localized polarization hole control units are arranged in a non-uniform segmented manner along the source-drain direction.

3. The locally charged, charge-controlled gallium nitride device resistant to single-event burn-out according to claim 1, characterized in that, The number of the plurality of local polarization hole control units is 2-10.

4. The locally charged, charge-controlled gallium nitride device resistant to single-event burn-out according to claim 1, characterized in that, The width of a single buried island along the source-drain direction ranges from 0.3 to 3 μm, and the thickness ranges from 30 to 150 nm; the thickness of a single polarization cap layer ranges from 0.5 to 10 nm.

5. The locally charged, charge-controlled gallium nitride device resistant to single-event burn-out according to claim 1, characterized in that, The material of the buried island is p-GaN.

6. The locally charged, charge-controlled gallium nitride device resistant to single-event burn-out according to claim 1, characterized in that, The polarization cap layer is made of AlN or AlGaN with an Al content greater than 0.

5.

7. The locally charged, charge-controlled gallium nitride device resistant to single-event burn-out according to claim 1, characterized in that, The number of stepped edges of the source stepped field plate is the same as the number of the localized polarization hole control units.

8. The locally charged, charge-controlled gallium nitride device resistant to single-event burn-out according to claim 1, characterized in that, The buried island is in a floating or quasi-floating state.

9. The locally charged, charge-controlled gallium nitride device resistant to single-event burn-out according to claim 1, characterized in that, At least one of the buried islands is electrically connected to the source electrode through a conductive via, a source opening, or a local contact structure.

10. A method for fabricating a locally charge-controlled gallium nitride device resistant to single-event burn-out, characterized in that, The preparation method includes: A core layer and a buffer layer are grown sequentially from bottom to top on the substrate. An initial embedded island layer and an initial polarization cap layer are epitaxially grown on the buffer layer; The initial buried island layer and the initial polarization cap layer are patterned into a segmented island structure arranged along the source-drain direction by photolithography and dry etching, and multiple local polarization hole control units are formed by etching downward; each local polarization hole control unit includes a buried island and a polarization cap layer disposed on the buried island. A spacer layer, a channel layer, and an initial barrier layer are sequentially grown in the buffer layer and the plurality of localized polarization hole control units. An epitaxial gate cap layer is grown on top of the initial barrier layer; A passivation layer is deposited on the surfaces of the initial barrier layer and the gate cap layer; The passivation layer is etched downwards from its upper surface to form a gate opening above the gate cap layer. Both sides of the initial barrier layer are etched away to obtain a barrier layer, and source and drain openings are formed on both sides of the barrier layer. A source is formed in the source opening, a drain is formed in the drain opening, and a gate is formed in the gate opening. A source electrode stepped field plate is fabricated on the passivation layer and the source electrode; the source electrode stepped field plate includes two or more stepped edges; at least one stepped edge is aligned with the center position of at least one buried island along the source-drain direction; the source electrode stepped field plate is electrically connected to the source electrode.

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