Multiple voltage domain synchronous clock circuit

Abstract

The disclosure provides a multi-voltage domain synchronous clock circuit, which can be applied to the technical field of integrated circuits. The multi-voltage domain synchronous clock circuit comprises: a first ring oscillator working in a first voltage domain and a second ring oscillator working in a second voltage domain different from the first voltage domain; a first flying capacitor connected between a connection node between adjacent first inverters in the first ring oscillator and a corresponding connection node between adjacent second inverters in the second ring oscillator; and a first clock signal output node and a second clock signal output node connected to corresponding first connection nodes in the first ring oscillator and the second ring oscillator respectively, for synchronously providing a first clock signal and a second clock signal in the first voltage domain and the second voltage domain respectively.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a multi-voltage domain synchronous clock circuit. Background Technology

[0002] For integrated circuits operating across multiple voltage domains, the synchronization of clock signals between devices operating in each voltage domain is crucial. However, in related technologies, the synchronization between clock signals in different voltage domains is low, limiting the performance of the integrated circuits. Summary of the Invention

[0003] In view of this, the present disclosure provides a multi-voltage domain synchronous clock circuit.

[0004] One aspect of this disclosure provides a multi-voltage domain synchronous clock circuit, comprising: a first ring oscillator operating in a first voltage domain and a second ring oscillator operating in a second voltage domain different from the first voltage domain, wherein the first ring oscillator includes a predetermined number of first inverters sequentially connected to form a ring topology, and the second ring oscillator includes a predetermined number of second inverters sequentially connected to form a ring topology; a first flying capacitor connecting a connection node between adjacent first inverters in the first ring oscillator and a corresponding connection node between adjacent second inverters in the second ring oscillator; and a first clock signal output node and a second clock signal output node, respectively connected to corresponding first connection nodes in the first ring oscillator and the second ring oscillator, for synchronously providing a first clock signal and a second clock signal in the first voltage domain and the second voltage domain, respectively.

[0005] According to embodiments of this disclosure, a multi-voltage domain synchronous clock circuit is provided. In this multi-voltage domain synchronous clock circuit, a first ring oscillator and a second ring oscillator can be coupled across the first and second voltage domains using a first flying capacitor. During this process, a first connection node in the first and second ring oscillators connected to the same first flying capacitor can be connected to a first clock signal output node and a second clock signal output node, respectively, so that the first and second clock signal output nodes synchronously provide a first clock signal and a second clock signal, respectively, in the first and second voltage domains. In this way, each voltage domain generates and maintains its own corresponding local clock signal, and the energy consumption for clock synchronization across different voltage domains is reduced.

[0006] According to embodiments of this disclosure, by using a circuit structure of a ring oscillator coupled by a flying capacitor, clock signals of different voltage domains in a chip can be automatically synchronized to drive devices in multiple voltage domains to operate.

[0007] Furthermore, since the multi-voltage domain clock synchronization circuit of this disclosure can automatically generate and maintain clock signals of different voltage domains without the need for other devices, it can also be used as the operating clock of an adiabatic circuit. Attached Figure Description

[0008] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings, which will be explained in conjunction with the drawings.

[0009] Figure 1A A schematic diagram of an inverter coupled by a flying capacitor according to an embodiment of the present disclosure is shown.

[0010] Figure 1B A schematic diagram of a multi-voltage domain synchronous clock circuit according to an embodiment of the present disclosure is shown.

[0011] Figure 2 A schematic diagram of a multi-voltage domain synchronous clock circuit according to another embodiment of the present disclosure is shown.

[0012] Figure 3 A schematic diagram of a multi-voltage domain synchronous clock circuit according to another embodiment of the present disclosure is shown.

[0013] Figure 4 A schematic diagram of a multi-voltage domain synchronous clock circuit according to another embodiment of the present disclosure is shown.

[0014] Figure 5 A schematic diagram of a third ring oscillator according to an embodiment of the present disclosure is shown.

[0015] Figure 6 A schematic diagram of a multi-voltage domain synchronous clock circuit according to another embodiment of the present disclosure is shown.

[0016] Figure 7 A schematic diagram of a multi-voltage domain synchronous clock circuit according to another embodiment of the present disclosure is shown. Detailed Implementation

[0017] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0019] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0020] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0021] It should be noted that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "installed," "connected," and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements. The terms "parallel," "perpendicular," and "equal" include the described situation and situations similar to the described situation, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism can be, for example, within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity can also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality can be, for example, a difference between the two equal items being less than or equal to 5% of either one. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] In integrated circuits that operate across multiple voltage domains, their clock signals must meet various requirements, such as clock synchronization, device safety (e.g., low risk of overstress), low power consumption, noise immunity, and clock domain localization (i.e., eliminating the need to distribute large-swing clock signals through large level shifters).

[0023] In some schemes, integrated circuits operating across multiple voltage domains may include level-shifting tree architectures and global clock distribution architectures.

[0024] The level-shifter tree architecture transmits the master clock signal to different voltage domains to distribute the clock signal to devices in each voltage domain. However, this architecture has several problems, such as high dynamic power consumption, significant clock transmission delay and jitter, the risk of devices operating under overload, and difficulty in scaling up to adapt to multi-voltage domain applications.

[0025] A global clock distribution architecture requires all voltage domains to use a uniform voltage level, or it requires additional complex isolation devices. This architecture goes against the original design intent of multi-domain power architectures, requires a large number of protection devices, limits voltage expansion, and makes it difficult to meet the needs of fine-grained power management.

[0026] In view of this, the present disclosure provides a multi-voltage domain synchronous clock circuit. In this multi-voltage domain synchronous clock circuit, each voltage domain can generate and maintain its corresponding local clock signal. Clock synchronization between different voltage domains is achieved based on a low-power signal coupling method, without relying on level converters in related technologies. The following description is in conjunction with the accompanying drawings.

[0027] Figure 1A A schematic diagram of an inverter coupled by a flying capacitor according to an embodiment of the present disclosure is shown. Figure 1B A schematic diagram of a multi-voltage domain synchronous clock circuit according to an embodiment of the present disclosure is shown.

[0028] like Figure 1A and Figure 1B As shown, the multi-voltage domain synchronous clock circuit of this embodiment includes multiple ring oscillators operating in multiple voltage domains. For example, the multiple voltage domains may include voltage domains such as 0~1 V, 1~2 V, and 2~3 V. For example, the multiple voltage domains may include a first voltage domain and a second voltage domain that are different from each other. The multiple ring oscillators may include a first ring oscillator operating in the first voltage domain and a second ring oscillator operating in the second voltage domain. The multi-voltage domain synchronous clock circuit of this disclosure embodiment will be described below with reference to a first ring oscillator and a second ring oscillator, but it should be understood that the embodiments of this disclosure are not limited to the case of including only two voltage domains and correspondingly two ring oscillators.

[0029] In this embodiment of the disclosure, a first ring oscillator includes a predetermined number of first inverters INV1 connected in sequence to form a ring topology. A second ring oscillator includes a predetermined number of second inverters INV2 connected in sequence to form a ring topology. Taking the first inverter as an example, the first inverter may include a first switching device T1 (e.g., a P-type field-effect transistor (PFET)) and a second switching device T2 (e.g., an N-type field-effect transistor (NFET)) connected in series. The first switching device T1 and the second switching device T2 can be turned off or on based on a signal received at a control terminal (e.g., a gate). The first switching device T1 and the second switching device T2 can be turned on complementaryly to each other; for example, when the first switching device T1 is on, the second switching device T2 is off, and vice versa. The control terminals of the first switching device T1 and the second switching device T2 (e.g., the gate of the PFET and the gate of the NFET) can be connected together as the input terminal of the first inverter INV1; the connection node between the first switching device T1 and the second switching device T2 can serve as the output terminal of the first inverter INV1. Similarly, the second inverter INV2 may also include a third switching device T3 (e.g., a PFET) and a fourth switching device T4 (e.g., an NFET), which can be turned off or on based on a signal received at a control terminal (e.g., a gate). The third switching device T3 and the fourth switching device T4 can be complementary in their on / off states; for example, when the third switching device T3 is on, the fourth switching device T4 is off, and vice versa. The control terminals of the third switching device T3 and the fourth switching device T4 (e.g., the gates of the PFET and the NFET) can be connected together as the input of the second inverter INV2; the connection node between the third switching device T3 and the fourth switching device T4 can serve as the output of the second inverter INV2.

[0030] In this embodiment, the number of first inverters INV1 is the same as the number of second inverters INV2, and can be an odd number greater than 1. It should be understood that multiple first inverters INV1 are connected sequentially, with the output of the last first inverter INV1 connected back to the input of the first first inverter INV1 to form the aforementioned ring topology. The second inverters INV2 are configured similarly, and will not be described in detail here.

[0031] As described above, the first inverter INV1 can operate in the first voltage domain; for example, the first inverter INV1 can be connected between the first voltage rail V0 and the second voltage rail V1. More specifically, the first switching device T1 (e.g., the source of a PFET) in the first inverter INV1 is connected to the second voltage rail V1, and the second switching device T2 (e.g., the source of an NFET) is connected to the first voltage rail V0. The second inverter INV2 can operate in the second voltage domain; for example, the second inverter INV2 can be connected between the second voltage rail V1 and the third voltage rail V2. More specifically, the first switching device T1 (e.g., the source of a PFET) in the second inverter INV2 is connected to the third voltage rail V2, and the second switching device T2 (e.g., the source of an NFET) is connected to the second voltage rail V1. The potential referred to here is the potential of the voltage rail relative to the ground signal, which will not be elaborated further. It should be understood that in some embodiments, the voltages of the first voltage rail V0, the second voltage rail V1, and the third voltage rail V2 can be regulated by an external voltage. For example, the voltage of the first voltage rail V0 may be 0 V, and after adjustment, the voltage of the first voltage rail may be 0.05 V. The voltage of the second voltage rail V1 may be 1 V, and after adjustment, the voltage of the first voltage rail may be 0.95 V. The voltage of the third voltage rail V2 may be 2 V, and after adjustment, the voltage of the third voltage rail V2 may be 2.05 V. It should be understood that this is only an example. In some embodiments, the potential difference between the first voltage rail V0 and the second voltage rail V1 may be different from (e.g., lower or higher than) the voltage difference between the second voltage rail V1 and the second voltage rail V2.

[0032] The first voltage domain and the second voltage domain may have a common voltage rail, such as the second voltage rail V1 in the above embodiment. More specifically, the first inverter INV1 (e.g., the source of the PFET) and the second inverter INV2 (e.g., the source of the NFET) may be connected together to the second voltage rail V1.

[0033] Furthermore, adjacent first inverters INV1 are connected via a connection node. For example, the output of the preceding first inverter INV1 is connected to the input of the immediately following first inverter INV1, forming the aforementioned connection node. It should be understood that the first and last first inverters INV1 are also adjacent inverters in the ring topology. Similarly, adjacent second inverters INV2 can also be connected via a connection node, and the first and last second inverters INV2 are also adjacent inverters in the ring topology.

[0034] As described above, the first inverter INV1 of the first ring oscillator and the second inverter INV2 of the second ring oscillator have the same number and both form a ring topology. Therefore, the number of connection nodes in the first ring oscillator and the second ring oscillator is the same. These connection nodes can correspond one-to-one with each other. Taking the first first inverter INV1 and the last first inverter INV1, and the first second inverter INV2 and the last second inverter INV2 as examples, the connection node between the first first inverter INV1 and the last first inverter INV1 can correspond to the connection node between the first second inverter INV2 and the last second inverter INV2. Similarly, the connection node between the first first inverter INV1 and the second first inverter INV1 can correspond to the connection node between the first second inverter INV2 and the second second second inverter INV2, and so on.

[0035] Furthermore, in this embodiment of the disclosure, the multi-voltage domain clock circuit may also include a first flying capacitor C1 between the connection nodes of adjacent first inverters INV1 in the first ring oscillator and the corresponding connection nodes of adjacent second inverters INV2 in the second ring oscillator.

[0036] Thus, the first ring oscillator and the second ring oscillator can achieve cross-domain coupling between the first voltage domain and the second voltage domain based on the first flying capacitor C1.

[0037] The multi-voltage domain synchronous clock circuit of this disclosure embodiment may further include a first clock signal output node CLK1 and a second clock signal output node CLK2. Furthermore, the first clock signal output node CLK1 and the second clock signal output node CLK2 can be respectively connected to the corresponding first connection node N1 in the first ring oscillator and the second ring oscillator. Thus, the first connection node N1 in the first ring oscillator and the corresponding first connection node N1 in the second ring oscillator can synchronously provide a first clock signal and a second clock signal in the first voltage domain and the second voltage domain, respectively, based on the "oscillation" of the first ring oscillator and the second ring oscillator.

[0038] According to embodiments of this disclosure, a first ring oscillator and a second ring oscillator can be coupled across a first flying capacitor C1 to a first voltage domain and a second voltage domain. In this process, a first connection node N1 in the first and second ring oscillators connected to the same first flying capacitor C1 can be connected to a first clock signal output node CLK1 and a second clock signal output node CLK2, respectively, so that the first clock signal output node CLK1 and the second clock signal output node CLK2 synchronously provide a first clock signal and a second clock signal, respectively, in the first and second voltage domains. Thus, each voltage domain generates and maintains its own local clock signal, and clock synchronization between different voltage domains can be achieved through low-power coupling. Furthermore, in embodiments of this disclosure, by using a circuit structure of ring oscillators coupled by flying capacitors, clock signals in different voltage domains within a chip can be automatically synchronized, driving devices in multiple voltage domains to operate. In addition, since the multi-voltage domain clock synchronization circuit of this disclosure can automatically generate and maintain clock signals in different voltage domains without the need for other devices, it can also be used as the operating clock for thermal insulation circuits.

[0039] Specifically, taking the first inverter INV1 and the second inverter INV2 (i.e., the first inverter INV1 and the second inverter INV2 connected via the same first flying capacitor C1) as an example, when the input signal is a low level ("0") signal, for example, the first switching device T1 (e.g., PFET) of the first inverter INV1 and the third switching device T3 (e.g., PFET) of the second inverter INV2 are turned on, which can electrically connect the first terminal of the first flying capacitor C1 to the second voltage rail V1 and the second terminal of the first flying capacitor C1 to the third voltage rail V2.

[0040] On the other hand, when the input signal is a high-level ("1") signal, for example, when the second switching device T2 (e.g., NFET) of the first inverter INV1 and the fourth switching device T4 (e.g., NFET) of the second inverter INV2 are turned on, the first terminal of the first flying capacitor C1 can be electrically connected to the first voltage rail V0, and the second terminal of the first flying capacitor C1 can be electrically connected to the second voltage rail V1.

[0041] According to embodiments of this disclosure, the input signal can toggle between a high-level ("1") signal and a low-level ("0") signal. In a ring topology, when the input of an inverter is low, resulting in a high-level output signal, this high-level signal passes through other inverters in the ring topology (the total number of inverters in the ring topology is odd, and the total number of inverters other than the first one is even), causing a high-level input signal to be input to the input of that inverter, thus toggling the inverter's state. In this way, a clock signal that toggles between high and low levels can be realized, the period of which can be determined by the total number of inverters in the ring topology. Accordingly, a first flying capacitor C1 can be connected between the first voltage rail V0 and the second voltage rail V1 during the first time period of the clock cycle, and between the second voltage rail V1 and the third voltage rail V2 during the second time period of the clock cycle. In the first time period, the first clock signal and the second clock signal may have high levels in the first voltage domain and the second voltage domain, respectively (corresponding to the level of the second voltage rail V1 and the level of the third voltage rail V2, respectively); in the second time period, the first clock signal and the second clock signal may have low levels in the first voltage domain and the second voltage domain, respectively (corresponding to the level of the first voltage rail V0 and the level of the second voltage rail V1, respectively).

[0042] More specifically, in the ring topology, each first inverter INV1 inverts the signal received from the upstream first inverter INV1 and outputs the inverted signal to the downstream first inverter INV1. Similarly, each second inverter INV2 in the ring topology inverts the signal received from the upstream second inverter INV2 and outputs the inverted signal to the downstream second inverter INV2. In this way, the signal is passed through the ring topology stage by stage, flipping between high and low levels. When the signal passes through an odd number of inverters in the ring topology, the level is flipped, thus achieving oscillation.

[0043] Taking the first inverter INV1 as an example again, since the first inverter INV1 causes a propagation delay, the oscillation frequency of the first ring oscillator is determined by the total delay. This total delay can be formed based on the number of stages of the first inverter INV1 and the propagation delay of each first inverter INV1. The second ring oscillator is similar and will not be elaborated further.

[0044] Because the first and second ring oscillators will "oscillate", the level of the same connection node will flip according to the oscillation frequency, for example from high level ("1") to low level ("0"), or from low level ("0") to high level ("1").

[0045] Thus, the first connection node N1 in the first ring oscillator and the corresponding first connection node N1 in the second ring oscillator can be based on the "oscillation" of the first ring oscillator and the second ring oscillator, so that the first clock signal output node CLK1 and the second clock signal output node CLK2 synchronously provide the first clock signal and the second clock signal in the first voltage domain and the second voltage domain, respectively.

[0046] In this embodiment, the multi-voltage domain synchronous clock circuit can be integrated into a chip. This chip can be a silicon-on-insulator (SOI) chip, a bulk silicon chip, or a three-dimensional stacked chip, etc. Because the multi-voltage domain synchronous clock circuit of this embodiment has strong process adaptability and does not depend on a specific process node, it can be implemented based on SOI technology, bulk silicon technology using triple-well technology, or three-dimensional (3D) device technology.

[0047] For three-dimensional stacked chips, different layers can have independent voltage domains. In response, the multi-voltage domain synchronous clock circuit based on embodiments of this disclosure can provide corresponding clock signals to devices operating on different layers. For example, when the first ring oscillator and the second ring oscillator are located on different layers of the three-dimensional stacked chip, the first ring oscillator and the second ring oscillator can provide a first clock signal and a second clock signal to devices on different layers, respectively. Thus, a multi-layer voltage and clock grid can be constructed for the three-dimensional stacked chip.

[0048] However, it should be understood that the multi-voltage domain synchronous clock circuit of the present disclosure embodiments is not limited to providing the aforementioned first clock signal and second clock signal for synchronization. Other clock signals provided by the multi-voltage domain synchronous clock circuit of the present disclosure embodiments will be described below with reference to the accompanying drawings.

[0049] Figure 2 A schematic diagram of a multi-voltage domain synchronous clock circuit according to another embodiment of the present disclosure is shown.

[0050] like Figure 2 As shown, the multi-voltage domain synchronous clock circuit of this embodiment may include a first ring oscillator based on a first inverter INV1, a second ring oscillator based on a second inverter INV2, a first flying capacitor C1, a first clock signal output node CLK1, and a second clock signal output node CLK2. In addition, the multi-voltage domain synchronous clock circuit may also include a first buffer BUF1 and a second buffer BUF2. The first buffer BUF1 is connected between the first clock signal output node CLK1 and the first connection node N1 of the first ring oscillator. The second buffer BUF2 is connected between the second clock signal output node CLK2 and the first connection node N1 of the second ring oscillator.

[0051] According to this embodiment, the first buffer BUF1 and the second buffer BUF2 can improve the quality of the first clock signal and the second clock signal without changing their phase and logic state, thereby improving the driving capability of the first clock signal and the second clock signal for the device. For example, each of the first buffer BUF1 and the second buffer BUF2 can include two cascaded inverters. The first inverter can amplify the signal from the connected first connection node N1, and the second inverter can flip the amplified signal, ensuring that the first clock signal and the second clock signal output by the first buffer BUF1 and the second buffer BUF2 are in phase with the signal from the first connection node N1. This improves the quality of the first clock signal and the second clock signal provided by the first clock signal output node CLK1 and the second clock signal output node CLK2.

[0052] In this embodiment, the first and second ring oscillators can be m-stage ring oscillators. For an m-stage ring oscillator, the signal will have two phase shifts after passing through each inverter stage. One phase shift may be a 180° phase shift due to the inverter inverting the signal, and the other phase shift may be an additional phase shift caused by the propagation delay of the signal in the inverter. Where m is a positive integer. Therefore, the total phase shift of the signal after passing through each stage of the inverter can be expressed as: That is, the phase shift between the clock signals corresponding to adjacent connected nodes in the same ring oscillator is... Based on this, the ring oscillator of this disclosure embodiment can synchronously provide different clock signals based on this clock phase shift, as described below with reference to the accompanying drawings.

[0053] Figure 3 A schematic diagram of a multi-voltage domain synchronous clock circuit according to another embodiment of the present disclosure is shown.

[0054] like Figure 3 As shown, the multi-voltage domain synchronous clock circuit of this embodiment may include a first ring oscillator based on a first inverter INV1, a second ring oscillator based on a second inverter INV2, a first flying capacitor C1, a first clock signal output node CLK1, and a second clock signal output node CLK2. Furthermore, the multi-voltage domain synchronous clock circuit of this embodiment may also include a third clock signal output node CLK3 and a fourth clock signal output node CLK4.

[0055] The third clock signal output node CLK3 and the fourth clock signal output node CLK4 are respectively connected to the second connection node N2 in the first and second ring oscillators, which is different from the first connection node N1. Thus, the third clock signal output node CLK3 and the fourth clock signal output node CLK4 can synchronously provide the third clock signal and the fourth clock signal in the first voltage domain and the second voltage domain, respectively. The third clock signal may have a first phase shift relative to the first clock signal, and the fourth clock signal may have a first phase shift relative to the second clock signal. For example, the first phase shift can be 0~360°. Figure 3 In the example, the first phase shift can be 216°.

[0056] Specifically, in this embodiment, the first and second ring oscillators are each 5-stage ring oscillators. Based on this, the signal transmitted in the first and second ring oscillators can have a phase shift after passing through each stage of the inverter as follows: .

[0057] Based on this, assuming the clock phase of the first connection node N1 is 0°, then the clock phase of the second connection node N2 in the above-mentioned 5-stage ring oscillator is 216°. It should be understood that, relative to the clock phase of the first connection node N1, the clock phase of the second connection node N2 here includes the aforementioned 180° phase shift and an additional 36° phase shift.

[0058] Similarly, relative to the clock phase of the first connection node N1, the clock phase of the third connection node N3 is 72°. It should be understood that when the signal propagates to the third connection node N3, the signal undergoes the same phase shift again; therefore, the clock phase of the third connection node N3 is... Based on this, after taking a 360° mold, we can obtain .

[0059] In addition, Figure 3 The system may also include a fourth connection node N4 and a fifth connection node N5. The clock phase shifts of these connection nodes (i.e., the clock phase shifts relative to the first connection node N1) can all follow the above physical laws, which will not be elaborated here.

[0060] Combined with the above Figure 2The described embodiments are similar, and buffers can be connected between the clock output node and the corresponding connection node in the ring oscillator. For example, a first buffer BUF1 can be connected between the first clock signal output node CLK1 and the first connection node N1 of the first ring oscillator. A second buffer BUF2 can be connected between the second clock signal output node CLK2 and the first connection node N1 of the second ring oscillator. A first buffer BUF1 can be connected between the third clock signal output node CLK3 and the second connection node N2 of the first ring oscillator. A second buffer BUF2 can be connected between the fourth clock signal output node CLK4 and the second connection node N2 of the second ring oscillator. Regarding the buffers, refer to the preceding description of the first buffer BUF1 and the second buffer BUF2, which will not be repeated here. Furthermore, it should be understood that the third connection node N3, the fourth connection node N4, and the fifth connection node N5, etc., can also be connected to the clock signal output node via buffers to provide different clock signals, which will not be repeated here.

[0061] Figure 4 A schematic diagram of a multi-voltage domain synchronous clock circuit according to another embodiment of the present disclosure is shown.

[0062] like Figure 4 As shown, the multi-voltage domain synchronous clock circuit of this embodiment may include a first ring oscillator based on a first inverter INV1, a second ring oscillator based on a second inverter INV2, a first flying capacitor C1, a first clock signal output node CLK1, a second clock signal output node CLK2, a third clock signal output node CLK3, and a fourth clock signal output node CLK4. Furthermore, the multi-voltage domain synchronous clock circuit of this embodiment may also include a fifth clock signal output node CLK5 and a sixth clock signal output node CLK6.

[0063] The fifth clock signal output node CLK5 and the sixth clock signal output node CLK6 are respectively connected to the third connection node N3 in the first and second ring oscillators, which are different from the first connection node N1 and the second connection node N2. In this way, the fifth clock signal output node CLK5 and the sixth clock signal output node CLK6 can synchronously provide the fifth clock signal and the sixth clock signal in the first voltage domain and the second voltage domain, respectively.

[0064] As described above, the third clock signal has a first phase shift relative to the first clock signal, and the fourth clock signal has a first phase shift relative to the second clock signal. In this embodiment, the first phase shift may be, for example, 200°. The fifth clock signal may have a second phase shift relative to the first clock signal that is different from the first phase shift, and the sixth clock signal may have a second phase shift relative to the second clock signal. For example, the second phase shift may be 0~360°. Specifically, the second phase shift may be 40°, etc.

[0065] Specifically, in this embodiment, the first and second ring oscillators are each 9-stage ring oscillators. Based on this, the signal transmitted in the first and second ring oscillators can have a phase shift of 180° + 20° = 200° after passing through each stage of inverters.

[0066] Based on this, assuming the clock phase of the first connection node N1 is 0°, then in the aforementioned 9-stage ring oscillator, the clock phase of the first connection node N1 is 0°, and the clock phase of the second connection node N2 is 200°. It should be understood that, relative to the clock phase of the first connection node N1, the clock phase of the second connection node N2 here includes the aforementioned 180° phase shift and an additional 20° phase shift. Similarly, the clock phase of the third connection node N3 is... The clock phase of the fourth connection node N4 is 240°. The clock phase of the fifth connection node N5 is 80°. The clock phase of the sixth connection node N6 is 280°. The clock phase of the seventh connection node N7 is 120°. The clock phase of the eighth connection node N8 is 320°. The clock phase of the ninth connection node N9 is 160°.

[0067] Combined with the above Figures 2-3The described embodiments are similar, and buffers can be connected between the clock output node and the corresponding connection node in the ring oscillator. For example, a first buffer BUF1 can be connected between the first clock signal output node CLK1 and the first connection node N1 of the first ring oscillator. A second buffer BUF2 can be connected between the second clock signal output node CLK2 and the first connection node N1 of the second ring oscillator. A first buffer BUF1 can be connected between the third clock signal output node CLK3 and the second connection node N2 of the first ring oscillator. A second buffer BUF2 can be connected between the fourth clock signal output node CLK4 and the second connection node N2 of the second ring oscillator. A first buffer BUF1 can be connected between the fifth clock signal output node CLK5 and the third connection node N3 of the first ring oscillator. A second buffer BUF2 can be connected between the sixth clock signal output node CLK6 and the third connection node N3 of the second ring oscillator. Regarding the buffers, refer to the preceding description of the first buffer BUF1 and the second buffer BUF2, which will not be repeated here.

[0068] It should be understood that, in the embodiments of this disclosure, other clock signal output nodes may also be included. The clock signals provided by other clock signal output nodes may have different phase shifts relative to the clock signals described above, which will not be elaborated here. It should also be understood that the fourth connection node N4, the fifth connection node N5, the sixth connection node N6, the seventh connection node N7, the eighth connection node N8, and the ninth connection node N9 may also be connected to the clock signal output nodes via buffers to provide different clock signals, which will not be elaborated here.

[0069] The above embodiments only illustrate a first ring oscillator operating in a first voltage domain and a second ring oscillator operating in a second voltage domain. According to other embodiments of this disclosure, the multi-voltage domain synchronous clock circuit may also include a third ring oscillator operating in a third voltage domain (e.g., 2-3 V) different from the first and second voltage domains.

[0070] Figure 5 A schematic diagram of a third ring oscillator according to an embodiment of the present disclosure is shown.

[0071] like Figure 5As shown, the third ring oscillator may include a predetermined number of third inverters INV3 connected in sequence to form a ring topology, a second flying capacitor C2 connecting the connection node between adjacent second inverters INV2 in the second ring oscillator and the corresponding connection node (e.g., a first connection node N1) between adjacent third inverters INV3 in the third ring oscillator, and a ninth clock signal output node. This ninth clock signal output node may be connected to the first connection node N1 in the third ring oscillator. Thus, the ninth clock signal output node can synchronously provide a ninth clock signal in the third voltage domain with the first clock signal output node CLK1 and the second clock signal output node CLK2 in a similar manner as described above.

[0072] However, it should be understood that the embodiments disclosed herein are not limited to this. In another embodiment, the second flying capacitor C2 may also be connected between the connection node between adjacent first inverters INV1 in the first ring oscillator and the corresponding connection node between adjacent third inverters INV3 in the third ring oscillator, which will not be elaborated here. In yet another embodiment of this disclosure, there may be multiple third ring oscillators. The third voltage domains in which each of the multiple third ring oscillators operates may be different from each other. The multi-voltage domain synchronous clock may also include third flying capacitors between corresponding connection nodes in adjacent third ring oscillators of the multiple third ring oscillators. In this way, the multiple third ring oscillators can synchronously provide clock signals based on the third flying capacitors via their respective clock signal output nodes, which will not be elaborated here.

[0073] Figure 6 A schematic diagram of a multi-voltage domain synchronous clock circuit according to another embodiment of the present disclosure is shown.

[0074] like Figure 6 As shown, the multi-voltage domain synchronous clock circuit of this embodiment further includes a first ring oscillator based on a first inverter INV1, a second ring oscillator based on a second inverter INV2, a first flying capacitor C1, a first clock signal output node CLK1, and a second clock signal output node CLK2. Furthermore, the multi-voltage domain synchronous clock circuit of this embodiment may also include a seventh clock signal output node CLK7 and an eighth clock signal output node CLK8.

[0075] The seventh clock signal output node CLK7 and the eighth clock signal output node CLK8 are respectively connected to the first connection node N1 of the first ring oscillator and the second ring oscillator. However, unlike the first clock signal output node CLK1 and the second clock signal output node CLK2, the seventh clock signal output node CLK7 and the eighth clock signal output node CLK8 can provide a seventh clock signal that is inverted with the first clock signal and an eighth clock signal that is inverted with the second clock signal, respectively.

[0076] Combined with the above Figure 2 The described embodiments are similar, and a buffer or an output inverter can be connected between the clock output node and the corresponding connection node in the ring oscillator. For example, a first buffer BUF1 is connected between the first clock signal output node CLK1 and the first connection node N1 of the first ring oscillator. A second buffer BUF2 is connected between the second clock signal output node CLK2 and the first connection node N1 of the second ring oscillator. A first output inverter INV1' is connected between the seventh clock signal output node CLK7 and the first connection node N1 of the first ring oscillator. A second output inverter INV2' is connected between the eighth clock signal output node CLK8 and the first connection node N1 of the second ring oscillator.

[0077] The first output inverter INV1' can output a seventh clock signal, which is inverted from the first clock signal (i.e., the first clock signal), via the seventh clock signal output node CLK7, based on the signal from the first connection node N1 of the first ring oscillator. The second output inverter INV2' can output an eighth clock signal, which is inverted from the second clock signal (i.e., the second clock signal), via the eighth clock signal output node CLK8, based on the signal from the first connection node N1 of the second ring oscillator.

[0078] In this embodiment of the disclosure, clock signals that are out of phase with each other can be output based on the same connection node, thereby providing multiple clock signals for devices operating in the same voltage domain to meet the clock signal requirements of each device operating in that voltage domain.

[0079] Figure 7 A schematic diagram of a multi-voltage domain synchronous clock circuit according to another embodiment of the present disclosure is shown.

[0080] like Figure 7 As shown, the multi-voltage domain synchronous clock circuit of this embodiment may include a delay-locked loop (LDL) and a ring oscillator. The LDL may include a series connection chain formed by cascading a predetermined number of first inverters INV1. The ring oscillator may include a predetermined number of second inverters INV2 connected sequentially to form a ring topology.

[0081] The multi-voltage domain synchronous clock circuit of this embodiment also includes a first flying capacitor C1 connected between the output terminals of each first inverter INV1 in the series connection chain and the output terminals of the corresponding second inverter INV2 in the ring oscillator. Furthermore, the multi-voltage domain synchronous clock circuit of this embodiment may also include a phase comparator and a processor. It should be understood that, in this embodiment, the aforementioned clock signal output nodes may also be included, for illustrative purposes only. Figure 7 Not shown in the image.

[0082] In this embodiment, Figure 7 The input of the leftmost first inverter INV1 (which can be considered the head first inverter INV1) can be connected to the reference clock terminal to receive the reference clock provided by the reference clock terminal. Figure 7 The output of the rightmost inverter INV1 (which can be considered the tail inverter INV1) generates the output clock. The phase comparator receives the reference clock and the output clock and compares their phases.

[0083] The processor can adjust the delay of the delay phase-locked loop (PLL) based on the comparison result of the phase comparator, so that the corresponding first and second inverters in the series-connected chain and the ring oscillator synchronously provide the first clock signal and the second clock signal in the first voltage domain and the second voltage domain, respectively. For example, the processor can be a flat-gain signal processing unit or an integrator signal processing unit. For example, in the embodiments of this disclosure, the delay of the PLL can be adjusted to adjust the parameters of the output clock (e.g., frequency and / or phase, etc.) so that the parameters of the output clock tend to be consistent with those of the reference clock. For example, the voltage of each voltage rail can be adjusted, the number of stages of the first and / or second inverters can be changed, the current output by each stage of the first and / or second inverters can be modulated, or even devices (e.g., PFETs, etc.) can be added between each first and / or second inverter and a specific voltage rail to adjust the on-time of the first and / or second inverters by controlling the on-time of the device, so that the parameters of the output clock tend to be consistent with those of the reference clock. Furthermore, in this embodiment, a frequency comparator can be used to compare the frequency of the reference clock and the frequency of the output clock so as to adjust the frequency according to the comparison result output by the frequency comparator.

[0084] In one embodiment, the output of the first inverter at the tail end can be selected to provide the first clock signal, and the output of the corresponding second inverter can be selected to provide the second clock signal. In another embodiment, the output of the first inverter located before the first inverter at the tail end can be selected to provide the first clock signal to adjust its phase. Furthermore, the output of the corresponding second inverter can be selected to provide the second clock signal. Thus, after the phase of the first clock signal is adjusted, the phase of the second clock signal will also change accordingly. This achieves synchronous adjustment of the first and second clock signals. Other synchronized clock signals can also be adjusted in this manner, which will not be elaborated here. It should also be understood that the above example only uses the case where the phase comparator is connected to the first ring oscillator; in some embodiments, the phase comparator can also be connected to the second ring oscillator, which will not be elaborated here.

[0085] As described above, the multi-voltage domain synchronous clock circuit of this disclosure supports cross-voltage domain tuning, frequency tuning, phase adjustment, and multi-voltage domain synchronization, and supports distributed, hierarchical, or adaptive control methods. Each voltage domain in this multi-voltage domain synchronous clock circuit has a corresponding local clock signal, and clock synchronization between different voltage domains is achieved based on a low-power signal coupling method, offering advantages such as high clock synchronization and low power consumption. This improves the performance of integrated circuits. Furthermore, in some embodiments, the duty cycle of the reference clock can be modulated by an external circuit, enabling the multi-voltage domain synchronous clock circuit of this disclosure to have an adjustable duty cycle.

[0086] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0087] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A multi-voltage domain synchronous clock circuit, comprising: A first ring oscillator operating in a first voltage domain and a second ring oscillator operating in a second voltage domain different from the first voltage domain, wherein the first ring oscillator includes a predetermined number of first inverters connected in sequence to form a ring topology, and the second ring oscillator includes the predetermined number of second inverters connected in sequence to form a ring topology. A first flying capacitor connecting the connection node between adjacent first inverters in the first ring oscillator and the corresponding connection node between adjacent second inverters in the second ring oscillator; and The first clock signal output node and the second clock signal output node are respectively connected to the corresponding first connection nodes in the first ring oscillator and the second ring oscillator, for synchronously providing the first clock signal and the second clock signal in the first voltage domain and the second voltage domain, respectively.

2. The multi-voltage domain synchronous clock circuit according to claim 1 further includes: The third clock signal output node and the fourth clock signal output node are respectively connected to the second connection nodes in the first ring oscillator and the second ring oscillator, which are different from the first connection node, to synchronously provide the third clock signal and the fourth clock signal in the first voltage domain and the second voltage domain, respectively, wherein the third clock signal has a first phase shift relative to the first clock signal, and the fourth clock signal has the first phase shift relative to the second clock signal.

3. The multi-voltage domain synchronous clock circuit according to claim 2 further includes: The fifth clock signal output node and the sixth clock signal output node are respectively connected to the third connection nodes in the first ring oscillator and the second ring oscillator, which are different from the first connection node and the second connection node, for synchronously providing the fifth clock signal and the sixth clock signal in the first voltage domain and the second voltage domain, respectively. The fifth clock signal has a second phase shift relative to the first clock signal, which is different from the first phase shift, and the sixth clock signal has the second phase shift relative to the second clock signal.

4. The multi-voltage domain synchronous clock circuit according to claim 1 further includes: The first buffer is connected between the first clock signal output node and the first connection node of the first ring oscillator; The second buffer is connected between the second clock signal output node and the first connection node of the second ring oscillator.

5. The multi-voltage domain synchronous clock circuit according to claim 4 further includes: The seventh clock signal output node and the eighth clock signal output node; A first output inverter is connected between the seventh clock signal output node and the first connection node of the first ring oscillator; The second output inverter is connected between the eighth clock signal output node and the first connection node of the second ring oscillator.

6. The multi-voltage domain synchronous clock circuit according to any one of claims 1 to 5, wherein, The first inverter is connected between the first voltage rail and the second voltage rail, and the second inverter is connected between the second voltage rail and the third voltage rail; During the first time period, the first clock signal and the second clock signal are respectively at high levels in the first voltage domain and the second voltage domain; during the second time period, the first clock signal and the second clock signal are respectively at low levels in the first voltage domain and the second voltage domain.

7. The multi-voltage domain synchronous clock circuit according to claim 6, wherein, The first inverter includes a first switching device and a second switching device connected in series between the first voltage rail and the second voltage rail. The control terminals of the first switching device and the second switching device are connected to the output terminal of the first inverter that is immediately preceding the first ring oscillator. The connection node between the first switching device and the second switching device serves as the output terminal of the first inverter. The second inverter includes a third switching device and a fourth switching device connected in series between the second voltage rail and the third voltage rail. The control terminals of the third switching device and the fourth switching device are connected together to the output terminal of the second inverter that is immediately preceding the second ring oscillator. The connection node between the third switching device and the fourth switching device serves as the output terminal of the second inverter.

8. The multi-voltage domain synchronous clock circuit according to any one of claims 1 to 5, further comprising: A third ring oscillator operating in a third voltage domain different from the first and second voltage domains includes the predetermined number of third inverters connected in sequence to form a ring topology. A second flying capacitor connecting the connection node between adjacent second inverters in the second ring oscillator and the corresponding connection node between adjacent third inverters in the third ring oscillator; as well as The ninth clock signal output node is connected to the connection node in the third ring oscillator corresponding to the first connection node, and is used to provide the ninth clock signal in the third voltage domain synchronously with the first clock signal output node and the second clock signal output node.

9. The multi-voltage domain synchronous clock circuit according to claim 8, wherein, The third ring oscillator is multiple, and the third voltage domain in which each of the multiple third ring oscillators operates is different from each other. The multi-voltage domain synchronization clock also includes a third flying capacitor between corresponding connection nodes in adjacent third ring oscillators among the multiple third ring oscillators.

10. The multi-voltage domain synchronous clock circuit according to any one of claims 1 to 5, wherein, The multi-voltage domain synchronous clock circuit is integrated into a chip; the chip is an SOI chip, a bulk silicon chip, or a three-dimensional stacked chip.

11. The multi-voltage domain synchronous clock circuit according to claim 10, wherein, The chip is a three-dimensional stacked chip, with the first ring oscillator and the second ring oscillator located on different layers of the three-dimensional stacked chip, so as to provide the first clock signal and the second clock signal to the devices on different layers respectively.

12. A multi-voltage domain synchronous clock circuit, comprising: A delay-locked loop includes a series connection chain of a predetermined number of first inverters, the first inverters operating in a first voltage domain, wherein the first inverter at the head of the series connection chain receives a reference clock and the first inverter at the tail generates an output clock. A ring oscillator, comprising the predetermined number of second inverters connected in sequence to form a ring topology, the second inverters operating in a second voltage domain different from the first voltage domain; A first flying capacitor is connected between the output terminal of each first inverter in the series connection chain and the output terminal of the corresponding second inverter in the ring oscillator; A phase comparator is used to compare the phases of the reference clock and the output clock; The processor is configured to adjust the delay of the delay-locked loop based on the comparison result of the phase comparator, so that the corresponding first inverter and second inverter in the series connection chain and the ring oscillator synchronously provide a first clock signal and a second clock signal in the first voltage domain and the second voltage domain, respectively.

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