A high voltage interlock loop monitoring system and method

Abstract

The application discloses a high-voltage interlocking loop monitoring system and method, and relates to the technical field of high-voltage safety of new energy vehicles. The system comprises a plurality of monitoring nodes, electronic switches, sampling units, storage units, control units and communication units. Each monitoring node is provided with a coded resistor connected in series to the interlocking loop, and the resistance values of the coded resistors are distributed according to a geometric progression. Each coded resistor is provided with an electronic switch connected in parallel at both ends. The control unit controls the on-off of the electronic switches. In a first mode, all coded resistors are bypassed to monitor the total resistance value of the loop. In a second mode, each coded resistor is connected to the loop one by one for independent measurement. The measured value is compared with the reference resistance value in the storage unit to determine the fault node. The application solves the positioning ambiguity problem of multiple concurrent faults through the segmentation sampling principle, has the functions of low-power operation, self-checking and calibration and dual-channel redundant fault tolerance, and significantly improves the fault positioning accuracy and functional safety of the high-voltage interlocking system.

Description

Technical Field

[0001] This invention belongs to the field of high-voltage safety technology for new energy vehicles, specifically relating to a precise location system and method for the breakpoint of a high-voltage interlock circuit, applicable to high-voltage electrical systems of pure electric vehicles, hybrid electric vehicles, fuel cell vehicles, etc. Background Technology

[0002] High-voltage interlocking is a key technology in the high-voltage safety system of new energy vehicles. Its basic principle is to connect all low-voltage monitoring contacts in the vehicle's high-voltage connectors, manual maintenance switches, high-voltage component covers, etc., into a closed loop. When any connector becomes loose or a cover is opened, the interlock loop breaks. Upon detecting this signal, the controller immediately cuts off the high-voltage relay, depressurizing the entire vehicle. However, in actual maintenance or troubleshooting scenarios, when the high-voltage interlock loop breaks, technicians face a dilemma: they can only determine that one loop is "broken," but there are dozens of connectors connected in series on that loop, making it impossible to pinpoint which connector is broken. They would need to disassemble and inspect all high-voltage connectors one by one, resulting in extremely low troubleshooting efficiency.

[0003] Currently, to address the aforementioned issues, a typical method for locating high-voltage interlock faults in existing technologies involves connecting a resistor with a different resistance value in parallel with each high-voltage connector. The fault location is determined by measuring the change in the total resistance of the circuit. For example, in patent publication number (CN120056736A), the fault location is determined by the different resistance values ​​when different interlock switches in the first detection branch are disconnected. However, this solution primarily targets single fault points. When multiple connectors experience poor contact simultaneously or multiple nodes disconnect simultaneously, the change in total resistance no longer possesses a unique mapping property. Combinations of different resistance values ​​may correspond to multiple possible fault point combinations, making accurate system analysis difficult. Summary of the Invention

[0004] To address the shortcomings of existing technologies, such as ambiguous resistance values ​​at multiple fault points, high static power consumption, and lack of self-testing and redundancy fault tolerance, this invention provides a high-voltage interlock circuit monitoring system and method. By using an coded resistor array in conjunction with an electronic switch bypass network and combining the principle of segmented sampling, independent measurement of each node is achieved. It also incorporates a built-in self-testing calibration and dual-channel redundant sampling architecture to achieve unambiguous fault location, low-power operation, and functional safety assurance.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A high-voltage interlock circuit monitoring system includes: multiple monitoring nodes, coded resistors, electronic switches, a sampling unit, a storage unit, and a control unit; each monitoring node is correspondingly located at a high-voltage connector in the high-voltage interlock circuit, and the coded resistor is connected in series in the high-voltage interlock circuit; each electronic switch is connected in parallel across each coded resistor, and the electronic switch has an on state and an off state; the sampling unit is electrically connected to the high-voltage interlock circuit, and measures the resistance value of the corresponding coded resistor when the electronic switch is in the off state, and outputs a resistance value detection signal; the storage unit stores the reference resistance value of the coded resistor of each monitoring node; and the control unit is connected to the control terminal of each electronic switch, the sampling unit, and the storage unit respectively.

[0007] Furthermore, the control unit controls each electronic switch to switch between on and off states, receives the resistance detection signal output by the sampling unit, compares this resistance detection signal with the reference resistance value in the storage unit, and determines the location of the monitoring node where the breakpoint occurred based on the comparison result; and the resistance value of the encoding resistor of the i-th monitoring node is... , where R is the reference resistance value and i is a positive integer.

[0008] Furthermore, the control unit has dual operating modes: in the first mode, all electronic switches are controlled to be in the on state, so that the sampling unit collects the total resistance value of the high-voltage interlock circuit at the first sampling frequency to determine whether there is an abnormality in the high-voltage interlock circuit; when the total resistance value is abnormal, it switches to the second mode, and in the second mode, each electronic switch is controlled to be switched to the off state in sequence, so that the sampling unit collects the resistance value of each coded resistor at the second sampling frequency; the second sampling frequency is higher than the first sampling frequency.

[0009] Furthermore, the sampling unit includes a constant current source and an analog-to-digital conversion module; the constant current source injects a constant current into the high-voltage interlock circuit, and the analog-to-digital conversion module is connected to both ends of the high-voltage interlock circuit to collect voltage signals to calculate resistance; the analog-to-digital conversion module includes a first analog-to-digital conversion channel and a second analog-to-digital conversion channel for synchronous sampling, and the control unit switches to the second analog-to-digital conversion channel when the first analog-to-digital conversion channel fails.

[0010] Furthermore, the system also includes a communication unit electrically connected to the control unit. After determining the location of the monitoring node, the control unit outputs fault information containing the fault node identifier through the communication unit.

[0011] The present invention also provides a method for monitoring high-voltage interlock circuits, comprising the following steps:

[0012] S1: Power-on initialization, self-test calibration, and acquisition of the initial resistance value of the coded resistor of each monitoring node, which is then stored as the reference resistance value;

[0013] S2: Enter the first mode, bypass all coded resistors, collect the total resistance value of the high voltage interlock circuit, and determine whether the total resistance value is abnormal.

[0014] S3: If the total resistance is abnormal, switch to the second mode, connect the coded resistor of each monitoring node to the high voltage interlock circuit in turn, and collect the current resistance value of each coded resistor.

[0015] S4: Compare the current resistance value of each coded resistor with the corresponding reference resistance value, determine the monitoring node with the resistance deviation as the fault node, and output the location information of the fault node.

[0016] Furthermore, in step S3, each coded resistor is individually connected to the high-voltage interlock circuit according to the binary search method; in step S4, the corresponding safety strategy is triggered according to the location of the fault node.

[0017] Furthermore, in step S4, the location information is sent to the vehicle controller or battery management system via the CAN bus, and the vehicle dashboard is controlled to display fault location prompt information.

[0018] Furthermore, in steps S1 and S3, resistance values ​​are acquired through the first analog-to-digital conversion channel and the second analog-to-digital conversion channel for synchronous sampling, and the acquisition is switched to the other channel when either channel fails.

[0019] Furthermore, the self-test calibration in step S1 includes: calibrating the constant current source accuracy of the sampling unit, the analog-to-digital conversion bias, and the on / off function of each electronic switch.

[0020] Compared with traditional solutions, the present invention has the following advantages:

[0021] (1) The present invention implements point-by-point selection and independent measurement of each monitoring node through an electronic switch array, so that the fault status of each node is determined independently, fundamentally avoiding the ambiguity problem of multi-point fault combination caused by resistance addition in the prior art, and realizing the unique and accurate identification of any number of fault points.

[0022] (2) In the first mode, all the coding resistors are bypassed by the electronic switch, the total resistance of the interlocking circuit is restored to the pure wire harness resistance, and the power consumption is close to zero; the coding resistors are only briefly connected in the second mode, which greatly reduces the risk of failure caused by long-term power supply of components.

[0023] (3) When the system of the present invention is powered on, it automatically performs constant current source accuracy calibration, ADC bias calibration and electronic switch function verification, establishes a reference resistor mapping table and stores it in non-volatile memory, thus eliminating the influence of temperature drift and device aging on measurement accuracy.

[0024] (4) The present invention adopts two independent ADCs to collect data synchronously and compare data in real time. When a single channel fails, it automatically switches to the other channel to ensure that the monitoring function is not lost due to a single hardware failure, and meets the safety level requirements of ISO 26262 ASIL C and above.

[0025] (5) The present invention can accurately output the name or location information of the specific fault node and report it through the CAN bus. Maintenance personnel do not need to check all high-voltage connectors one by one, and directly shorten the maintenance time from several hours to minutes. Attached Figure Description

[0026] This manual includes the following figures, which illustrate the following:

[0027] Figure 1 This is a block diagram of the overall hardware structure of the system of the present invention;

[0028] Figure 2 This is the overall logical flowchart of the method of the present invention;

[0029] Figure 3 A diagram illustrating the operating state of a single coded resistor provided in an embodiment of the present invention;

[0030] Figure 4 The diagram illustrates the working state of multiple coded resistors provided in this embodiment of the invention. Detailed Implementation

[0031] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, in order to help those skilled in the art to have a more complete, accurate and in-depth understanding of the concept and technical solutions of the present invention, and to facilitate its implementation.

[0032] like Figure 1As shown, the high-voltage interlock circuit monitoring system provided by this invention mainly includes multiple monitoring nodes, coded resistors, electronic switches, sampling units, storage units, control units, and communication units. The interlock contacts and connecting harnesses of each high-voltage connector are connected in series to form the main line of the high-voltage interlock circuit. A monitoring node is set at each high-voltage connector, and each monitoring node includes a coded resistor connected in series in the main line of the high-voltage interlock circuit. An electronic switch, preferably a MOSFET, is connected in parallel across the two ends of each coded resistor. Its source and drain are connected to the two ends of the coded resistor, and its gate is connected as a control terminal to the general-purpose input / output port of the control unit. The sampling unit includes a constant current source and an analog-to-digital converter module. The constant current source is connected in series in the high-voltage interlock circuit, injecting a preset constant current into the entire circuit; in this embodiment, the constant current is preferably 10mA. The input terminal of the analog-to-digital converter module is connected between the output terminal of the constant current source and the end of the circuit, acquiring the voltage signals at both ends of the circuit. The analog-to-digital conversion module internally includes a first analog-to-digital conversion channel and a second analog-to-digital conversion channel. These two channels independently and synchronously acquire the same voltage signal. The control unit compares the sampled data from the two channels in real time. When the deviation between any two channels exceeds a preset threshold, that channel is deemed faulty, and the system automatically switches to the other channel for independent operation. The control unit is electrically connected to the control terminals of each electronic switch, the data output terminal of the analog-to-digital conversion module, and the data port of the storage unit. The storage unit is preferably a non-volatile memory such as EEPROM or embedded Flash, storing the reference resistance value of the coded resistor for each monitoring node and preset parameters. The communication unit is preferably a CAN transceiver, connected to the CAN controller inside the control unit and connected to the vehicle controller and battery management system via the CAN bus.

[0033] In this embodiment, to achieve unique identifiability for any single-point or multi-point concurrent fault, the resistance values ​​of the coded resistors of each monitoring node are distributed according to a geometric progression. As a preferred embodiment, the common ratio of this geometric progression is 2, meaning the resistance value of the coded resistor of the i-th monitoring node is... Where R is the reference resistance value and i is a positive integer. In this embodiment, the reference resistance value R is taken as 10Ω, so the resistance values ​​of each node are 10Ω, 20Ω, 40Ω, 80Ω, and 160Ω respectively, and so on for subsequent nodes. The accuracy of each coded resistor is preferably ±0.5% or higher to ensure the accuracy of resistance measurement. The mathematical principle of this allocation scheme with a common ratio is that the sum of the resistance values ​​of any one or more nodes is not equal to the sum of the resistance values ​​of any other different combination of nodes. That is, each set of fault nodes uniquely corresponds to a binary number, where the i-th bit is 1 to indicate that the node is faulty and 0 to indicate that the node is normal. The decimal value of this binary number and the total resistance increment satisfy the relationship that the total resistance increment is equal to the decimal value multiplied by the reference resistance value R. Therefore, by measuring the total resistance increment, the unique distribution of fault nodes can be deduced. This uniqueness holds true in both single-point fault and multi-point concurrent fault scenarios.

[0034] like Figure 2 The diagram illustrates the complete workflow of the high-voltage interlock circuit monitoring method of the present invention. It includes the following steps.

[0035] S1: The control unit sequentially controls each electronic switch to the off state, allowing the coded resistor of each monitoring node to be individually connected to the high-voltage interlock circuit. Each time a coded resistor is connected, the constant current source injects a constant 10mA current into the circuit. The analog-to-digital converter (ADC) acquires the voltage signal across the circuit and calculates the initial resistance value of the coded resistor according to Ohm's law. The control unit writes this initial resistance value as the reference resistance value for that monitoring node into the reference resistance mapping table in the storage unit. Simultaneously, the control unit also executes the following self-test calibration sub-process: calibrating the output current accuracy of the constant current source; verifying that the deviation between the actual output current and the nominal value of 10mA is within ±0.5% using the built-in precision reference resistor; correcting the deviation by adjusting the adjustable reference inside the constant current source if it exceeds the limit; calibrating the bias and gain of the ADC module; and verifying the on / off function of each electronic switch to ensure the normal operation of all components of the system. After the self-test calibration is completed, the system automatically enters the first working mode.

[0036] S2: The control unit switches all electronic switches to the ON state, and each coded resistor is bypassed by its parallel MOSFET. At this time, the total resistance of the high-voltage interlock circuit main line is approximately equal to the sum of the resistances of each section of the wiring harness. A constant current source continuously injects a constant current of 10mA into the circuit. The analog-to-digital conversion module acquires the voltage across the circuit at the first sampling frequency. In this embodiment, the first sampling period is 100ms, i.e., the sampling frequency is 10Hz. The control unit calculates the total circuit resistance R based on the acquired voltage and constant current values. total And compare this value with the preset normal resistance range R in the storage unit. min ~R max Perform a comparison. If the calculated R... totalIf the value falls within this normal range, the high-voltage interlock circuit is considered to be in normal condition, and the monitoring process will continue to repeat this step with a period of 100ms. If R total If the value exceeds the normal range, it indicates that there is a break point fault or short circuit abnormality in the high-voltage interlock circuit, and the system will immediately and automatically switch to the second working mode.

[0037] S3: The control unit switches the sampling frequency from 100ms in the first sampling period to 1ms (1kHz) in the second sampling period, and begins the segmented sampling process. The control unit sequentially controls each electronic switch to the off state according to a preset scanning sequence. This preset scanning sequence is preferably a binary search sequence, pre-set according to fault occurrence frequency statistics or circuit topology priority, prioritizing scanning high-frequency fault nodes or key nodes involving the high-voltage main circuit. When the control unit controls the electronic switch of a monitoring node to turn off, the electronic switch changes from conducting to off. The previously short-circuited coded resistor is unblocked and connected in series separately to the high-voltage interlock circuit. At the same time, the electronic switches of all other monitoring nodes remain conducting, meaning their respective coded resistors are still bypassed. Therefore, only one coded resistor is effectively connected in the high-voltage interlock circuit at this time. A constant current of 10mA injected by the constant current source flows through this coded resistor. The analog-to-digital conversion module acquires the voltage across the circuit at a 1ms period and calculates the current resistance value. The control unit records this current resistance value and marks the corresponding monitoring node number. After completing the measurement at the current node, the control unit returns the electronic switch to the off state to bypass the coded resistor, and then moves to the next monitoring node to perform the same operation, thus completing the polling measurement of all N monitoring nodes one by one. In this embodiment, if there are 10 monitoring nodes in the loop, the entire segmentation sampling process can complete the data acquisition of all nodes within 10ms, resulting in extremely fast positioning speed.

[0038] S4: The control unit compares the current resistance value of each monitoring node with the corresponding reference resistance value stored in the reference resistance mapping table in the storage unit. For the i-th monitoring node, the control unit calculates the deviation ΔR between the current resistance value and the reference resistance value. i And compare the absolute value of the deviation with a preset deviation threshold. If ΔR i If the absolute value of ΔR is less than or equal to a preset threshold, the monitoring node is determined to be in normal condition; if ΔR iIf the absolute value of the current resistance is greater than a preset threshold and significantly greater than the reference resistance, the monitoring node is determined to have an open-circuit fault, meaning the high-voltage connector is disconnected or has poor contact. If the current resistance is significantly less than the reference resistance or even close to zero, the monitoring node is determined to have a short-circuit fault. The fault code "HVIL_FAULT Node Name" is then recorded. For example, if the current resistance of the PTC heater high-voltage connector is much greater than the reference resistance of 80Ω, the control unit determines that the node is faulty and records "HVIL_FAULT_PTC Heater High-Voltage Connector". After the control unit completes the individual determination of all nodes using the above method, a complete list of faulty nodes is obtained.

[0039] The control unit transmits fault information via the CAN bus to the vehicle controller or battery management system through the communication unit. The vehicle controller or battery management system then displays specific fault location information on the instrument panel, such as "Please check the PTC heater high-voltage connector." Simultaneously, the control unit triggers corresponding safety strategies based on the location and importance of the fault: if the fault is a critical node in the high-voltage main circuit, the high-voltage relay is disconnected and actively discharged; if it is a non-critical node, a power-limiting operation strategy is triggered, allowing the vehicle to travel to a service station in limp mode.

[0040] Figure 3 and Figure 4 The specific working relationship between the encoding resistor and the electronic switch is further described. Figure 3 The diagram illustrates the equivalent circuit of a single monitoring node. When the electronic switch is in the ON state, the source-drain junction of the electronic switch exhibits extremely low impedance, which is much smaller than the resistance of the encoding resistor. Therefore, all current flows through the electronic switch and bypasses the encoding resistor, effectively bypassing it. The resistance presented externally at the node is the ON resistance of the electronic switch. This state corresponds to normal operation in the first working mode. When the electronic switch is in the OFF state, the source-drain junction of the electronic switch exhibits extremely high impedance, approximating an open circuit. Current is forced to flow through the encoding resistor. The resistance presented externally at this node is the actual resistance value of the encoding resistor. This state corresponds to the segmented sampling measurement in the second working mode.

[0041] Figure 3 The overall topology of multiple monitoring nodes connected in series in a high-voltage interlocking circuit is shown. The coded resistors of each node are connected in parallel with the electronic switches, and the nodes are connected in series in the main line in the order of their numbers. The control terminal of the electronic switch of each monitoring node is independently connected to different general input and output ports of the control unit. The control unit can independently control the on / off state of any electronic switch without affecting the state of other electronic switches.

[0042] In this embodiment, the first and second analog-to-digital conversion channels of the analog-to-digital conversion module employ physically independent sample-and-hold circuits and analog-to-digital conversion cores. Both channels synchronously acquire the same analog voltage signal from both ends of the high-voltage interlock circuit and output their respective digital conversion results to the control unit. The control unit internally runs a channel health monitoring program. The control unit calculates the deviation between the sampled values ​​of the two channels in real time. If the deviation exceeds a preset threshold, the channel with the larger deviation is determined to be faulty, and the system automatically switches to the other healthy channel to operate independently, ensuring that a single channel hardware failure does not lead to the loss of monitoring functionality.

[0043] In this embodiment, the gate drive voltage of the N-channel MOSFET typically needs to reach above 10V to ensure full conduction. However, the general-purpose input / output (GPIO) ports of the control unit only output a logic high level of 3.3V or 5V. Therefore, the GPIO ports of the control unit need to be connected to the gates of each electronic switch via a drive circuit. This drive circuit includes a level shifter, a gate drive resistor, and a pull-down resistor. The level shifter converts the 3.3V logic high level output by the control unit into a 12V gate drive voltage to ensure the MOSFET is fully turned on. The gate drive resistor is used to limit the gate charging current and suppress oscillation. The pull-down resistor pulls the gate down to ground potential when the GPIO ports of the control unit are in a high-impedance state to prevent the MOSFET from being falsely turned on. In addition, each GPIO port is configured to output a low level by default after power-on reset, which controls all electronic switches to be in the off state by default. This ensures that each coded resistor is in the connected loop state before the system is fully initialized, ensuring that the resistance value of the high-voltage interlock circuit is always measurable and avoiding monitoring blind spots caused by the start-up delay of the control unit.

[0044] The role and effect of the embodiments

[0045] This invention combines electronic switch arrays with segmented sampling technology to achieve independent, point-by-point measurement of the resistance values ​​of each monitoring node in a high-voltage interlock circuit. This fundamentally overcomes the mathematical ambiguity in existing technologies where the total resistance change cannot uniquely map to the fault point in the event of multiple concurrent faults. Whether it's a single-point fault or a simultaneous multi-point fault, the system can accurately identify the specific location of each fault node and output a clear fault identifier, completely solving the industry problem of traditional solutions failing to locate faults or making incorrect location errors in multi-point fault scenarios.

[0046] This invention employs intelligent switching between dual operating modes. During normal vehicle operation, all coded resistors are bypassed via electronic switches, restoring the total resistance of the interlocking circuit to a pure wiring harness resistance. This results in near-zero static power consumption and significantly reduces the risk of component failure caused by prolonged energization of the coded resistors. When an anomaly is detected, the system automatically switches to a high-precision scanning mode, measuring the actual resistance of each node at millisecond-level speeds. This addresses the dual requirements of 24 / 7 real-time monitoring and accurate fault diagnosis, significantly improving the system's reliability and durability.

[0047] This invention incorporates a comprehensive self-calibration mechanism. Upon system power-up, it automatically performs constant current source accuracy calibration, analog-to-digital converter bias calibration, and electronic switch function verification. The actual initial resistance values ​​of each node are stored as reference values ​​in non-volatile memory. Subsequent fault determinations are based on these measured reference values ​​rather than theoretical nominal values, effectively eliminating the impact of temperature drift and component aging on measurement accuracy. Simultaneously, the dual-channel redundant sampling architecture enables synchronous acquisition and real-time comparison of two independent analog-to-digital conversion channels. Automatic and seamless switching occurs in case of single-channel failure, ensuring that monitoring functionality is not lost due to a single hardware failure, meeting the ASIL C level requirements of the ISO 26262 functional safety standard.

[0048] In summary, this invention not only significantly improves the fault diagnosis coverage and location accuracy of high-voltage interlock systems, reducing the traditional hourly troubleshooting time to minutes, thus greatly improving vehicle maintainability and user experience, but also comprehensively enhances the system's reliability, durability, and functional safety through the integrated application of low-power design, self-calibration mechanisms, and redundant fault-tolerant architecture. It can be widely applied to high-voltage safety systems in various new energy vehicles such as pure electric vehicles, hybrid electric vehicles, and fuel cell vehicles.

[0049] The present invention has been described above by way of example with reference to the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvements made using the inventive concept and technical solution; or the direct application of the inventive concept and technical solution to other situations without modification, are all within the protection scope of the present invention.

Claims

1. A high-voltage interlock circuit monitoring system, characterized in that, include: The system comprises multiple monitoring nodes, coded resistors, electronic switches, a sampling unit, a storage unit, and a control unit. Each monitoring node is correspondingly located at a high-voltage connector in a high-voltage interlock circuit. The coded resistor is connected in series in the high-voltage interlock circuit. Each electronic switch is connected in parallel across each coded resistor, and each electronic switch has an on state and an off state. The sampling unit is electrically connected to the high-voltage interlock circuit. When the electronic switch is in the off state, it measures the resistance value of the corresponding coded resistor and outputs a resistance detection signal. The storage unit stores the reference resistance value of the coded resistor of each monitoring node. The control unit is connected to the control terminal of each electronic switch, the sampling unit, and the storage unit, respectively.

2. The high-voltage interlock circuit monitoring system according to claim 1, characterized in that, The control unit controls each of the electronic switches to switch between an on and off state, receives the resistance detection signal output by the sampling unit, compares the resistance detection signal with the reference resistance value in the storage unit, and determines the location of the monitoring node where the breakpoint occurs based on the comparison result; and the resistance value of the encoding resistor of the i-th monitoring node is... , where R is the reference resistance value and i is a positive integer.

3. The high-voltage interlock circuit monitoring system according to claim 1, characterized in that, The control unit has dual operating modes: in the first mode, all the electronic switches are controlled to be in the on state, so that the sampling unit collects the total resistance value of the high voltage interlock circuit at a first sampling frequency to determine whether there is an abnormality in the high voltage interlock circuit; When the total resistance is abnormal, the system switches to the second mode. In the second mode, each of the electronic switches is sequentially switched to the off state, so that the sampling unit collects the resistance value of each of the coded resistors at a second sampling frequency. The second sampling frequency is higher than the first sampling frequency.

4. The high-voltage interlock circuit monitoring system according to claim 1, characterized in that, The sampling unit includes a constant current source and an analog-to-digital converter module; the constant current source injects a constant current into the high-voltage interlock circuit, and the analog-to-digital converter module is connected to both ends of the high-voltage interlock circuit to collect voltage signals to calculate resistance; the analog-to-digital converter module includes a first analog-to-digital converter channel and a second analog-to-digital converter channel for synchronous sampling, and the control unit switches to the second analog-to-digital converter channel when the first analog-to-digital converter channel fails.

5. The high-voltage interlock circuit monitoring system according to claim 1, characterized in that, The system also includes a communication unit electrically connected to the control unit. After determining the location of the monitoring node, the control unit outputs fault information containing the fault node identifier through the communication unit.

6. A monitoring method for a high-voltage interlock circuit monitoring system according to any one of claims 1-5, characterized in that, Includes the following steps: S1: Power-on initialization, self-test calibration, and acquisition of the initial resistance value of the coded resistor of each monitoring node, which is then stored as the reference resistance value; S2: Enter the first mode, bypass all the coded resistors, collect the total resistance value of the high voltage interlock circuit, and determine whether the total resistance value is abnormal; S3: If the total resistance value is abnormal, switch to the second mode, and connect the coded resistor of each monitoring node to the high-voltage interlock circuit in turn, and collect the current resistance value of each coded resistor respectively; S4: Compare the current resistance value of each of the coded resistors with the corresponding reference resistance value, determine the monitoring node with the resistance value deviation as the fault node, and output the location information of the fault node.

7. The high-voltage interlock circuit monitoring method according to claim 6, characterized in that, In step S3, each of the encoded resistors is individually connected to the high-voltage interlock circuit according to the binary search method; in step S4, the corresponding safety strategy is triggered according to the location of the fault node.

8. The high-voltage interlock circuit monitoring method according to claim 6, characterized in that, In step S4, the location information is sent to the vehicle controller or battery management system via the CAN bus, and the vehicle dashboard is controlled to display fault location prompt information.

9. The high-voltage interlock circuit monitoring method according to claim 6, characterized in that, In steps S1 and S3, resistance values ​​are acquired through the first analog-to-digital conversion channel and the second analog-to-digital conversion channel for synchronous sampling, and the acquisition is switched to the other channel when either channel fails.

10. The high-voltage interlock circuit monitoring method according to claim 6, characterized in that, The self-test calibration in step S1 includes calibrating the constant current source accuracy, analog-to-digital conversion bias, and on / off function of each electronic switch of the sampling unit.

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