A digital down conversion method for high-precision PRI waveform of airborne radar
By separating the filtering and data extraction of digital downconversion and employing counting extraction and multiplier multiplexing techniques, the problem of limited PRI cycle accuracy in airborne radar was solved, achieving high-precision waveform design and improved anti-interference capability.
Patent Information
- Application Number
- CN202611306218.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-26
- Publication Date
- 2026-11-03
AI Technical Summary
In traditional airborne radar digital downconversion methods, the binding of digital filtering and data extraction limits the accuracy of the PRI period, makes it impossible to extract non-integer points, restricts the expansion of waveform types, and cannot effectively support anti-interference design.
The filtering and data extraction of digital downconversion are separated. The signal within the effective sampling window is extracted in integer multiples by counting extraction method, and invalid signals within the receiving block are discarded. A multi-channel digital mixer and filter multiplier multiplexing architecture is adopted to improve the FPGA processing capability.
The accuracy of the PRI period of the airborne radar waveform has been improved, the variety of waveforms has been increased, the anti-interference performance has been enhanced, and the multi-channel processing capability and detection performance have been improved.
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Figure CN123029471A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of airborne radar digital intermediate frequency reception and FPGA-based digital downconversion technology, specifically relating to a digital downconversion method for high-precision PRI waveforms in airborne radar. Background Technology
[0002] With airborne radar detection increasingly hampered by electronic interference, airborne radar needs to continuously enhance its anti-jamming measures to cope with complex electronic environments. Expanding the variety of airborne radar waveforms is an effective way to increase the difficulty of detection, and improving the PRI period accuracy of airborne radar waveforms is one of the important methods for expanding the variety of waveforms.
[0003] The accuracy of the PRI period in airborne radar waveforms is typically limited by the baseband signal data rate after digital down-conversion data extraction. Effective accumulation of one frame of echo signal requires that the phase of each PRI echo signal be continuous; therefore, the PRI period... Data rate with baseband signal Must meet It is an integer. For example, when the digital down-conversion baseband signal data rate is... Traditional designs require an PRI period accuracy of 1µs for airborne radar waveforms; however, when the baseband signal data rate is... When the PRI period accuracy of the airborne radar waveform is 0.2µs, then the accuracy of the PRI period is 0.2µs.
[0004] The design limitations of PRI period accuracy in airborne radar waveforms are primarily due to the need to conserve FPGA resources during digital down-conversion processing of digital intermediate frequency (IF) sampling reception. This is achieved by leveraging the simultaneous digital filtering and data decimation capabilities of FIR filters, which utilize a filtering-decimation-while-filtering algorithm architecture to significantly reduce FPGA resource usage. However, this traditional design approach, which combines digital down-conversion filtering and decimation, while reducing FPGA resource consumption, has significant drawbacks in the face of increasingly severe electromagnetic interference. It cannot achieve integer-point decimation processing for airborne radar waveforms with higher PRI period accuracy, limits the expansion of airborne radar waveform types, and to some extent, fails to effectively support the design of anti-jamming waveforms for airborne radar.
[0005] In view of the aforementioned technical problems, this application is hereby submitted. Summary of the Invention
[0006] The purpose of this application is to address the need to increase the variety of airborne radar waveforms by improving the accuracy of the PRI period in the context of airborne radar anti-jamming. Traditional digital intermediate frequency receivers, based on FPGA-based digital down-conversion, bind digital filtering and data extraction, and cannot effectively handle the PRI period. Data rate with baseband signal Between To address the issue of limiting waveform variety expansion by performing decimation processing on non-integer waveforms, this paper proposes a digital down-conversion method for high-precision PRI waveforms in airborne radar. This method separates the traditional integrated digital down-conversion filtering and decimation processing, and uses counting decimation to reduce the speed of signals within sampling windows of different baseband data rates, thereby improving the digital intermediate frequency reception and processing capability for high-precision PRI waveforms in airborne radar.
[0007] The technical solution of this application is:
[0008] A digital down-conversion method for high-precision PRI waveforms in airborne radar includes:
[0009] Multiplexing of multi-channel digital mixer multipliers:
[0010] Based on the digital intermediate frequency receiver sampling rate and FPGA digital down-conversion high-speed processing clock Determine the parallelism of the multiplier multiplexing in multi-channel receiving digital mixer and digital filter. ;
[0011] Divide the receiving channel into Group, among which, For the total number of receiving channels, each group Each channel uses FPGA digital down-conversion high-speed clock processing. Digital mixing is achieved through a multiplier multiplexing architecture;
[0012] Multiplexing of multi-channel digital filter multipliers:
[0013] Digital filtering is based on the number of filter coefficients ,use Multiplexed multipliers simultaneously perform coefficient multiplication, combining all... The results of multiplying the digital filters are summed to obtain the final digital filter result.
[0014] Effective sampling window signal count data extraction:
[0015] According to the PRI cycle Effective width of sampling window FPGA digital down-conversion high-speed processing clock and the parallelism of the multiplexed digital mixer multiplier for multi-channel reception. By optimizing the effective sampling window The internal data is processed by counting points to achieve integer multiple data extraction, and the receiving data is blocked. Invalid signals are not extracted or discarded.
[0016] According to at least one embodiment of this application, in the above-described digital down-conversion method for high-precision PRI waveforms for airborne radar, during the multiplexing of the multi-channel digital mixer multiplier, when the digital intermediate frequency receiver sampling rate... Larger than the FPGA digital down-conversion high-speed processing clock In this process, the digital downconversion is split into two cascaded stages. The first stage uses the digital downconversion method and performs a first decimation of the signal to obtain a lower speed signal. The second stage processes the signal through a multiplexed digital mixer architecture.
[0017] According to at least one embodiment of this application, in the above-described digital down-conversion method for high-precision PRI waveforms for airborne radar, the multi-channel digital filter multiplier multiplexing is achieved through... A multiplexed multiplier, employing FPGA digital down-conversion high-speed clock processing. ,accomplish The process involves multiplying each filter coefficient separately.
[0018] According to at least one embodiment of this application, in the above-described digital down-conversion method for high-precision PRI waveforms for airborne radar, the baseband data rate after digital down-conversion decimation is [not specified in the original text]. ,in, The data extraction factor for digital downconversion;
[0019] Effective width of sampling window Data extraction is performed on the internal signal, and the number of baseband sample points for the received echo signal at each PRI is [number missing]. It is an integer.
[0020] According to at least one embodiment of this application, in the above-described digital down-conversion method for high-precision PRI waveforms for airborne radar, the effective sampling window... Internal signals are extracted, specifically as follows:
[0021] Within the effective sampling window Internal high-speed clock processing via FPGA digital down-conversion The generated count value is The cyclic counter, and the receiving block The counter will be reset to zero.
[0022] Each count to At that time, the digitally filtered signal of the corresponding multiplexed channel is selected to obtain the extracted baseband signal sample points;
[0023] For receiving block The signal is not extracted and the data is discarded directly. Attached Figure Description
[0024] Figure 1A high-efficiency digital downconversion architecture diagram provided in the embodiments of this application;
[0025] Figure 2 Data timing diagram for multiplier multiplexing provided in embodiments of this application;
[0026] Figure 3 A diagram illustrating a multiplier multiplexing calculation method provided in this application embodiment;
[0027] Figure 4 A diagram illustrating the digital filtering calculation method provided in an embodiment of this application;
[0028] Figure 5 This is a timing diagram of the counting extraction process provided in an embodiment of this application.
[0029] To better illustrate this embodiment, some content in the accompanying drawings may be omitted, enlarged, or reduced. They are for illustrative purposes only and should not be construed as limiting the scope of this application. Detailed Implementation
[0030] To make the technical solution and advantages of this application clearer, the technical solution of this application will be described in a clearer and more complete manner below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only some embodiments of this application, and are only used to explain this application, not to limit this application. It should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, and other related parts can be referred to the general design.
[0031] Furthermore, unless otherwise defined, the technical or scientific terms used in this application description shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The word "comprising" as used in this application description indicates that the concept preceding the word encompasses the concepts listed following the word and their equivalents, without excluding other related concepts.
[0032] Because the airborne radar processing system only processes the PRI cycle Remove receiver block Effective sampling window outside The signals inside are processed ( ), then only the effective sampling window is needed Data rate with baseband signal satisfy The result should be an integer. Based on the characteristics of airborne radar waveforms and signal processing, this application provides a digital down-conversion method for high-precision PRI waveforms in airborne radar. This method decouples digital filtering and data extraction in digital down-conversion and uses a counting method to manage the effective sampling window. The internal signal is decimated by an integer multiple and the receiver is blocked. Invalid signals are not extracted and are discarded directly.
[0033] The digital down-conversion method for high-precision PRI waveforms in airborne radar employs a counting and decimation approach for the effective sampling window. The internal signal is decimated by an integer multiple, and then the receiving block is increased. The accuracy can effectively improve the PRI cycle accuracy to the timing reference clock when designing airborne radar waveforms.
[0034] Since the generation and reception of airborne radar waveforms depend on various timing pulses, the minimum accuracy of the PRI period is the system's timing reference clock. The digital intermediate frequency receiver sampling rate It is usually set to an integer multiple of the timing reference clock, that is... , Since the value is an integer, the method in this application is set to address the PRI period accuracy of airborne radar waveforms. Design requirements.
[0035] Airborne radar typically includes multiple digital intermediate frequency (IF) receiving channels. The key to the method in this application is that it separates the digital filtering and data extraction processes of digital down-conversion, and uses a counting method to select the effective sampling window. The internal signal is decimated. However, this filtering and decimation splitting method violates the principle of maximizing FPGA resource conservation and will inevitably lead to a significant increase in the critical multiplier resources of the FPGA. Therefore, the prerequisite for implementing the counting decimation project is to realize digital mixing and digital filtering based on the FPGA multiplier multiplexing architecture.
[0036] This application relates to a digital down-conversion method for high-precision PRI waveforms in airborne radar. The technical implementation scheme includes a multi-channel digital mixer multiplier multiplexing design, a multi-channel digital filter multiplier multiplexing design, and an effective sampling window signal counting data extraction design.
[0037] For digital down-conversion and counting decimation of high-precision PRI waveforms in airborne radar, an FPGA-based algorithm implementation architecture is as follows: Figure 1 As shown.
[0038] Multiplexing of multi-channel digital mixer multipliers:
[0039] Based on the digital intermediate frequency receiver sampling rate and FPGA digital down-conversion high-speed processing clock Determine the parallelism of the multiplier multiplexing in multi-channel receiving digital mixer and digital filter. .
[0040] If the total number of receiving channels is One, and The receiving channel will then be divided into Groups, each group Each channel uses FPGA digital down-conversion high-speed clock processing. Digital mixing is achieved through a multiplier multiplexing architecture.
[0041] The timing sequence for processing multi-channel intermediate frequency received signals using the multiplier multiplexing digital mixing method is as follows: Figure 2 As shown. Due to the FPGA digital down-conversion high-speed processing clock. It is the original digital intermediate frequency receiver sampling rate. of Times, in use When processing each channel signal, each sample point can obtain The same data: i.e. Figure 2 The first sample point of the middle channel 1 go through After processing indivual They are the same number, from channel 2 to channel 3. And so on. Each sample point in each channel is processed by the FPGA digital down-conversion high-speed clock. All are then processed into The same data.
[0042] The method for calculating the multiplication of digital mixing coefficients by multiplexing multipliers is as follows: Figure 3 As shown:
[0043] (a) High-speed clock processing using FPGA digital down-conversion The generated count is A loop counter;
[0044] (b) For the first sample point, channel 1 data is processed when the counter is 1. The data from channel 2 is mixed with the multiplier in a digital frequency mixing operation, and when the counter is 2, the data from channel 2 is... Digital mixing is performed with the multiplier, and so on, with the counter as... Time will pass data Perform digital mixing operations with the multiplier;
[0045] (c) The same processing method as the first sample point is used for the second and all subsequent sample points.
[0046] Using the method described above, a multiplier in the FPGA is time-division multiplexed to achieve... Digital mixing calculation processing for each channel, compared to traditional methods using The method of simultaneous processing by multiple multipliers, employing a multiplier multiplexing digital mixer architecture, effectively reduces the number of FPGA multiplier resources required to the original level. .
[0047] However, when the digital intermediate frequency receiver sampling rate Larger than the FPGA digital down-conversion high-speed processing clock In such cases, a multiplexed digital mixer architecture cannot be directly used. In this application scenario, the digital downconversion can be split into two cascaded stages. The first stage uses a traditional digital downconversion method and performs a first decimation of the signal to obtain a lower-speed signal. Then, the second stage processes the signal using a multiplexed digital mixer architecture, while still achieving the goal of saving FPGA resources to the greatest extent.
[0048] Multiplexing of multi-channel digital filter multipliers:
[0049] Digital filtering is a further processing of the results of digital mixing. Unlike digital mixing, which only requires a single multiplier, digital filtering requires processing based on the number of filter coefficients. ,use Multiplexed multipliers perform coefficient multiplication simultaneously.
[0050] A method for calculating the multiplication of digital filter coefficients using multiplexed multipliers in a multi-channel digital filter is described, such as... Figure 4 As shown. (Through) A multiplexed multiplier, employing FPGA digital down-conversion high-speed clock processing. ,accomplish The process of multiplying each filter coefficient separately is consistent with the multi-channel digital mixer multiplexing method described above. After the multipliers perform coefficient multiplication and reuse processing, then all the multipliers are used... The results of multiplying the digital filters are summed to obtain the final digital filter result.
[0051] Digital filter multiplier multiplexing design Each receiving channel is multiplexed A multiplier is used to implement digital filtering, which is much faster than traditional methods. One multiplier, multiplier resources reduced to the original This further reduces FPGA resource overhead.
[0052] Effective sampling window signal count data extraction:
[0053] According to the PRI cycle Effective width of sampling window FPGA digital down-conversion high-speed processing clock and the parallelism of the multiplexed digital mixer multiplier for multi-channel reception. By optimizing the effective sampling window The internal data is processed by counting points to achieve integer multiple data extraction, and the receiving data is blocked. Invalid signals are not extracted or discarded.
[0054] Airborne radar transmit waveform PRI period The sampling window period is the same as the receiving window period. Let the data decimation factor of the digital down-conversion be... The baseband data rate after digital down-conversion decimation Then the number of baseband sample points for each PRI receiving the echo signal is .
[0055] If the traditional digital down-conversion flow extraction method is used to process all sample signals after digital filtering... The number of baseband signal samples obtained after decimation is 100%. ;if If the value is not an integer, traditional data extraction methods cannot process the sample points in the fractional part, which leads to accumulated errors and causes abnormalities in subsequent airborne radar signal processing.
[0056] However, because the airborne radar processing system only processes the valid time of the receiving sampling window... The echo signal inside is processed and received by the block. There is no echo, so only the effective width of the sampling window needs to be considered. Data extraction is performed on the internal signal; waveform parameters only need to be designed. It can be an integer.
[0057] Count data extraction is the effective sampling window Internal signals are extracted, and the processing timing is as follows: Figure 5 As shown:
[0058] (a) To ensure that each effective sampling window The effective signal is extracted and processed within the effective sampling window. The count is reset and cleared on the falling edge of the pulse, within the effective sampling window. Internal high-speed clock processing via FPGA digital down-conversion The generated count value is The cyclic counter, and the receiving block The counter will be reset to zero.
[0059] (b) In each count to At that time, the digitally filtered signal of the corresponding multiplexed channel is selected to obtain the extracted baseband signal sample points;
[0060] (c) For receiving block The signal is not extracted and the data is discarded directly;
[0061] (d) By analogy, the counting and extraction processing of each PRI echo signal is realized.
[0062] The digital down-conversion method for high-precision PRI waveforms in airborne radar disclosed in the above embodiments addresses the design requirement of improving the PRI period accuracy of airborne radar anti-jamming waveforms. When performing digital intermediate frequency reception and digital down-conversion processing based on FPGA, it reduces the resources required for multi-channel reception digital mixing and digital filtering by multiplexing FPGA multipliers, and uses a counting method to achieve data speed-down processing, offering the following advantages:
[0063] Enhanced multi-channel digital down-conversion processing capabilities: By increasing the FPGA processing clock speed to the required baseband data rate. Times, to achieve Each receiving channel uses a multiplexer for digital mixing and filtering, reducing the number of FPGA multipliers required to the level of traditional methods. This enhances the FPGA-based digital down-conversion multi-channel receiving and processing capabilities.
[0064] It improves the ability to process anti-jamming waveforms of airborne radar: by splitting digital filtering and data extraction, it uses a counting method to extract signals in the effective sampling window in integer multiples, while discarding signals with non-integer points of the received block, thus changing the drawback of traditional data pipeline extraction that makes it impossible to extract non-integer points.
[0065] It improves the flexibility of PRI period accuracy design for airborne radar waveforms and effectively improves the accuracy of waveform parameters to the timing reference clock, thereby increasing the detection performance of airborne radar. It also enhances the anti-jamming performance of airborne radar in terms of the variety of waveform period types and high accuracy.
[0066] The digital down-conversion method for high-precision PRI waveforms of airborne radar disclosed in the above embodiments can be widely applied to digital down-conversion processing of multi-channel narrowband receivers in airborne radar, increasing the number of receiving and processing channels in a single module, and adapting to higher-precision non-integer PRI waveform designs. It is an important method to improve the anti-interference waveform processing capability of airborne radar.
[0067] The technical solution of this application has been described in conjunction with the preferred embodiments shown in the accompanying drawings. Those skilled in the art should understand that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.
Claims
1. A digital down-conversion method for high-precision PRI waveforms in airborne radar, characterized in that, include: Multiplexing of multi-channel digital mixer multipliers: Based on the digital intermediate frequency receiver sampling rate and FPGA digital down-conversion high-speed processing clock Determine the parallelism of the multiplier multiplexing in multi-channel receiving digital mixer and digital filter. ; Divide the receiving channel into Group, among which, For the total number of receiving channels, each group Each channel uses FPGA digital down-conversion high-speed clock processing. Digital mixing is achieved through a multiplier multiplexing architecture; Multiplexing of multi-channel digital filter multipliers: Digital filtering is based on the number of filter coefficients ,use Multiplexed multipliers simultaneously perform coefficient multiplication, combining all... The results of multiplying the digital filters are summed to obtain the final digital filter result. Effective sampling window signal count data extraction: According to the PRI cycle Effective width of sampling window FPGA digital down-conversion high-speed processing clock and the parallelism of the multi-channel receiving digital mixer multiplier. By optimizing the effective sampling window The internal data is processed by counting points to achieve integer multiple data extraction, and the receiving data is blocked. Invalid signals are not extracted or discarded.
2. The digital down-conversion method for high-precision PRI waveforms in airborne radar according to claim 1, characterized in that, In multi-channel digital mixer multiplier multiplexing, when the digital intermediate frequency receiver sampling rate... Larger than the FPGA digital down-conversion high-speed processing clock In this process, the digital downconversion is split into two cascaded stages. The first stage uses the digital downconversion method and performs the first decimation of the signal to obtain a lower speed signal. The second stage processes the signal through a multiplexed digital mixer architecture.
3. The digital down-conversion method for high-precision PRI waveforms in airborne radar according to claim 2, characterized in that, In the multiplexing of multi-channel digital filter multipliers, through A multiplexed multiplier, employing FPGA digital down-conversion high-speed clock processing. ,accomplish The process involves multiplying each filter coefficient separately.
4. The digital down-conversion method for high-precision PRI waveforms in airborne radar according to claim 3, characterized in that, In the effective sampling window signal counting data extraction, the baseband data rate after digital down-conversion extraction ,in, The data extraction factor for digital downconversion; Effective width of sampling window Data extraction is performed on the internal signal, and the number of baseband sample points for the received echo signal at each PRI is [number missing]. It is an integer.
5. The digital down-conversion method for high-precision PRI waveforms in airborne radar according to claim 4, characterized in that, For the effective sampling window Internal signals are extracted, specifically as follows: Within the effective sampling window Internal high-speed clock processing via FPGA digital down-conversion The generated count value is The cyclic counter, and the receiving block The counter will be reset to zero. Each count to At that time, the digitally filtered signal of the corresponding multiplexed channel is selected to obtain the extracted baseband signal sample points; For receiving block The signal is not extracted and the data is discarded directly.