A risc-v random hyper-heuristic method based on learning-guided search budget allocation
By predicting optimization potential using a large language model and combining it with the restart MCMC algorithm, the problems of resource waste and low verification efficiency in RISC-V compilation optimization are solved, achieving more efficient super-optimization search and optimized code discovery.
Patent Information
- Application Number
- CN202610889428.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-18
- Publication Date
- 2026-11-03
AI Technical Summary
Existing RISC-V compilation optimization methods struggle to discover non-intuitive optimal instruction sequences on a global scale, and traditional methods cannot dynamically adjust verification strategies, leading to resource waste and low verification efficiency.
The search time budget is allocated using the optimization potential prediction value based on a large language model, and combined with the restart Markov chain Monte Carlo algorithm, the test case set is dynamically adjusted to optimize the instruction sequence of RISC-V basic blocks.
It improves the utilization of computing resources and verification efficiency, and significantly enhances the efficiency of super-optimization search and the quality of optimization code.
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Figure CN123030283A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of computer compiler optimization technology, and in particular relates to a RISC-V stochastic superoptimization method based on learning-guided search budget allocation. Background Technology
[0002] Currently, compiler optimization for Reduced Instruction Set Computing (RISC-V) architectures primarily relies on pre-defined heuristics employed by traditional compilers (such as the -O3 level optimizations in compilers like LLVM and GCC). These methods improve program performance through local instruction manipulation, but due to the exponential expansion of the instruction space and complex data flow dependencies, it is difficult to discover non-intuitive optimal instruction sequences globally. To address this, researchers have proposed super-optimization techniques that overcome the optimization bottleneck of traditional compilers by searching for semantically equivalent but less costly instruction sequences throughout the entire program space. Among these, stochastic super-optimization methods based on Markov Chain Monte Carlo (MCMC) algorithms (such as the STOKE tool) demonstrate strong search capabilities and can handle relatively complex instruction sequences. However, these methods still face two key challenges in practical applications: resource allocation for search and verification efficiency.
[0003] Specifically, existing stochastic superoptimization methods typically allocate a uniform, fixed search time to all basic blocks to be optimized. However, in practical applications, many basic blocks optimized by modern compilers tend to be locally or even globally optimal, or are difficult to improve within a limited time through random perturbations due to strong data flow dependencies. This results in a significant waste of computational resources on basic blocks lacking optimization space. Furthermore, in the process of correctness verification based on test cases, there is a fundamental contradiction in the number of test cases: too few test cases can increase search throughput, but may easily misclassify semantically unequal code sequences as equivalent, potentially leading to runtime errors; too many test cases can enhance verification accuracy, but will significantly reduce search efficiency due to excessive computational overhead. Traditional methods rely on fixed loss functions and static test sets, making it impossible to dynamically adjust verification strategies during the search process, thus making it difficult to achieve efficient superoptimization while ensuring correctness. Summary of the Invention
[0004] To address the aforementioned technical problems, this invention provides a RISC-V stochastic superoptimization method based on learning-guided search budget allocation, comprising: Based on the target RISC-V basic block, large language models are used to generate predicted values of optimization potential. Based on the predicted optimization potential, allocate a search time budget to the target RISC-V basic block; Based on the search time budget, a search and verification loop based on the restart Markov chain Monte Carlo algorithm is executed to obtain the optimized instruction sequence.
[0005] Preferably, the process of obtaining the predicted value of the optimization potential includes: The target RISC-V basic block is input into a pre-trained large language model. The large language model is guided by prompt words to output the probability value that the target RISC-V basic block has a semantically equivalent and lower-cost rewrite instruction sequence, which is used as the optimization potential prediction value.
[0006] Preferably, the process of allocating the search time budget includes: Obtain the basic time budget and perform a nonlinear transformation on the predicted value of the optimization potential to obtain the predicted value after contrast enhancement; The search time budget for the target RISC-V basic block is calculated based on the base time budget and the contrast-enhanced prediction value.
[0007] Preferably, the process of executing the search and verification loop based on the restarted Markov chain Monte Carlo algorithm includes: Initialize the current instruction sequence of the Markov chain and set up an initial test case set containing randomly generated states; A mutation operation is applied to the current instruction sequence to generate a candidate instruction sequence; The candidate instruction sequence is simulated and verified using the initial test case set, and the state of the Markov chain is updated based on the verification results.
[0008] Preferably, the mutation operation includes: One valid instruction in the current instruction sequence is randomly deleted with a preset probability. The positions of two non-adjacent instructions in the current instruction sequence are randomly swapped with a preset probability. The register or immediate operand of one instruction in the current instruction sequence is randomly changed with a preset probability. The instruction in the current instruction sequence is randomly replaced with a newly generated unconstrained legal instruction with a preset probability.
[0009] Preferably, the process of simulating and verifying the candidate instruction sequence includes: The candidate instruction sequence and the target RISC-V basic block are quickly simulated and executed in a lightweight virtual machine, and the execution results are compared on the initial test case set. If the execution results of all test cases are consistent, the candidate instruction sequence is determined to have passed the simulation verification.
[0010] Preferably, after simulation verification, the method further includes: The candidate instruction sequence and the target RISC-V basic block are encoded into an SMT expression, and the SMT solver is called to perform formal equivalence verification. If the SMT solver determines that the two sequences are equivalent, it outputs the candidate instruction sequence as the optimized instruction sequence. If the SMT solver determines that the two solutions are not equivalent and outputs a counterexample, then a restart process is executed.
[0011] Preferably, the restart process includes: The counterexamples are added to the initial test case set to obtain the expanded test case set; The search loop of the Markov chain Monte Carlo algorithm is restarted using the expanded test case set.
[0012] Preferably, the target RISC-V basic block is a fixed-length, loop-free instruction sequence composed of supported RISC-V instructions, including instructions encoded using 32-bit fixed-length encoding.
[0013] Preferably, after obtaining the optimized instruction sequence, the method further includes: The optimized instruction sequence is stored in the super-optimized cache database for subsequent continuous iterative optimization.
[0014] Compared with the prior art, the present invention has the following advantages and technical effects: First, this invention introduces a large language model to predict the optimization potential of each basic block and dynamically allocates the search time budget based on the prediction value. This allows computing resources to be allocated preferentially to basic blocks with higher optimization potential, avoiding the waste of resources caused by uniform fixed time allocation, thereby discovering more high-quality optimization instruction sequences within the same time budget.
[0015] Secondly, this invention employs a restarted Markov chain Monte Carlo algorithm, initiating the search with a small number of initial test cases. The test set is dynamically expanded and the search process restarted only when a counterexample is found during formal verification. This significantly reduces the number of unnecessary test cases while ensuring strict semantic equivalence, thereby substantially lowering verification overhead. The synergistic effect of these mechanisms enables this invention to significantly improve the overall efficiency of the super-optimization search and the quantity and quality of the optimized code under the same time constraints as existing methods. Attached Figure Description
[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of the overall RISC-V super-optimized framework according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the large model prediction probability distribution curve in an embodiment of the present invention; Figure 3 This is a comparison chart showing the optimization effectiveness of the restart MCMC algorithm and the original MCMC algorithm in this embodiment of the invention; Figure 4 This is an example diagram of basic block optimization in an embodiment of the present invention. Detailed Implementation
[0017] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0018] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.
[0019] like Figure 1 As shown, this embodiment provides a RISC-V stochastic superoptimization method based on learning-guided search budget allocation, including: Based on the target RISC-V basic block, large language models are used to generate predicted values of optimization potential. Based on the predicted optimization potential, allocate a search time budget to the target RISC-V basic block; Based on the search time budget, execute a search and verification loop based on the restart Markov chain Monte Carlo algorithm to obtain the optimized instruction sequence.
[0020] This embodiment, targeting the RISC-V instruction set architecture, proposes a more efficient stochastic superoptimization method. By introducing a learning-guided and verification acceleration mechanism, it improves superoptimization performance from two key dimensions: search resource allocation and verification efficiency. Specifically, this embodiment first proposes a dynamic time budget allocation mechanism based on a large language model. Before performing the superoptimization search, it utilizes the code analysis capabilities of an LLM to predict the optimization probability of all instruction sequences to be optimized, and dynamically allocates the search time budget according to the optimization probability. This allocates more search time to code sequences with optimization potential, thereby improving overall optimization efficiency.
[0021] In addition, this embodiment proposes a restart MCMC algorithm. This method no longer presets a fixed test case size, but starts the verification process on a smaller scale and dynamically expands the test set according to the verification progress. This reduces the number of test cases as much as possible while ensuring correctness, thereby improving the super-optimization efficiency.
[0022] This embodiment selects five typical open-source computationally intensive programs—OpenSSL, libYUV, GMP, FFTW3, and Zstd—to evaluate the proposed method. Experimental results show that the method can uncover RISC-V optimization fragments that were not discovered at the LLVM-O3 optimization level. Furthermore, this embodiment randomly collected 500 RISC-V instruction sequences from open-source projects and validated the proposed LLM-driven time budget prediction mechanism based on the Gemini-3.1-pro-preview and Claude-opus-4.6 models. The results show that both models achieve a prediction accuracy exceeding 91% on the test set.
[0023] Compared with the RISC-V superoptimization benchmark method based on the STOKE framework, the LLM bootstrap time budget allocation and restart MCMC method proposed in this embodiment can discover more high-quality optimization fragments under the same time constraints, significantly improving the superoptimization efficiency.
[0024] Furthermore, the process of obtaining the predicted value of the optimization potential includes: The target RISC-V basic block is input into a pre-trained large language model. The large language model is guided by prompt words to output the probability value of the existence of a semantically equivalent and less costly rewritten instruction sequence for the target RISC-V basic block, which is used as the optimization potential prediction value.
[0025] Furthermore, inspired by STOKE, a typical x86 architecture super-optimization tool, this embodiment proposes an efficient super-optimization method for RISC-V, with the overall architecture as follows: Figure 1 As shown, given a sequence of RISC-V basic blocks, the system first enters a time budget prediction process based on a large language model to analyze the over-optimization potential of the basic blocks and dynamically allocate time budgets. Then, the system enters the MCMC core search loop. During the search, the mutation module continuously proposes candidate instruction sequences, which are then rapidly simulated and executed by a lightweight virtual machine, with test cases used for verification. Code that fails correctness verification or has higher costs is quickly eliminated. For candidate programs verified by the simulator, the system then calls the SMT solver (Z3) for rigorous formal equivalence verification. If verification fails, the system extracts counterexamples to expand the test set and restarts the MCMC search; if verification passes, the optimized basic blocks are output, and newly discovered better basic blocks are stored in the database to support subsequent continuous iterative optimization.
[0026] Furthermore, the process of allocating the search time budget includes: Obtain the basic time budget and perform a nonlinear transformation on the optimization potential prediction to obtain the contrast-enhanced prediction; The search time budget for the target RISC-V basic block is calculated based on the base time budget and the contrast-enhanced prediction.
[0027] Furthermore, the process of executing the search and verification loop based on the restarted Markov chain Monte Carlo algorithm includes: Initialize the current instruction sequence of the Markov chain and set up an initial test case set containing randomly generated states; A mutation operation is applied to the current instruction sequence to generate a candidate instruction sequence; The candidate instruction sequence is simulated and verified using an initial test case set, and the state of the Markov chain is updated based on the verification results.
[0028] Furthermore, mutation operations include: Delete one valid instruction from the current instruction sequence at a preset probability; Randomly swap the positions of two non-adjacent instructions in the current instruction sequence with a preset probability; The register or immediate operand of one instruction in the current instruction sequence is randomly changed with a preset probability. Replace one instruction in the current instruction sequence with a newly generated unconstrained legal instruction at a preset probability.
[0029] Furthermore, the process of simulating and verifying the candidate instruction sequence includes: The program rapidly simulates the execution of candidate instruction sequences and target RISC-V basic blocks in a lightweight virtual machine and compares the execution results on an initial test case set. If the execution results of all test cases are consistent, the candidate instruction sequence is deemed to have passed the simulation verification.
[0030] Furthermore, traditional superoptimization methods typically allocate a uniform search time to all target basic blocks. However, in real-world codebases, many basic blocks generated by modern compilers (such as LLVM-O3) are already close to optimal or exhibit complex mathematical dependencies, making further improvement difficult within a limited search time.
[0031] To address this issue, this embodiment introduces a time budget prediction mechanism based on Large Language Model (LLM). Leveraging the code understanding and semantic reasoning capabilities of LLM, the optimization potential of each basic block is evaluated before the search.
[0032] Specifically, this embodiment defines optimization potential as the probability that a semantically equivalent but less costly rewritten code exists. Through carefully designed prompts, the LLM outputs a score P for each basic block. opt ∈[0,1] indicates its potential for optimization.
[0033] Based on P opt This embodiment breaks away from the uniform timeout allocation method and instead adopts a learning-guided budget allocation strategy. To further amplify the difference between high-potential and low-potential basic blocks, this embodiment applies a nonlinear transformation function f(·) to enhance the contrast of budget allocation. The search budget for the target basic block T is defined as: Budget(T) = B base ·(1+λ·f(P opt )) Here, f(·) is implemented as a sigmoid-based sharpening function: Here, k controls the drasticness of the transformation, B base It is the basic budget, λ = Budget max -Budget min This mechanism controls the allocation scope. It tilts computational resources toward basic blocks with higher optimization potential, thereby improving overall search efficiency and resource utilization in large program spaces.
[0034] Furthermore, this embodiment employs a stochastic superoptimization method based on the MCMC algorithm to achieve superoptimization search of RISC-V basic blocks. Specifically, this embodiment models the optimization task of basic blocks as a cost minimization problem. First, a cost function is defined, which consists of two parts: an index eq(·) for measuring semantic correctness, and a performance term index perf(·) for measuring program execution efficiency. Specifically, it can be expressed as: C(R,T)=eq(R,T)+perf(R,T) Where T represents the target program and R is the candidate rewrite program. eq(·) measures the similarity between the two programs. This term is zero if and only if the two programs are completely equivalent. perf(·) quantifies the performance improvement of the optimized program relative to the target program. The goal of this embodiment is to find R such that the total cost c(R; T) is minimized.
[0035] Since the cost function is expected to be highly irregular and unsuitable for exact optimization techniques similar to STOKE tools, this embodiment employs a Markov Chain Monte Carlo (MCMC) sampling algorithm for optimization. This algorithm maintains a current program R and generates a mutated program R. ∗ As the next step in the chain. R ∗ It's either accepted or rejected. If accepted, R... ∗ Replace the current program R; otherwise, generate another candidate program based on R. The algorithm iterates until the set optimization time is reached.
[0036] In MCMC search, the process of generating candidate programs is represented by a series of mutation operations. To perform MCMC sampling in the search space, this embodiment represents candidate programs as fixed-length, loop-free instruction sequences. The program selects from four possible mutation operations. Currently supported mutation operations are shown in Table 1.
[0037] Table 1 Because the MCMC algorithm has extremely high mutation throughput requirements, this embodiment specifically designs a high-efficiency simulator for RISC-V implementation. This simulator directly supports fast parsing based on 32-bit fixed-length instruction encoding, and can efficiently read or mutate instruction fields using bitwise operations. The virtual machine only maintains general-purpose registers, and by high-speed simulation execution and comparison of register states, the execution latency of a single test is greatly compressed. After the virtual machine finishes execution, the system obtains the execution results of the candidate program on each test case to calculate the correctness metric eq(·) in the loss function.
[0038] Furthermore, after simulation verification, it also includes: The candidate instruction sequence and the target RISC-V basic block are encoded into SMT expressions, and the SMT solver is called to perform formal equivalence verification. If the SMT solver determines that the instructions are equivalent, it outputs the candidate instruction sequence as the optimized instruction sequence. If the SMT solver determines that the two are not equivalent and outputs a counterexample, then a restart process is executed.
[0039] Furthermore, in this embodiment, after each mutation is generated, the candidate program is first verified using a lightweight simulator to filter out erroneous or uncorrected rewrites. Since simulation-based verification is limited to a finite test set, it cannot guarantee strict global semantic equivalence. Therefore, only after successful simulator verification is the candidate program submitted to the Z3SMT solver for rigorous formal equivalence verification.
[0040] This embodiment precisely encodes the program's instruction semantics and states into SMT expressions, which are then passed to the Z3 solver to determine if any input could cause inconsistencies between the mutated program's output and the source program's output. If the verification fails, meaning a counterexample has been found that causes inconsistencies, the system extracts this counterexample and adds it to the simulator's test dataset, then restarts the MCMC search process using the restart MCMC mechanism. This counterexample-based verification loop (CEGIS) allows for dynamic expansion of the preset test set, significantly improving verification efficiency.
[0041] Furthermore, the restart process includes: Adding counterexamples to the initial test case set yields the expanded test case set; Restart the search loop of the Markov chain Monte Carlo algorithm using the expanded test case set.
[0042] Furthermore, traditional MCMC-based superoptimization relies on a fixed loss function during the search process, which cannot be modified during execution. However, a finite set of test cases is inherently incomplete and cannot fully capture the semantics of the program, making it impossible to determine whether two programs are truly equivalent based solely on testing. Therefore, even if the MCMC process converges, the result may still be incorrect under complete semantics. To ensure correctness, formal methods such as symbolic execution or SMT-based verification are needed. If a candidate program fails formal verification, previous optimization efforts may be wasted.
[0043] Furthermore, the number of test cases determines search efficiency and verification accuracy. While smaller test sets can improve search throughput, they increase the risk of receiving incorrect code sequences; conversely, while larger test sets can improve verification accuracy, they significantly increase evaluation overhead, thereby reducing MCMC search efficiency.
[0044] To address the aforementioned issues, this embodiment proposes a restarted MCMC algorithm. This eliminates the need for manually determining the number of test cases and enables optimization with a minimal number of test cases. The specific process is as follows: Initially, the system starts the MCMC search using only a small number of randomly generated test case states. If a candidate rewrite is determined to be equivalent under the current test set, it enters the formal verification phase. If the verification passes, the optimization is successful and terminates. Otherwise, counterexamples generated by the solver are added to the test set, and the system restarts the MCMC optimization process using the expanded test set.
[0045] Furthermore, the target RISC-V basic block is a fixed-length, loop-free instruction sequence consisting of supported RISC-V instructions, including 32-bit fixed-length encoded instructions.
[0046] Furthermore, after obtaining the optimized instruction sequence, it also includes: The optimized instruction sequence is stored in the super-optimized cache database for subsequent continuous iterative optimization.
[0047] To address the challenge of traditional compiler optimization techniques struggling to discover non-intuitive optimal solutions in complex instruction spaces due to heuristic limitations and the exponential expansion of the instruction space, this embodiment designs and implements a stochastic superoptimization system for the RISC-V architecture. To solve the problem of inefficient uniform allocation of search time across a vast search space, this embodiment innovatively introduces a prior analysis mechanism based on Large Language Models (LLM) to predict the optimization potential of instruction sequences before searching. Based on this prediction, the system dynamically allocates the search time budget for each candidate basic block, thereby improving computational resource utilization and overall optimization efficiency. Furthermore, this embodiment proposes a restart-based MCMC algorithm, significantly reducing verification overhead while ensuring correctness. This embodiment undergoes extensive experimental evaluation on classic computationally intensive open-source libraries such as OpenSSL, GMP, FFTW3, libYUV, and Zstd. Experimental results show that the system can consistently discover instruction sequences superior to those optimized by LLVM-O3. Further evaluation shows that the proposed prior analysis mechanism based on Large Language Models achieves a prediction accuracy exceeding 91%. Compared to the STOKE-based benchmark implementation, the method in this embodiment can discover more high-quality optimization fragments under the same time budget, demonstrating its effectiveness and practical value.
[0048] As a preferred implementation method, the performance evaluation experiments in this embodiment were conducted on the QEMUv9.0.2 simulation platform, and all test programs were compiled in the LLVMv20.1.8 environment. To verify the universality of the optimization method, this embodiment selected five representative open-source computing libraries covering different application areas as optimization targets, including OpenSSL (encryption algorithm), libYUV (video processing), GMP (multi-precision arithmetic), FFTW3 (discrete Fourier transform), and Zstd (data compression), as shown in Table 2.
[0049] Table 2 To verify the effectiveness of the method in this embodiment, this embodiment uses wlllvm to compile these open-source computing libraries into RISC-V assembly files and extracts the basic blocks to be optimized. Since the backend currently supports a limited number of instruction types, this embodiment only extracts those basic blocks composed of supported instructions for over-optimization.
[0050] Specifically, to verify the effectiveness of the LLM-based dynamic allocation mechanism for search time budget and the restart MCMC method proposed in this embodiment, this embodiment collected 500 basic block instances from the super-optimized cache database of the open source library to form a prediction dataset, of which 30% were successfully optimized instances and 70% were unsuccessfully optimized instances.
[0051] The collected instances are each predicted using a large model to obtain their corresponding probabilities. In this embodiment, instances with a predicted probability exceeding 0.5 and which are actually optimized are defined as true positives.
[0052] Prediction performance based on large language models: This embodiment selected two large models (Gemini-3.1-pro-preview and Claude-opus-4.6) with relatively good code understanding and analysis capabilities for testing. The comparison of the prediction accuracy of the large models for over-optimization potential is shown in Table 3. The large language models can screen out basic blocks with optimization potential with a high accuracy (over 91%). The predicted probability P output by the model is... opt The result shows a significant positive correlation with whether the basic block can actually be successfully optimized.
[0053] Table 3 Figure 2 This diagram displays the probability distribution curves predicted by the large model. To more clearly illustrate the data distribution patterns, the original discrete frequency histogram has been transformed into a smooth curve through fitting. Furthermore, this embodiment also... Figure 2 The distributions (a) and (b) in the figure were subjected to non-linear contrast stretching, which yielded (c) and (d) respectively.
[0054] The purpose of this is that the dynamic search budget allocation strategy in this embodiment is designed as follows: when calculating the time budget, the system considers the prediction probability P... opt A high-contrast function f(·) is introduced for nonlinear mapping stretching to further widen the budget allocation gap between high-potential and low-potential basic blocks. Figures (c) and (d) visually illustrate the effect of this contrast stretching, which not only effectively amplifies the model's ability to distinguish instances in detail but also demonstrates the rationality of the dynamic time allocation formula design in this embodiment. The smoothed curves after stretching clearly show a significant difference in the distribution of successfully optimized and unsuccessfully optimized basic blocks when determining their optimization potential. This proves that the large model has learned the patterns and optimization difficulty of assembly instructions through massive amounts of code data.
[0055] The effectiveness of restarting MCMC, such as Figure 3 As shown in the figure, this embodiment sets the initial number of test cases to 50, 100, 200, 400, and 800 respectively, and measures the reduction ratio of the number of basic blocks after optimization compared to the original number of instructions. It can be seen from the figure that as the size of the test cases increases, the reduction ratio of instructions first increases and then decreases.
[0056] When the MCMC algorithm is restarted with only 50 initial test cases, its optimized instruction ratio can reach the level that the original MCMC algorithm can achieve with a fixed test case size of 200 or 400. In other words, under the restarted MCMC setting, this embodiment only requires a small number of initial test cases to achieve better optimization results.
[0057] As shown in Table 4, compared with the Baseline (original MCMC algorithm), the LLM-based time budget prediction strategy and the restarted MCMC algorithm proposed in this embodiment can discover more optimized basic blocks and optimized instruction sequences within the same time budget, providing the possibility for further efficient super-optimization. The optimization results of the Baseline and the method of this embodiment are compared in Table 4, where Restarted represents the restarted MCMC algorithm and LLM represents the LLM-based time budget prediction strategy.
[0058] Table 4 In the evaluation, this embodiment set a 10-minute timeout for the super-optimization of each basic block. This embodiment used the reduction in the number of instructions as the optimization criterion and statistically analyzed the change in the number of instruction lines before and after optimization, the number of basic blocks successfully optimized, and the overall optimization improvement ratio.
[0059] Table 5 shows the evaluation results of the super-optimization system in this embodiment on various open-source libraries. Among them, "Number of basic blocks to be optimized" represents the total number of basic blocks used for super-optimization in each program, "Number of basic blocks successfully optimized" represents the number of basic blocks that found better instruction sequences, and "Total number of instructions before / after optimization" counts the total number of assembly instructions for this batch of basic blocks before and after optimization.
[0060] Table 5 Experimental results show that even when faced with highly optimized mature open-source libraries (such as LLVM-O3 compilation artifacts), the super-optimized system in this embodiment can still reliably find rewrite sequences with shorter execution cycles within a large computational library. As shown in Table 5, the system successfully optimized 78 and 139 basic blocks in the FFTW3 and Zstd projects, respectively.
[0061] To further analyze the effect of super-optimization, this embodiment selects the RISC-V instruction code of the core hotspot function ZSTD_row_nextIndex in the Zstd program, which was successfully optimized. This embodiment extracts and compares the assembly code of the ZSTD_row_nextIndex function before super-optimization (generated by LLVM-O3) and after super-optimization by the system in this embodiment. Figure 4As shown, the number of basic block instructions has been reduced from 8 to 6 after optimization.
[0062] In summary, this embodiment proposes an efficient stochastic superoptimization method for the RISC-V instruction set architecture, integrating learning guidance and verification acceleration mechanisms. By introducing a dynamic allocation mechanism for the search time budget based on a large language model, adaptive allocation of search resources is achieved. Simultaneously, a restart-based MCMC verification strategy is designed, which significantly reduces verification overhead while ensuring equivalence through dynamic expansion of test case size. Experimental results show that the proposed method not only uncovers a large number of optimization fragments that LLVM-O3 failed to discover, but also exhibits good optimization capabilities on various open-source computationally intensive programs. Furthermore, prediction results based on Gemini-3.1-pro-preview and Claude-opus-4.6 verify the effectiveness of the method in evaluating optimization potential, with a prediction accuracy exceeding 91%. Compared with RISC-V superoptimization benchmark methods based on the STOKE framework, the method in this embodiment can discover more high-quality optimization results under the same time budget, significantly improving the overall efficiency and practicality of superoptimization.
[0063] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A RISC-V stochastic superoptimization method based on learning-guided search budget allocation, characterized in that, include: Based on the target RISC-V basic block, large language models are used to generate predicted values of optimization potential. Based on the predicted optimization potential, allocate a search time budget to the target RISC-V basic block; Based on the search time budget, a search and verification loop based on the restart Markov chain Monte Carlo algorithm is executed to obtain the optimized instruction sequence.
2. The method according to claim 1, characterized in that, The process of obtaining the predicted value of the optimization potential includes: The target RISC-V basic block is input into a pre-trained large language model. The large language model is guided by prompt words to output the probability value that the target RISC-V basic block has a semantically equivalent and lower-cost rewrite instruction sequence, which is used as the optimization potential prediction value.
3. The method according to claim 1, characterized in that, The process of allocating the search time budget includes: Obtain the basic time budget and perform a nonlinear transformation on the predicted value of the optimization potential to obtain the predicted value after contrast enhancement; The search time budget for the target RISC-V basic block is calculated based on the base time budget and the contrast-enhanced prediction value.
4. The method according to claim 1, characterized in that, The process of executing the search and verification loop based on the restarted Markov chain Monte Carlo algorithm includes: Initialize the current instruction sequence of the Markov chain and set up an initial test case set containing randomly generated states; A mutation operation is applied to the current instruction sequence to generate a candidate instruction sequence; The candidate instruction sequence is simulated and verified using the initial test case set, and the state of the Markov chain is updated based on the verification results.
5. The method according to claim 4, characterized in that, The mutation operation includes: One valid instruction in the current instruction sequence is randomly deleted with a preset probability. The positions of two non-adjacent instructions in the current instruction sequence are randomly swapped with a preset probability. The register or immediate operand of one instruction in the current instruction sequence is randomly changed with a preset probability. The instruction in the current instruction sequence is randomly replaced with a newly generated unconstrained legal instruction with a preset probability.
6. The method according to claim 4, characterized in that, The process of simulating and verifying the candidate instruction sequence includes: The candidate instruction sequence and the target RISC-V basic block are quickly simulated and executed in a lightweight virtual machine, and the execution results are compared on the initial test case set. If the execution results of all test cases are consistent, the candidate instruction sequence is determined to have passed the simulation verification.
7. The method according to claim 6, characterized in that, After simulation verification, it also includes: The candidate instruction sequence and the target RISC-V basic block are encoded into an SMT expression, and the SMT solver is called to perform formal equivalence verification. If the SMT solver determines that the two sequences are equivalent, it outputs the candidate instruction sequence as the optimized instruction sequence. If the SMT solver determines that the two solutions are not equivalent and outputs a counterexample, then a restart process is executed.
8. The method according to claim 7, characterized in that, The restart process includes: The counterexamples are added to the initial test case set to obtain the expanded test case set; The search loop of the Markov chain Monte Carlo algorithm is restarted using the expanded test case set.
9. The method according to claim 1, characterized in that, The target RISC-V basic block is a fixed-length, non-cyclic instruction sequence composed of supported RISC-V instructions, including instructions using 32-bit fixed-length encoding.
10. The method according to claim 1, characterized in that, After obtaining the optimized instruction sequence, it also includes: The optimized instruction sequence is stored in the super-optimized cache database for subsequent continuous iterative optimization.
