Mastering circuit, mastering node, controlled node and computing system

Abstract

The application discloses a master control circuit, a master control node, a controlled node and a computing system, and relates to the technical field of servers, and comprises the following steps: a slave device in the controlled node is managed by the master control circuit in the master control node without setting a manager in the controlled node. In this way, on the premise that the slave device in the controlled node can be managed, only one manager needs to be set, so that hardware resources can be saved, and hardware cost can be reduced. Furthermore, different management ports are divided according to the positions of the devices for management, which is relatively convenient. Moreover, a technician only needs to develop a set of codes, and the development cost is relatively low. In addition, in the management process, the technician only needs to log in to the management interface of one manager, can monitor the master control node and the controlled node, and does not need to switch among multiple independent management interfaces, so that the management cost can be reduced.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to main control circuits, main control nodes, controlled nodes and computing systems. Background Technology

[0002] In the field of server technology, with the rapid development of artificial intelligence, its demand for computing power is also increasing. Graphics Processing Units (GPUs) have strong computing power, so current artificial intelligence servers are generally equipped with multiple GPUs. However, the computing power of a single server is also limited. Therefore, two servers are usually interconnected through a Peripheral Component Interconnect Express (PCI) adapter card to achieve interconnection.

[0003] In this scenario, each of the two servers needs its own motherboard, with a manager on the motherboard controlling the internal components of each server. This results in high hardware and management costs. Furthermore, separate code needs to be developed, leading to high development costs. In short, current server interconnection scenarios suffer from excessively high costs. Summary of the Invention

[0004] This application provides a main control circuit, a main control node, a controlled node, and a computing system to address the high cost issue in server interconnection scenarios.

[0005] This application provides a main control circuit, which includes: The power board includes a first connector, a second connector, a third connector, and a first set of master devices of the master control node; the first connector and the second connector are respectively connected to the third connector, the third connector is connected to the slave device in the controlled node, and the first set of master devices is connected to the second connector; the master control circuit is located inside the master control node and outside the controlled node. The manager includes a first set of management ports, a second set of management ports, and a third set of management ports; the first set of management ports is connected to the second set of master devices of the master control node, the second set of management ports is connected to the first connector, and the third set of management ports is connected to the second connector.

[0006] This application also provides a master node, including: Main equipment; The aforementioned main control circuit.

[0007] This application also provides a controlled node, including: From the equipment; The device is connected to the aforementioned main control circuit.

[0008] This application also provides a computing system, including: The aforementioned master control node; The aforementioned controlled nodes; The master node is connected to the controlled node.

[0009] According to this application, the master control node includes a master device and a master control circuit. The master control circuit includes a manager and a power board. The multiple management ports of the manager are divided into different groups of management ports, namely the first group of management ports, the second group of management ports, and the third group of management ports mentioned above. The devices to be managed in the master control node and the controlled node are divided into different groups of devices, namely the first group of master devices, the second group of master devices, and the slave devices mentioned above. The first group of management ports can be connected to the second group of master devices (excluding the power board in the master control node), enabling the manager to manage the second group of master devices. The second group of management ports can be connected to a first connector, the first connector can be connected to a third connector, and the third connector can be connected to a slave device, enabling the manager to manage the slave device. The third group of management ports can be connected to a second connector, the second connector can be connected to the first group of master devices, enabling the manager to manage the first group of master devices. Furthermore, the second connector is also connected to the third connector, allowing the manager to manage the slave device through this path.

[0010] With the aforementioned master control circuit structure, no manager is needed in the controlled node; the slave devices in the controlled node can be managed through the master control circuit in the master node. This ensures that the slave devices in the controlled node can be managed, requiring only one manager, thus saving hardware resources related to the manager and its peripherals, such as Double Data Rate (DDR) memory adapters, reducing hardware costs. Furthermore, managing devices through different management ports based on their location is more convenient. Moreover, technicians only need to develop one set of code, resulting in lower development costs. Additionally, during management, technicians only need to log into a single manager interface to monitor both the master and controlled nodes, eliminating the need to switch between multiple independent management interfaces, further reducing management costs. For example, in AI server applications, the manager can simultaneously control all graphics processors connected to both the master and controlled nodes, facilitating management.

[0011] Furthermore, there is no need to add new circuit boards to any node. Instead, the power board can be used, and by changing some of the internal connections, the slave devices can be managed, which can save hardware costs. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the structure of a node in the related technology provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the first type of main control circuit provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of the second type of main control circuit provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of the third type of main control circuit provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of the fourth type of main control circuit provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of the fifth type of main control circuit provided in the embodiments of this application; Figure 7 This is a schematic diagram of the sixth type of main control circuit provided in the embodiments of this application; Figure 8 This is a schematic diagram of the structure of a master control node provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of the first type of controlled node provided in the embodiments of this application; Figure 10 This is a schematic diagram of the structure of the second type of controlled node provided in the embodiments of this application; Figure 11 This application provides a schematic diagram of the structure of a computing system according to an embodiment of the present application. Figure 12 A schematic diagram of the grouping of management ports of a manager provided in an embodiment of this application; Figure 13 A schematic diagram of a circuit board structure provided in an embodiment of this application; Figure 14 This is a schematic diagram of another master control node provided in an embodiment of this application; Figure 15 This is a schematic diagram of another controlled node provided in an embodiment of this application; Figure 16 This is a schematic diagram illustrating the connection relationship between the master node and the controlled node provided in an embodiment of this application. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0015] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] With the rapid development of Artificial Intelligence (AI), the demand for intelligent computing power continues to rise, giving rise to the following technological trends: First, architectural evolution. From a "Central Processing Unit (CPU) center" to a "Graphics Processing Unit (GPU) / accelerator center," heterogeneous computing has become mainstream. In this model, the CPU serves as the control and management unit, while accelerator cards such as GPUs undertake the vast majority of computing tasks.

[0018] Second, interconnection technology. This includes intra-machine interconnection and inter-machine interconnection. Intra-machine interconnection typically uses NVLink or Peripheral Component Interconnect Express (PCIE) bus.

[0019] Existing multi-GPU AI servers commonly use configurations with 8 or 16 GPUs. The GPUs and onboard management are handled by a manager via I2C, including tasks such as acquiring device temperature and power consumption, obtaining status information, reporting anomalies, and upgrading firmware (FW).

[0020] like Figure 1As shown, node 0 of the motherboard houses a manager. This manager manages the central processing unit (CPU), real-time clock (RTL), M.2 board, M.2 slot, complex programmable logic device (CPLD), clock buffer, mainboard voltage regulator (MBVR), and sensors within the motherboard via the I2C bus. It also manages external components via the I2C bus, including the switch board (SW board), smart NIC management interface controller (SMNIC), non-volatile memory express backplane (NVME BP), power supply unit (PSU), fan board, power board, peripheral component interconnect express connector board (PCIE Conn board), and quad small form-factor connector. The system manages the Pluggable (QSFP) optical module management board, etc. The graphics processor is usually connected to the switch board so that the manager can manage the graphics processor through the switch board.

[0021] In server interconnection scenarios within related technologies, two servers are connected via a peripheral component interconnection fast bus adapter. However, each server has its own motherboard so that a manager on the motherboard can manage the devices within the node. This results in high hardware and management costs. Furthermore, separate code needs to be developed for each different manager, leading to high development costs.

[0022] To address the aforementioned technical problems, embodiments of this application provide a main control circuit, such as... Figure 2As shown, the main control circuit can be located within the main control node or outside the controlled nodes. Both the main control node and the controlled nodes can be servers. Both the main control node and the controlled nodes can include devices to be managed. Devices to be managed in the main control node can be called master devices, and devices to be managed in the controlled nodes can be called slave devices. Since the locations of the devices to be managed are different, for ease of management, this solution divides the devices to be managed into different groups, which are managed separately by the main control circuit through different management paths and management methods.

[0023] Accordingly, the main control circuit provided in the embodiments of this application may include a power supply board and a manager.

[0024] The power board, also known as a power control board or power switch board, may include multiple connectors and a first set of main devices.

[0025] The multiple connectors include a first connector, a second connector, and a third connector. The first and third connectors can be sideband connectors (Sideband Conn), and the second connector can be a power connector (PWR Conn).

[0026] The first group of master devices can be master devices located on the power board in the master control node. For example, the master devices on the power board can include one or more devices such as complex programmable logic devices, field replaceable units (FRUs), input / output expanders (IO expanders), temperature sensors (TSensors), electrically erasable programmable read-only memory (EEPROM), and electrical fuses.

[0027] The manager can be a Baseboard Management Controller (BMC). The manager includes multiple management ports, which can be I2C management ports. Each set of management ports can be used to manage different devices, which can be master devices in the master node (master devices within the power board, or master devices outside the power board) or slave devices in the controlled node. In this solution, the multiple sets of management ports can include a first set of management ports, a second set of management ports, and a third set of management ports.

[0028] Both the first and second connectors can be connected to the third connector. The third connector is connected to the slave device in the controlled node, and the first group of master devices is connected to the second connector.

[0029] The first set of management ports can connect to the second set of master devices in the master node. The second set of management ports can connect to the first connector, and the third set of management ports can connect to the second connector. The second set of master devices may include one or more devices such as a non-volatile memory high-speed channel backplane, a smart network interface card (NIC) management port controller, and a switch board. The non-volatile memory high-speed channel backplane can connect to a hard drive. The switch board can be equipped with graphics processor slots for connecting multiple graphics processors; for example, it can connect up to eight graphics processors.

[0030] In the above structure, the manager can directly manage the second group of master devices through the first group of management ports, manage the slave devices in the controlled nodes through the communication links between the second group of management ports, the first connector, and the third connector, and through the communication links between the third group of management ports, the second connector, and the third connector, and manage the first group of master devices on the circuit board through the communication link between the third group of management ports and the second connector. These management operations can include monitoring the operating status of each device, alarms, and control operations.

[0031] The main control circuit of this application includes a power board and a manager. The manager comprises multiple management ports divided into different groups, namely the first group of management ports, the second group of management ports, and the third group of management ports described above. The devices to be managed in the master node and the controlled node are divided into different groups, namely the first group of master devices, the second group of master devices, and the slave devices described above. The first group of management ports can be connected to the second group of master devices outside the power board in the master node, enabling the manager to manage the second group of master devices. The second group of management ports can be connected to a first connector, and the first connector can be connected to a third connector. The third connector connects to a slave device, enabling the manager to manage the slave device. The third group of management ports can be connected to a second connector, and the second connector connects to the first group of master devices, enabling the manager to manage the first group of master devices. Furthermore, the second connector also connects to the third connector, allowing the manager to manage slave devices through this path.

[0032] With the aforementioned master control circuit structure, no manager is needed in the controlled node; the slave devices in the controlled node can be managed through the master control circuit in the master node. This ensures that the slave devices in the controlled node can be managed, requiring only one manager, thus saving hardware resources related to the manager and its peripherals, such as Double Data Rate (DDR) memory adapters, reducing hardware costs. Furthermore, managing devices through different management ports based on their location is more convenient. Moreover, technicians only need to develop one set of code, resulting in lower development costs. Additionally, during management, technicians only need to log into a single manager interface to monitor both the master and controlled nodes, eliminating the need to switch between multiple independent management interfaces, further reducing management costs. For example, in AI server applications, the manager can simultaneously control all graphics processors connected to both the master and controlled nodes, facilitating management.

[0033] Furthermore, there is no need to add new circuit boards to any node. Instead, the power board can be used, and by changing some of the internal connections, the slave devices can be managed, which can save hardware costs.

[0034] In some alternative implementations, based on the foregoing embodiments, the second connector may include multiple sets of pins, which may include a first set of pins and a second set of pins. The first set of pins may be connected to a first set of master devices, and the second set of pins may be connected to a third connector. Accordingly, the structure of the main control circuit may be as follows: Figure 3 As shown.

[0035] In this way, after connecting the first set of pins to the first group of master devices, the manager can manage the first group of master devices through the first set of pins. After connecting the second set of pins to the third connector, the manager can manage the slave devices through the communication link between the second set of pins and the third connector. By dividing the pins on the second connector, the management path can be isolated, making it easier to locate the fault point during later maintenance.

[0036] In some optional implementations, based on the foregoing embodiments, the master control node may further include a third group of master devices, which may be master devices located outside the power supply board within the master control node. For example, the third group of master devices may include one or more devices such as a peripheral component interconnect fast bus adapter card, a power supply unit, a fan board, a four-channel small hot-swappable optical module management board, etc. The fan board may be a 4-fan board or an 8-fan board, etc.

[0037] The power board may also include at least one switch, each of which may include a master switch and multiple slave switches. The switch may be an I2C switch. Half of the multiple slave switches may be connected to a third connector, and each of the other half of the slave switches may be used to connect to one or more master devices in a third group of master devices. For example, a switch may include two slave switches, one of which may be connected to a third connector, and the other slave switch may be connected to one master device in a third group of master devices. Alternatively, a switch may include four slave switches, two of which may be connected to a third connector, and the other two slave switches may each be connected to one master device in a third group of master devices.

[0038] Specifically, the power supply board includes at least a first switch, which may include a first master switch, a first slave switch, and a second slave switch. The first master switch can be connected to a second set of pins, the first slave switch can be connected to a third connector, and the second slave switch can be connected to one or more master devices (including the first master device) in the third set of master devices. Correspondingly, the main control circuit can be as follows: Figure 4 As shown, the manager can be used to control the connection between the first master switch and the first slave switch, or to control the connection between the first master switch and the second slave switch.

[0039] In such Figure 4 Based on the main control circuit shown, the main control circuit may further include a second switch. The second switch includes a second master switch terminal, a third slave switch terminal, and a fourth slave switch terminal. The second master switch terminal is connected to a second set of pins, the third slave switch terminal is connected to a third connector, and the fourth slave switch terminal is connected to one or more master devices (including the second master device) in the third set of master devices. Accordingly, the main control circuit can be as follows: Figure 5 As shown, the manager can be used to control the connection between the second master switch and the third slave switch, or to control the connection between the master switch and the fourth slave switch.

[0040] The second and fourth slave switching terminals can first be connected to the connectors on the power board, and then the connectors can be connected to the corresponding master devices.

[0041] Of course, the main control circuit can also include more switches, as follows: Figure 4 and Figure 5 The connection method shown can connect more master devices, which will not be elaborated here.

[0042] In this way, when the manager controls the connection between the first master switch and the first slave switch, it can manage the slave devices. When controlling the connection between the first master switch and the second slave switch, it can manage the master devices connected to the second slave switch. Similarly, when controlling the connection between the second master switch and the third slave switch, the manager can manage the slave devices. When controlling the connection between the second master switch and the fourth slave switch, it can manage the master devices connected to the fourth slave switch. By extending the links through the switches, the manager can switch between different links to perform corresponding management operations through logical control, even with a limited number of its own management ports. This saves hardware resources and allows it to manage more devices.

[0043] Furthermore, connecting the first and third slave switches to the third connector, and then connecting them to the slave devices in the controlled node via the third connector, prevents the formation of a secondary switch. A secondary switch refers to a switch where a slave switch (output) is connected to the master switch (input) of another switch, forming a two-stage cascaded topology. In such a structure, the manager needs to go through multiple layers of selection commands to access a slave device in the controlled node, which is complex and prone to logical errors. In this solution, the slave switch corresponding to the slave device is directly connected to the third connector. As long as the link connection is correct, management operations can be achieved through simple selection commands, which is more convenient, reduces the probability of management errors, and further reduces management costs.

[0044] In some alternative implementations, based on the foregoing embodiments, the master node may further include a main board (MB), which includes a fourth group of master devices for the master node. The fourth group of master devices may include one or more of the following on the main board: a central processing unit, a real-time clock, an M.2 adapter card, an M.2 slot, a complex programmable logic device, a clock buffer, a main board voltage regulator, sensors, etc.

[0045] The manager's multiple management ports can also include a fourth management port.

[0046] The management unit can be located inside the motherboard, while the first, second, and third master devices are located outside the motherboard, and the fourth management port connects to the fourth master device. Correspondingly, the main control circuitry can be as follows: Figure 6 As shown. One of the management ports in the fourth group can be connected to one or more master devices in the fourth group of master devices.

[0047] By connecting the fourth management port to the fourth master device, devices on the motherboard can also be managed, simplifying management. No motherboard needs to be configured in the controlled node, further saving hardware costs. Furthermore, there's no need to maintain different board part numbers.

[0048] Accordingly, on the motherboard, the first set of management ports of the manager can first connect to the first set of connectors on the motherboard, and the first set of connectors connects to the second set of master devices. The second set of management ports can connect to the second set of connectors on the motherboard, and the second set of connectors connects to the first connector on the power board. The third set of management ports can connect to the third set of connectors on the motherboard, and the third set of connectors connects to the second connector on the power board.

[0049] In some alternative implementations, based on the foregoing embodiments, the main control circuit may further include at least one repeater, which may be an I2C repeater. The repeater is connected between the first connector and the third connector, and also between the second connector and the third connector. The number of repeaters connected between the first connector and the third connector may be equal to the number of management ports included in the second set of management ports. Accordingly, the main control circuit may be as follows: Figure 7 As shown. Repeaters can be used to receive, amplify, and forward signals (such as signals from the manager and signals from the device to be managed) to extend the transmission distance of the signal and ensure that it can be correctly identified at the receiving end.

[0050] In such Figure 3 In the main control circuit shown, a repeater can also be connected between the first group of pins and the first group of main devices. Specifically, the repeater between the second connector and the third connector can be between the second group of pins and the third connector.

[0051] In such Figure 4 In the main control circuit shown, the first group of master devices can be connected to a repeater between the first group of pins, and the second slave switch can also be connected to a repeater between the first master device. Specifically, the repeater between the second connector and the third connector can be between the first slave switch and the third connector.

[0052] In such Figure 5 In the main control circuit shown, a repeater can also be connected between the fourth slave switching terminal and the second master device. Specifically, the repeater between the second connector and the third connector can be located between the third slave switching terminal and the third connector.

[0053] In this way, by amplifying the signal through a repeater, the accuracy of signal transmission can be guaranteed. In particular, in this scheme, the manager inside the master node needs to control the slave devices in other controlled nodes. The transmission link is relatively long. Setting up a repeater can effectively enhance the signal and ensure that the original management information is retained when it reaches the controlled node, so as to realize safe management operation and avoid equipment failure caused by erroneous signals.

[0054] This application also provides a master control node, which includes at least one master device and a master control circuit. The specific structure of the master control circuit and its connection relationship with the master device can be referred to the foregoing embodiments, and will not be repeated here. Correspondingly, the structure of the master control node can be referred to the foregoing embodiments. Figures 2 to 7 .

[0055] The master control node of this application includes a master device and a master control circuit. The master control circuit includes a manager and a power board. The multiple management ports included in the manager are divided into different groups of management ports, namely the first group of management ports, the second group of management ports, and the third group of management ports mentioned above. The devices to be managed included in the master control node and the controlled node are divided into different groups of devices, namely the first group of master devices, the second group of master devices, and the slave devices mentioned above. The first group of management ports can be connected to the second group of master devices outside the power board in the master control node, enabling the manager to manage the second group of master devices. The second group of management ports can be connected to a first connector, the first connector can be connected to a third connector, and the third connector can be connected to a slave device, enabling the manager to manage the slave device. The third group of management ports can be connected to a second connector, the second connector can be connected to the first group of master devices, enabling the manager to manage the first group of master devices. Furthermore, the second connector is also connected to the third connector, allowing the manager to manage the slave device through this path.

[0056] With the aforementioned master control circuit structure, no manager is needed in the controlled node; the slave devices in the controlled node can be managed through the master control circuit in the master node. This ensures that the slave devices in the controlled node can be managed, requiring only one manager, thus saving hardware resources related to the manager and its peripherals, such as Double Data Rate (DDR) memory adapters, reducing hardware costs. Furthermore, managing devices through different management ports based on their location is more convenient. Moreover, technicians only need to develop one set of code, resulting in lower development costs. Additionally, during management, technicians only need to log into a single manager interface to monitor both the master and controlled nodes, eliminating the need to switch between multiple independent management interfaces, further reducing management costs. For example, in AI server applications, the manager can simultaneously control all graphics processors connected to both the master and controlled nodes, facilitating management.

[0057] Furthermore, no new circuit boards need to be added to any node; instead, a power board can be used, and by modifying some of the internal connections, slave devices can be managed, saving hardware costs. In some optional implementations, based on the aforementioned embodiments, the master node may further include a fourth connector, which may be a Type-C interface. The third connector can connect to the fourth connector, and the fourth connector can connect to the slave device in the controlled node. Accordingly, the structure of the master node can be as follows: Figure 8 As shown.

[0058] This application also provides a controlled node, such as... Figure 9 As shown, the controlled node may include at least one group of slave devices, each group of slave devices being connected to the aforementioned master control circuit, so that the manager in the master control circuit can manage the slave devices.

[0059] The controlled node in the embodiments of this application does not require a manager, and therefore does not require a motherboard. Instead, the main control circuit connected to it can perform related management operations, which can save hardware resources and reduce costs.

[0060] In some alternative implementations, based on the foregoing embodiments, the controlled node may further include a power supply board and a first slave connector. The first slave connector may be a Type-C interface. The power supply board may include a second slave connector, which may be a sideband connector. The slave devices may include a first group of slave devices and a second group of slave devices, the second group of slave devices including a first subgroup of slave devices and a second subgroup of slave devices.

[0061] The first group of slave devices can be slave devices located within the power supply board of the controlled node. For example, they can include one or more devices such as complex programmable logic devices, field-swappable units, input / output expanders, temperature sensors, electrically erasable programmable read-only memory, and fuses. The second group of slave devices can be slave devices located outside the power supply board.

[0062] The first subgroup of slave devices in the second group may include one or more devices such as a non-volatile memory high-speed channel backplane, a smart network interface card management port controller, and a switching board. The second subgroup of slave devices in the second group may include one or more devices such as a peripheral component interconnect fast bus adapter card, a power supply unit, a fan board, and a four-channel small hot-swappable optical module management board.

[0063] The first slave connector can be connected to the second slave connector and the main control circuit respectively. The second slave connector can be connected to the first group of slave devices and the second subgroup of slave devices respectively. The first slave connector is connected to the first subgroup of slave devices. Accordingly, the structure of the controlled node can be as follows: Figure 10 As shown.

[0064] In some optional implementations, based on the foregoing embodiments, the power board included in the master control node and the power board included in the slave control node may have the same structure. That is, the components included in the two power boards and the connection methods between the components are the same. However, the connectors on the power boards that have external connections are different.

[0065] Accordingly, the power board may include a first connector, a second connector, a third connector, and a second slave connector. As a power board in a controlled node, its second slave connector needs to connect to the first slave connector of the controlled node; however, as a power board in a master node, the second slave connector does not need to connect to any external connectors on the power board. Similarly, as a power board in a master node, its first connector connects to the second set of management ports in the manager, its second connector connects to the third set of management ports in the manager, and its third connector connects to the fourth connector in the master node; however, as a power board in a controlled node, its first, second, and third connectors do not need to connect to any external connectors on the power board.

[0066] In this way, the same power board structure can be used, and different external connection methods can be adopted in different types of nodes. There is no need to develop corresponding power boards for the master node and the controlled node separately. Instead, only the external connection method needs to be changed, which is more convenient and can reduce development costs.

[0067] This application provides a computing system including a master node and a controlled node, which are interconnected. For example, the Type-C interface of the master node and the Type-C interface of the controlled node are connected via a cable. Figure 11 As shown.

[0068] The computing system of this application only needs to set up a manager in the master node to manage the devices included in the master node and the controlled node, which can save hardware resources.

[0069] The structure of the above-mentioned computing system will be explained in detail below with a specific example.

[0070] like Figure 12As shown, the management ports on the manager are divided into four groups. The first group of management ports is dedicated to the master devices outside the motherboard in the master node, including I2C6, I2C7, I2C8, I2C9, and I2C14. The second group of management ports is dedicated to the slave devices in the controlled nodes, including I2C10, I2C11, and I2C12. The third group of management ports is shared by the master devices in the master node and the slave devices in the controlled nodes, including I2C13, I2C15, and I2C16. The fourth group of management ports is dedicated to the master devices inside the motherboard in the master node, including I2C1, I2C2, I2C3, I2C4, and I2C5. Among them, I2C1 is dedicated to managing the central processing unit and real-time clock, I2C2 is dedicated to managing the M.2 adapter card, I2C3 is dedicated to managing the M.2 slot, I2C4 is dedicated to managing complex programmable logic and clock buffers, and I2C5 is dedicated to managing the motherboard voltage regulator and sensors.

[0071] Both the master node and the controlled node can include, for example: Figure 13 The power board shown includes a sideband connector 1 (J20), a sideband connector 2 (J1), a sideband connector 3 (J29), and a power connector (PJ4). Sideband connector 1 is the first connector of the power board in the master control node, sideband connector 2 is the third connector of the power board in the master control node, sideband connector 3 is the second slave connector of the power board in the controlled node, and the power connector is the second connector of the power board in the master control node.

[0072] The following section describes the manager's management path in two parts.

[0073] Part 1, the second group of management ports (I2C10 to I2C12).

[0074] refer to Figures 13 to 16 Sideband connector 1 connects to connectors 4, 5, and 6 in the manager, corresponding to the three communication links from I2C10 to I2C12 respectively. Each of the three communication links between sideband connector 1 and sideband connector 2 is equipped with an I2C repeater. Sideband connector 2 connects to the Type-C interface of the master node.

[0075] The Type-C interface of the master node is connected to the Type-C interface of the controlled node.

[0076] The pins corresponding to I2C10 and I2C11 in the Type-C interface of the controlled node are connected to the switching board in the controlled node. The pins corresponding to I2C12 in the Type-C interface of the controlled node are connected to the sideband connector 3 on the power board of the controlled node.

[0077] The pins corresponding to I2C12 in the sideband connector 3 on the power board of the controlled node are connected to the I2C repeater (U23), and then the I2C repeater (U23) is connected to complex programmable logic devices, field replaceable units, input / output expanders, temperature sensors, electrically erasable programmable read-only memory, electric fuses, etc.

[0078] The I2C10 to I2C12 mentioned above are management ports specifically for the manager to manage slave devices such as switching boards, complex programmable logic devices, field-replaceable units, input / output expanders, temperature sensors, electrically erasable programmable read-only memory, and electric fuses in the controlled nodes. These are also known as the second set of management ports.

[0079] Part Two, the third group of management ports (I2C13 to I2C16).

[0080] The power connector connects to connectors 7, 8, 9, and 10 in the manager, which correspond to the four management ports I2C13 to I2C16, respectively.

[0081] First, on the master control node side, I2C13 is connected to the I2C switch (U32). Among them, the S0 of the I2C switch (U32) is connected to the I2C repeater (U24), the I2C repeater (U24) is connected to the PCIe connector (J21) on the power board, and the PCIe connector (J21) is connected to the PCIe adapter board.

[0082] The S1 port of the I2C switch (U32) is also connected to the I2C repeater (U25), which in turn is connected to the sideband connector 2. The sideband connector 2 is connected to the Type-C interface of the master node.

[0083] The Type-C interface of the master node is connected to the Type-C interface of the controlled node.

[0084] On the controlled node side, the pins of the Type-C interface of the controlled node corresponding to I2C13 are connected to the sideband connector 3 in the controlled node. The pins of the sideband connector 3 in the controlled node corresponding to I2C13 are connected to the I2C repeater (U24), which is then connected to the PCIE connector, and the PCIE connector (J21) is connected to the PCIE card in the controlled node.

[0085] In this way, when the management controller switches the I2C switch (U32) in the master node to S0, it can manage the PCIE adapter card in the master node; when the switch of the I2C switch (U32) is switched to S1, it can manage the PCIE adapter card in the controlled node.

[0086] Second, on the master control node side, I2C15 is connected to the I2C switch (U26). Specifically, the S0 pin of the I2C switch (U26) connects to the I2C repeater (U25), which in turn connects to the power supply unit connectors (PJ1 and PJ2) on the power board. Each power supply unit connector (PJ1 and PJ2) can connect to one or more power supply units (e.g., one power supply unit connector can connect to two power supply units). The S1 pin of the I2C switch (U26) connects to the I2C repeater (U24), which in turn connects to the sideband connector 2 in the master control node. The sideband connector 2 in the master control node connects to the Type-C interface of the master control node.

[0087] The Type-C interface of the master node is connected to the Type-C interface of the controlled node.

[0088] On the controlled node side, the pin corresponding to I2C13 in the Type-C interface of the controlled node is connected to the sideband connector 3 in the controlled node. The pin corresponding to I2C15 in the sideband connector 3 in the controlled node is connected to the I2C repeater (U25), which is then connected to the power supply unit connectors (PJ1 and PJ2), which are connected to the power supply unit in the controlled node.

[0089] In this way, when the management controller switches the I2C switch (U26) in the master node to S0, it can manage the power supply unit in the master node; when the switch of the I2C switch (U26) is switched to S1, it can manage the power supply unit in the controlled node.

[0090] Third, on the master node side, the I2C16 is connected to the I2C switch (U26).

[0091] The I2C switch (U26) has its S0 connection connected to the I2C repeater (U19), which is connected to the fan board connector (J10) on the power board, which is connected to the 8 fan boards in the master control node.

[0092] The S1 connection of the I2C switch (U26) is to the I2C repeater (U11), which is connected to the fan board connector (J11) on the power board, which is connected to the 4-fan board in the master node.

[0093] The S2 connector of the I2C switch (U26) connects to the I2C repeater (U13), which in turn connects to the sideband connector 2 on the power supply board. The sideband connector 2 connects to the Type-C interface of the master node.

[0094] The Type-C interface of the master node is connected to the Type-C interface of the controlled node.

[0095] On the controlled node side, the pins of the Type-C interface of the controlled node corresponding to I2C16 are connected to the sideband connector 3 in the controlled node. The pins of the sideband connector 3 corresponding to I2C16 are connected to the I2C repeater (U19) in the controlled node. The I2C repeater (U19) is connected to the fan board connector (J10) on the power board of the controlled node. The fan board connector (J10) connects to an 8-fan board.

[0096] Similarly, on the master node side, the S3 connection of the master node's I2C switch (U26) is connected to the I2C repeater (U11), which is connected to the sideband connector 2 on the power board. The sideband connector 2 is connected to the master node's Type-C interface.

[0097] The Type-C interface of the master node is connected to the Type-C interface of the controlled node.

[0098] On the controlled node side, the pins of the Type-C interface of the controlled node corresponding to I2C16 are connected to the sideband connector 3 in the controlled node. The pins of the sideband connector 3 corresponding to I2C16 are connected to the I2C repeater (U11) in the controlled node. The I2C repeater (U11) is connected to the fan board connector (J11) on the power board of the controlled node. The fan board connector (J11) is connected to a 4-fan board.

[0099] In this way, when the management controller switches the I2C switch (U26) in the master node to S0, it can manage the 8 fan boards in the master node; when the switch switches the I2C switch (U26) to S1, it can manage the 4 fan boards in the master node; when the switch switches the I2C switch (U26) to S2, it can manage the 8 fan boards in the controlled node; and when the switch switches the I2C switch (U26) to S3, it can manage the 4 fan boards in the controlled node.

[0100] The I2C13 port is the management port for the PCIe adapter cards included in both the master and slave nodes. I2C15 is the management port for the power supply units included in both the master and slave nodes. I2C16 is the management port for the fan boards included in both the master and slave nodes.

[0101] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0102] The foregoing has provided a detailed description of the main control circuit, main control node, controlled node, and computing system provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A main control circuit, characterized in that, The main control circuit includes: The power board includes a first connector, a second connector, a third connector, and a first group of master devices of the master control node; the first connector and the second connector are respectively connected to the third connector, the third connector is connected to the slave device in the controlled node, and the first group of master devices is connected to the second connector; the master control circuit is located inside the master control node and outside the controlled node; The manager includes a first set of management ports, a second set of management ports, and a third set of management ports; the first set of management ports is connected to the second set of master devices of the master control node, the second set of management ports is connected to the first connector, and the third set of management ports is connected to the second connector.

2. The main control circuit according to claim 1, characterized in that, The second connector includes a first set of pins and a second set of pins. The first set of pins is connected to the first set of master devices, and the second set of pins is connected to the third connector.

3. The main control circuit according to claim 2, characterized in that, The master control node also includes a third group of master devices, which are located outside the power board. The power board also includes a first switch, which includes a first master switch, a first slave switch, and a second slave switch. The first master switch is connected to the second group of pins, the first slave switch is connected to the third connector, and the second slave switch is connected to the first master device in the third group of master devices. The manager is used to control the connection between the first master switch and the first slave switch, or to control the connection between the first master switch and the second slave switch.

4. The main control circuit according to claim 3, characterized in that, The power board also includes a second switch, which includes a second master switch, a third slave switch, and a fourth slave switch. The second master switch is connected to the second set of pins, the third slave switch is connected to the third connector, and the fourth slave switch is connected to the second master device in the third set of master devices. The manager is used to control the connection between the second master switch and the third slave switch, or to control the connection between the master switch and the fourth slave switch.

5. The main control circuit according to claim 3 or 4, characterized in that, The master control node also includes a motherboard, the manager is located inside the motherboard, the first group of master devices, the second group of master devices and the third group of master devices are located outside the motherboard, and the motherboard includes the fourth group of master devices of the master control node; The manager also includes a fourth set of management ports, which are connected to the fourth set of master devices.

6. The main control circuit according to claim 5, characterized in that, The first group of main devices is located within the power board, and the first group of main devices includes one or more of the following devices in the power board: complex programmable logic devices, field-replaceable units, input / output expanders, temperature sensors, electrically erasable programmable read-only memory, and electric fuses.

7. The main control circuit according to claim 5, characterized in that, The second group of master devices is located outside the power board, and includes one or more devices among the following: non-volatile memory high-speed channel backplane, smart network card management port controller, and switching board.

8. The main control circuit according to claim 5, characterized in that, The third group of main devices is located outside the power supply board. The third group of main devices includes one or more of the following: a peripheral component interconnect fast bus adapter card, a power supply unit, a fan board, and a four-channel small hot-swappable optical module management board.

9. The main control circuit according to any one of claims 1 to 4, characterized in that, Both the first connector and the third connector are sideband connectors on the power board, and the second connector is a power connector in the power board.

10. The main control circuit according to any one of claims 1 to 4, characterized in that, The main control circuit further includes at least one repeater connected between the first connector and the third connector, and between the second connector and the third connector.

11. A master control node, characterized in that, include: Main equipment; The main control circuit as described in any one of claims 1 to 10.

12. A controlled node, characterized in that, include: The slave device is connected to the master control circuit as described in any one of claims 1 to 10.

13. The controlled node according to claim 12, characterized in that, The controlled node further includes a power supply board and a first slave connector. The power supply board includes a second slave connector. The slave device includes a first group of slave devices and a second group of slave devices. The second group of slave devices includes a first subgroup of slave devices and a second subgroup of slave devices. The first slave connector is connected to the second slave connector and the main control circuit respectively; the second slave connector is connected to the first group of slave devices and the second subgroup of slave devices respectively; and the first slave connector is connected to the first subgroup of slave devices. The first group of slave devices is located inside the slave power board, and the second group of slave devices is located outside the slave power board.

14. The controlled node according to claim 13, characterized in that, The power supply board in the slave circuit has the same structure as the power supply board in the master circuit.

15. A computing system, characterized in that, include: The master control node as described in claim 11; The controlled node as described in any one of claims 12 to 14; The master node is connected to the controlled node.

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