Connecting device and electronic device

Abstract

The application discloses a connecting device and electronic equipment, and relates to the technical field of servers. On one hand, the application provides a connecting device which is coupled with a first circuit board. The connecting device comprises: a sideband connecting circuit which is coupled with the first circuit board and is configured to output a power enable signal to the first circuit board and receive a power feedback signal related to the power enable signal output by the first circuit board; at least one data transmission circuit group which is coupled with the first circuit board and is configured to receive a first data signal output by the first circuit board, the first data signal comprising at least one of a PCIe high-speed signal, a PCIe reference clock signal and a PCIe reset signal; and a first control circuit comprising at least one data port, one data port being coupled with one data transmission circuit group, the first control circuit being configured to receive and process the first data signal.

Description

Technical Field

[0001] This application relates to the field of server technology, and more particularly to a connection device and electronic device. Background Technology

[0002] With the rapid development of the digital economy, modern server data centers are facing an explosive growth in computing power and storage demands. As the core node of a data center, the compatibility and scalability of the server's architecture directly determine the deployment flexibility and service support capabilities of the data center. Against this industry backdrop, servers need to be compatible with diverse expansion devices such as NVMe (Non-Volatile Memory Express) hard drives, PCIe (Peripheral Component Interconnect Express) cards, and OCP (Open Compute Project) network cards to meet the flexible deployment needs of different business scenarios such as cloud computing and big data analytics, and to promote the efficient implementation of data processing and storage services.

[0003] In practical applications, these diverse expansion devices need to be coupled to the server motherboard via specific connection devices to achieve signal transmission and data interaction. However, the interface signal definitions of different expansion devices, such as hard drive backplanes, PCIe adapter boards, and OCP adapter boards, vary greatly. This requires the design of dedicated connectors and signal links, resulting in high motherboard adaptation costs, poor expandability, and an inability to flexibly adjust the connection type of PCIe ports for expansion devices according to actual business needs. This can easily lead to resource waste, performance bottlenecks, or device compatibility conflicts.

[0004] Therefore, there is an expectation for an improved connection device and electronic device that can at least solve one of the above problems. Summary of the Invention

[0005] This application provides a connection device and an electronic device to at least solve the problems of high cost and poor expandability of motherboards for adapting to different expansion devices in the related art.

[0006] On one hand, a connection device is provided, coupled to a first circuit board. The connection device includes: a sideband connection circuit coupled to the first circuit board, configured to output a power enable signal to the first circuit board and receive a power feedback signal related to the power enable signal output by the first circuit board; at least one data transmission circuit group coupled to the first circuit board, configured to receive a first data signal output by the first circuit board, the first data signal including at least one of a PCIe high-speed signal, a PCIe reference clock signal, and a PCIe reset signal; and a first control circuit including at least one data port coupled to the data transmission circuit group, the first control circuit being configured to receive the first data signal and process the first data signal.

[0007] On the other hand, an electronic device is provided, including the connection device as described above.

[0008] This application constructs a topology by splitting and integrating the signals received and / or transmitted by the connection device. The embodiments of this application construct a topology in which a data transmission circuit group receives a first data signal, and a sideband connection circuit receives and / or outputs sideband control signals. This structure classifies and integrates different types of signals, enabling the data transmission circuit group to receive the first data signal related to the PCIe signal, and the sideband connection circuit to receive and / or output sideband control signals related to the first circuit board, such as power enable signals and power feedback signals. The first data signal is, for example, a common signal between different expansion devices, while the sideband control signals differ depending on the definition of different types of first circuit boards or expansion devices. This application achieves broad adaptability of the connection device to various types of first circuit boards by transmitting the common first data signal through the data transmission circuit group and placing the potentially differing sideband control signals in the sideband connection circuit. This achieves compatibility with various types of expansion devices, dynamic bandwidth allocation, and efficient management, thereby promoting the evolution of electronic device storage and expansion architecture towards a more efficient, flexible, and low-cost direction. Attached Figure Description

[0009] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the structure of an electronic device according to some embodiments; Figure 2 This is a schematic diagram of a connection device according to some embodiments; Figure 3This is a schematic diagram of another connection device provided according to some embodiments; Figure 4 This is a schematic diagram of a data transmission circuit according to some embodiments; Figure 5 This is a schematic diagram of the structure of another electronic device according to some embodiments; Figure 6 This is a schematic diagram of a bandwidth configuration circuit according to some embodiments. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0012] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0013] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0014] In this document, the use of "configured to" implies open and inclusive language, which does not exclude devices configured to perform additional tasks or steps. In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document. In describing some embodiments, the term "connected" and its derivative expressions may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other.

[0015] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0016] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "multiple" means two or more. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," both including the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural.

[0017] As used herein, depending on the context, the term “if” is optionally interpreted as meaning “when…” or “in response to determination” or “in response to detection.” Similarly, depending on the context, the phrases “if it is determined…” or “if [the stated condition or event] is detected” are optionally interpreted as meaning “in response to determination…” or “in response to detection [the stated condition or event]” or “in response to detection [the stated condition or event].” The use of “based on” implies openness and inclusivity, as processes, steps, calculations, or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0018] With the rapid development of the digital economy, servers need to be compatible with a variety of expansion devices such as NVMe hard drives, PCIe standard cards, and OCP network cards. These diverse expansion devices need to be coupled to the server through specific connection devices to achieve signal transmission and data interaction. However, different expansion devices have significantly different interface signal definitions, requiring the design of dedicated connectors and signal links. This results in high motherboard adaptation costs and poor expandability, making it impossible to flexibly adjust the connection type of PCIe port expansion devices according to actual business needs in practical applications.

[0019] In view of this, embodiments of this application provide a connection device and an electronic device. See also... Figure 1 This is a schematic diagram of the structure of an electronic device according to some embodiments.

[0020] The electronic device 100 includes a connection device 200 and a first circuit board 300, wherein the connection device 200 is coupled to the first circuit board 300.

[0021] In some embodiments, the connection device 200 includes a power supply circuit 210, a sideband connection circuit 220, a data transmission circuit group 230, and a first control circuit 240.

[0022] The power supply circuit 210 is configured to provide a power signal VDD, for example, to power the first circuit board 300. Exemplarily, the voltage of the power signal VDD is 12V or 3.3V.

[0023] The sideband connection circuit 220 is coupled to the first circuit board 300. The sideband connection circuit 220 is configured to transmit a sideband control signal Vsb, which includes, for example, at least one of a board parameter signal, a board communication signal, a power enable signal EN, a power feedback signal PWRGD, and an in-situ signal PRSNT. The board parameter signal and the board communication signal are transmitted, for example, using an IIC (Inter-Integrated Circuit) bus.

[0024] In this embodiment, the first circuit board 300 is configured to output an in-situ signal PRSNT to the sideband connection circuit 220, the in-situ signal PRSNT being used to indicate that the first circuit board 300 has been coupled to the connection device 200.

[0025] After acquiring the presence signal PRSNT through the sideband connection circuit 220, the first control circuit 240 in the connection device 200 can determine whether the first circuit board 300 has been inserted and reliably coupled. Therefore, the connection device 200 can automatically detect the insertion status of the first circuit board 300, avoiding accidental power supply or misconfiguration when not connected or with an unreliable connection. This improves the reliability and ease of use of the connection device 200 and further enhances its adaptability to diverse expansion devices. For example, the presence signal PRSNT can serve as a trigger condition for the first control circuit 240 to initiate subsequent control processes.

[0026] For example, the first circuit board 300 is also configured to power the first circuit board 300 and / or an extension device coupled to the first circuit board 300 based on a power signal VDD in response to a power enable signal EN.

[0027] For example, the first circuit board 300 is also configured to output a power feedback signal PWRGD to the sideband connection circuit 220, wherein the power feedback signal PWRGD is used to characterize that the power status of the first circuit board 300 and / or the extension device coupled to the first circuit board 300 is good.

[0028] Therefore, this application achieves complete timing control of the power supply process for the first circuit board 300 and its extended devices by coordinating the presence signal PRSNT, the power enable signal EN, and the power feedback signal PWRGD: first, presence is detected; then, power is enabled according to the device type; and finally, subsequent operations are performed only after confirming that the power supply is good. This process improves the reliability and safety of the connection device 200 in supplying power to different extended devices, avoids malfunctions or even equipment damage due to improper power supply timing, and expands the applicability of the connection device 200.

[0029] For example, board parameter signals are used to read relevant information of the first board 300, and board communication signals are used to connect the device 200 to the first board 300 or to the expansion device.

[0030] The data transmission circuit group 230 is coupled to the first circuit board 300, and the data transmission circuit group 230 is configured to receive the first data signal Vp.

[0031] The data transmission circuit group 230 includes one or more data transmission circuits. In this embodiment, the data transmission circuit group 230 is described as including two data transmission circuits: a first data transmission circuit 231 and a second data transmission circuit 232. Exemplarily, the data transmission circuit group 230 may include one, three, or four data transmission circuits, and this application does not limit this.

[0032] The first data transmission circuit 231 is coupled to the first circuit board 300 and configured to receive the first sub-data signal Vp1. The second data transmission circuit 232 is coupled to the first circuit board 300 and configured to receive the second sub-data signal Vp2.

[0033] In this embodiment, the first data transmission circuit 231 and the second data transmission circuit 232 are selected from MCIO (Multi-fiber Channel I / O) connectors. For example, the first data transmission circuit 231 and the second data transmission circuit 232 are selected from MCIO X8 connectors.

[0034] For example, each first circuit board 300 is paired with a data transmission circuit group 230, and the connection device 200 may include both types of connectors simultaneously. The first data signal Vp includes one or more first sub-data signals, such as a first sub-data signal Vp1 and a second sub-data signal Vp2. The first data signal Vp includes a PCIe high-speed signal.

[0035] The first control circuit 240 includes at least one data port coupled to a data transmission circuit group 230. The first control circuit 240 is configured to receive and process a first data signal Vp. For example, the first control circuit 240 is selected from a CPU (Central Processing Unit).

[0036] The first circuit board 300 is coupled to the connection device 200 and is used for coupling with an expansion device. For example, the first circuit board 300 can be selected from any one of a hard drive backplane, a PCIe adapter board, or an OCP adapter board. The expansion device can be selected from PCIe devices such as NVMe hard drives, PCIe standard cards, or OCP network cards.

[0037] For electronic device 100, it needs to be coupled to different expansion devices. Therefore, electronic device 100 needs to be coupled to different first circuit boards 300 to achieve coupling with the corresponding expansion devices. The connection device 200 provided in this application embodiment effectively improves the compatibility and expandability of electronic device 100, and is compatible with various first circuit boards 300 such as hard disk backplanes, PCIe adapter boards, and OCP adapter boards. Electronic device 100 does not need to design separate connection schemes for different first circuit boards 300 or expansion devices, which not only significantly reduces the adaptation cost of adding expansion devices to the electronic device 100 system, but also better supports the diverse configuration needs of electronic device 100.

[0038] Specifically, the data transmission circuit group 230 is mainly used to receive general data signals such as the first data signal Vp. These signals are universal across different expansion devices, and the data transmission circuit group 230 can be reused when the first circuit board 300 is coupled to different expansion devices. For signals that differ due to the type of the first circuit board 300, such as board parameter signals, board communication signals, power enable signals EN, power feedback signals PWRGD, and presence signals PRSNT, this embodiment integrates them into the sideband connection circuit 220 for transmission. Thus, by dedicating the data transmission circuit group 230 to receiving general data such as the first data signal Vp, and the sideband connection circuit 220 receiving and / or outputting sideband control signals related to the first circuit board 300, the connection device 200 achieves broad adaptability to various types of first circuit boards 300.

[0039] Furthermore, by splitting and integrating the signals transmitted by the connection device 200, this embodiment of the application constructs a topology in which the data transmission circuit group 230 receives the first data signal Vp, the sideband connection circuit 220 receives and / or outputs the sideband control signal Vsb, and the power supply circuit 210 is independently powered. This structure, by classifying and integrating different types of signals, enables the data transmission circuit group to receive the first data signal Vp related to the PCIe signal, and the sideband connection circuit 220 to receive and / or output the sideband control signal Vsb related to the first circuit board 300, such as the power enable signal EN and the power feedback signal PWRGD. Among them, the first data signal Vp is a common signal between different expansion devices, while the sideband control signal Vsb varies depending on the definition of different types of first circuit boards 300 or expansion devices. This application transmits the common first data signal Vp through the data transmission circuit group 230 and places the potentially different sideband control signal Vsb into the sideband connection circuit 220, thereby realizing the wide adaptation of the connection device to various types of first circuit boards, achieving compatibility with various types of expansion devices, effectively reducing the types of connectors required by the connection device 200 and the number of connection cables required by the electronic device 100, further optimizing the PCB (Printed Circuit Board) layout, reducing hardware design complexity and manufacturing difficulty.

[0040] In some embodiments, see Figure 2 This is a schematic diagram of a connection device according to some embodiments. The connection device 200 includes a first control circuit 240 and a plurality of data transmission circuit groups 230.

[0041] The first control circuit 240 includes multiple data ports, namely PE0, PE1...Pen.

[0042] The connection device 200 includes multiple data transmission circuit groups 230 corresponding to the number of data ports. The multiple data transmission circuit groups 230 are respectively coupled to multiple data ports of the first control circuit 240 to output the corresponding first data signal Vp to the data ports of the first control circuit 240.

[0043] One data port of the first control circuit 240 is coupled to a data transmission circuit group 230. Generally, the bandwidth of each data port of the first control circuit 240 is at most x16. Therefore, in this embodiment, two data transmission circuits are used to form a data transmission circuit group to form a bandwidth of x16. That is, each data transmission circuit group 230 includes a first data transmission circuit 231 and a second data transmission circuit 232. The bandwidth of the first data transmission circuit 231 and the second data transmission circuit 232 is, for example, x8. The first data transmission circuit 231 leads out channel 0-channel 7, and the second data transmission circuit 232 leads out channel 8-channel 15.

[0044] During system design, to meet the different functional requirements of electronic device 100 in different application scenarios, electronic device 100 needs to be coupled with different expansion devices. These expansion devices may have different bandwidths; for example, NVMe hard drives have a bandwidth of x4 or x2, PCIe network cards have a bandwidth of x16, and Multi OCP network cards have two x8 bandwidths. Furthermore, a data transmission circuit group 230 can be spliced ​​together from two x8 data transmission circuits to form a complete x16 high-speed channel, ensuring that each data port of the first control circuit 240 can interact with the first circuit board 300 with maximum bandwidth, meeting the data transmission bandwidth requirements of high-speed expansion devices. When the connection device 200 is coupled with different expansion devices, a bandwidth matching the expansion device needs to be set to ensure the stable and reliable operation of electronic device 100. Therefore, this application embodiment also provides a connection device 200 capable of configuring the bandwidth of the data transmission circuit group 230, such as... Figure 3 As shown.

[0045] See Figure 1 and Figure 3 , Figure 3This is a schematic diagram of another connection device provided according to some embodiments. In some embodiments, the connection device 200 further includes an input / output expansion circuit 250 and a second control circuit 260. The data transmission circuit group 230 is also configured to receive a connection control signal Vs, which includes, for example, a first sub-connection control signal Vs1 received by the first data transmission circuit 231 and a second sub-connection control signal Vs2 received by the second data transmission circuit 232. Exemplarily, the connection control signal Vs includes a first bandwidth configuration signal Vbw1 provided by the first circuit board 300, the first sub-connection control signal Vs1 includes a first sub-bandwidth configuration signal Vbw11, and the second sub-connection control signal Vs2 includes a second sub-bandwidth configuration signal Vbw12.

[0046] In this embodiment, the first bandwidth configuration signal Vbw1 includes two sub-bandwidth configuration signals, namely the first sub-bandwidth configuration signal Vbw11 and the second sub-bandwidth configuration signal Vbw12. The first data transmission circuit 231 is configured to receive the first sub-bandwidth configuration signal Vbw11, which is used to characterize the bandwidth configuration information of the first data transmission circuit 231. The second data transmission circuit 232 is configured to receive the second sub-bandwidth configuration signal Vbw12, which is used to characterize the bandwidth configuration signal of the second data transmission circuit 232. For example, when the data transmission circuit group 230 includes two data transmission circuits, the first data transmission circuit 231 and the second data transmission circuit 232, the first bandwidth configuration signal Vbw1 includes a four-bit binary code, the first sub-bandwidth configuration signal Vbw11 includes a two-bit binary code, and the second sub-bandwidth configuration signal Vbw12 includes a two-bit binary code.

[0047] The input / output expansion circuit 250 provides a low-speed input / output interface, facilitating signal interaction between the connection device 200 and more types of peripheral management modules. The second control circuit 260 can share some of the control tasks of the first control circuit 240, such as handling the connection control signal Vs and managing the input / output expansion circuit 250, thereby improving the control efficiency and response speed of the entire connection device 200.

[0048] This application provides a bandwidth configuration signal directly through the first circuit board 300, enabling the connection device 200 to automatically set the bandwidth for each data transmission circuit. When different types of expansion devices are inserted, the first circuit board 300 only needs to provide the corresponding first bandwidth configuration signal Vbw1, allowing the data transmission circuit group 230 in the connection device 200 to be configured as needed into different combinations such as x2, x4, x8, and x16, thereby adapting to the different PCIe channel width requirements of various expansion devices such as NVMe hard drives, PCIe standard cards, and OCP network cards. This eliminates the need for the connection device 200 to design dedicated connectors and signal links for each expansion device, and the motherboard side does not need to rearrange wiring for different expansion devices, further reducing motherboard adaptation costs and improving the versatility and expansion flexibility of the connection device 200. This allows for convenient adjustment of the PCIe port expansion device connection type according to business needs in practical applications.

[0049] The input / output expansion circuit 250 is coupled to the data transmission circuit group 230 to receive the first bandwidth configuration signal Vbw1, and the input / output expansion circuit 250 is configured to output a second bandwidth configuration signal Vbw2 based on the first bandwidth configuration signal Vbw1.

[0050] In this embodiment, the input / output expansion circuit 250 can also be coupled to multiple data transmission circuit groups 230 to receive multiple first bandwidth configuration signals Vbw1 output by the multiple data transmission circuit groups 230. The input / output expansion circuit 250 is also configured to output a second bandwidth configuration signal Vbw2 based on the multiple first bandwidth configuration signals Vbw1. The input / output expansion circuit 250 includes, for example, 16 input / output I / O pins, and each binary signal of the first bandwidth configuration signal Vbw1 is mapped one-to-one to one input / output I / O pin of the input / output expansion circuit 250. When the first bandwidth configuration signal Vbw1 output by the data transmission circuit group 230 includes a four-bit binary code, the input / output expansion circuit 250 can be used to receive the first bandwidth configuration signals Vbw1 output by four groups of data transmission circuit groups 230. If the connection device 200 includes more groups of data transmission circuit groups 230, the number of input / output expansion circuits 250 can be increased according to the actual application scenario.

[0051] For example, the input of the input / output expansion circuit 250 receives one or more first bandwidth configuration signals Vbw1, which are selected from binary code. Specifically, the input / output expansion circuit 250 is configured to output a second bandwidth configuration signal Vbw2 suitable for IIC transmission based on the first bandwidth configuration signal Vbw1 of binary code.

[0052] In this embodiment, the input / output expansion circuit 250 is coupled to the data transmission circuit group 230. It receives the first bandwidth configuration signal Vbw1 in parallel binary form provided by the first circuit board 300 through the data transmission circuit group 230, and converts it into a second bandwidth configuration signal Vbw2 suitable for IIC transmission. Since the second bandwidth configuration signal Vbw2 adopts the IIC bus format, it can easily cooperate with the existing IIC signal channel in the sideband connection circuit 220, enabling the first control circuit 240 or the second control circuit 260 to uniformly read the bandwidth configuration information of each data transmission circuit group 230 through the sideband connection circuit 220. This eliminates the need to set up a dedicated parallel signal reading line for each data transmission circuit group 230, further reducing the wiring complexity inside the connection device 200.

[0053] The second control circuit 260 is coupled to the input / output expansion circuit 250, and the second control circuit 260 is configured to output a third bandwidth configuration signal Vbw3 based on the second bandwidth configuration signal Vbw2. The second control circuit 260 is, for example, selected from a CPLD (Complex Programmable Logic Device).

[0054] In this embodiment, the second control circuit 260 is specifically configured to sequentially read the level states of each input / output (IO) pin of the input / output expansion circuit 250, and output a third bandwidth configuration signal Vbw3 generated based on the level states of each IO pin to the first control circuit 240. The third bandwidth configuration signal Vbw3 is transmitted, for example, via eSPI (Enhanced Serial Peripheral Interface).

[0055] The first control circuit 240 is also coupled to the second control circuit 260. Specifically, the first control circuit 240 is configured to group the first data signal Vp based on Vbw3 and a bandwidth lookup table, and process different groups of the first data signal Vp respectively. That is, the first control circuit 240 is configured to allocate the bandwidth of the current data port based on the third bandwidth configuration signal Vbw3 and the bandwidth lookup table.

[0056] In some embodiments, the second control circuit 260 is further configured to output a third bandwidth configuration signal Vbw3 to the third control circuit 270 or the BIOS (Basic Input / Output System), with the BIOS performing the bandwidth configuration.

[0057] In this embodiment, the bandwidth lookup table is shown in Table 1. When the first sub-bandwidth configuration signal Vbw11 is 00, it indicates that the first data transmission circuit 231 is not coupled to the expansion device. When the first sub-bandwidth configuration signal Vbw11 is 01, it indicates that the first data transmission circuit 231 is configured with one x8 bandwidth. When the first sub-bandwidth configuration signal Vbw11 is 11, it indicates that the first data transmission circuit 231 is configured with two x4 bandwidths. When the first sub-bandwidth configuration signal Vbw11 is 10, it indicates that the first data transmission circuit 231 is configured with four x2 bandwidths. The correspondence between the second sub-bandwidth configuration signal Vbw12 and the bandwidth of the second data transmission circuit 232 is similar, and therefore will not be described again.

[0058] The second control circuit 260 sequentially reads the level states of each input / output IO pin of the input / output expansion circuit 250, and generates a third bandwidth configuration signal Vbw3 based on these level states. This signal is then output to the first control circuit 240 or the third control circuit 270 / BIOS via a serial interface such as eSPI. This process converts the parallel bandwidth configuration information, originally scattered across multiple IO pins, into a serial, unified signal format that is easy for the control circuit to read. This allows the first control circuit 240 to directly connect to each data transmission circuit group 230 without occupying a large number of IO pins, simplifying the control signal wiring within the connection device 200 and reducing the IO resource usage of the first control circuit 240.

[0059] Furthermore, the second control circuit 260 can also output a third bandwidth configuration signal Vbw3 to the BIOS, which will then configure the bandwidth during the system startup phase. This means that the connection device 200 is compatible with the existing platform management mechanism of the electronic device 100, and can achieve bandwidth configuration through the BIOS, further enhancing the applicability of the connection device 200 on different platforms.

[0060] Table 1. Bandwidth Lookup Table

[0061] The connection device 200 receives the first bandwidth configuration signal Vbw1 output by the first circuit board 300, processes the first bandwidth configuration signal Vbw1, and outputs it to the first control circuit 240.

[0062] The connection device 200 provided in this application embodiment can automatically match the optimal bandwidth according to the type of expansion device coupled to the first circuit board 300, supporting various expansion devices with bandwidths of x2, x4, x8, and x16, and realizing dynamic bandwidth adaptation. Specifically, the first bandwidth configuration signal Vbw1 includes a four-bit binary code, and different bandwidth configurations are obtained according to the bandwidth lookup table, covering the different bandwidth requirements of expansion devices such as NVMe hard drives and PCIe network cards.

[0063] The connection device 200 in this embodiment also has a bandwidth adaptive function, which can automatically select the optimal configuration among multiple bandwidth modes such as x2, x4, x8, and x16 according to the bandwidth configuration signal Vbw1 output by the first circuit board 300, so as to achieve dynamic and seamless bandwidth adaptation. Specifically, the connection device 200 determines the specific bandwidth configuration by parsing the first bandwidth configuration signal Vbw1 (e.g., a four-bit binary code) and according to a predefined mapping strategy (such as a bandwidth lookup table), thereby achieving accurate response and on-demand allocation to the bandwidth requirements of the extended device.

[0064] In some embodiments, the connection device 200 further includes a third control circuit 270, which is coupled to the second control circuit 260 and the sideband connection circuit 220. The third control circuit 270 is configured to output an access communication signal based on the sideband control signal Vsb. The third control circuit 270 is, for example, selected from a BMC (Baseboard Management Controller). The third control circuit 270 outputs signals to the second control circuit 260 via an IIC, or receives signals output by the second control circuit 260 via an IIC.

[0065] In this embodiment, the sideband connection circuit 220 outputs the presence signal PRSNT in the sideband control signal Vsb to the second control circuit 260 and the third control circuit 270 to indicate that the first circuit board 300 is in place, thereby enabling the third control circuit 270 to communicate and access according to the different logic of the first circuit board 300.

[0066] The sideband connection circuit 220 simultaneously outputs the presence signal PRSNT to both the second control circuit 260 and the third control circuit 270, enabling the third control circuit 270 to promptly detect whether the first circuit board 300 has been coupled to the connection device 200. Thus, once the first circuit board 300 is inserted, the third control circuit 270 can initiate subsequent processes based on the presence signal PRSNT, communicating and accessing according to the different logic of the first circuit board 300, thereby achieving automatic identification and management of different types of expansion devices.

[0067] Meanwhile, the third control circuit 270 outputs access communication signals based on the sideband control signal Vsb, enabling the connection device 200 to perform status monitoring, configuration distribution, and fault diagnosis on the first circuit board 300 and expansion devices without occupying the high-speed data path. This design allows the connection device 200 to not only automatically adapt to the high-speed data interfaces of diverse expansion devices such as NVMe hard drives, PCIe standard cards, and OCP network cards, but also to provide a unified management interface at the system level. This eliminates the need to design dedicated management circuits and communication protocols for each type of expansion device, further simplifying the circuit structure and reducing production costs.

[0068] For example, the data transmission circuit provided in this application can be as follows: Figure 4 As shown, Figure 4 This is a schematic diagram of a data transmission circuit according to some embodiments. The first data transmission circuit 231 is used as an example for illustration. To enable the data transmission circuit group 230 to be flexibly compatible with various bandwidth expansion devices, the first data transmission circuit 231 uses an MCIO connector with a bandwidth of x8.

[0069] The first data transmission circuit 231 includes the P and N pins of TX_[7:0] and the P and N pins of RX_[7:0], wherein the P and N pins are... Figure 4 The positive and negative pins in the circuit. The first data signal Vp is mainly received or output by the P and N pins of TX_[7:0] and the P and N pins of RX_[7:0]. In addition, some related signals that are compatible with the first circuit board 300 are integrated into the SB pin of the first data transmission circuit 231. The first data transmission circuit 231 also includes, for example, the A and B pins of SB0, SB1, SB2, SB6, SB8, SB10, SB12, SB14, SB16 and SB18.

[0070] In some embodiments, the SB pin of the first data transmission circuit 231 can also be used to receive signals such as PCIe card related signals, PCIe source judgment signals, and VPP (Virtual Pin Port) function related identification signals, and output the above signals to the relevant circuits of the connection device 200 such as the data transmission circuit group 230 or the input / output expansion circuit 250.

[0071] PCIe standard card related signals include the wake-up signal WAKE for the first circuit board 300 to wake up the first control circuit 240, and the power management signal PCIe_PWRBRK for the first circuit board 300.

[0072] The PCIe source determination signal includes a processor selection signal CPU_select, which indicates whether the PCIe signal on the first circuit board 300 originates from CPU0 or CPU1. In other words, the PCIe source determination signal includes a processor selection signal CPU_select, which indicates whether the first data signal originates from processor 0 or processor 1.

[0073] Alternatively, the PCIe source determination signal includes an HBA determination signal CPU_HBA_select, which indicates whether the PCIe connection of the first circuit board 300 is directly connected to the CPU or originates from an HBA (Host Bus Adapter). In other words, the PCIe source determination signal includes a host bus adapter determination signal CPU_HBA_select, which indicates whether the first data signal originates from the processor or from the host bus adapter.

[0074] VPP function-related identification signals include the VPP address signal VPPaddr and the VPP bus signal VPPI2C.

[0075] In this application, the first data transmission circuit 231, in addition to having TX / RX pins for high-speed differential data transmission, also includes various control and identification signal pins required to adapt to the first circuit board 300. These pins can receive PCIe card-related signals, PCIe source judgment signals, and VPP function-related identification signals, and output these signals to relevant circuits in the connection device 200, such as the data transmission circuit group 230 or the input / output expansion circuit 250. Thus, in addition to the high-speed data path, an auxiliary signal path is established between the first circuit board 300 and the connection device 200 through the same first data transmission circuit 231. This eliminates the need for separate sideband connectors or cables between the connection device 200 and the first circuit board 300 to transmit these management signals, reducing the number of connectors and motherboard wiring complexity, and improving the integration and reliability of the connection device 200.

[0076] For example, the WAKE signal and the PCIe_PWRBRK power management signal enable the connection device 200 to support the power management functions of a standard PCIe card. The CPU_select processor selection signal or the CPU_HBA_select host bus adapter judgment signal enables the connection device 200 to identify the source of the current PCIe signal. In multi-processor systems or scenarios with both direct CPU connection and HBA connection, this identification signal helps the first control circuit 240 or the second control circuit 260 correctly determine the processor affiliation or link type corresponding to each data port, thereby rationally allocating bandwidth and configuring data paths, avoiding signal conflicts or resource waste caused by incorrect source identification. The VPP address signal VPPaddr and the VPP bus signal VPPI2C enable the connection device 200 to identify and manage virtual pin interface functions, further enhancing the connection device 200's functional support and configuration flexibility for diverse expansion devices.

[0077] In some embodiments, the first data signal Vp further includes at least one of PCIe signals such as the PCIe reference clock signal PCIe 100M Clock and the PCIe reset signal PCIe Reset.

[0078] The first data transmission circuit 231 is also configured to receive at least one of the following: a PCIe high-speed signal, a PCIe reference clock signal PCIe100M Clock, and a PCIe reset signal PCIe Reset.

[0079] The wake-up signal WAKE and the power management signal PCIe_PWRBRK are also integrated into the first data transmission circuit 231, which enables the connection device 200 to integrate all signals except for the power circuit 210 and the sideband connection circuit 220 into the first data transmission circuit 231, whether it is coupled to a PCIe card or a hard drive, thereby adapting to various types of expansion devices.

[0080] When the expansion device is a hard drive and the first circuit board 300 is selected from the hard drive backplane, the expansion device also has hot-swapping capability. VPP is the core mechanism supporting hot-swapping of the expansion device. It transmits hot-swapping control signals through the IIC bus to replace the physical pins in related technologies. When the expansion device is inserted or removed, the physical state change of the slot is converted into a digital signal. The IIC encodes the signal into a VPP data packet. After the first control circuit 240 parses the VPP packet, it triggers an interrupt to notify the operating system, thereby achieving secure hot-swapping management. In addition, the VPP signal can also be used to control the LED indicator lights of the NVMe hard drive or other devices in the electronic device 100. The first control circuit 240 directly sends VPP test signals through the IIC bus, which can realize the control of the hard drive positioning light, status light, and error light. In view of this, the embodiments of this application also provide an electronic device, such as Figure 5 As shown.

[0081] See Figure 5 The diagram below is a schematic diagram of the structure of another electronic device provided according to some embodiments. In some embodiments, the first control circuit 240 is also configured to output a first virtual interface signal VPPI, and the connection device 200 further includes a level conversion circuit 280 and a multiplexing circuit 290.

[0082] The level conversion circuit 280 is coupled to the first control circuit 240 to receive the first virtual interface signal VPPI. The level conversion circuit 280 is configured to perform level conversion on the first virtual interface signal VPPI and output the level-converted first virtual interface signal VPPI.

[0083] Multiplexing circuit 290 is coupled to level conversion circuit 280 to receive the first virtual interface signal VPPI after level conversion. Multiplexing circuit 290 is configured to output one or more second virtual interface signals based on the first virtual interface signal VPPI. The second virtual interface signals include, for example, a first channel signal VPP0, a second channel signal VPP1, a third channel signal VPP2, a fourth channel signal VPP3, a fifth channel signal VPP4, and a sixth channel signal VPP5. Figure 5Taking the multiplexing circuit 290, which includes six output ports (C0, C1, C2, C3, C4, and C5), as an example, the output ports C0, C1, C2, C3, C4, and C5 respectively output six second virtual interface signals: a first channel signal VPP0, a second channel signal VPP1, a third channel signal VPP2, a fourth channel signal VPP3, a fifth channel signal VPP4, and a sixth channel signal VPP5. Exemplarily, the multiplexing circuit 290 can also output one, two, or three second virtual interface signals; this application does not limit this.

[0084] In this embodiment, the multiplexing circuit 290 is selected from an 8-channel IIC bus multiplexer, which can solve the address conflict problem when multiple IIC slave devices share the bus and realize time-sharing access to multiple devices with the same address.

[0085] In some embodiments, the connection control signal Vs further includes a second virtual interface signal, and the data transmission circuit group 230 is also coupled to the multiplexing circuit 290 to receive the second virtual interface signal, with one data transmission circuit group 230 receiving one second virtual interface signal.

[0086] The data transmission circuit group 230 is also configured to receive the second virtual interface signal and output the second virtual interface signal to the first circuit board 300.

[0087] The first control circuit 240, through the level conversion circuit 280 and the multiplexing circuit 290, can expand the limited virtual interface signals into multiple independently accessible virtual interface channels. This allows the connection device 200 to flexibly manage the virtual pin functions of various expansion devices when connected, adapting to the management needs of various expansion devices such as NVMe hard drives, PCIe standard cards, and OCP network cards. In practical applications, users can replace or add expansion devices according to business needs. The connection device 200 can identify and manage new devices through the multiplexing mechanism without modifying the motherboard hardware design, thereby improving the expandability, versatility, and maintainability of the electronic device 100, while reducing motherboard adaptation costs.

[0088] See Figure 5The electronic device 100 also includes a fourth control circuit 310. The fourth control circuit 310 includes one or more input / output expansion modules 311, which are coupled to the data transmission circuit group 230 to receive a second virtual interface signal. The input / output expansion modules 311 are configured to output test signals based on the second virtual interface signal. The fourth control circuit may be, for example, selected from a CPLD.

[0089] In this embodiment, the fourth control circuit 310 includes an input / output expansion module 311 with an I2C / I2C to general-purpose input / output (GPIO) interface. Through I2C or the expanded GPIO, the first control circuit 240 operates the GPIO by outputting a first virtual interface signal VPPI on one port, thereby enabling testing of the first circuit board 300 and / or extended devices using VPP. Exemplarily, the fourth control circuit 310 utilizes logic simulation to include one or more input / output expansion modules 311.

[0090] In some embodiments, the input / output expansion module 311 is specifically configured to transmit signals with the first control circuit 240 via the IIC bus. In response to operations such as start signal, address matching, and data transmission, the input / output expansion module 311 outputs a serial data signal SDA and a serial clock signal SCL.

[0091] In some embodiments, the input / output expansion module 311 further includes one or more registers for configuring signal input / output direction, reading input status, setting output level, etc. When the first control circuit 240 accesses the registers of the input / output expansion module 311 via the IIC bus, the fourth control circuit 310 is configured to resolve address and data and perform corresponding read / write operations on the registers of the input / output expansion module 311. For example, the fourth control circuit 310 maps a storage unit to an output register of the input / output expansion module 311. When the first control circuit 240 writes data to this register, the fourth control circuit 310 controls the corresponding GPIO output level according to the written value.

[0092] In some embodiments, the input / output expansion module 311 is specifically configured to output corresponding signals via GPIO based on the serial data signal SDA and the serial clock signal SCL, or to output the serial data signal SDA and the serial clock signal SCL based on the level state of GPIO.

[0093] In this embodiment, the fourth control circuit 310 controls its GPIO pins to output corresponding level signals based on register configuration, serial data signal SDA, and serial clock signal SCL, thereby driving the corresponding LEDs, etc. For example, the output register inside the fourth control circuit 310 is configured to a high level, and the corresponding GPIO pin of the fourth control circuit 310 outputs a high-level signal, thus lighting the LED coupled to that pin.

[0094] In some embodiments, the first control circuit 240 outputs a first virtual interface signal VPPI, which includes at least the target device's VPP address signal VPPaddr and a test command. The first virtual interface signal VPPI is processed by a level conversion circuit 280, a multiplexing circuit 290, and a data transmission circuit group 230 to output a test signal Vtst. The input / output expansion module 311 parses the target VPP address based on the test signal Vtst and matches it with its own address. After matching the target VPP address, the fourth control circuit 310 modifies the corresponding register value based on the test signal Vtst and controls the GPIO pins of the fourth control circuit 310 to output the corresponding level signal to drive the corresponding light-emitting diode (LED). The mapping relationship of the VPP address signal VPPaddr is shown in Table 2.

[0095] Table 2. Mapping Relationship of VPP Address Signal VPPaddr

[0096] In some embodiments, the first circuit board 300 can be coupled to multiple hard drives, and one input / output expansion module 311 can perform testing of two hard drives. When the number of hard drives coupled to the first circuit board 300 is greater than two, the fourth control circuit 310 includes multiple input / output expansion modules 311 to perform testing of multiple hard drives. The first control circuit 240 accesses the input / output expansion modules 311 included in the fourth control circuit 310 via IIC, which requires an IIC address.

[0097] Therefore, the first control circuit 240 and the fourth control circuit 310 need to define a set of IIC addresses, and the fourth control circuit 310 needs to be able to resolve which CPU and which data port the current PCIe signal comes from.

[0098] In some embodiments, the following table rules are defined: a data port refers to which data port of the CPU the CPU's PCIe originates from; the VPP address signal VPPaddr is a unique set of addresses that primarily map to the data port address; for example, if the VPP address signal VPPaddr is 0001, it maps to data port PE0<7:0>. The data transmission circuit group 230 outputs a test signal Vtst based on the second virtual interface signal VPP0 and transmits the test signal Vtst to the fourth control circuit 310 of the first circuit board 300. The fourth control circuit 310 determines the data port address of the first control circuit 240 based on the test signal Vtst, and further determines that the IIC communication address of this data port is 0x40.

[0099] In some embodiments, the first control circuit 240 includes two CPUs, CPU0 and CPU1. The data transmission circuit group 230 is further configured to receive a processor selection signal CPU_select to distinguish whether the PCIe-related signals originate from CPU0 or CPU1 of the first control circuit 240. For example, a low level CPU_select indicates that the PCIe-related signals originate from CPU0 of the first control circuit 240, and a high level CPU_select indicates that the PCIe-related signals originate from CPU1 of the first control circuit 240.

[0100] In some embodiments, the bandwidth of the extended device is x2, and the first data transmission circuit 231 or the second data transmission circuit 232 can connect four extended devices. In this case, the first control circuit 240 and the fourth control circuit 310 are mapped according to an address with a bandwidth of x2. When the fourth control circuit 310 detects that the VPP address signal VPPaddr is 0001, the fourth control circuit 310 determines the data port address of the first control circuit 240 according to the test signal Vtst, and further determines that the IIC communication address of the data port is 0x40 and 0x42.

[0101] In some embodiments, the electronic device 100 further includes a bandwidth configuration circuit 320, which is configured to output a first bandwidth configuration signal Vbw1.

[0102] Figure 5 The bandwidth configuration circuit 320 shown in the figure employs, for example, as... Figure 6 The structure shown is implemented as follows: Figure 6 This is a schematic diagram of a bandwidth configuration circuit according to some embodiments. The bandwidth configuration circuit 320 includes at least one bandwidth configuration module. Figure 6In the illustrated embodiment, the bandwidth configuration circuit 320 includes two bandwidth configuration modules, a first bandwidth configuration module 321 and a second bandwidth configuration module 322, as an example for explanation. It should be understood that the bandwidth configuration circuit 320 in this embodiment may also include one bandwidth configuration module, three bandwidth configuration modules, or four bandwidth configuration modules, and this application does not limit this.

[0103] The first bandwidth configuration module 321 includes a first resistor R1 and a second resistor R2. The second terminal of the first resistor R1 is grounded. The first terminal of the second resistor R2 is coupled to a first voltage terminal VCC, and the second terminal of the second resistor R2 is grounded, for example, the second voltage terminal. The voltage signals output by the first resistor R1 and the second resistor R2 are used to form a first bandwidth configuration signal Vbw1. For example, the first terminal of the first resistor R1 and the first terminal of the second resistor R2 are used to output a first sub-bandwidth configuration signal Vbw11. Figure 6 In this context, the first sub-bandwidth configuration signal Vbw11 is, for example, "10". It should be understood that the connection methods of the first resistor R1, the second resistor R2, the first voltage terminal VCC, and the ground terminal can be adjusted to form different first bandwidth configuration signals.

[0104] The second bandwidth configuration module 322 includes a third resistor R3 and a fourth resistor R4, the second terminals of which are both grounded. The voltage signals output by the third resistor R3 and the fourth resistor R4 are used to form a first bandwidth configuration signal Vbw1. For example, the first terminals of the third resistor R3 and the fourth resistor R4 are used to output a second sub-bandwidth configuration signal Vbw12. Figure 6 In this context, the second sub-bandwidth configuration signal Vbw12 is, for example, "00". The first bandwidth configuration signal Vbw1 includes the first sub-bandwidth configuration signal Vbw11 and the second sub-bandwidth configuration signal Vbw12.

[0105] Combination Figure 3 and Figure 6 The transmission process of the first bandwidth configuration signal Vbw1 is described below. In some embodiments, the first data transmission circuit 231 is coupled to the first bandwidth configuration module 321 to receive the first sub-bandwidth configuration signal Vbw11 output by the first bandwidth configuration module 321, and outputs the first sub-bandwidth configuration signal Vbw11 to the input / output expansion circuit 250. The second data transmission circuit 232 is coupled to the second bandwidth configuration module 322 to receive the second sub-bandwidth configuration signal Vbw12 output by the second bandwidth configuration module 322, and outputs the second sub-bandwidth configuration signal Vbw12 to the input / output expansion circuit 250.

[0106] The electronic device 100 provided in this application embodiment uses a multiplexing circuit 290 to solve the IIC address conflict problem, and works with the fourth control circuit 310 to simulate the input / output expansion module 311 to realize the hot-plugging and testing of multiple expansion devices VPP, wherein the test includes, for example, LED lighting control.

[0107] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0108] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0109] The foregoing has provided a detailed description of a connection device and electronic device provided in this application. The electronic device is, for example, selected from servers. Specific examples have been used herein to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A connecting device, said connecting device being coupled to a first circuit board, characterized in that, The connecting device includes: A sideband connection circuit, coupled to the first circuit board, is configured to output a power enable signal to the first circuit board and receive a power feedback signal related to the power enable signal output by the first circuit board. At least one data transmission circuit group, the data transmission circuit group being coupled to the first circuit board and configured to receive a first data signal output by the first circuit board, the first data signal including at least one of a PCIe high-speed signal, a PCIe reference clock signal and a PCIe reset signal; A first control circuit includes at least one data port, one of the data ports being coupled to a data transmission circuit group, the first control circuit being configured to receive the first data signal and process the first data signal.

2. The connecting device according to claim 1, characterized in that, The first control circuit includes multiple data ports, and the connection device includes: Multiple data transmission circuit groups are provided, and each of the multiple data transmission circuit groups is coupled to a corresponding data port.

3. The connecting device according to claim 1, characterized in that, The data transmission circuit group includes one or more data transmission circuits; The data transmission circuit is coupled to the first circuit board and is configured to receive the first sub-data signal; The first data signal includes one or more of the first sub-data signals.

4. The connecting device according to claim 3, characterized in that, It also includes input / output expansion circuitry and a second control circuitry; The data transmission circuit group is also configured to receive a first bandwidth configuration signal provided by the first circuit board; The input / output expansion circuit is coupled to the data transmission circuit group and is configured to output a second bandwidth configuration signal based on the first bandwidth configuration signal. The second control circuit is coupled to the input / output expansion circuit and is configured to output a third bandwidth configuration signal based on the second bandwidth configuration signal; The first control circuit is also coupled to the second control circuit. Specifically, the first control circuit is configured to group the first data signal and process different groups of the first data signal based on the third bandwidth configuration signal and the bandwidth lookup table.

5. The connecting device according to claim 4, characterized in that, The second control circuit is specifically configured to sequentially read the level states of each input / output pin of the input / output expansion circuit, and generate a third bandwidth configuration signal based on the level states of each input / output pin.

6. The connecting device according to claim 4, characterized in that, The input / output expansion circuit is coupled to a plurality of the data transmission circuit groups, and the input / output expansion circuit is configured to output a second bandwidth configuration signal based on a plurality of first bandwidth configuration signals.

7. The connecting device according to claim 6, characterized in that, The first bandwidth configuration signal includes two sub-bandwidth configuration signals, each of which includes two binary bits; When the sub-bandwidth configuration signal is 00, it indicates that the data transmission circuit is not coupled to the extension device; When the sub-bandwidth configuration signal is 01, it indicates that the data transmission circuit is configured with an x8 bandwidth; When the sub-bandwidth configuration signal is 11, it indicates that the data transmission circuit is configured with two x4 bandwidths; When the sub-bandwidth configuration signal is 10, it indicates that the data transmission circuit is configured with four x2 bandwidths.

8. The connecting device according to claim 4, characterized in that, Also includes: The third control circuit, coupled to the second control circuit and the sideband connection circuit, is configured to output access communication signals based on the sideband control signals.

9. The connecting device according to any one of claims 1 to 8, characterized in that, The first control circuit is also configured to output a first virtual interface signal, and the connection device further includes: A level conversion circuit, coupled to the first control circuit, is configured to perform level conversion on the first virtual interface signal; A multiplexing circuit, coupled to the level conversion circuit, is configured to output one or more second virtual interface signals based on the first virtual interface signal; The data transmission circuit group is also coupled to the multiplexing circuit, and one of the data transmission circuit groups receives one second virtual interface signal.

10. The connecting device according to any one of claims 1 to 8, characterized in that, The sideband connection circuit is further configured to receive an in-situ signal output by the first circuit; the in-situ signal is used to characterize the coupling between the first circuit board and the connection device.

11. The connecting device according to any one of claims 1 to 8, characterized in that, The data transmission circuit is also configured to receive a PCIe source determination signal; The PCIe source determination signal includes a processor selection signal indicating whether the first data signal originates from processor 0 or processor 1; or, The PCIe source determination signal includes a host bus adapter determination signal for indicating whether the first data signal comes from the processor or from the host bus adapter.

12. The connecting device according to any one of claims 1 to 8, characterized in that, Also includes: A power supply circuit configured to provide a power signal; The power signal includes at least one of a 12V power signal and a 3.3V power signal.

13. An electronic device, characterized in that, include: A connecting device, wherein the connecting device is the connecting device as described in any one of claims 1-12.

14. The electronic device according to claim 13, characterized in that, It also includes a fourth control circuit, which includes an input / output expansion module; The input / output expansion module is coupled to the data transmission circuit group of the connection device to receive the second virtual interface signal, and the input / output expansion module is configured to output a test signal based on the second virtual interface signal.

15. The electronic device according to claim 14, characterized in that, The input / output expansion module is also configured to output a serial data signal and a serial clock signal in response to at least one of a start signal, an address matching operation, and a data transmission operation.

16. The electronic device according to claim 14, characterized in that, The input / output expansion module also includes one or more registers; The register is used to store the write data of the first control circuit, and the write data of the first control circuit is used to indicate at least one of the following: the input / output direction of the configuration signal, reading the input status, and setting the output level.

17. The electronic device according to claim 16, characterized in that, The fourth control circuit is coupled to the register and is further configured to control the output level of the corresponding general-purpose input / output interface based on the write data of the first control circuit stored in the register.

18. The electronic device according to any one of claims 13 to 17, characterized in that, Also includes: A bandwidth configuration circuit, which is configured to output a first bandwidth configuration signal.

19. The electronic device according to claim 18, characterized in that, The bandwidth configuration circuit includes one or more bandwidth configuration modules, the bandwidth configuration module including: A first resistor, configured to be electrically connected to a first voltage terminal or a second voltage terminal; A second resistor, configured to be electrically connected to either the first voltage terminal or the second voltage terminal; The voltage signals output by the first resistor and the second resistor of the bandwidth configuration module are used to form a sub-bandwidth configuration signal.

20. The electronic device according to any one of claims 13 to 17, characterized in that, Also includes: A first circuit board is configured to output an in-situ signal when coupled to the connection device.

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