Layout structure of bidirectional buffer

Abstract

The utility model provides a layout structure of a bidirectional buffer. The layout structure comprises a bonding pad layout area and a first / second port layout area, the bonding pad layout area comprises a first bonding pad used for signal input, a second bonding pad used for signal input and output, a third bonding pad used for being connected with a power supply and a fourth bonding pad used for being grounded; the first port layout area and the second port layout area respectively comprise a control port area and at least one data port area; the first control port area and the second control port area are respectively connected with the first bonding pads, and the at least one first data port area and the at least one second data port area are sequentially arranged along the first direction and are connected with the second bonding pads in a one-to-one correspondence manner; one of the first and second control port areas is configured to control the transmission direction of a data signal, the other one is configured to control the output state of the circuit, and the first and second data port areas comprise a bidirectional data logic module configured to receive and send out the data signal. The layout structure can realize miniaturization of the chip.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology. Specifically, it relates to a layout structure of a bidirectional buffer. Background Technology

[0002] Bidirectional buffers can enable the selection and switching of multiple data streams to meet different data selection requirements; they can also serve as circuit drivers, providing sufficient current and power. Therefore, bidirectional buffers are widely used in applications such as bidirectional communication between the main control chip and the controlled device, data selection, data isolation, and motor driving. They are commonly found in the interfaces of LCD screens, printers, sensors, or communication modules, and have a wide range of applications.

[0003] The eight-channel tri-state output bidirectional buffer is one of the most typical bidirectional buffer products. Firstly, to achieve flexible signal control and bidirectional data transmission, the circuit needs two tri-state gates to control the input and output respectively, allowing the circuit to switch flexibly between input and output. Secondly, the transmission of 8-bit, 16-bit, 32-bit, and 64-bit data (power of 2) between the main control chip and the controlled device is most common; therefore, the eight-channel bidirectional buffer is the most widely used. When less than eight channels of data transmission are required, only some channels need to be selected; when more than eight channels of data transmission are required, multiple eight-channel bidirectional buffers can be used simultaneously.

[0004] As application scenarios become more and more widespread, eight-channel tri-state output bidirectional buffers are gradually developing towards miniaturization and micro-miniaturization. Therefore, how to optimize their structure is a practical problem that needs to be solved. Utility Model Content

[0005] To address the aforementioned technical problems, this invention proposes a layout structure for a bidirectional buffer. By rationally arranging each layout area, the layout areas are arranged in a regular and compact manner, which helps to reduce the size of the chip.

[0006] To achieve the above objectives, the layout structure of the bidirectional buffer provided by this utility model includes a pad layout area, a first port layout area, and a second port layout area.

[0007] The pad layout area includes two first pads for signal input, at least one pair of second pads for signal input and output, a third pad for connecting power supply, and a fourth pad for grounding;

[0008] Two first pads are located on one side of the pad layout area along a first direction, and the two first pads are distributed along a second direction; two pairs of second pads are distributed along the second direction and are arranged sequentially with the first pads along the first direction, with the first direction perpendicular to the second direction;

[0009] The first port layout area and the second port layout area are arranged along the second direction. The first port layout area includes a first control port area and at least one first data port area connected by a metal wiring layer. The second port layout area includes a second control port area and at least one second data port area connected by a metal wiring layer.

[0010] The first control port area and the second control port area are respectively connected to the first pad; at least one first data port area and at least one second data port area are arranged sequentially along the first direction and are connected to the second pad one by one.

[0011] One of the first control port area and the second control port area is configured to control the transmission direction of the data signal, and the other is configured to control the output state of the circuit. The first data port area and the second data port area include a bidirectional data logic module, which is configured to both receive and transmit data signals.

[0012] Optionally, the first control port area and the second control port area are disposed below the first pad in a third-party direction, and the third-party direction is perpendicular to the aforementioned first direction and second direction, respectively; the first data port area and the second data port area are disposed below the corresponding second pad in a third-party direction.

[0013] Optionally, the third pad and the fourth pad are respectively disposed on both sides of the pad layout area along the first direction, and the third pad is disposed between a pair of second pads adjacent to the first pad.

[0014] Optionally, the first data port area and the second data port area have the same structure.

[0015] Optionally, the first data port area and the second data port area include a first submodule, a second submodule and a third submodule; the first submodule includes an output NMOS transistor, the second submodule is a bidirectional data logic module, and the third submodule includes an output PMOS transistor.

[0016] Optionally, the second submodule is positioned in the second direction between the first and third submodules to achieve a compact arrangement.

[0017] Optionally, the first submodule and the third submodule are connected to the second pad corresponding to the data port area.

[0018] Optionally, the first control port area and the second control port area are symmetrically arranged in the second direction.

[0019] Optionally, the first control port area includes a first control module (112), and the second control port area includes a second control module;

[0020] The first control module is configured such that when the first control module receives a high-level signal, the first data port area receives a data signal and the second data port area sends a data signal; when the first control module receives a low-level signal, the second data port area receives a data signal and the first data port area sends a data signal.

[0021] The second control module is configured such that when the second control module receives a high-level signal, the circuit output is in a high-impedance state, and when the second control module receives a low-level signal, the circuit is in a data signal transmission state.

[0022] Optionally, the first control port area further includes a first electrostatic discharge (ESD) protection structure, and the second control port area further includes a second ESD protection structure. The first ESD protection structure and the second ESD protection structure can protect the circuit from ESD damage.

[0023] Optionally, the first electrostatic protection structure and the second electrostatic protection structure are the same structure.

[0024] Optionally, the first electrostatic protection structure and the second electrostatic protection structure are separated by a first control module and a second control module.

[0025] Optionally, the first electrostatic protection structure and the second electrostatic protection structure can be independently selected from Zener diodes, solid-state diodes, varistors, or filters.

[0026] Optionally, the layout structure in the embodiments of this utility model achieves the effect of an eight-way tri-state output bidirectional buffer. The first port layout area includes eight first data port areas arranged sequentially along a first direction, and the second port layout area includes eight second data port areas arranged sequentially along the first direction.

[0027] Optionally, the aforementioned layout structure also includes an electrostatic discharge (ESD) protection zone configured for ESD protection of the power supply to ground; this ESD protection zone is located on one side of the first port layout area and the second port layout area along the first direction and is partially surrounded by the first port layout area and the second port layout area.

[0028] According to the layout structure of the bidirectional buffer provided in this embodiment of the utility model, by rationally arranging each layout area, each layout area becomes more regular and compact, thereby reducing the size of the layout and facilitating the miniaturization and micro-miniaturization of the chip.

[0029] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this utility model, the accompanying drawings used in the embodiments of this utility model will be described below. For clarity, the regions / structures in the drawings are not drawn to scale.

[0031] Figure 1 This diagram shows an overall layout of the bidirectional buffer in one embodiment of the present invention.

[0032] Figure 2 This diagram shows a schematic representation of the pad layout area of ​​a bidirectional buffer in one embodiment of the present invention.

[0033] Figure 3 This invention illustrates a schematic diagram of the structure of the first port layout area and the second port layout area of ​​a bidirectional buffer in one embodiment of the present invention.

[0034] Figure 4 This invention illustrates a schematic diagram of the structure of the first data port area and the second data port area of ​​a bidirectional buffer in one embodiment of the present invention.

[0035] Figure 5 The diagram shows a layout structure of an eight-channel tri-state output bidirectional buffer in a specific embodiment of the present invention.

[0036] 100 - First port layout area; 110 - First control port area; 111 - First electrostatic discharge (ESD) protection structure; 112 - First control module; 120 - First data port area; 121 - First submodule; 122 - Second submodule; 123 - Third submodule; 200 - Second port layout area; 210 - Second control port area; 211 - Second ESD protection structure; 212 - Second control module; 220 - Second data port area; 221 - First submodule; 222 - Second submodule; 223 - Third submodule; 300 - ESD protection zone; 900 - Pad layout area; 910 - First pad; 920 - Second pad; 930 - Third pad; 940 - Fourth pad. Detailed Implementation

[0037] In the description of this utility model, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0038] In related technologies, the layout size of bidirectional buffers is relatively large, resulting in a large overall chip size and affecting their application. To address this, this invention provides a new layout structure for bidirectional buffers, in which each layout area is arranged in a regular and compact manner, thereby saving layout area and making the overall chip size smaller, which in turn helps to reduce chip size.

[0039] like Figure 1 As shown, the overall layout structure of the bidirectional buffer includes at least a pad layout area 900, a first port layout area 100, and a second port layout area 200. The first port layout area 100 and the second port layout area 200 are located below the pad layout area 900.

[0040] The pad layout area 900 is the layout area for the chip to implement signal input and output. The pad layout area 900 has multiple pads, whose main function is to electrically connect to the pins via metal bonding wires to realize the input and / or output of information data. For example... Figure 1 and Figure 2 As shown, the pad layout area 900 includes four types of pads: first pad 910, second pad 920, third pad 930, and fourth pad 940. The first pad 910 is used for signal input; the second pads 920 are arranged in pairs for signal input and output; the third pad 930 is used for power connection; and the fourth pad 940 is used for grounding.

[0041] The first pad 910 and the second pad 920 are arranged in two rows within the pad layout area 900. Each row of pads includes a first pad 910 and at least one second pad 920 arranged sequentially along the first direction. The two first pads 910 are distributed along the second direction, and the two pairs of second pads 920 are distributed along the second direction. Figure 2 In the example shown, each row of pads includes one first pad 910 and eight second pads 920. The nine pads are arranged sequentially along the first direction, and the two rows of pads are symmetrical along the second direction. The first direction is perpendicular to the second direction, and both are parallel to the upper (or lower) surface of the chip substrate.

[0042] In an optional embodiment, the third pad 930 is disposed between two rows of second pads 920 and on a side relatively close to the first pad 910; the fourth pad 940 is disposed on the side of the pad layout area 900 opposite to the first pad 910. Specifically, the third pad 930 is disposed between a pair of second pads 920 adjacent to the first pad 910; the fourth pad 940 may be disposed between the pair of second pads 920 furthest from the first pad 910.

[0043] The pad layout area 900 is located above the first port layout area 100 and the second port layout area 200 in a third direction. The third direction is perpendicular to the first and second directions respectively; more specifically, the third direction points from the lower surface (or back surface) of the chip to the upper surface of the chip.

[0044] like Figure 3 As shown, the first port layout area 100 and the second port layout area 200 have the same structure and are arranged along the second direction. The first port layout area 100 includes a first control port area 110 and at least one first data port area 120, and the second port layout area 200 includes a second control port area 210 and at least one second data port area 220. The first control port area 110 and the second control port area 210 are symmetrically arranged in the second direction. For ease of description, the first control port area 110 and the second control port area 210 will be collectively referred to as control port areas, and the first data port area 120 and the second data port area 220 will be collectively referred to as data port areas.

[0045] In various optional embodiments of this utility model, the first control port area 110 is connected to one of the first pads 910, and the first data port area 120 is connected one-to-one with a row of second pads 920. The first control port area 110 and the first data port area 120 are arranged in the same way as the first pads 910 and second pads 920 in the row, that is, one first control port area 110 and at least one first data port area 120 are arranged sequentially along the first direction. The second control port area 210 is connected to another first pad 910, and the second data port area 220 is connected one-to-one with another row of second pads 920. Similarly, one second control port area 210 and at least one second data port area 220 are arranged sequentially along the first direction. In one optional embodiment, the control port area and data port area are arranged compactly along the first direction, which is beneficial to reducing the area of ​​the first port layout area 100 and the second port layout area 200.

[0046] The first control port area 110, the first data port area 120, the second control port area 210, and the second data port area 220 are respectively connected to the corresponding pads through a metal wiring layer. In an optional embodiment, the control port area and the corresponding first pad 910, and the data port area and the corresponding second pad 920 are arranged close to each other in the first and second directions. For example, according to the orthographic projection on the upper surface of the substrate, the orthographic projection of each pad is located in the corresponding port area. This allows the signal to be transmitted directly and smoothly, while avoiding the area occupation caused by excessively long transmission lines or too many bends.

[0047] In various optional embodiments of this utility model, the data port area is used to receive signals and input or output data information, and the control port area is used to receive signals and control the function of the circuit structure. In the first control port area 110 and the second control port area 210, one control port area is used for enable control, receiving an enable control signal input from the outside to the corresponding first pad 910, and controlling the output state of the circuit; the other control port area is used for direction control, receiving a direction control signal input from the outside to the corresponding first pad 910, and controlling the data signal transmission direction of the circuit.

[0048] Further reference Figure 3 The first control port area 110 includes a first electrostatic discharge (ESD) protection structure 111 and a first control module 112, and the second control port area 210 includes a second ESD protection structure 211 and a second control module 212. In the layout, the first control module 112 and the second control module 212 are arranged facing each other; along the second direction, the first ESD protection structure 111 and the second ESD protection structure 211 are respectively arranged on both sides of the layout, and the aforementioned first control module 112 and second control module 212 are arranged between the first ESD protection structure 111 and the second ESD protection structure 211.

[0049] The first electrostatic discharge (ESD) protection structure 111 and the second ESD protection structure 211 are used to protect the circuit structure from ESD damage. In various optional embodiments of this invention, the ESD protection structure can be a Zener diode, a solid-state diode, a varistor, a filter device, a composite ESD protection device, or an absorption circuit, etc. The first ESD protection structure 111 and the second ESD protection structure 211 can have the same structure.

[0050] In an optional embodiment, the first electrostatic discharge (ESD) protection structure 111 and the second ESD protection structure 211 are configured as the same ESD protection structure and are connected to the first control module 112 and the second control module 212 respectively through two ports.

[0051] The first control module 112 is a direction control module, used to receive direction control signals from the corresponding first pad 910, process them, and transmit them to the corresponding data port area. For example, when the direction control signal is high, the direction control module controls the first data port area 120 to receive external input signals, and the second data port area 220 to output signals; when the direction control signal is low, the direction control module controls the second data port area 220 to receive external input signals, and the first data port area 120 to output signals. The second control module 212 is an enable control module, used to receive enable control signals from the corresponding first pad 910, process them, and transmit them to the corresponding data port area. For example, when the enable control signal is high, the enable control module controls the data port area to achieve a high-impedance output; when the enable control signal is low, the enable control module controls the data port area to perform data signal transmission.

[0052] The structure of the first data port area 120 and the second data port area 220 is as follows: Figure 4 As shown, the first data port area 120 and the second data port area 220 have the same circuit structure and are arranged symmetrically at the center. The first data port area 120 includes a first submodule 121, a second submodule 122 and a third submodule 12; the second data port area 220 includes a first submodule 221, a second submodule 222 and a third submodule 223.

[0053] The first submodules 121 and 221 are output NMOS modules, each including an output NMOS transistor. The third submodules 123 and 223 are output PMOS modules, each including an output PMOS transistor. The second submodules 122 and 222 are bidirectional data logic modules. In the second direction, the second submodule is positioned between the first and third submodules, allowing the output signal lines of the bidirectional data logic module to be directly output to the NMOS and PMOS transistors in the second direction, which is beneficial for signal output.

[0054] In an optional embodiment, the first port layout area 100 includes eight first data port areas 120, and the second port layout area 200 includes eight second data port areas 220, enabling the layout structure to achieve the effect of an eight-way tri-state output bidirectional buffer. The first control port area 110 and the second control port area 210 are symmetrical in the second direction, the first control port area 110 and the eight first data port areas 120 are arranged along the first direction, and the second control port area 210 and the eight second data port areas 220 are arranged along the first direction.

[0055] Further reference Figure 1 and Figure 3The layout structure provided in this embodiment may further include an electrostatic discharge (ESD) protection zone 300, which is configured for ESD protection from power to ground. The ESD protection zone 300 is disposed on one side of the entire layout area along the first direction and is located near the first pad 910. For example... Figure 1 As shown, the electrostatic discharge protection zone 300 is partially surrounded by the first port layout area 100, and the electrostatic discharge protection zone 300 is partially surrounded by the second port layout area 200. Figure 3 As shown, along the second direction, the size of the first control port area 110 is slightly smaller than that of the first data port area 210, and the size of the second control port area 210 is slightly smaller than that of the second data port area 220. An electrostatic discharge (ESD) protection zone 300 is located between the first control port area 110 and the second control port area 210. By setting the ESD protection zone 300, an ESD protection structure for the power supply to ground is added, protecting the power supply from ESD damage and thus ensuring a normal power supply for the entire layout.

[0056] To further describe the features of the layout structure provided in the embodiments of this utility model, the layout structure of an eight-way tri-state output bidirectional buffer is used as an example below, in conjunction with... Figure 5 as well as Figures 1 to 4 An exemplary description is provided of the layout structure and the functions it implements.

[0057] The pad layout area 900 includes the following four types of pads:

[0058] The two first pads 910 are control pads DIR and OEb, respectively, wherein control pad DIR is connected to the first control port area 110 and control pad OEb is connected to the second control port area 210.

[0059] The second pad 920 includes 16 input / output pads: A1, A2, A3, A4, A5, A6, A7, A8, B1, B2, B3, B4, B5, B6, B7, and B8, which are evenly arranged in a 2x8 grid. The control pad OEb is arranged in a row with pads B1 to B8 along the first direction, and the control pad DIR is arranged in another row with pads A1 to A8 along the first direction. In addition, pads A1 and B1 are a pair, pads A2 and B2 are a pair, and so on.

[0060] The third pad 930 is the VCC pad connected to the power supply; the fourth pad 940 is the GND pad for grounding.

[0061] In the first control port area 110, the first control module 112 is a direction control module, which receives external control signals through the corresponding control pad DIR. In the second control port area 210, the second control module 212 is an enable control module, which receives external control signals through the corresponding control pad OEb. The first data port area 120 and the second data port area 220 are respectively connected to the corresponding input / output pads. When one set is used as a data input port, the other set is used as a data output port, forming 8 pairs of bidirectional data ports.

[0062] External control signals are transmitted to the enable control module via the control pad OEb and to the direction control module via the control pad DIR. After processing, they are transmitted to the 16 data port areas via the metal wiring layer to control the operation of the bidirectional data logic modules.

[0063] When the signal received by the control pad OEb is high, the data port is set to high impedance regardless of the signal received by the control pad DIR.

[0064] When the signal received by the control pad OEb is low, the data port enters the data signal transmission state. If the signal received by the control pad DIR is high, the first data port area 120 receives the external data input signal through pads A1-A8, processes it, and transmits it to the second data port area 220, where it is output to the outside through pads B1-B8. Conversely, if the signal received by the control pad DIR is low, the second data port area 220 receives the external data input signal through pads B1-B8, processes it, and transmits it to the first data port area 120, where it is output to the outside through pads A1-A8. This process enables the transmission of 8-bit data signals between buses, and allows for free switching of the data transmission direction during transmission.

[0065] In addition, the layout of this eight-channel tri-state output bidirectional buffer also includes an electrostatic discharge (ESD) protection zone 300, which is configured for ESD protection from power to ground. Along the second direction, the ESD protection zone 300 is located between the first control port area 110 and the second control port area 210, close to the first pad 910.

[0066] According to the layout structure of the bidirectional buffer provided by this utility model, by reasonably arranging the layout and wiring, the layout area is reduced while the signal transmission efficiency is improved and the production cost is reduced.

[0067] The above description is merely a specific implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.

Claims

1. A layout structure for a bidirectional buffer, characterized in that, It includes a pad layout area (900), a first port layout area (100), and a second port layout area (200); The pad layout area (900) includes two first pads (910) for signal input, at least one pair of second pads (920) for signal input and output, a third pad (930) for connecting to power supply, and a fourth pad (940) for grounding. Two first pads (910) are disposed on one side of the pad layout area (900) along a first direction, and the two first pads (910) are distributed along a second direction; two pairs of second pads (920) are distributed along the second direction and are arranged sequentially with the first pads (910) along the first direction, the first direction being perpendicular to the second direction; The first port layout area (100) and the second port layout area (200) are arranged along a second direction. The first port layout area (100) includes a first control port area (110) and at least one first data port area (120) connected by a metal wiring layer. The second port layout area (200) includes a second control port area (210) and at least one second data port area (220) connected by a metal wiring layer. The first control port area (110) and the second control port area (210) are respectively connected to the first pad (910), and at least one of the first data port areas (120) and at least one of the second data port areas (220) are arranged sequentially along the first direction and are connected to the second pad (920) one by one. One of the first control port area (110) and the second control port area (210) is configured to control the transmission direction of the data signal, and the other is configured to control the output state of the circuit. The first data port area (120) and the second data port area (220) include bidirectional data logic modules, which are configured to both receive and transmit data signals.

2. The layout structure according to claim 1, characterized in that, The first control port area (110) and the second control port area (210) are disposed below the first pad (910) in a third direction, the third direction being perpendicular to the first direction and the second direction, respectively; The first data port area (120) and the second data port area (220) are positioned below the corresponding second pad (920) in a third-party orientation.

3. The layout structure according to claim 1, characterized in that, The third pad (930) and the fourth pad (940) are respectively disposed on both sides of the pad layout area (900) along the first direction, and the third pad (930) is disposed between a pair of second pads (920) adjacent to the first pad (910).

4. The layout structure according to claim 1 or 2, characterized in that, The first data port area (120) and the second data port area (220) have the same structure.

5. The layout structure according to claim 4, characterized in that, The first data port area (120) includes a first submodule (121), a second submodule (122), and a third submodule (123); The first submodule (121) includes an output NMOS transistor, the second submodule (122) is the bidirectional data logic module, and the third submodule (123) includes an output PMOS transistor; The second submodule (122) is disposed in the second direction between the first submodule (121) and the third submodule (123).

6. The layout structure according to claim 1 or 2, characterized in that, The first control port area (110) and the second control port area (210) are symmetrically arranged in the second direction.

7. The layout structure according to claim 6, characterized in that, The first control port area (110) includes a first control module (112), and the second control port area (210) includes a second control module (212); The first control module (112) is configured such that when the first control module (112) receives a high-level signal, the first data port area (120) receives a data signal and the second data port area (220) sends a data signal; when the first control module (112) receives a low-level signal, the second data port area (220) receives a data signal and the first data port area (120) sends a data signal. The second control module (212) is configured such that when the second control module (212) receives a high-level signal, the circuit outputs a high-impedance state, and when the second control module (212) receives a low-level signal, the circuit is in a data signal transmission state.

8. The layout structure according to claim 7, characterized in that, The first control port area (110) further includes a first electrostatic discharge protection structure (111), and the second control port area (210) further includes a second electrostatic discharge protection structure (211). The first electrostatic discharge protection structure (111) and the second electrostatic discharge protection structure (211) are identical in structure. The first electrostatic discharge protection structure (111) and the second electrostatic discharge protection structure (211) are separated by a first control module (112) and a second control module (212).

9. The layout structure according to claim 1 or 2, characterized in that, The first port layout area (100) includes eight first data port areas (120) arranged sequentially along the first direction, and the second port layout area (200) includes eight second data port areas (220) arranged sequentially along the first direction.

10. The layout structure according to claim 1 or 2, characterized in that, It also includes an electrostatic discharge protection zone (300) configured for electrostatic discharge protection of the power supply to ground; The electrostatic protection zone (300) is located on one side of the first port layout area (100) and the second port layout area (200) along the first direction, and is partially surrounded by the first port layout area (100) and the second port layout area (200).

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