Pixel driving circuit and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a pixel driving circuit and a display panel, the pixel driving circuit comprising a data writing module, a first storage capacitor, a second storage capacitor, a driving transistor, a control transistor and a switch module; wherein the data writing module is used for writing amplitude information of a data signal into the data node and writing pulse width information of the data signal into the control node in a data writing stage; the switch module is used for selectively conducting in response to a switch control signal between a light-emitting stage and a reset stage, so as to establish a charge exchange path between the data node and the control node; the application selectively conducts according to a charge state or gray scale data in the charging stage through the switch module, realizes adaptive adjustment of the charging process on the same pixel driving circuit, effectively solves the problem of voltage spikes caused by residual charge coupling in the pixel driving circuit, and improves the display effect of the panel.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a pixel driving circuit and a display panel. Background Technology

[0002] Mini LED and Micro LED self-emissive display devices, due to their advantages such as high brightness, high contrast, and low power consumption, have become an important development direction in the high-end display field. The pixel driving circuit of such display devices typically includes a storage capacitor, a driving transistor, and a light-emitting device; the storage capacitor is used to store data voltage, and the driving transistor is used to drive the light-emitting device to emit light according to the data voltage.

[0003] However, during the reset phase of the pixel driving circuit in the related technology, the residual charge in the storage capacitor is coupled to the reset signal through the parasitic capacitance. The resulting voltage spike causes the driving transistor to be mis-turned, causing the dark field that should be black to emit abnormal light, which seriously affects the display contrast and black state performance.

[0004] Therefore, how to effectively eliminate voltage spikes caused by residual charge coupling in pixel driving circuits is a problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides a pixel driving circuit and a display panel. The application uses a switching module to selectively conduct during the charging stage based on the charge state or grayscale data, thereby achieving adaptive adjustment of the charging process on the same pixel driving circuit. This effectively solves the problem of voltage spikes caused by residual charge coupling in the pixel driving circuit and improves the display effect of the panel.

[0006] In a first aspect, this application provides a pixel driving circuit, comprising: a data writing module connected to a data node and a control node, configured to: during a data writing phase, write amplitude information of a data signal to the data node and write pulse width information of the data signal to the control node; a first storage capacitor connected between the data node and a power supply terminal; a second storage capacitor connected between the control node and a low-level terminal; a driving transistor, the control terminal of which is connected to the data node, and the first terminal of which is connected to the power supply terminal; a control transistor, the control terminal of which is connected to the output terminal of the data writing module, the first terminal of which is connected to the second terminal of the driving transistor, and the second terminal of which is connected to a light-emitting device; and a switching module connected between the data node and the control node, configured to: between a light-emitting phase and a reset phase, selectively conduct in response to a switch control signal to establish a charge exchange path between the data node and the control node; wherein the switch control signal is generated based on the charge state of the data node or the grayscale data of the current frame.

[0007] Secondly, this application provides a display panel, the display panel including: a pixel driving circuit; and a grayscale detection module connected to the switching module of the pixel driving circuit, configured to: generate a switching control signal based on the current grayscale data.

[0008] The technical solution provided in this application has at least the following beneficial effects: (1) This application sets up a switching module connected between the data node and the control node in the pixel driving circuit, and adds a charging stage between the light emission stage and the reset stage, so that the switching module selectively conducts in response to the switching control signal generated according to the charge state of the data node or the grayscale data of the current frame, and establishes a charge exchange path between the data node and the control node, so that the residual charge in the first storage capacitor and the second storage capacitor can be fully neutralized and redistributed, thereby adjusting the potential of the data node and the control node to a balanced state before the reset signal arrives, eliminating the problem of residual charge being coupled to the reset signal through parasitic capacitance to generate voltage spikes, avoiding the driving transistor from being mis-conducted due to voltage spikes, and improving the contrast and black state performance of the display panel.

[0009] (2) The switch control signal in this embodiment is generated based on the charge state of the data node or the grayscale data of the current frame. Therefore, the switch module can selectively conduct according to the actual residual charge of each pixel, so that the charging process matches the actual residual charge. Under different grayscale and different display scenarios, the charge neutralization of the adaptive degree can be achieved, avoiding the problem of insufficient or excessive charging under the fixed charging method, and ensuring that each pixel can enter a stable voltage state during the reset phase. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0011] Figure 1 The diagram shown is a schematic diagram of a pixel driving circuit provided in an embodiment of this application.

[0012] Figure 2 The figure shown is a timing diagram provided in an embodiment of this application.

[0013] Figure 3 The diagram shown is a schematic diagram of another pixel driving circuit provided in an embodiment of this application.

[0014] Figure 4 The diagram shown is a schematic diagram of a pixel driving circuit provided in an embodiment of this application.

[0015] Figure 5 The figure shown is a step diagram of a reference voltage provided in an embodiment of this application.

[0016] Figure 6 The diagram shown is a circuit diagram of a voltage detection module provided in an embodiment of this application.

[0017] Figure 7 The diagram shown is a structural schematic of a display panel provided in an embodiment of this application.

[0018] Figure 8 The diagram shown is a structural schematic of a grayscale detection module provided in an embodiment of this application.

[0019] Figure 9 The diagram shown is a structural schematic of a grayscale detection module provided in an embodiment of this application.

[0020] Explanation of reference numerals in the attached figures: 10. Display panel; 100. Pixel driving circuit; 110. Data writing module; 120. Switching module; 130. Voltage detection module; 131. First detection unit; 132. Second detection unit; 133. OR gate; 200. Grayscale detection module; 210. Difference calculation unit; 220. Threshold selection unit; 221. Logic judge; M1, driving transistor; M2, control transistor; M3, first write transistor; M4, second write transistor; C1, first storage capacitor; C2, second storage capacitor; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; T14, fourteenth transistor; T15, fifteenth transistor; T16, sixteenth transistor; T17, seventeenth transistor; T18, eighteenth transistor; T19, nineteenth transistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; A1, Data Node; A2, Control Node; Scan, Scan Line; PAM_Data, First Data Line; PWM_Data, Second Data Line; U1, First Comparator; U2, Second Comparator; U3, Third Comparator; VSS, Low Level Terminal; VDD, Power Supply Terminal; OLED, Light Emitting Device. Detailed Implementation

[0021] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0022] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0023] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0024] Figure 1 The diagram shown is a structural schematic of a pixel driving circuit 100 provided in an embodiment of this application; as shown Figure 1As shown, the pixel driving circuit 100 provided in this embodiment is applied to self-emissive display devices such as Mini LED and Micro LED. The pixel driving circuit 100 includes at least a data writing module 110, a first storage capacitor C1, a second storage capacitor C2, a driving transistor M1, a control transistor M2, and a switching module 120.

[0025] like Figure 1 As shown, in this embodiment, the data writing module 110 is connected to data node A1 and control node A2. During the data writing stage, the data writing module 110 writes the amplitude information of the data signal to data node A1 and the pulse width information of the data signal to control node A2. Specifically, the amplitude information refers to the amplitude modulation data used to control the light emission brightness, and the pulse width information refers to the pulse width modulation data used to control the light emission time. The data writing module 110 writes these two types of information to the corresponding storage capacitors through two paths, respectively, to prepare for subsequent light emission driving.

[0026] In this embodiment, the first storage capacitor C1 is connected between data node A1 and the power supply terminal VDD, and is used to store the amplitude information written to data node A1. During the light-emitting stage, the voltage stored in the first storage capacitor C1 acts on the control terminal of the driving transistor M1, determining the magnitude of the driving current output by the driving transistor M1, thereby controlling the brightness of the OLED. In this embodiment, the second storage capacitor C2 is connected between control node A2 and the low-level terminal VSS, and is used to store the pulse width information written to control node A2. During the light-emitting stage, the voltage stored in the second storage capacitor C2, together with the external scanning signal, acts to control the conduction time of the control transistor M2, thereby determining the light-emitting duration of the OLED.

[0027] In this embodiment, the control terminal of the driving transistor M1 is connected to the data node A1, and the first terminal of the driving transistor M1 is connected to the power supply terminal VDD. The driving transistor M1 is the main component in the pixel driving circuit 100 that controls the light emission brightness. It generates a corresponding driving current based on the voltage of the data node A1, and the magnitude of this driving current determines the light emission brightness of the OLED. In this embodiment, the control terminal of the control transistor M2 is connected to the output terminal of the data writing module 110, the first terminal of the control transistor M2 is connected to the second terminal of the driving transistor M1, and the second terminal of the control transistor M2 is connected to the OLED. The control transistor M2 is controlled by the voltage output of the data writing module 110 and is used to control the on / off time of the driving current flowing to the OLED, thereby determining the light emission duration of the OLED in each display cycle.

[0028] In some embodiments, the switch module 120 is connected between the data node A1 and the control node A2; after the light emission stage ends and before the reset stage begins, the switch module 120 selectively turns on in response to the switch control signal to establish a charge exchange path between the data node A1 and the control node A2; wherein, the reset stage is to reset the voltage on the data node A1 and the control node A2.

[0029] Specifically, after the light-emitting phase ends, a certain amount of charge remains in the first storage capacitor C1 and the second storage capacitor C2. The presence of this residual charge causes data node A1 and control node A2 to be in an uncertain voltage state at the beginning of the reset phase. When the reset signal arrives, this residual charge will couple to the reset signal through parasitic capacitance, generating a voltage spike. This voltage spike may cause the driving transistor M1 to be mis-activated, resulting in abnormal light emission from the dark field that should be black.

[0030] In this embodiment, the switching module 120 introduces a charging phase between the light-emitting phase and the reset phase. Before the reset signal arrives, it connects data node A1 and control node A2, allowing the residual charges in the first storage capacitor C1 and the second storage capacitor C2 to neutralize and redistribute. After charge neutralization, the voltages of data node A1 and control node A2 tend to be balanced, entering a relatively stable and safe voltage window. When the reset phase officially begins, since the residual charges have been effectively neutralized, the reset signal will not be affected by charge coupling interference, thereby avoiding voltage spikes and fundamentally eliminating the risk of abnormal light emission in the dark field.

[0031] It should also be noted that the switch module 120 is selectively turned on in response to the switch control signal, rather than being in a fixed state of being fully on or fully off. In other words, the switch module 120 does not simply perform the same degree of charge neutralization in every cycle, but determines whether to turn on and the degree of turn-on based on the actual charge state of the pixel or the grayscale data of the current frame, thereby achieving a match between the charging process and the actual residual charge.

[0032] This combination Figure 2 The timing diagram shown below illustrates the working principle of the pixel driving circuit 100 in this embodiment: (1) Data writing stage: The data writing module 110 is in working state, writing the amplitude information of the data signal into the data node A1 and storing it in the first storage capacitor C1; at the same time, it writes the pulse width information of the data signal into the control node A2 and stores it in the second storage capacitor C2; at this time, the data node A1 and the control node A2 respectively establish the potential corresponding to the gray level to be displayed, preparing for subsequent light emission driving.

[0033] (2) Light-emitting stage: The driving transistor M1 generates a corresponding driving current based on the voltage of data node A1. The magnitude of this driving current determines the brightness of the OLED. Simultaneously, the control transistor M2 controls the on / off time of the driving current flowing to the OLED based on the comparison result between the voltage of control node A2 and the external ramp signal, thereby determining the light-emitting duration of the OLED in this display cycle. During this stage, the switching module 120 is in the off state, there is no charge exchange path between data node A1 and control node A2, and the first storage capacitor C1 and the second storage capacitor C2 work independently.

[0034] (3) Charging stage: The switch module 120 is turned on in response to the switch control signal, and a charge exchange path is established between the data node A1 and the control node A2. The residual charge in the data node A1 and the control node A2 flows from the node with higher potential to the node with lower potential, and charge neutralization and redistribution occur, so that the potential of the data node A1 and the control node A2 tends to be balanced and enters a relatively stable voltage state.

[0035] (4) Reset Phase: A reset signal is applied to data node A1 and control node A2 to perform a reset operation. Since the residual charge in the first storage capacitor C1 and the second storage capacitor C2 has been fully neutralized and redistributed through the charge exchange path during the charging phase, the potentials of data node A1 and control node A2 are within a relatively stable and safe voltage window. Therefore, when the reset signal arrives, the residual charge will not couple to the reset signal through parasitic capacitance to generate a voltage spike, thus avoiding the problem of the driving transistor M1 being mis-activated and abnormal light emission in the dark field, ensuring the black state performance and contrast of the display panel 10.

[0036] In summary, this application, by setting a switching module 120 connected between data node A1 and control node A2 in the pixel driving circuit 100 and adding a charging phase between the light emission phase and the reset phase, enables the switching module 120 to selectively conduct in response to a switching control signal generated based on the charge state of data node A1 or the grayscale data of the current frame. This establishes a charge exchange path between data node A1 and control node A2, allowing the residual charge in the first storage capacitor C1 and the second storage capacitor C2 to be fully neutralized and redistributed. As a result, the potentials of data node A1 and control node A2 are adjusted to a balanced state before the reset signal arrives, eliminating the problem of residual charge coupling to the reset signal through parasitic capacitance and generating voltage spikes. This also avoids the driving transistor M1 from being mis-converted due to voltage spikes, thus improving the contrast and black state performance of the display panel 10.

[0037] Optionally, since the switch control signal is generated based on the charge state of data node A1 or the grayscale data of the current frame, the switch module 120 can selectively turn on according to the actual residual charge of each pixel, so that the charging process matches the actual residual charge. Under different grayscale and different display scenarios, adaptive charge neutralization can be achieved, avoiding the problem of insufficient or excessive charging under the fixed charging method, and ensuring that each pixel can enter a stable voltage state during the reset phase.

[0038] Therefore, this application achieves adaptive adjustment of the charging process and effective suppression of dark field luminescence on the same pixel driving circuit 100 by selectively turning on the switch module 120 according to the charge state or grayscale data during the charging stage, thereby improving the display effect of the self-emissive display device in high-contrast display scenarios.

[0039] Figure 3 The diagram shown is a structural schematic of another pixel driving circuit 100 provided in an embodiment of this application; as shown Figure 3 As shown, the pixel driving circuit 100 in this embodiment further includes a voltage detection module 130, which is connected to the control terminal of the data node A1 and the switch module 120, and is configured to generate a switch control signal according to the charge state of the data node A1 and output it to the switch module 120.

[0040] It should be noted that during the charging phase, the voltage detection module 130 first samples the voltage of data node A1 to obtain a voltage value that reflects the residual charge of the first storage capacitor C1. When the residual voltage of data node A1 is higher than the reference voltage, it indicates that the residual charge in the first storage capacitor C1 is large. At this time, the voltage detection module 130 outputs a valid level switch control signal to the control terminal of the switch module 120, turning on the switch module 120 and establishing a charge exchange path between data node A1 and control node A2, so that the residual charge in the first storage capacitor C1 and the second storage capacitor C2 can be neutralized. When the residual voltage of data node A1 is not higher than the reference voltage, it indicates that the residual charge in the first storage capacitor C1 is small. At this time, the voltage detection module 130 outputs an invalid level switch control signal, the switch module 120 remains in the off state, and no charge exchange path is established between data node A1 and control node A2.

[0041] Therefore, in this embodiment, the voltage detection module 130 determines in real time whether to initiate the charging process based on the actual charge state of data node A1, so that the charging operation matches the actual residual charge of the pixel. When the pixel has a large residual charge, the charging is triggered, and the charge is fully neutralized; when the pixel has a small residual charge or is almost non-existent, the charging is skipped, avoiding unnecessary charge exchange operations. This ensures the effective elimination of residual charge, avoids new charge imbalance problems that may be introduced by overcharging, and reduces unnecessary switching actions and power consumption.

[0042] Figure 4 The diagram shown is a schematic diagram of a pixel driving circuit 100 provided in an embodiment of this application; as follows: Figure 4 As shown, the switching module 120 of this embodiment includes: a first transistor T1, the control terminal of the first transistor T1 serves as the control terminal of the switching module 120, the first terminal of the first transistor T1 is connected to the data node A1, and the second terminal of the first transistor T1 is connected to the control node A2.

[0043] In some embodiments, the voltage detection module 130 includes a second transistor T2 and a first comparator U1; the control terminal of the second transistor T2 is connected to the detection control terminal DUC, and the first terminal of the second transistor T2 is connected to the data node A1; the non-inverting input terminal of the first comparator U1 is connected to the second terminal of the second transistor T2, the inverting input terminal of the first comparator U1 is connected to the reference voltage terminal Vj, and the output terminal of the first comparator U1 is connected to the control terminal of the first transistor T1.

[0044] It should be noted that the working principle of the switch module 120 and the voltage detection module 130 in this embodiment is as follows: (1) The second transistor T2 is used to sample the residual voltage of data node A1: When a valid level is applied to the detection control terminal DUC, the second transistor T2 is turned on, transmitting the voltage of data node A1 to the non-inverting input terminal of the first comparator U1. The first comparator U1 compares the sampled voltage of data node A1 with a reference voltage: when the sampled voltage is higher than the reference voltage, the first comparator U1 outputs a valid level to the control terminal of the first transistor T1; when the sampled voltage is not higher than the reference voltage, the first comparator U1 outputs an invalid level. The reference voltage can be a preset fixed voltage, or it can be as follows: Figure 5 The stepped voltage shown can also be a ramp voltage.

[0045] (2) The control terminal of the first transistor T1 receives the switching control signal of the first comparator U1: When the first comparator U1 outputs an effective level, the first transistor T1 is turned on, and a charge exchange path is established between the data node A1 and the control node A2, so that the residual charge in the first storage capacitor C1 and the second storage capacitor C2 is neutralized; when the first comparator U1 outputs an invalid level, the first transistor T1 is turned off, and the charge exchange path between the data node A1 and the control node A2 is cut off.

[0046] In this embodiment, since the residual voltage of data node A1 can directly reflect the residual charge of the first storage capacitor C1, and the reference voltage can be set to a threshold corresponding to the safe voltage window, the voltage detection module 130 can determine whether to enable charging based on the actual charge state of the pixel. When the reference voltage is a stepped voltage, by setting multiple stepped levels, different conduction levels or conduction times can be corresponding to different voltage ranges, achieving multi-level control. When the reference voltage is a ramp voltage, the pulse width of the first comparator U1 output changes with the intersection of the sampled voltage and the reference voltage, which can continuously adjust the conduction time of the first transistor T1, achieving fine control of the charging duration. In addition, a fixed reference voltage can also be connected to the inverting input of the first comparator U1. In this case, the voltage detection module 130 uses a fixed threshold to determine whether charging needs to be enabled, which is suitable for scenarios where charging accuracy requirements are not high.

[0047] like Figure 4 As shown, the data writing module 110 of this embodiment includes a first writing transistor M3, a second writing transistor M4, and a third comparator U3; the control terminal of the first writing transistor M3 is connected to the scan line Scan, the first terminal of the first writing transistor M3 is connected to the first data line PAM_Data, and the second terminal of the first writing transistor M3 is connected to the data node A1; the control terminal of the second writing transistor M4 is connected to the control terminal of the first writing transistor M3, the first terminal of the second writing transistor M4 is connected to the second data line PWM_Data, and the second terminal of the second writing transistor M4 is connected to the control node A2; the non-inverting input terminal of the third comparator U3 is connected to the control node A2, the inverting input terminal of the third comparator U3 is connected to the reference pulse signal terminal Sweep, and the output terminal of the third comparator U3 is connected to the control terminal of the control transistor M2.

[0048] It should be noted that the working principle of the data writing module 110 in this embodiment is as follows: (1) When the scan signal on the scan line Scan is at an effective level, the first write transistor M3 and the second write transistor M4 are turned on at the same time. The amplitude information on the first data line PAM_Data is written to the data node A1 through the first write transistor M3 and stored by the first storage capacitor C1. The pulse width information on the second data line PWM_Data is written to the control node A2 through the second write transistor M4 and stored by the second storage capacitor C2.

[0049] (2) The third comparator U3 compares the voltage of control node A2 with the reference pulse signal. When the voltage of the reference pulse signal is lower than the voltage of control node A2, the third comparator U3 outputs an effective level to the control terminal of control transistor M2, turning on control transistor M2 and driving current to flow through the light-emitting device OLED, causing the OLED to start emitting light; when the voltage of the reference pulse signal is higher than the voltage of control node A2, the third comparator U3 outputs an invalid level, turning off control transistor M2 and causing the OLED to stop emitting light. The conduction time of control transistor M2 in each cycle is determined by the intersection point of the voltage of control node A2 and the reference pulse signal, thereby controlling the light emission duration of the light-emitting device OLED.

[0050] Therefore, in this embodiment, the data writing module 110 writes the amplitude information and pulse width information into the corresponding storage capacitors through two paths, and converts the pulse width information into a time control signal through the third comparator U3 during the light emission stage, thereby realizing independent control of the light emission brightness and light emission duration.

[0051] Figure 6 The diagram shown is a circuit diagram of a voltage detection module 130 provided in an embodiment of this application; it should be noted that, Figure 4 The circuit shown, consisting of the second transistor T2 and the first comparator U1, is one implementation of the voltage detection module 130. Figure 6 The circuit shown is another implementation of the voltage detection module 130; as Figure 6 As shown, the voltage detection module 130 in this embodiment consists of a first detection unit 131, a second detection unit 132, and an OR gate 133.

[0052] Specifically, the two input terminals of the first detection unit 131 are connected to the data node A1 and the control node A2, respectively. The first detection unit 131 has a built-in first offset voltage introduced by the layout design. When the voltage difference between the data node A1 and the control node A2 is greater than the first offset voltage, the first detection unit 131 outputs an effective level. When the voltage difference is less than or equal to the offset voltage, the first detection unit 131 outputs an invalid level. In other words, the first detection unit 131 is used to determine whether the voltage of the data node A1 is higher than the voltage of the control node A2 by more than a preset threshold.

[0053] In this embodiment, the two input terminals of the second detection unit 132 are connected to the control node A2 and the data node A1, respectively. The second detection unit 132 has a built-in second offset voltage, which is the same magnitude as the first offset voltage but in the opposite direction. The control node A2 is connected to the non-inverting input terminal, and the data node A1 is connected to the inverting input terminal. When the voltage difference between the control node A2 and the data node A1 is greater than the second offset voltage, the second detection unit 132 outputs an effective level; when the voltage difference is less than or equal to the offset voltage, the second detection unit 132 outputs an invalid level.

[0054] Furthermore, in this embodiment, the output terminals of the first detection unit 131 and the second detection unit 132 are respectively connected to the two input terminals of the OR gate 133. When either the first detection unit 131 or the second detection unit 132 outputs a valid level, the OR gate 133 outputs a valid switch control signal to the control terminal of the switch module 120, causing the switch module 120 to conduct. Only when the absolute value of the voltage difference between data node A1 and control node A2 is less than the offset voltage, neither detection unit outputs a high level, the OR gate 133 outputs an invalid level, and the switch module 120 remains off.

[0055] The voltage detection module 130 in this embodiment can detect whether the voltage difference between data node A1 and control node A2 exceeds a preset dead zone window. Charging is only triggered when the voltage difference between the two nodes exceeds the dead zone range defined by the offset voltage, thus avoiding false triggering caused by small voltage fluctuations.

[0056] like Figure 6 As shown, the circuit structures of the first detection unit 131 and the second detection unit 132 in this embodiment are the same, both including a third transistor T3. The control terminal of the third transistor T3 is connected to the clock signal terminal CLK, and the first terminal of the third transistor T3 is connected to the low-level terminal VSS. Optionally, the first detection unit 131 and the second detection unit 132 in this embodiment further include a fourth transistor T4. The control terminal of the fourth transistor T4 is connected to the data node A1 or the control node A2, and the first terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3. Specifically, for the first detection unit 131, the control terminal of the fourth transistor T4 is connected to the data node A1; for the second detection unit 132, the control terminal of the fourth transistor T4 is connected to the control node A2.

[0057] Optionally, the first detection unit 131 and the second detection unit 132 in this embodiment further include a fifth transistor T5. The control terminal of the fifth transistor T5 is connected to the control node A2 or the data node A1, and the first terminal of the fifth transistor T5 is connected to the second terminal of the third transistor T3. Specifically, for the first detection unit 131, the control terminal of the fifth transistor T5 is connected to the control node A2; for the second detection unit 132, the control terminal of the fifth transistor T5 is connected to the data node A1.

[0058] In some embodiments, the first detection unit 131 and the second detection unit 132 of this embodiment further include a sixth transistor T6 and a seventh transistor T7. The control terminal of the sixth transistor T6 serves as the first output terminal of the first detection unit 131 or the second detection unit 132, and the first terminal of the sixth transistor T6 is connected to the second terminal of the fourth transistor T4. The control terminal of the seventh transistor T7 serves as the second output terminal of the first detection unit 131 or the second detection unit 132, and the first terminal of the seventh transistor T7 is connected to the second terminal of the fifth transistor T5, and the second terminal of the seventh transistor T7 is connected to the first output terminal. The second terminal of the sixth transistor T6 is connected to the second output terminal.

[0059] In some embodiments, the first detection unit 131 and the second detection unit 132 of this embodiment further include an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13; specifically, the control terminal of the eighth transistor T8 is connected to the first output terminal, the first terminal of the eighth transistor T8 is connected to the second output terminal, and the second terminal of the eighth transistor T8 is connected to the power supply terminal VDD; the control terminal of the ninth transistor T9 is connected to the second output terminal, the first terminal of the ninth transistor T9 is connected to the first output terminal, and the second terminal of the ninth transistor T9 is connected to the power supply terminal VDD; the control terminal of the tenth transistor T10 is connected to the clock signal terminal CLK, and the first terminal of the tenth transistor T10 is connected to the clock signal terminal CLK. The first terminal of the sixth transistor T6 is connected to the first terminal; the second terminal of the tenth transistor T10 is connected to the power supply terminal VDD; the control terminal of the eleventh transistor T11 is connected to the clock signal terminal CLK; the first terminal of the eleventh transistor T11 is connected to the second output terminal; the second terminal of the eleventh transistor T11 is connected to the power supply terminal VDD; the control terminal of the twelfth transistor T12 is connected to the clock signal terminal CLK; the first terminal of the twelfth transistor T12 is connected to the first output terminal; the second terminal of the twelfth transistor T12 is connected to the power supply terminal VDD; the control terminal of the thirteenth transistor T13 is connected to the clock signal terminal CLK; the first terminal of the thirteenth transistor T13 is connected to the first terminal of the seventh transistor T7; the second terminal of the thirteenth transistor T13 is connected to the power supply terminal VDD.

[0060] It should be noted that, taking the first detection unit 131 as an example, its operating timing is controlled by a clock signal and is divided into two operating stages: a pre-charge stage and a comparison latch stage. The circuit structure of this embodiment is described below: (1) During the pre-charge phase, the clock signal is low: the third transistor T3 is turned off, and the fourth transistor T4 and the fifth transistor T5, which are differential input pairs, have no tail current flowing through them. This causes the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 to turn on, pre-charging the first output terminal, the second output terminal, and the internal nodes to the power supply voltage VDD. Specifically, the tenth transistor T10 is used to pre-charge the first terminal of the sixth transistor T6, the thirteenth transistor T13 is used to pre-charge the first terminal of the seventh transistor T7, the eleventh transistor T11 is used to pre-charge the second output terminal, and the twelfth transistor T12 is used to pre-charge the first output terminal. After this pre-charge process, both the first and second output terminals are reset to the power supply voltage VDD, and the circuit enters a metastable state, preparing for the subsequent comparison operation.

[0061] (2) During the compare-latch phase, the clock signal goes high: the third transistor T3 turns on, providing tail current to the fourth transistor T4 and the fifth transistor T5 of the differential input pair, causing the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 to turn off, and the first and second output terminals float. At this time, ① If there is a difference between the voltage at data node A1 connected to the control terminal of the fourth transistor T4 and the voltage at control node A2 connected to the control terminal of the fifth transistor T5, the currents flowing through the two differential input transistors will be unequal. This current difference is transmitted through the differential node where the fourth transistor T4 and the fifth transistor T5 are located to the cross-coupled positive feedback latch structure composed of the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9. Specifically, the first terminals of the fourth transistor T4 and the fifth transistor T5 are connected to the second terminal (common source node) of the third transistor T3, and their second terminals are respectively connected to the first terminals of the sixth transistor T6 and the seventh transistor T7; the sixth transistor T6 and the seventh transistor T7 form a back-to-back inverter positive feedback loop—the control terminal of the sixth transistor T6 is connected to the second output terminal and the second terminal is connected to the first output terminal, and the control terminal of the seventh transistor T7 is connected to the first output terminal and the second terminal is connected to the second output terminal, which is used to amplify the differential current signal into a digital level; the eighth transistor T8 and the ninth transistor T9 also form a cross-coupled structure to further enhance the positive feedback latch.

[0062] ② When the voltage connected to the control terminal of the fourth transistor T4 is higher than the voltage connected to the control terminal of the fifth transistor T5 by more than one offset voltage, the current flowing through the fourth transistor T4 is greater than that through the fifth transistor T5. This causes the internal node on one side of the fourth transistor T4 to discharge faster, and the potential at its corresponding output terminal drops. This drop is rapidly amplified through the cross-coupled positive feedback structure, ultimately pulling that output terminal low and the other output terminal high to the power supply voltage VDD, and the circuit latches into a stable state.

[0063] ③ When the voltage connected to the control terminal of the fifth transistor T5 is higher than the voltage connected to the control terminal of the fourth transistor T4 by more than one offset voltage, the current flowing through the fifth transistor T5 is greater than that of the fourth transistor T4. The above process occurs symmetrically, and the final state of the two output terminals is the opposite of the above situation.

[0064] ④ When the absolute value of the voltage difference between the control terminal of the fourth transistor T4 and the control terminal of the fifth transistor T5 is less than the offset voltage, the current difference between the fourth transistor T4 and the fifth transistor T5 is extremely small. The cross-coupled positive feedback cannot establish a clear latching state, and the output terminal remains in a pre-charge state or is at an invalid level, thus forming a dead zone that does not respond to small voltage fluctuations.

[0065] It should be noted that the offset voltage in this embodiment is implemented as follows: the width-to-length ratios of the fourth transistor T4 and the fifth transistor T5 are different. Specifically, in one detection unit, the width-to-length ratio of the fourth transistor T4 is smaller than that of the fifth transistor T5, generating a positive offset voltage. This means that the voltage connected to the control terminal of the fourth transistor T4 must be higher than the voltage connected to the control terminal of the fifth transistor T5 to achieve current balance. In the other detection unit, the width-to-length ratio of the fourth transistor T4 is also smaller than that of the fifth transistor T5, but due to the cross-connection of the inputs, it is equivalent to detecting the voltage difference in opposite directions. The two detection units are used to detect the two directions of the voltage difference, respectively, together forming a dead zone window centered at zero.

[0066] Figure 7 The diagram shown is a structural schematic of a display panel 10 provided in an embodiment of this application; as shown Figure 7 As shown, the display panel 10 in this embodiment includes a plurality of pixel units arranged in an array, each pixel unit employing as shown in the figure. Figure 1 The pixel driving circuit 100 shown is shown.

[0067] The display panel 10 in this embodiment also includes a grayscale detection module 200, which is connected to the switching module 120 of the pixel driving circuit 100 and is configured to generate a switching control signal based on the current grayscale data; it should be noted that, as described above Figure 3Unlike the embodiment shown where the voltage detection module 130 is located inside the pixel circuit, this embodiment places the grayscale detection module 200 outside the pixel unit, for example, integrated into the panel's driver chip; furthermore, Figure 3 The voltage detection module 130 shown generates a switch control signal based on the charge state of data node A1, while the grayscale detection module 200 in this embodiment generates a switch control signal based on the grayscale data of the current frame.

[0068] It should be noted that during the driving process of the display panel 10, the driving chip acquires the grayscale data of each pixel in the current frame image. For the 8-bit color depth display panel 10, the grayscale range is 0 to 255 grayscale levels. Different grayscale levels correspond to different data voltages, and thus to different charge states. The grayscale detection module 200 utilizes the correspondence that high grayscale levels correspond to higher data voltages (i.e., more charge is stored in the first storage capacitor C1) and low grayscale levels correspond to lower data voltages (i.e., less charge is stored in the first storage capacitor C1) to estimate the charge state of the pixels based on the grayscale data of the current frame, and generates corresponding switching control signals based on the estimation results. Specifically, this includes the following implementation methods: (1) Method of controlling charging time based on grayscale data: In some embodiments, the grayscale detection module 200 includes a voltage comparison circuit. This voltage comparison circuit uses a ramp signal as a reference and the grayscale voltage of the current frame as input to compare the grayscale voltage with the ramp signal. The ramp signal is a voltage that changes linearly with time. The intersection of the grayscale voltage and the ramp signal determines the width of the output pulse of the comparison circuit. That is, the higher the grayscale voltage, the later the intersection occurs, and the wider the output pulse. This pulse width is applied as a switch control signal to the control terminal of the switch module 120 to control the conduction time of the switch module 120 during the charging stage: the higher the grayscale, the more residual charge in the first storage capacitor C1, the wider the pulse width, the longer the conduction time of the switch module 120, and the more fully the charge is neutralized; the lower the grayscale, the narrower the pulse width, and the shorter the conduction time of the switch module 120. This achieves adaptive adjustment of the charging time according to the grayscale.

[0069] (2) Control of conduction intensity based on grayscale data: In some embodiments, the transistor in the switching module 120 is a P-type transistor, and its control terminal (gate) is directly connected to the grayscale voltage as the switching control signal, without the need for an additional voltage comparison circuit. The on-resistance of the P-type transistor changes continuously with the gate voltage. The higher the grayscale voltage, the smaller the gate-source voltage difference of the P-type transistor, the greater the on-resistance, and the weaker the charging intensity; the lower the grayscale voltage, the greater the gate-source voltage difference of the P-type transistor, the smaller the on-resistance, and the stronger the charging intensity. Since the grayscale voltage itself reflects the charge state of data node A1, the gate of the P-type transistor can be directly controlled by the grayscale voltage to achieve adaptive adjustment of the charging intensity according to the charge state, while eliminating the need for a voltage comparison circuit and further simplifying the circuit structure.

[0070] (3) Dynamic adjustment method based on the gray level change of historical frames: In some embodiments, the gray level detection module 200 not only considers the gray level data of the current frame, but also combines the gray level data of historical frames to calculate the gray level change between the previous and next frames; then outputs the corresponding switch control signal according to the gray level change to realize the different degrees of conduction state of the switch module 120.

[0071] Therefore, it can be seen that the grayscale detection module 200 in this embodiment is located outside the pixel unit, eliminating the need to set a voltage detection circuit inside each pixel, which is beneficial for improving the pixel aperture ratio and reducing the pixel circuit complexity.

[0072] Figure 8 The diagram shown is a structural schematic of a grayscale detection module 200 provided in an embodiment of this application; as shown Figure 8 As shown, the grayscale detection module 200 in this embodiment includes a difference calculation unit 210, a threshold selection unit 220, and a second comparator U2.

[0073] like Figure 8 As shown, the difference calculation unit 210 in this embodiment is connected to the current frame register and the history frame register, respectively, and is used to calculate the grayscale change between the grayscale voltage of the current frame and the grayscale voltage of the previous frame. Specifically, the current frame register stores the grayscale voltage data of the current display frame, and the history frame register stores the grayscale voltage data of the previous display frame. The difference calculation unit 210 subtracts the two and takes the absolute value to obtain the grayscale change between the current frame and the previous frame. This grayscale change reflects the degree of change in pixel brightness. The larger the change, the greater the amplitude of the pixel switching from high brightness to low brightness, the more drastic the change in charge state in data node A1, and the higher the risk of residual charge.

[0074] like Figure 8As shown, in this embodiment, the threshold selection unit 220 is connected to the difference calculation unit 210. It receives the grayscale change output by the difference calculation unit 210 and selects one from multiple preset reference voltages as the current comparison threshold based on the grayscale change. The threshold selection unit 220 internally stores multiple preset reference voltages, each corresponding to a different grayscale change range. The threshold selection unit 220 determines the range to which the grayscale change belongs based on its magnitude and selects the corresponding voltage from the multiple preset reference voltages as the current comparison threshold. When the grayscale change is large, a lower reference voltage is selected as the current comparison threshold; when the grayscale change is small, a higher reference voltage is selected as the current comparison threshold.

[0075] like Figure 8 As shown, in this embodiment, the second comparator U2 is connected to the output of the threshold selection unit 220, the current frame register, and the control terminal of the switch module 120, respectively. The two inputs of the second comparator U2 receive the grayscale voltage of the current frame and the current comparison threshold output by the threshold selection unit 220, respectively. The second comparator U2 compares the grayscale voltage of the current frame with the current comparison threshold, and outputs a corresponding switch control signal to the control terminal of the switch module 120 based on the comparison result.

[0076] In this embodiment, the grayscale detection module 200 dynamically adjusts the comparison threshold using grayscale change information between historical frames and the current frame, thereby controlling the output of the switch control signal. When the screen undergoes a significant brightness shift, a lower threshold makes charging easier to trigger or allows for a longer charging time, effectively eliminating the risk of residual charge caused by drastic charge changes. When the screen changes smoothly or is static, a higher threshold causes charging to end earlier or reduces the number of charging cycles, avoiding unnecessary power consumption.

[0077] In some embodiments, such as Figure 8As shown, the threshold selection unit 220 includes: a logic determiner 221, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16. Specifically, the logic determiner 221 is connected to the output terminal of the difference calculation unit 210 and is configured to output different selection signals according to the grayscale change. The first terminal of the first resistor R1 is connected to the power supply terminal VDD. The control terminal of the fourteenth transistor T14 is connected to the first output terminal of the logic determiner 221, and the first terminal of the fourteenth transistor T14 is connected to the second terminal of the first resistor R1. The second terminal of the fourteenth transistor T14 serves as the output terminal of the threshold selection unit 220. The first terminal of the second resistor R2 is connected to the first resistor R1. The second terminal of resistor R1 is connected; the control terminal of the fifteenth transistor T15 is connected to the second output terminal of logic 221, the first terminal of the fifteenth transistor T15 is connected to the second terminal of the second resistor R2, and the second terminal of the fifteenth transistor T15 is connected to the second terminal of the fourteenth transistor T14; the first terminal of the third resistor R3 is connected to the second terminal of the second resistor R2; the control terminal of the sixteenth transistor T16 is connected to the third output terminal of logic 221, the first terminal of the sixteenth transistor T16 is connected to the second terminal of the third resistor R3, and the second terminal of the sixteenth transistor T16 is connected to the second terminal of the fourteenth transistor T14; the first terminal of the fourth resistor R4 is connected to the second terminal of the third resistor R3, and the second terminal of the fourth resistor R4 is connected to the low-level terminal VSS.

[0078] It should be noted that the working principle of the threshold selection unit 220 in this embodiment is as follows: the first resistor R1 to the fourth resistor R4 are connected in series between the power supply terminal VDD and the low-level terminal VSS, forming a resistor voltage divider network, generating multiple reference voltages with different voltage values ​​at different nodes. Among them, the voltage at the second end of the first resistor R1 is the highest, the voltage at the second end of the second resistor R2 is medium, and the voltage at the second end of the third resistor R3 is the lowest. The logic judge 221 outputs the corresponding selection signal through its three output terminals based on the grayscale change output by the difference calculation unit 210. When the grayscale change belongs to the first interval (maximum change), the first output terminal is valid, the fourteenth transistor T14 is turned on, and the highest voltage is output to the output terminal of the threshold selection unit 220 as the current comparison threshold; when the grayscale change belongs to the second interval (medium change), the second output terminal is valid, the fifteenth transistor T15 is turned on, and the medium voltage is output to the output terminal; when the grayscale change belongs to the third interval (minimum change), the third output terminal is valid, the sixteenth transistor T16 is turned on, and the lowest voltage is output to the output terminal.

[0079] In this embodiment, the threshold selection unit 220 selects a corresponding output from multiple preset reference voltages based on different ranges of grayscale change. When the grayscale change is large, a lower reference voltage is selected to make charging easier to trigger; when the grayscale change is small, a higher reference voltage is selected to end charging earlier, thereby achieving adaptive adjustment of charging intensity according to the degree of change in the image.

[0080] Figure 9 The diagram shown is a circuit diagram of a switch module 120 provided in an embodiment of this application; as follows: Figure 9 As shown, the switching module 120 in this embodiment includes a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19. The control terminal of the seventeenth transistor T17 is connected to the first output terminal Vo1 of the grayscale detection module 200, the first terminal of the seventeenth transistor T17 is connected to the data node A1, and the second terminal of the seventeenth transistor T17 is connected to the control node A2. The control terminal of the eighteenth transistor T18 is connected to the second output terminal Vo2 of the grayscale detection module 200, the first terminal of the eighteenth transistor T18 is connected to the data node A1, and the second terminal of the eighteenth transistor T18 is connected to the control node A2. The control terminal of the nineteenth transistor T19 is connected to the third output terminal Vo3 of the grayscale detection module 200, the first terminal of the nineteenth transistor T19 is connected to the data node A1, and the second terminal of the nineteenth transistor T19 is connected to the control node A2.

[0081] It should be noted that the grayscale detection module 200 in this embodiment includes a first output terminal Vo1, a second output terminal Vo2, and a third output terminal Vo3, which respectively control the on and off states of the seventeenth transistor T17, the eighteenth transistor T18, and the nineteenth transistor T19. Specifically: (1) When the grayscale change is large, it means that the pixel switches from high brightness to low brightness by a large margin. The charge state in data node A1 changes drastically and the risk of residual charge is high. At this time, the grayscale detection module 200 outputs effective levels through the first output terminal Vo1, the second output terminal Vo2 and the third output terminal Vo3, so that the seventeenth transistor T17, the eighteenth transistor T18 and the nineteenth transistor T19 are all turned on. The parallel branch of the three transistors works at the same time, the equivalent on-resistance is minimized, strong charging is achieved, and the charge transfer is completed at the fastest speed.

[0082] (2) When the gray level change is in a medium range, the residual charge risk is medium. The gray level detection module 200 outputs an effective level through the first output terminal Vo1 and the second output terminal Vo2, and outputs an invalid level through the third output terminal Vo3, so that the seventeenth transistor T17 and the eighteenth transistor T18 are turned on and the nineteenth transistor T19 is turned off, thereby achieving medium-to-charge and achieving a balance between charge transfer efficiency and power consumption.

[0083] (3) When the gray level change is small, it indicates that the pixel brightness changes slowly and the risk of residual charge is low. The gray level detection module 200 outputs an effective level only through the first output terminal Vo1, and an invalid level through the second output terminal Vo2 and the third output terminal Vo3. Only the seventeenth transistor T17 is turned on, and the eighteenth transistor T18 and the nineteenth transistor T19 are turned off to achieve weak charging and perform fine charge balance to avoid overcharging.

[0084] (4) When the gray level change is very small or zero, all three output terminals of the gray level detection module 200 output an invalid level, all three transistors are turned off, and no charging operation is performed, thereby avoiding unnecessary power consumption.

[0085] Therefore, the conduction strength of the switching module 120 in this embodiment is dynamically adjusted according to the magnitude of grayscale changes, realizing a gradual adjustment from weak to medium and then to strong charging. This effectively reduces the risk of overcharging caused by large current surges, reduces node voltage overshoot and loop oscillations, and suppresses the reverse injection effect and charge rebound phenomenon at the end of the charge sharing phase, thereby improving charge balance accuracy and display driving stability. Simultaneously, it improves the residual charge elimination capability in large grayscale switching scenarios and reduces ineffective power consumption in small grayscale changing scenarios.

[0086] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0087] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0088] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A pixel driving circuit, characterized in that, The pixel driving circuit includes: The data writing module, connected to the data node and the control node, is configured to: during the data writing phase, write the amplitude information of the data signal to the data node and write the pulse width information of the data signal to the control node; A first storage capacitor is connected between the data node and the power supply terminal; A second storage capacitor is connected between the control node and the low-level terminal; A driving transistor, wherein the control terminal of the driving transistor is connected to the data node, and the first terminal of the driving transistor is connected to the power supply terminal; A control transistor, wherein the control terminal of the control transistor is connected to the output terminal of the data writing module, the first terminal of the control transistor is connected to the second terminal of the driving transistor, and the second terminal of the control transistor is connected to the light-emitting device; A switch module, connected between the data node and the control node, is configured to selectively conduct in response to a switch control signal between the light emission phase and the reset phase, so as to establish a charge exchange path between the data node and the control node; wherein the switch control signal is generated based on the charge state of the data node or the grayscale data of the current frame.

2. The pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit also includes: The voltage detection module, connected to the control terminals of the data node and the switch module, is configured to generate the switch control signal based on the charge state of the data node and output it to the switch module.

3. The pixel driving circuit according to claim 2, characterized in that, The switching module includes: The first transistor has a control terminal that serves as the control terminal of the switching module. The first terminal of the first transistor is connected to the data node, and the second terminal of the first transistor is connected to the control node.

4. The pixel driving circuit according to claim 3, characterized in that, The voltage detection module includes: The second transistor has its control terminal connected to the detection control terminal, and its first terminal connected to the data node. A first comparator has its non-inverting input connected to the second terminal of the second transistor, its inverting input connected to a reference voltage terminal, and its output connected to the control terminal of the first transistor.

5. The pixel driving circuit according to claim 3, characterized in that, The voltage detection module includes: The first detection unit, whose two input terminals are respectively connected to the data node and the control node, is configured to output an effective level when the voltage difference between the data node and the control node is greater than the first offset voltage. The second detection unit, whose two input terminals are respectively connected to the control node and the data node, is configured to output an effective level when the voltage difference between the control node and the data node is greater than the second offset voltage. The OR gate, whose two inputs are respectively connected to the outputs of the first detection unit and the second detection unit, is configured to output a valid switch control signal when either the first detection unit or the second detection unit outputs a valid level.

6. The pixel driving circuit according to claim 5, characterized in that, The first detection unit and / or the second detection unit include: The third transistor has its control terminal connected to the clock signal terminal and its first terminal connected to the low-level terminal. The fourth transistor has its control terminal connected to the data node or the control node, and its first terminal is connected to the second terminal of the third transistor. The fifth transistor, wherein the control terminal of the fifth transistor is connected to the control node or the data node, and the first terminal of the fifth transistor is connected to the second terminal of the third transistor; The sixth transistor, the control terminal of which serves as the first output terminal of the first detection unit or the second detection unit, and the first terminal of the sixth transistor is connected to the second terminal of the fourth transistor; A seventh transistor, wherein the control terminal of the seventh transistor serves as the second output terminal of the first detection unit or the second detection unit, the first terminal of the seventh transistor is connected to the second terminal of the fifth transistor, and the second terminal of the seventh transistor is connected to the first output terminal; wherein, the second terminal of the sixth transistor is connected to the second output terminal; The eighth transistor has a control terminal connected to the first output terminal, a first terminal connected to the second output terminal, and a second terminal connected to the power supply terminal. The ninth transistor has a control terminal connected to the second output terminal, a first terminal connected to the first output terminal, and a second terminal connected to the power supply terminal. The tenth transistor has its control terminal connected to the clock signal terminal, its first terminal connected to the first terminal of the sixth transistor, and its second terminal connected to the power supply terminal. The eleventh transistor has its control terminal connected to the clock signal terminal, its first terminal connected to the second output terminal, and its second terminal connected to the power supply terminal. The twelfth transistor has its control terminal connected to the clock signal terminal, its first terminal connected to the first output terminal, and its second terminal connected to the power supply terminal. The thirteenth transistor has its control terminal connected to the clock signal terminal, its first terminal connected to the first terminal of the seventh transistor, and its second terminal connected to the power supply terminal.

7. A display panel, characterized in that, The display panel includes: The pixel driving circuit according to claim 1; The grayscale detection module, connected to the switching module of the pixel driving circuit, is configured to generate a switching control signal based on the current grayscale data.

8. The display panel according to claim 7, characterized in that, The grayscale detection module includes: The difference calculation unit, connected to the current frame register and the history frame register respectively, is configured to calculate the gray level change between the gray level voltage of the current frame and the gray level voltage of the previous frame. The threshold selection unit, connected to the difference calculation unit, is configured to select one of multiple preset reference voltages as the current comparison threshold based on the grayscale change. The second comparator is connected to the output of the threshold selection unit, the current frame register, and the control terminal of the switch module, and is configured to output a corresponding switch control signal based on the comparison result between the current frame grayscale voltage and the current comparison threshold.

9. The display panel according to claim 8, characterized in that, The threshold selection unit includes: The logic judge, connected to the output of the difference calculation unit, is configured to output different selection signals according to the grayscale change. The first resistor, with its first end connected to the power supply terminal; The fourteenth transistor has its control terminal connected to the first output terminal of the logic detector, its first terminal connected to the second terminal of the first resistor, and its second terminal serving as the output terminal of the threshold selection unit. The second resistor has its first end connected to the second end of the first resistor. The fifteenth transistor has its control terminal connected to the second output terminal of the logic detector, its first terminal connected to the second terminal of the second resistor, and its second terminal connected to the second terminal of the fourteenth transistor. A third resistor, wherein the first end of the third resistor is connected to the second end of the second resistor; The sixteenth transistor has its control terminal connected to the third output terminal of the logic detector, its first terminal connected to the second terminal of the third resistor, and its second terminal connected to the second terminal of the fourteenth transistor. The fourth resistor has its first end connected to the second end of the third resistor, and its second end is connected to a low-level terminal.

10. The display panel according to claim 8, characterized in that, The switching module includes: The seventeenth transistor has its control terminal connected to the first output terminal of the grayscale detection module, its first terminal connected to the data node, and its second terminal connected to the control node. The eighteenth transistor has its control terminal connected to the second output terminal of the grayscale detection module, its first terminal connected to the data node, and its second terminal connected to the control node. The nineteenth transistor has its control terminal connected to the third output terminal of the grayscale detection module, its first terminal connected to the data node, and its second terminal connected to the control node.

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