Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are disclosed. The display device includes a display panel including a pixel, a gate driver providing a gate signal to the pixel, a light emitting driver providing a light emitting signal to the pixel, a data driver providing a data voltage to the pixel, a gamma voltage generating circuit providing a gamma voltage to the data driver, and a voltage control circuit generating a compensated high gamma voltage, a compensated low gamma voltage, and a compensated reference voltage by compensating the high gamma voltage, the low gamma voltage, and the reference voltage based on a sensed power voltage measured from a power line transmitting a first power voltage, and providing the compensated high gamma voltage and the compensated low gamma voltage to the gamma voltage generating circuit and the compensated reference voltage to the pixel.

Description

Technical Field

[0001] This invention relates to a display device. More specifically, this invention relates to a display device with compensated gamma voltage and an electronic device including such a display device. Background Technology

[0002] The display device may include a display panel comprising pixels, a data driver providing a data voltage to each of the pixels, and a gamma voltage generating circuit providing a gamma voltage to the data driver. Each of the pixels may emit light based on at least one gate signal, at least one light-emitting signal, and a voltage including the data voltage and a first power supply voltage.

[0003] If noise is generated at the first power supply voltage, the difference between the first power supply voltage and the gamma voltage may change, thereby potentially altering the brightness of the light emitted by the pixels. If the brightness of the light emitted from the pixels changes due to the noise generated at the first power supply voltage, the image quality of the display device may degrade. Summary of the Invention

[0004] One object of the present invention is to provide a display device with improved image quality and an electronic device including such a display device.

[0005] However, the purpose of this invention is not limited to such purpose, and various extensions can be made without departing from the concept and scope of this invention.

[0006] To achieve the aforementioned objective of the present invention, a display device according to an embodiment includes: a display panel including pixels; a gate driver providing a gate signal to the pixels; a light-emitting driver providing a light-emitting signal to the pixels; a data driver providing a data voltage to the pixels; a gamma voltage generation circuit providing a gamma voltage to the data driver; and a voltage control circuit that generates a compensated high gamma voltage, a compensated low gamma voltage, and a compensated reference voltage based on a sensed power supply voltage measured from a power line transmitting a first power supply voltage, and compensates a high gamma voltage, a low gamma voltage, and a reference voltage, and provides the compensated high gamma voltage and the compensated low gamma voltage to the gamma voltage generation circuit, and provides the compensated reference voltage to the pixels.

[0007] In one embodiment, the pixel may include: a first transistor including a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor transmitting the data voltage to a fourth node in response to a write gate signal; a first capacitor connected between the first node and the fourth node; a second capacitor connected between the fourth node and the power line; a third transistor connecting the first node to the third node in response to a compensation gate signal; a fourth transistor transmitting a first initialization voltage to the first node in response to an initialization gate signal; a fifth transistor transmitting the compensation reference voltage to the fourth node in response to the compensation gate signal; a sixth transistor connecting the third node to the fifth node in response to a first light emission signal; a seventh transistor transmitting a second initialization voltage to the fifth node in response to a bypass gate signal; and a light-emitting element including a first terminal connected to the fifth node and a second terminal receiving a second power supply voltage.

[0008] In one embodiment, the pixel may further include: an eighth transistor that transmits the first power supply voltage to the second node in response to the second light emission signal.

[0009] In one embodiment, the pixel may further include a ninth transistor that transmits a bias voltage to the second node in response to the bypass gate signal.

[0010] In one embodiment, the voltage control circuit may include: a subtractor that outputs a power supply voltage offset by subtracting a reference power supply voltage (which serves as a target voltage for the first power supply voltage) from the sensed power supply voltage; a first adder that outputs a compensated high gamma voltage by adding the power supply voltage offset to the high gamma voltage; a second adder that outputs a compensated low gamma voltage by adding the power supply voltage offset to the low gamma voltage; and a third adder that outputs a compensated reference voltage by adding the power supply voltage offset to the reference voltage.

[0011] In one embodiment, the voltage control circuit may further include: a digital-to-analog converter that generates the reference power supply voltage by converting a digital-to-analog conversion reference power supply voltage code.

[0012] In one embodiment, the voltage control circuit may further include: a clamper that clamps the power supply voltage offset output from the subtractor based on the minimum offset and the maximum offset, and outputs it to the first adder, the second adder and the third adder.

[0013] In one embodiment, the voltage control circuit can be implemented as a power management integrated circuit.

[0014] In one embodiment, the gamma voltage generation circuit can generate the gamma voltage by dividing the compensated high gamma voltage and the compensated low gamma voltage.

[0015] To achieve the aforementioned objective of the present invention, a display device according to an embodiment includes: a display panel including pixels; a gate driver providing a gate signal to the pixels; a light-emitting driver providing a light-emitting signal to the pixels; a data driver providing a data voltage to the pixels; a gamma voltage generation circuit providing a gamma voltage to the data driver; a gamma voltage control circuit generating a compensated high gamma voltage and a compensated low gamma voltage based on a sensed power supply voltage measured from a power supply line transmitting a first power supply voltage, and providing the compensated high gamma voltage and the compensated low gamma voltage to the gamma voltage generation circuit; and a reference voltage generation circuit generating a compensated reference voltage based on the compensated high gamma voltage and providing the compensated reference voltage to the pixels.

[0016] In one embodiment, the pixel may include: a first transistor including a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor transmitting the data voltage to a fourth node in response to a write gate signal; a first capacitor connected between the first node and the fourth node; a second capacitor connected between the fourth node and the power line; a third transistor connecting the first node to the third node in response to a compensation gate signal; a fourth transistor transmitting a first initialization voltage to the first node in response to an initialization gate signal; a fifth transistor transmitting the compensation reference voltage to the fourth node in response to the compensation gate signal; a sixth transistor connecting the third node to the fifth node in response to a first light emission signal; a seventh transistor transmitting a second initialization voltage to the fifth node in response to a bypass gate signal; and a light-emitting element including a first terminal connected to the fifth node and a second terminal receiving a second power supply voltage.

[0017] In one embodiment, the pixel may further include: an eighth transistor that transmits the first power supply voltage to the second node in response to the second light emission signal.

[0018] In one embodiment, the pixel may further include a ninth transistor that transmits a bias voltage to the second node in response to the bypass gate signal.

[0019] In one embodiment, the reference voltage generation circuit may include: an operational amplifier including a first input terminal, a second input terminal, and an output terminal connected to the second input terminal and outputting the compensated reference voltage; a first resistor connected between the input terminal receiving the compensated high gamma voltage and the first input terminal of the operational amplifier; and a second resistor connected between the first input terminal of the operational amplifier and ground.

[0020] In one embodiment, the compensation reference voltage can be calculated using the following mathematical formula: [Mathematical expression] , In the mathematical formula, VREF is the compensation reference voltage, R1 is the resistance of the first resistor, R2 is the resistance of the second resistor, and VGMHC is the compensation high gamma voltage.

[0021] In one embodiment, the gamma voltage control circuit may include: a subtractor that outputs a power supply voltage offset by subtracting a reference power supply voltage (which serves as a target voltage for the first power supply voltage) from the sensed power supply voltage; a first adder that outputs the compensated high gamma voltage by adding the power supply voltage offset to the high gamma voltage; and a second adder that outputs the compensated low gamma voltage by adding the power supply voltage offset to the low gamma voltage.

[0022] In one embodiment, the gamma voltage generation circuit can generate the gamma voltage by dividing the compensated high gamma voltage and the compensated low gamma voltage.

[0023] To achieve the aforementioned objective of the present invention, an electronic device according to an embodiment includes: a processor for generating input image data; a display device for displaying an image based on the input image data; and a power module connected to the processor and the display device. The display device includes: a display panel including pixels; a gate driver for providing a gate signal to the pixels; a light-emitting driver for providing a light-emitting signal to the pixels; a data driver for providing a data voltage to the pixels; a gamma voltage generation circuit for providing a gamma voltage to the data driver; and a voltage control circuit for generating a compensated high gamma voltage, a compensated low gamma voltage, and a compensated reference voltage based on a sensed power supply voltage measured from a power line transmitting a first power supply voltage, and providing the compensated high gamma voltage and the compensated low gamma voltage to the gamma voltage generation circuit, and providing the compensated reference voltage to the pixels.

[0024] In one embodiment, the pixel may include: a first transistor including a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; a second transistor transmitting the data voltage to a fourth node in response to a write gate signal; a first capacitor connected between the first node and the fourth node; a second capacitor connected between the fourth node and the power line; a third transistor connecting the first node to the third node in response to a compensation gate signal; a fourth transistor transmitting a first initialization voltage to the first node in response to an initialization gate signal; a fifth transistor transmitting the compensation reference voltage to the fourth node in response to the compensation gate signal; a sixth transistor connecting the third node to the fifth node in response to a first light emission signal; a seventh transistor transmitting a second initialization voltage to the fifth node in response to a bypass gate signal; and a light-emitting element including a first terminal connected to the fifth node and a second terminal receiving a second power supply voltage.

[0025] In one embodiment, the voltage control circuit may include: a subtractor that outputs a power supply voltage offset by subtracting a reference power supply voltage (which serves as a target voltage for the first power supply voltage) from the sensed power supply voltage; a first adder that outputs a compensated high gamma voltage by adding the power supply voltage offset to the high gamma voltage; a second adder that outputs a compensated low gamma voltage by adding the power supply voltage offset to the low gamma voltage; and a third adder that outputs a compensated reference voltage by adding the power supply voltage offset to the reference voltage.

[0026] In the display device and electronic device according to embodiments of the present invention, a compensated high gamma voltage, a compensated low gamma voltage, and a compensated reference voltage are generated based on a sensed power supply voltage to compensate for a high gamma voltage, a low gamma voltage, and a reference voltage. Even if noise is generated at the first power supply voltage, the brightness of the light emitted from the pixel can remain unchanged. Accordingly, the image quality of the display device can be improved.

[0027] However, the effects of the present invention are not limited to those described above, and various extensions can be made without departing from the concept and scope of the present invention. Attached Figure Description

[0028] Figure 1 This is a block diagram illustrating a display device according to one embodiment.

[0029] Figure 2 It is shown Figure 1 The circuit diagram of the pixels.

[0030] Figure 3 It is shown Figure 2 Timing diagram of the signal.

[0031] Figure 4 It is shown Figure 1 Block diagram of the voltage control circuit.

[0032] Figure 5 This is a block diagram illustrating a display device according to one embodiment.

[0033] Figure 6 It is shown Figure 5 Block diagram of the gamma voltage control circuit.

[0034] Figure 7 It is shown Figure 5 A block diagram of the reference voltage generation circuit.

[0035] Figure 8 This is a block diagram illustrating an electronic device according to one embodiment.

[0036] Figure 9 This illustrates an electronic device according to an embodiment.

[0037] Explanation of reference numerals in the attached figures 10: Electronic devices 12: Processors 14: Power supply module 100, 101: Display device 110: Display panel; 120: Gate driver 130: Light-emitting driver; 140: Data driver 150: Gamma voltage generation circuit; 160: Voltage control circuit 180: Gamma voltage control circuit; 190: Reference voltage generation circuit C1: First capacitor; C2: Second capacitor EL: Light-emitting element; PX: Pixel T1-T9: Transistors 1 to 9 Detailed Implementation

[0038] Hereinafter, a display device and an electronic device according to embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals are used for the same constituent elements.

[0039] Figure 1 This is a block diagram illustrating a display device 100 according to an embodiment. Figure 2 It is shown Figure 1 The circuit diagram of the pixel PX. Figure 3 It is shown Figure 2 The timing diagrams for signals EM2, EM1, GI, GC, GW, and EB. Figure 4 It is shown Figure 1 Block diagram of voltage control circuit 160.

[0040] Reference Figure 1 , Figure 2 , Figure 3 as well as Figure 4 According to one embodiment, the display device 100 may include a display panel 110, a gate driver 120, a light-emitting driver 130, a data driver 140, a gamma voltage generation circuit 150, a voltage control circuit 160, and a controller 170.

[0041] The display panel 110 may include pixels PX. In one embodiment, pixels PX may include red pixels that emit red light, green pixels that emit green light, and blue pixels that emit blue light.

[0042] Each of the pixels PX can emit light based on at least one gate signal GS, at least one emission signal ES, and a voltage including a data voltage VDAT and a compensation reference voltage VREFC. In one embodiment, each of the pixels PX can emit light based on a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI, a first emission signal EM1, a second emission signal EM2, a bypass gate signal EB, a data voltage VDAT, a first power supply voltage ELVDD, a second power supply voltage ELVSS, a compensation reference voltage VREFC, a first initialization voltage VINIT, a second initialization voltage AINIT, and a bias voltage VBIAS.

[0043] Each pixel PX may include at least one transistor, at least one capacitor, and a light-emitting element EL. In one embodiment, each pixel PX may include a first transistor T1, a second transistor T2, a first capacitor C1, a second capacitor C2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a light-emitting element EL. In another embodiment, each pixel PX may further include an eighth transistor T8 and a ninth transistor T9.

[0044] The first transistor T1 can generate a drive current based on the voltage difference between the first node N1 and the second node N2. The first transistor T1 may include a gate connected to the first node N1, a first terminal connected to the second node N2, and a second terminal connected to the third node N3.

[0045] The second transistor T2 can transmit a data voltage VDAT to the fourth node N4 in response to the write gate signal GW. The second transistor T2 may include a gate for receiving the write gate signal GW, a first terminal for receiving the data voltage VDAT, and a second terminal connected to the fourth node N4.

[0046] A first capacitor C1 may be connected between a first node N1 and a fourth node N4. The first capacitor C1 may include a first terminal connected to the first node N1 and a second terminal connected to the fourth node N4.

[0047] The second capacitor C2 can be connected between the fourth node N4 and the power line PL that transmits the first power supply voltage ELVDD. The second capacitor C2 may include a first terminal connected to the fourth node N4 and a second terminal connected to the power line PL.

[0048] The third transistor T3 can connect the first node N1 to the third node N3 in response to the compensation gate signal GC. The third transistor T3 may include a gate for receiving the compensation gate signal GC, a first terminal connected to the first node N1, and a second terminal connected to the third node N3.

[0049] The fourth transistor T4 can transmit a first initialization voltage VINIT to the first node N1 in response to the initialization gate signal GI. The fourth transistor T4 may include a gate for receiving the initialization gate signal GI, a first terminal for receiving the first initialization voltage VINIT, and a second terminal connected to the first node N1.

[0050] The fifth transistor T5 can transmit a compensation reference voltage VREFC to the fourth node N4 in response to the compensation gate signal GC. The fifth transistor T5 may include a gate for receiving the compensation gate signal GC, a first terminal for receiving the compensation reference voltage VREFC, and a second terminal connected to the fourth node N4.

[0051] The sixth transistor T6 can connect the third node N3 to the fifth node N5 in response to the first light-emitting signal EM1. The sixth transistor T6 may include a gate for receiving the first light-emitting signal EM1, a first terminal connected to the third node N3, and a second terminal connected to the fifth node N5.

[0052] The seventh transistor T7 can transmit a second initialization voltage AINIT to the fifth node N5 in response to the bypass gate signal EB. The seventh transistor T7 may include a gate for receiving the bypass gate signal EB, a first terminal for receiving the second initialization voltage AINIT, and a second terminal connected to the fifth node N5.

[0053] The light-emitting element EL can emit light based on the drive current generated by the first transistor T1. The light-emitting element EL may include a first terminal (e.g., anode) connected to the fifth node N5 and a second terminal (e.g., cathode) receiving a second power supply voltage ELVSS. In one embodiment, the light-emitting element EL may be one of an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot light-emitting diode, and a micro light-emitting diode.

[0054] The eighth transistor T8 can transmit a first power supply voltage ELVDD to the second node N2 in response to the second light-emitting signal EM2. The eighth transistor T8 may include a gate for receiving the second light-emitting signal EM2, a first terminal connected to the power supply line PL, and a second terminal connected to the second node N2.

[0055] The ninth transistor T9 can transmit a bias voltage VBIAS to the second node N2 in response to the bypass gate signal EB. The ninth transistor T9 may include a gate for receiving the bypass gate signal EB, a first terminal for receiving the bias voltage VBIAS, and a second terminal connected to the second node N2.

[0056] During the first time period P1, a first initialization voltage VINIT can be applied to the first node N1 by means of the fourth transistor T4, which is turned on in response to the initialization gate signal GI. Accordingly, during the first time period P1, the first transistor T1 can be turned on.

[0057] In the second time period P2, the value obtained by subtracting the threshold voltage (VTH) of the first transistor T1 from the first power supply voltage ELVDD can be applied to the first node N1 through the eighth transistor T8 (turned on in response to the second light emission signal EM2), the first transistor T1 (turned on), and the third transistor T3 (turned on in response to the compensation gate signal GC). In the second time period P2, the compensation reference voltage VREFC can be applied to the fourth node N4 through the fifth transistor T5 (turned on in response to the compensation gate signal GC). The voltage of the fourth node N4 can change from the data voltage (VDAT') of the previous frame to the compensation reference voltage VREFC. In the second time period P2, due to the coupling effect of the first capacitor C1, the voltage of the first node N1 can be (ELVDD - VTH + VREFC - VDAT').

[0058] During the third time period P3, a first initialization voltage VINIT can be applied to the first node N1 by means of a fourth transistor T4, which is turned on in response to the initialization gate signal GI. Accordingly, during the third time period P3, the first transistor T1 can be turned on.

[0059] During the fourth time period, the value of (ELVDD - VTH), which is the first power supply voltage ELVDD minus the threshold voltage (VTH) of the first transistor T1, can be applied to the first node N1 through the eighth transistor T8 (turned on in response to the second light emission signal EM2), the first transistor T1 (turned on), and the third transistor T3 (turned on in response to the compensation gate signal GC). During the fourth time period P4, the compensation reference voltage VREFC can be applied to the fourth node N4 through the fifth transistor T5 (turned on in response to the compensation gate signal GC). The voltage of the fourth node N4 may remain unchanged. During the fourth time period P4, since the voltage of the fourth node N4 remains unchanged, the voltage of the first node N1 can be maintained at (ELVDD - VTH).

[0060] In the fifth time period P5, the data voltage VDAT can be applied to the fourth node N4 by the second transistor T2, which is turned on in response to the write gate signal GW. The voltage of the fourth node N4 can change from the compensation reference voltage VREFC to the data voltage VDAT. In the fifth time period P5, the voltage of the first node N1 can become (ELVDD-VTH+VDAT-VREFC) due to the coupling effect of the first capacitor C1.

[0061] In the sixth time period P6, the second initialization voltage AINIT can be applied to the fifth node N5 by the seventh transistor T7, which is turned on in response to the bypass gate signal EB. In the sixth time period P6, the bias voltage VBIAS can be applied to the second node N2 by the ninth transistor T9, which is turned on in response to the bypass gate signal EB.

[0062] In the seventh time period P7, a current path can be formed by the eighth transistor T8, which is turned on in response to the second light-emitting signal EM2, the first transistor T1, the sixth transistor T6, which is turned on in response to the first light-emitting signal EM1, and the light-emitting element EL. The drive current (IEL) generated by the first transistor T1 can flow through the current path. The drive current (IEL) can be calculated based on mathematical formula 1.

[0063] [Mathematical Expression 1]

[0064] In Equation 1, K is a proportionality constant, and VSG is the voltage difference between the first terminal and the gate of the first transistor T1. According to Equation 1, the drive current (IEL) can be determined by the compensation reference voltage VREFC and the data voltage VDAT, and is independent of the threshold voltage (VTH) of the first transistor T1. In the seventh time period P7, the light-emitting element EL can emit light with a brightness corresponding to the difference between the compensation reference voltage VREFC and the data voltage VDAT.

[0065] Gate driver 120 may provide at least one gate signal GS to each of the pixels PX. In one embodiment, gate signal GS may include a write gate signal GW, a compensation gate signal GC, and an initialization gate signal GI. Gate driver 120 may generate gate signal GS based on a first control signal CNT1. The first control signal CNT1 may include a gate start signal, a gate clock signal, etc.

[0066] The light-emitting driver 130 can provide at least one light-emitting signal ES to each of the pixels PX. In one embodiment, the light-emitting signal ES may include a first light-emitting signal EM1, a second light-emitting signal EM2, and a bypass gate signal EB. The light-emitting driver 130 can generate the light-emitting signal ES based on a second control signal CNT2. The second control signal CNT2 may include a light-emitting start signal, a light-emitting clock signal, etc.

[0067] Data driver 140 can provide a data voltage VDAT to each of the pixels PX. Data driver 140 can generate the data voltage VDAT based on the output image data IMD2, the gamma voltage VGAM, and a third control signal CNT3. The output image data IMD2 may include grayscale values. Data driver 140 can select the gamma voltage corresponding to the grayscale value from the gamma voltage VGAM as the data voltage VDAT. The third control signal CNT3 may include a load signal, a data clock signal, an output data enable signal, etc.

[0068] The gamma voltage generation circuit 150 can provide a gamma voltage VGAM to the data driver 140. The gamma voltage generation circuit 150 can generate the gamma voltage VGAM based on a compensated high gamma voltage VGMHC and a compensated low gamma voltage VGMLC. In one embodiment, the gamma voltage generation circuit 150 can generate the gamma voltage VGAM by dividing the compensated high gamma voltage VGMHC and the compensated low gamma voltage VGMLC. The compensated high gamma voltage VGMHC can be the maximum voltage in the gamma voltage VGAM, and the compensated low gamma voltage VGMLC can be the minimum voltage in the gamma voltage VGAM.

[0069] Voltage control circuit 160 can provide a compensated high gamma voltage VGMHC and a compensated low gamma voltage VGMLC to gamma voltage generation circuit 150, and can provide a compensated reference voltage VREFC to each of the pixels PX. Voltage control circuit 160 can compensate the high gamma voltage VGMH, low gamma voltage VGMLC, and reference voltage VREF based on the sensed power supply voltage ELVDDS to generate the compensated high gamma voltage VGMHC, the compensated low gamma voltage VGMLC, and the compensated reference voltage VREFC. The sensed power supply voltage ELVDDS can be measured in the power line PL that transmits the first power supply voltage ELVDD.

[0070] In one embodiment, the voltage control circuit 160 may include a subtractor 161, a first adder 162, a second adder 163, and a third adder 164. In another embodiment, the voltage control circuit 160 may also include a digital-to-analog converter 165 and a clamp 166.

[0071] Subtractor 161 outputs a supply voltage offset ΔELVDD as the value obtained by subtracting the reference supply voltage ELVDDR from the sensed supply voltage ELVDDS. The reference supply voltage ELVDDR can be the target voltage of the first supply voltage ELVDD.

[0072] The first adder 162 adds the power supply voltage offset ΔELVDD to the high gamma voltage VGMH and outputs a compensated high gamma voltage VGMHC. The second adder 163 adds the power supply voltage offset ΔELVDD to the low gamma voltage VGML and outputs a compensated low gamma voltage VGMLC. The third adder 164 adds the power supply voltage offset ΔELVDD to the reference voltage VREF and outputs a compensated reference voltage VREFC.

[0073] The digital-to-analog converter 165 can generate a reference power supply voltage ELVDDR by converting the digital-to-analog converter to a reference power supply voltage code ELVDDR_CD. In one embodiment, the reference power supply voltage code ELVDDR_CD can be stored in a register.

[0074] Clamp 166 can clamp the power supply voltage offset ΔELVDD output from subtractor 161 based on minimum offset OF1 and maximum offset OF2, and output it to first adder 162, second adder 163, and third adder 164. If the power supply voltage offset ΔELVDD is less than minimum offset OF1, clamp 166 can output minimum offset OF1 as power supply voltage offset ΔELVDD; if the power supply voltage offset ΔELVDD is greater than maximum offset OF2, maximum offset OF2 can be output as power supply voltage offset ΔELVDD.

[0075] In one embodiment, the voltage control circuit 160 can be implemented as a power management integrated circuit (PMIC).

[0076] If noise such as ripples occurs at the first power supply voltage ELVDD, the first power supply voltage ELVDD may change. If the difference between the first power supply voltage ELVDD and the data voltage VDAT changes, the brightness of the light emitted from the pixel PX may vary, potentially leading to a degrade in the image quality of the display device. Accordingly, in the prior art, adaptive voltage compensation (AVC) is used to compensate for changes in the first power supply voltage ELVDD, thereby compensating for high gamma voltage VGMH and low gamma voltage VGML, thereby compensating for the image quality of the display device. However, according to the prior art... Figure 2 In a pixel PX, the light-emitting element EL can emit light with a brightness corresponding to the difference between the reference voltage VREF and the data voltage VDAT. However, in the prior art, only the high gamma voltage VGMH and the low gamma voltage VGML are compensated, while the reference voltage VREF is not compensated. Accordingly, in the prior art, if noise is generated at the first power supply voltage ELVDD, only the data voltage VDAT changes in response to the change at the first power supply voltage ELVDD, while the reference voltage VREF remains unchanged. Therefore, the brightness of the light emitted from the pixel PX may vary, resulting in a decrease in the image quality of the display device. However, in a display device 100 according to one embodiment, the voltage control circuit 160 can generate a compensated high gamma voltage VGMHC, a compensated low gamma voltage VGMLC, and a compensated reference voltage VREFC based on sensing the power supply voltage ELVDD to compensate for the high gamma voltage VGMH, the low gamma voltage VGML, and the reference voltage VREF. Even if noise is generated at the first power supply voltage ELVDD, the difference between the compensated reference voltage VREFC and the data voltage VDAT may not change. Therefore, even if noise is generated at the first power supply voltage ELVDD, the brightness of the light emitted from the pixel PX will not change, thus improving the image quality of the display device 100.

[0077] The controller 170 can control the gate driver 120, the light-emitting driver 130, and the data driver 140. The controller 170 can provide a first control signal CNT1 to the gate driver 120, a second control signal CNT2 to the light-emitting driver 130, and output image data IMD2 and a third control signal CNT3 to the data driver 140. The controller 170 can generate output image data IMD2, the first control signal CNT1, the second control signal CNT2, and the third control signal CNT3 based on the input image data IMD1 and the control signal CNT0. In one embodiment, the input image data IMD1 may include red image data, green image data, and blue image data. The control signal CNT0 may include a vertical synchronization signal, a horizontal synchronization signal, a master clock signal, an input data enable signal, etc.

[0078] Figure 5 This is a block diagram illustrating a display device 101 according to an embodiment. Figure 6 It is shown Figure 5 Block diagram of the gamma voltage control circuit 180. Figure 7 It is shown Figure 5 Block diagram of the reference voltage generation circuit 190.

[0079] Reference Figure 5 , Figure 6 as well as Figure 7 A display device 101 according to one embodiment may include a display panel 110, a gate driver 120, a light-emitting driver 130, a data driver 140, a gamma voltage generation circuit 150, a gamma voltage control circuit 180, a reference voltage generation circuit 190, and a controller 170. (Refer to...) Figures 5 to 7 In the description of the display device 101, the reference is omitted. Figures 1 to 4 The description describes a configuration that is substantially the same as or similar to that of the display device 100.

[0080] The gamma voltage control circuit 180 can provide the gamma voltage generation circuit 150 with a compensated high gamma voltage VGMHC and a compensated low gamma voltage VGMLC. The gamma voltage control circuit 180 can generate the compensated high gamma voltage VGMHC and the compensated low gamma voltage VGMLC by compensating the high gamma voltage VGMH and the low gamma voltage VGMLC based on the sensed power supply voltage ELVDDS.

[0081] In one embodiment, the gamma voltage control circuit 180 may include a subtractor 181, a first adder 182, and a second adder 183. In another embodiment, the gamma voltage control circuit 180 may further include a digital-to-analog converter 185 and a clamper 186.

[0082] Subtractor 181 can output the power supply voltage offset ΔELVDD as the value obtained by subtracting the reference power supply voltage ELVDDR from the sensed power supply voltage ELVDDS.

[0083] The first adder 182 can add the power supply voltage offset ΔELVDD to the high gamma voltage VGMH and output it as the compensated high gamma voltage VGMHC. The second adder 183 can add the power supply voltage offset ΔELVDD to the low gamma voltage VGML and output it as the compensated low gamma voltage VGMLC.

[0084] The digital-to-analog converter 185 can convert the reference power supply voltage code ELVDDR_CD to generate the reference power supply voltage ELVDDR. The clamper 186 can clamp the power supply voltage offset ΔELVDD output from the subtractor 181 based on the minimum offset OF1 and the maximum offset OF2, and output it to the first adder 182 and the second adder 183.

[0085] In one embodiment, the gamma voltage control circuit 180 can be implemented as a power management integrated circuit (PMIC).

[0086] The reference voltage generation circuit 190 can provide a compensated reference voltage VREFC to each of the pixels PX. The reference voltage generation circuit 190 can generate the compensated reference voltage VREFC based on the compensated high gamma voltage VGMHC.

[0087] In one embodiment, the reference voltage generation circuit 190 may include an operational amplifier AMP, a first resistor R1, a second resistor R2, and a capacitor C.

[0088] An operational amplifier (AMP) may include a first input terminal IN+, a second input terminal IN-, and an output terminal OUT for an output compensation reference voltage VREFC. The output terminal OUT can be connected to the second input terminal IN-. Accordingly, the operational amplifier AMP can be used with negative feedback.

[0089] The first resistor R1 can be connected between the input terminal TIM that receives the compensated high gamma voltage VGMHC and the first input terminal IN+ of the operational amplifier AMP. The first resistor R1 may include a first terminal connected to the input terminal TIM and a second terminal connected to the first input terminal IN+ of the operational amplifier AMP.

[0090] The second resistor R2 can be connected between the first input terminal IN+ of the operational amplifier AMP and ground GND. The second resistor R2 may include a first terminal connected to the first input terminal IN+ of the operational amplifier AMP and a second terminal connected to ground GND.

[0091] Capacitor C can be connected between the first input terminal IN+ of the operational amplifier AMP and ground GND. Capacitor C may include a first terminal connected to the first input terminal IN+ of the operational amplifier AMP and a second terminal connected to ground GND. In other words, capacitor C can be connected in parallel with the second resistor R2.

[0092] The compensation reference voltage VREFC can be calculated using mathematical formula 2.

[0093] [Mathematical Expression 2]

[0094] In Equation 2, VREF is the compensation reference voltage VREFC, R1 is the resistance of the first resistor R1, and R2 is the resistance of the second resistor R2. According to Equation 2, the compensation reference voltage VREFC can be proportional to the compensation high gamma voltage VGMHC. Accordingly, the reference voltage generation circuit 190 can generate a compensated reference voltage VREFC corresponding to the compensation high gamma voltage VGMHC compensated by the gamma voltage control circuit 180.

[0095] In one embodiment, the reference voltage generation circuit 190 may be implemented as an external circuit separate from the gamma voltage control circuit 180, which is implemented as a power management integrated circuit (PMIC).

[0096] Figure 8 This is a block diagram illustrating an electronic device 10 according to an embodiment.

[0097] Reference Figure 8 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0098] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0099] Memory 13 can store data information required for the operation of processor 12 or display module 11. When processor 12 runs an application stored in memory 13, it inputs image data ( Figure 1 IMD1) and control signals ( Figure 1 The CNT0 signal can be transmitted to the display module 11, and the display module 11 can output image information based on the input image data IMD1 and the control signal CNT0.

[0100] The power module 14 may include a power supply module such as a power adapter and a battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0101] At least one of the above-described electronic devices 10 may be included in the display device according to the above embodiments. Figure 1 100 and Figure 5Within display devices 100 and 101. Furthermore, some of the individual modules functionally contained within a single module may be included within display devices 100 and 101, while others may be provided independently of display devices 100 and 101. For example, display devices 100 and 101 may include display module 11, while processor 12, memory 13, and power module 14 may be provided in the form of other devices within electronic device 10 that differ from display devices 100 and 101.

[0102] Figure 9 This is a diagram illustrating an electronic device according to an embodiment.

[0103] Reference Figure 9 The electronic devices of the display devices 100 and 101 according to the embodiments may include not only electronic devices for displaying images (smartphone 10_1a, tablet PC 10_1b, laptop computer 10_1c, television (TV) 10_1d, desktop display 10_1e, etc.), but also wearable electronic devices including display module 11 (such as smart glasses 10_2a, head-mounted display 10_2b, smartwatch 10_2c, etc.) and vehicle electronic devices 10_3 including display module 11 (such as car dashboard, center fascia, center information display (CID) arranged on the dashboard, room mirror display, etc.).

[0104] Industrial practicality The display device according to an exemplary embodiment of the present invention can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart tablets, smartwatches, portable media players (PMPs), personal digital assistant terminals (PDAs), MP3 players, vehicles, etc.

[0105] The display device and electronic device according to exemplary embodiments of the present invention have been described above with reference to the accompanying drawings. However, the foregoing embodiments are exemplary, and modifications and alterations can be made by those skilled in the art without departing from the scope of the technical concept of the present invention as set forth in the claims.

Claims

1. A display device, comprising: Display panel, including pixels; A gate driver provides a gate signal to the pixel; A light-emitting driver provides a light-emitting signal to the pixel; The data driver provides data voltage to the pixel; A gamma voltage generation circuit provides a gamma voltage to the data driver; as well as A voltage control circuit generates a compensated high gamma voltage, a compensated low gamma voltage, and a compensated reference voltage by compensating for a high gamma voltage, a low gamma voltage, and a reference voltage based on a sensed power supply voltage measured from a power supply line transmitting a first power supply voltage, and provides the compensated high gamma voltage and the compensated low gamma voltage to the gamma voltage generation circuit, and provides the compensated reference voltage to the pixel.

2. The display device as claimed in claim 1, wherein, The pixels include: The first transistor includes a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; The second transistor transmits the data voltage to the fourth node in response to the write gate signal; A first capacitor is connected between the first node and the fourth node; The second capacitor is connected between the fourth node and the power line; The third transistor connects the first node to the third node in response to a compensation gate signal; The fourth transistor transmits a first initialization voltage to the first node in response to an initialization gate signal; The fifth transistor transmits the compensation reference voltage to the fourth node in response to the compensation gate signal; The sixth transistor connects the third node to the fifth node in response to the first light-emitting signal; The seventh transistor, in response to a bypass gate signal, transmits a second initialization voltage to the fifth node; and The light-emitting element includes a first terminal connected to the fifth node and a second terminal receiving a second power supply voltage.

3. The display device as claimed in claim 2, wherein, The pixels also include: The eighth transistor transmits the first power supply voltage to the second node in response to the second light emission signal.

4. The display device as claimed in claim 2, wherein, The pixels also include: The ninth transistor transmits a bias voltage to the second node in response to the bypass gate signal.

5. The display device as claimed in claim 1, wherein, The voltage control circuit includes: The subtractor outputs a power supply voltage offset by subtracting a reference power supply voltage, which is the target voltage of the first power supply voltage, from the sensed power supply voltage. The first adder adds the power supply voltage offset to the high gamma voltage and outputs the compensated high gamma voltage. The second adder adds the power supply voltage offset to the low gamma voltage and outputs the compensated low gamma voltage; and The third adder adds the power supply voltage offset to the reference voltage and outputs the compensation reference voltage.

6. The display device as claimed in claim 5, wherein, The voltage control circuit also includes: A digital-to-analog converter generates the reference power supply voltage by converting the reference power supply voltage code from digital to analog.

7. The display device as claimed in claim 5, wherein, The voltage control circuit also includes: A clamper clamps the power supply voltage offset output from the subtractor based on the minimum and maximum offsets, and outputs it to the first adder, the second adder, and the third adder.

8. The display device as claimed in claim 1, wherein, The voltage control circuit is implemented as a power management integrated circuit.

9. The display device as claimed in claim 1, wherein, The gamma voltage generation circuit generates the gamma voltage by dividing the compensated high gamma voltage and the compensated low gamma voltage.

10. A display device, comprising: Display panel, including pixels; A gate driver provides a gate signal to the pixel; A light-emitting driver provides a light-emitting signal to the pixel; The data driver provides data voltage to the pixel; A gamma voltage generation circuit provides a gamma voltage to the data driver; A gamma voltage control circuit generates a compensated high gamma voltage and a compensated low gamma voltage by compensating for high gamma voltage and low gamma voltage based on a sensed power supply voltage measured from a power supply line transmitting a first power supply voltage, and provides the compensated high gamma voltage and the compensated low gamma voltage to the gamma voltage generation circuit. as well as A reference voltage generation circuit generates a compensation reference voltage based on the compensation high gamma voltage and provides the compensation reference voltage to the pixel.

11. The display device as claimed in claim 10, wherein, The pixels include: The first transistor includes a gate connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; The second transistor transmits the data voltage to the fourth node in response to the write gate signal; A first capacitor is connected between the first node and the fourth node; The second capacitor is connected between the fourth node and the power line; The third transistor connects the first node to the third node in response to a compensation gate signal; The fourth transistor transmits a first initialization voltage to the first node in response to an initialization gate signal; The fifth transistor transmits the compensation reference voltage to the fourth node in response to the compensation gate signal; The sixth transistor connects the third node to the fifth node in response to the first light-emitting signal; The seventh transistor, in response to a bypass gate signal, transmits a second initialization voltage to the fifth node; and The light-emitting element includes a first terminal connected to the fifth node and a second terminal receiving a second power supply voltage.

12. The display device as claimed in claim 11, wherein, The pixels also include: The eighth transistor transmits the first power supply voltage to the second node in response to the second light emission signal.

13. The display device as claimed in claim 11, wherein, The pixels also include: The ninth transistor transmits a bias voltage to the second node in response to the bypass gate signal.

14. The display device as claimed in claim 10, wherein, The reference voltage generation circuit includes: An operational amplifier includes a first input terminal, a second input terminal, and an output terminal connected to the second input terminal and outputting the compensation reference voltage; A first resistor is connected between the input terminal receiving the compensated high gamma voltage and the first input terminal of the operational amplifier; and The second resistor is connected between the first input terminal of the operational amplifier and ground.

15. The display device as claimed in claim 14, wherein, The compensation reference voltage is calculated using the following mathematical formula: [Mathematical expression] ， In the mathematical formula, VREF is the compensation reference voltage, R1 is the resistance of the first resistor, R2 is the resistance of the second resistor, and VGMHC is the compensation high gamma voltage.

16. The display device as claimed in claim 10, wherein, The gamma voltage control circuit includes: The subtractor outputs a power supply voltage offset by subtracting a reference power supply voltage, which is the target voltage of the first power supply voltage, from the sensed power supply voltage. The first adder adds the power supply voltage offset to the high gamma voltage and outputs the compensated high gamma voltage. The second adder adds the power supply voltage offset to the low gamma voltage and outputs the compensated low gamma voltage.

17. The display device as claimed in claim 10, wherein, The gamma voltage generation circuit generates the gamma voltage by dividing the compensated high gamma voltage and the compensated low gamma voltage.

18. An electronic device comprising: The processor generates the input image data; The display device displays an image based on the input image data; as well as The power module is connected to the processor and the display device. The display device is the display device as described in any one of claims 1 to 17.

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