Liquid crystal display screen area transmittance dynamic adjustment circuit, driving method and display module

Abstract

The present application relates to liquid crystal display driving technology field, disclose a kind of liquid crystal display screen area transmittance dynamic adjustment circuit, driving method and display module.Circuit includes the reference voltage generation unit connected in turn, double holding unit, library selection unit, positive and negative Gamma generation unit and Gamma bus isolation and precharge unit, and timing control unit.Double holding unit's working library exports current line with reference voltage, standby library preloads next line with reference voltage;Same group of Gamma binding point parameter remains unchanged in positive and negative polarity pairing unit.Output is prohibited in sequence, isolation and precharge Gamma bus is only when line band scanning ends, polarity pairing is completed and preloading is completed, switch holding library is accessed new reference voltage and restores source output.The present application can reduce the direct current residue caused by line band boundary switching disturbance and polarity misplacement.

Description

Technical Field

[0001] This invention relates to the field of liquid crystal display driving technology, specifically to a dynamic adjustment circuit, driving method, and display module for regional transmittance of a liquid crystal display screen. Background Technology

[0002] Liquid crystal display modules typically provide data voltages corresponding to gray levels to pixel electrodes via source drivers, and determine the mapping relationship between digital gray levels and data voltages using a Gamma reference voltage. For display modules employing local dimming backlighting, the luminous intensity of different backlight zones can be adjusted according to the image content, and the target transmittance of the liquid crystal layer can be changed accordingly to balance brightness, contrast, and power consumption.

[0003] When the regional transmittance updates with the image content, the Gamma reference voltage corresponding to different regions needs to be updated during the scanning process. To reduce the number of digital-to-analog conversion channels and analog reference channels, multiple reference voltages for Gamma binding points can be generated sequentially by sharing digital-to-analog conversion resources and sample-and-hold resources.

[0004] However, when sharing analog-to-digital conversion resources and switching reference voltages at the line band boundary, a significant voltage difference may exist between the new reference voltage and the currently used reference voltage. This charge redistribution among the sample-and-hold node, reference bus, and source driver inputs can easily create transient disturbances. If switching occurs directly while the source driver is still in output mode, these transient disturbances may be transmitted to the pixel data voltage, causing line band seams or short-term brightness fluctuations.

[0005] Furthermore, liquid crystal pixels typically employ alternating positive and negative polarities to reduce the DC component. If the Gamma binding point parameter in the same region changes between a positive polarity driving cycle and its paired negative polarity driving cycle, the effective trans-voltage relative to the common voltage under the two polarities may no longer correspond, thus resulting in residual DC.

[0006] Furthermore, the update of the row-band reference voltage is constrained by both the pre-loading time and the boundary switching time. Shortening the write time of the standby holding library may result in some column groups or Gamma binding points not yet reaching the target voltage; extending the pre-charge, setup, or stabilization wait time may occupy the limited row-band boundary time period. Therefore, simply setting up dual holding libraries or only selecting blank time period switching is still insufficient to simultaneously ensure that the next set of reference voltages is fully pre-loaded, the positive and negative polarity pairing is not broken, and the switching transient is not transmitted to the source line.

[0007] Therefore, existing regional transmittance adjustment circuits still need to address a specific problem: how to update the regional Gamma reference voltage at the line band level while sharing reference voltage generation resources, and how to balance reference bus switching stability and positive / negative polarity drive consistency during the update process. Summary of the Invention

[0008] To address the shortcomings of existing technologies, the present invention aims to provide a dynamic adjustment circuit, driving method, and display module for regional transmittance of a liquid crystal display screen.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] A dynamic transmittance adjustment circuit for a liquid crystal display screen is applied to a liquid crystal display screen, the liquid crystal display screen including multiple row strips and multiple column groups, the multiple row strips and multiple column groups intersect to form multiple display areas, each column group corresponds to at least one Gamma binding point, the dynamic transmittance adjustment circuit includes a reference voltage generation unit, a dual hold unit, a library selection unit, a positive and negative Gamma generation unit, a Gamma bus isolation and pre-charge unit, and a timing control unit;

[0011] The reference voltage generation unit, dual hold unit, library selection unit, positive and negative Gamma generation unit, and Gamma bus isolation and precharge unit are connected in sequence. The Gamma bus isolation and precharge unit is connected to the positive Gamma reference input terminal and the negative Gamma reference input terminal of the source driver via the positive Gamma reference bus and the negative Gamma reference bus. The timing control unit is connected to the reference voltage generation unit, dual hold unit, library selection unit, Gamma bus isolation and precharge unit, and the source output enable terminal of the source driver, respectively.

[0012] Under the control of the timing control unit, the same set of Gamma binding point parameters remains unchanged within the polarity pairing unit consisting of one positive polarity drive cycle and one negative polarity drive cycle; the two holding libraries of the dual holding unit alternately serve as the working library and the waiting library. During the period when the working library outputs the Gamma binding point reference voltage of the current row band, the reference voltage generation unit preloads the Gamma binding point reference voltage of the next row band into the waiting library according to the column group selection information and the binding point selection information;

[0013] Only when the current row band scan ends, the polarity pairing unit completes, and the Gamma binding point reference voltage of the next row band is pre-loaded, the timing control unit sequentially disables the source driver output, disconnects the positive and negative Gamma generation units from the positive and negative Gamma reference buses, pre-charges the positive and negative Gamma reference buses, switches the holding library, and connects the new positive and negative Gamma reference voltages to their respective Gamma reference buses after they are established; the pre-charging ends and the source driver output is restored after the positive and negative Gamma reference buses stabilize.

[0014] In a preferred embodiment, the reference voltage generation unit includes a target parameter latching unit, a shared digital-to-analog converter, a digital-to-analog converter output buffer, and an analog demultiplexer;

[0015] The parameter input terminal of the target parameter latch unit receives the target parameter signal TARGET_CODE_CK, the latch control terminal receives the parameter submission signal PAIR_COMMIT, and the output terminal is connected to the digital input terminal of the shared digital-to-analog converter.

[0016] The clock and update terminals of the shared digital-to-analog converter receive the digital-to-analog converter clock signal DAC_CLK and the digital-to-analog converter latch signal DAC_LATCH, respectively, and its analog output terminal is connected to the common analog input terminal of the analog demultiplexer through the digital-to-analog converter output buffer.

[0017] The analog demultiplexer transmits the analog reference voltage output by the shared digital-to-analog converter to the write node of the corresponding column group and Gamma binding point according to the column group address COL_GROUP_ADDR and the binding point address BIND_ADDR.

[0018] In a preferred embodiment, the dual holding unit is provided with a write node, a first sampling switch, a second sampling switch, a first holding capacitor, a second holding capacitor, a first holding buffer, and a second holding buffer for each Gamma binding point of each column group;

[0019] The write node is connected to the first holding capacitor and the first holding buffer respectively through the first sampling switch, and is connected to the second holding capacitor and the second holding buffer respectively through the second sampling switch. The other ends of the first holding capacitor and the second holding capacitor are respectively connected to analog ground.

[0020] The outputs of the first holding buffer and the second holding buffer are respectively connected to the two analog inputs of the library selection switch in the library selection unit;

[0021] The first sampling switch and the second sampling switch are controlled by the first loading signal LOAD_A and the second loading signal LOAD_B, respectively, and the first loading signal LOAD_A and the second loading signal LOAD_B are not effective at the same time; the library selection switch is controlled by the library selection signal BANK_SEL, and adopts a switching method of disconnecting first and then turning on.

[0022] In a preferred embodiment, the Gamma bus isolation and precharge unit includes a positive Gamma isolation switch, a negative Gamma isolation switch, a positive Gamma precharge switch, a negative Gamma precharge switch, a first precharge resistor, and a second precharge resistor;

[0023] The positive Gamma isolation switch is connected between the positive Gamma output terminal of the positive and negative Gamma generation unit and the positive Gamma reference bus; the negative Gamma isolation switch is connected between the negative Gamma output terminal of the positive and negative Gamma generation unit and the negative Gamma reference bus.

[0024] The positive precharge voltage terminal is connected to the positive Gamma reference bus through the first precharge resistor and the positive Gamma precharge switch, and the negative precharge voltage terminal is connected to the negative Gamma reference bus through the second precharge resistor and the negative Gamma precharge switch. The positive Gamma precharge switch and the negative Gamma precharge switch are controlled by the precharge control signal PRE.

[0025] In a preferred embodiment, the timing control unit includes a Gamma bus stability detection unit and a timeout counter;

[0026] The Gamma bus stability detection unit includes a window comparator, which detects whether the positive Gamma reference bus and the negative Gamma reference bus have entered the corresponding target voltage window.

[0027] The timing control unit ends the precharge and resumes the source driver output only when both the positive Gamma reference bus and the negative Gamma reference bus enter the corresponding target voltage window;

[0028] When the timeout counter reaches the preset timeout value and the positive Gamma reference bus or the negative Gamma reference bus does not enter the corresponding target voltage window, the timing control unit maintains the source driver in the output disabled state and re-executes the precharge.

[0029] In a preferred embodiment, the timing control unit includes a polarity state counter, a column group counter, a binding point counter, and a state machine;

[0030] The polarity state counter records the positive polarity drive completion state and negative polarity drive completion state corresponding to the same set of Gamma binding point parameters according to the polarity signal POL, and generates a polarity pairing completion flag when both completion states are valid.

[0031] The column group counter and the binding point counter generate the column group selection information and the binding point selection information, and generate a pre-installation completion flag after the column group and Gamma binding point that need to be updated have been written.

[0032] The state machine enters the database switching state only when the line band end flag, the polarity pairing completion flag, and the pre-installation completion flag are all valid; the polarity pairing completion flag and the pre-installation completion flag are cleared after a database switching is completed.

[0033] In a preferred embodiment, the timing control unit outputs an enable signal OE_SRC, an isolation control signal ISO_GAMMA, a precharge control signal PRE, and a library selection signal BANK_SEL during the library switching process.

[0034] The source output enable signal OE_SRC remains disabled from the moment the source driver output is disabled until the precharge ends and the positive Gamma reference bus and the negative Gamma reference bus are stable.

[0035] The isolation control signal ISO_GAMMA remains in an isolated state from the time the Gamma reference bus is isolated until a new positive Gamma reference voltage and negative Gamma reference voltage are established.

[0036] The precharge control signal PRE remains valid from the start of precharge until the positive Gamma reference bus and the negative Gamma reference bus stabilize.

[0037] The BANK_SEL signal toggles only when the source driver output is disabled, the Gamma reference bus is isolated, and the bus is in a precharge state.

[0038] A driving method for a dynamic transmittance adjustment circuit for a liquid crystal display screen is provided, applied to a liquid crystal display screen having multiple row bands and multiple column groups, wherein the multiple row bands and multiple column groups intersect to form multiple display areas. The dynamic transmittance adjustment circuit is connected to a source driver, a positive Gamma reference bus, and a negative Gamma reference bus, and has two holding libraries that alternately serve as working libraries and standby libraries, including:

[0039] S101, Obtain the target transmittance parameters for each display area;

[0040] S102, Generate the Gamma binding point parameters for each column group based on the target penetration rate parameters;

[0041] S103 ensures that the same set of Gamma binding point parameters remain unchanged within a polar pairing unit consisting of a positive polarity driving cycle and a negative polarity driving cycle.

[0042] S104, during the output of the Gamma binding point reference voltage of the current row band in the working library, the Gamma binding point reference voltage of the next row band is pre-loaded into the standby library according to the column group selection information and the binding point selection information;

[0043] S105, determine whether the current row band scan has ended, whether the polarity pairing unit has been completed, and whether the Gamma binding point reference voltage of the next row band has been pre-installed; if any condition is not met, maintain the working library output; if all three conditions are met, execute S106.

[0044] S106, disable the source driver output, disconnect the connection between the positive Gamma reference voltage and the positive Gamma reference bus and the connection between the negative Gamma reference voltage and the negative Gamma reference bus respectively, and then precharge the positive Gamma reference bus and the negative Gamma reference bus.

[0045] S107, switch the standby library to the new working library, after the new positive Gamma reference voltage and negative Gamma reference voltage are established, connect the new positive Gamma reference voltage and negative Gamma reference voltage to the positive Gamma reference bus and negative Gamma reference bus respectively, and end the precharge and restore the source driver output after the positive Gamma reference bus and negative Gamma reference bus are stable.

[0046] In a preferred embodiment, in step S104, the Gamma binding point parameters of the next row are converted into an analog reference voltage by a shared digital-to-analog converter, and the analog reference voltage is written sequentially to the holding nodes of the corresponding column group and Gamma binding point according to the column group address COL_GROUP_ADDR and the binding point address BIND_ADDR by an analog demultiplexer. After all the holding nodes that need to be updated have been written, a pre-loading completion flag LOAD_NEXT_DONE is generated.

[0047] In step S105, the positive polarity drive completion state POS_DONE and the negative polarity drive completion state NEG_DONE are recorded according to the polarity signal POL, and a polarity pairing completion flag PAIR_DONE is generated when both the positive polarity drive completion state POS_DONE and the negative polarity drive completion state NEG_DONE correspond to the same set of Gamma binding point parameters.

[0048] After step S107 is completed, the pre-installation completion flag LOAD_NEXT_DONE and the polarity pairing completion flag PAIR_DONE are cleared, and the original working library is set as the library to be used in the next round of pre-installation.

[0049] A display module includes a timing controller, a source driver, a gate driver, a partition backlight driver, a partition backlight, a regional liquid crystal panel, and a dynamic adjustment circuit for the regional transmittance of the liquid crystal display screen according to any one of claims 1 to 7.

[0050] The timing controller is connected to the regional transmittance dynamic adjustment circuit, the source driver, the gate driver, and the partition backlight driver, respectively.

[0051] The region transmittance dynamic adjustment circuit is connected to the positive Gamma reference input terminal, the negative Gamma reference input terminal, and the source output enable terminal of the source driver.

[0052] The partition backlight driver is connected to the partition backlight, and the backlight partitions of the partition backlight have a preset mapping relationship with multiple display areas of the regional liquid crystal panel;

[0053] The timing controller generates target transmittance parameters and backlight driving parameters for each display area based on image data, and synchronizes the Gamma reference voltage generated by the regional transmittance dynamic adjustment circuit, the data output of the source driver, the horizontal band scanning of the gate driver, and the emission timing of the partitioned backlight.

[0054] Compared with the shortcomings of the prior art, the beneficial effects of the present invention are as follows:

[0055] This invention allows the reference voltage of the next row band to be pre-loaded into another holding library while the current row band outputs the reference voltage from the working library. This enables the two-dimensional region parameters to be pipelined and updated according to the row band time address and column group physical address, thereby reducing the update wait time of the region reference voltage while reusing the shared digital-to-analog converter.

[0056] Furthermore, this invention maintains the regional Gamma binding point parameters within a complete positive and negative polarity pairing unit and uses the polarity pairing completion status as one of the conditions for library switching permission, which can reduce DC residue caused by the mismatch of reference parameters used in the positive and negative polarity drives of the same region.

[0057] Furthermore, this invention first disables the source driver output and isolates the Gamma reference bus during library switching, then precharges the Gamma reference bus before completing library switching, establishment, and reconnection. This can reduce the impact of library switching and reference bus charge redistribution on pixel data voltage.

[0058] Furthermore, this invention sets the end of the line band, the completion of polarity pairing, and the completion of the pre-installation of the next line band as common switching conditions; if any condition is not met, the current working library is maintained, thereby avoiding premature switching before the reference voltage is established or the polarity pairing is completed, and improving the continuity of the area transmittance update process.

[0059] Furthermore, the three switching conditions work in conjunction with the predetermined library replacement sequence: the pre-loading completion condition prevents incompletely written holding libraries from being connected to the output; the polarity pairing completion condition prevents parameter sets from being changed between opposite polarity drives; and the line band end condition restricts switching to the boundaries of adjacent line bands. Based on this, source output disable, bus isolation, and pre-charge operation suppress the propagation of reference node charge redistribution to pixel data voltage. Thus, the condition judgments and the library replacement sequence work together in the same regional reference update process.

[0060] In addition, the shared digital-to-analog converter writes the reference voltage to each hold node in turn through the column group address and the binding point address. Each column group only needs to set up two sets of hold networks, A and B, without having to set up an independent analog reference generation link for each row band, which is beneficial for controlling the circuit size. Attached Figure Description

[0061] Figure 1 This is a block diagram of a display module system according to an embodiment of the present invention;

[0062] Figure 2 This is a schematic diagram of the dynamic penetration rate adjustment circuit corresponding to the c-th column group and the k-th Gamma binding point in one embodiment of the present invention.

[0063] Figure 3 This is a schematic diagram of the timing of the pre-loading and warehouse switching control of the conveyor belt according to an embodiment of the present invention;

[0064] Figure 4 This is a schematic diagram of a dynamic adjustment driving method for regional transmittance of a liquid crystal display screen according to an embodiment of the present invention. Detailed Implementation

[0065] To make the objectives, technical solutions, and effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the described embodiments are only for explaining the invention and not for limiting it. Those skilled in the art can make adaptive adjustments to the connection methods, effective signal levels, number of devices, and parameters in the embodiments without departing from the concept of the invention.

[0066] Generally, in this invention, a "row band" refers to one or more scan rows in a liquid crystal panel that use the same set of regional Gamma reference voltages between two adjacent region reference switches; a "column group" refers to a group of source drive channels that share the same set of Gamma binding point reference voltages. M row bands and N column groups intersect to form a region Z(r, c), where r = 1 to M and c = 1 to N. The row bands and column groups are not required to be of the same size as the backlight partitions; only a defined mapping relationship needs to be established.

[0067] Generally, the "Gamma binding point" referred to in this invention is a discrete reference point used to determine the grayscale-data voltage mapping curve. Each column group can be set with K Gamma binding points, where k = 1 to K. The source driver can perform voltage division or interpolation between adjacent Gamma binding points to obtain the data voltage corresponding to the input grayscale.

[0068] Generally, the "working library" referred to in this invention is the holding library currently connected to the positive and negative Gamma generation circuit and providing a reference voltage for the current line band; the "standby library" is another holding library disconnected from the output path and used to preload the reference voltage for the next line band. When holding library A is the working library, holding library B is the standby library; when holding library B is the working library, holding library A is the standby library.

[0069] Generally, the "polarity pairing unit" referred to in this invention includes a positive polarity driving cycle and a negative polarity driving cycle driven by the same set of regional Gamma binding point parameters. The positive polarity driving cycle may precede or follow the negative polarity driving cycle. The cycle may correspond to one frame, one row, one row, or multiple scanning units, specifically determined by the frame inversion, row inversion, column inversion, dot inversion, or combinations thereof adopted by the display module.

[0070] It should be pointed out that, Figure 2 Only one set of analog hold and reference generation paths is deployed for the c-th column group and the k-th Gamma binding point. The remaining Gamma binding points corresponding to the same column group are set repeatedly according to k = 1 to K, and the circuits corresponding to the remaining column groups are set repeatedly according to c = 1 to N. The shared digital-to-analog converter U2, digital-to-analog converter output buffer U3, analog demultiplexer U4, and timing control unit U10 can be shared by multiple column groups and multiple Gamma binding points.

[0071] Example 1: Dynamic Adjustment Circuit and Display Module for Regional Transmittance

[0072] See Figure 1The display module in this embodiment includes a timing controller, a dynamic regional transmittance adjustment circuit, a source driver, a gate driver, a zone backlight driver, a zone backlight, and an M×N region liquid crystal panel. After image data is input to the timing controller, the timing controller outputs pixel grayscale data and scan-related signals on the one hand, and forms target transmittance parameters and zone backlight control parameters based on the image characteristics of each region on the other hand.

[0073] Specifically, the timing controller provides the regional transmittance dynamic adjustment circuit with target transmittance-related codes, frame synchronization, line band end, and polarity information. Based on this, the regional transmittance dynamic adjustment circuit provides the source driver with positive and negative Gamma reference voltages corresponding to each column group of the current line band. The source driver generates source data voltages based on the image grayscale data and the Gamma reference voltages, and the gate driver selects the panel scanning rows according to the scanning timing. Correspondingly, the partition backlight driver drives the partition backlight according to the partition backlight control parameters to coordinate the liquid crystal transmittance adjustment with the partition backlight brightness.

[0074] It should be noted that the partitioned backlight is located on the backlight incident side of the M×N area LCD panel. The partitioned backlight and the M×N area LCD panel have an optical illumination relationship. The partitioned backlight does not output electrical control signals to the M×N area LCD panel for controlling the liquid crystal pixels. The pixel transmission state of the M×N area LCD panel is determined by the data voltage output by the source driver and the scan signal output by the gate driver. The area transmittance dynamic adjustment circuit and the partitioned backlight driver operate according to the target transmittance parameters and backlight driving parameters generated by the timing controller based on the same image data, so that the liquid crystal transmittance adjustment and the partitioned backlight brightness are coordinated in timing.

[0075] Optionally, the target transmittance parameter can be determined by one or more of the following: grayscale statistics of the current area, target brightness, driving intensity of the corresponding backlight zone, and panel calibration data. The timing controller can use a lookup table, piecewise linear interpolation, or a calibration function to convert the regional target transmittance parameter into digital target codes corresponding to K Gamma binding points. The digital target codes are obtained through... Figure 2 The external network TARGET_CODE_CK input target parameter latch register U1 is shown.

[0076] For example, but not limited to, for the r-th row band, c-th column group, and k-th Gamma binding point, the target reference voltage Vtarget(r, c, k) can first be obtained from the calibration table, and then quantized into target code according to the input range of the shared digital-to-analog converter U2. The number of bits of the target code can be selected based on brightness uniformity, Gamma accuracy, and digital-to-analog conversion setup time; for example, an 8-bit to 14-bit target code can be used. This example does not constitute a limitation on the number of bits of the digital-to-analog converter.

[0077] See Figure 2 The data input of the target parameter latch register U1 is connected to TARGET_CODE_CK, and the latch control terminal is connected to PAIR_COMMIT output by the timing control unit U10. U1 can sequentially latch target codes belonging to the same submitted parameter set according to the column group address and binding point address, and provide the currently selected target code to the shared digital-to-analog converter U2; before the end of the complete polarity pairing unit, the upstream does not replace the submitted parameter set with a new parameter set. Thus, the same region uses a consistent Gamma binding point parameter within a complete polarity pairing unit. The output of U1 is connected to the digital input of the shared digital-to-analog converter U2.

[0078] The shared digital-to-analog converter U2 receives DAC_CLK and DAC_LATCH and converts the target code latched by U1 into an analog voltage. The analog output of the shared digital-to-analog converter U2 is connected to the non-inverting input of the digital-to-analog converter output buffer U3; the output of U3 is fed back to its inverting input to form a voltage follower. The VDAC output of U3 is connected to the common analog input of the analog demultiplexer U4.

[0079] The address control pin of analog demultiplexer U4 receives COL_GROUP_ADDR and BIND_ADDR respectively, enabling VDAC to be routed to the specified column group and the specified Gamma binding point; the enable pin of U4 receives SEL_CK. For Figure 2 The c-th column group and k-th Gamma binding point, as expanded, form the write node W_CK through the corresponding output of U4. The timing control unit U10 can sequentially traverse c=1 to N and k=1 to K, enabling a shared digital-to-analog converter U2 to sequentially complete the writing of multiple standby holding nodes.

[0080] The write node W_CK is divided into two independent paths, A and B. In path A, W_CK is connected to the first holding node via the A-path sampling switch SW1. The first holding capacitor C1 is connected between the first holding node and analog ground. The first holding node is connected to the non-inverting input of the first holding buffer U5. The output of U5 is fed back to its inverting input and outputs the A-bank buffer voltage. In path B, W_CK is connected to the second holding node via the B-path sampling switch SW2. The second holding capacitor C2 is connected between the second holding node and analog ground. The second holding node is connected to the non-inverting input of the second holding buffer U6. The output of U6 is fed back to its inverting input and outputs the B-bank buffer voltage.

[0081] Sampling switch SW1 for channel A is controlled by LOAD_A, and sampling switch SW2 for channel B is controlled by LOAD_B. Generally, LOAD_A and LOAD_B are not active simultaneously to avoid unnecessary charge exchange between the A and B holding nodes via the write node. The capacitances of the first holding capacitor C1 and the second holding capacitor C2 can be determined based on the standby holding time, leakage current during sampling switch shutdown, input bias current of the subsequent buffer, and allowable voltage droop.

[0082] The outputs of the first holding buffer U5 and the second holding buffer U6 are respectively connected to the two inputs of the library selection switch SW3. The library selection switch SW3 is controlled by BANK_SEL and preferably uses a disconnect-then-connect switching method. When BANK_SEL indicates that library A is the working library, the timing control unit U10 uses LOAD_B to preload library B; when BANK_SEL indicates that library B is the working library, the timing control unit U10 uses LOAD_A to preload library A.

[0083] The output of library selector switch SW3 is connected to the non-inverting input of positive Gamma output buffer U7. The output of U7 is fed back to its inverting input and outputs the new positive Gamma reference voltage VGAMMA_P_NEW_CK. The external common voltage VCOM_REF is connected to the non-inverting input of common voltage buffer U8. The output of U8 is fed back to its inverting input and outputs VCOM_BUF.

[0084] The non-inverting input of the negative gamma mirror operational amplifier U9 is connected to VCOM_BUF, and VGAMMA_P_NEW_CK is connected to the inverting input of U9 via input resistor R1. The output of U9 is connected to its inverting input via feedback resistor R2 and outputs a new negative gamma reference voltage VGAMMA_N_NEW_CK. The general relationship is: VGAMMA_N_NEW_CK = (1 + R2 / R1) × VCOM_BUF - (R2 / R1) × VGAMMA_P_NEW_CK. When R1 = R2, the relationship simplifies to VGAMMA_N_NEW_CK = 2 × VCOM_BUF - VGAMMA_P_NEW_CK. Therefore, the positive and negative gamma reference voltages can form a corresponding relationship around the common buffer voltage.

[0085] The new positive Gamma reference voltage is connected to the positive Gamma reference terminal of the source driver interface J1 via the positive Gamma isolation switch SW4, and the new negative Gamma reference voltage is connected to the negative Gamma reference terminal of the source driver interface J1 via the negative Gamma isolation switch SW5. SW4 and SW5 are controlled by the same Gamma isolation signal ISO_GAMMA. When ISO_GAMMA is inactive, SW4 and SW5 are disconnected to isolate the positive and negative Gamma generation circuits from the Gamma reference bus on the source driver side; when ISO_GAMMA is active, SW4 and SW5 are closed to connect the new reference voltage to the corresponding Gamma reference bus.

[0086] The positive precharge voltage VPRE_P is connected to the positive Gamma reference bus via the positive Gamma precharge resistor R3 and the positive Gamma precharge switch SW6. The negative precharge voltage VPRE_N is connected to the negative Gamma reference bus via the negative Gamma precharge resistor R4 and the negative Gamma precharge switch SW7. SW6 and SW7 are controlled by the same precharge signal PRE. It should be noted that R3 and R4 are passive devices without control terminals. U10 controls SW6 and SW7 to connect or disconnect the precharge branch, rather than directly controlling R3 and R4.

[0087] Optionally, VPRE_P and VPRE_N can be a fixed precharge level, a precharge level with a predetermined offset from VCOM_REF, or an intermediate precharge level formed based on the old and new reference voltages. R3 and R4 are used to limit the precharge transient current and, together with the equivalent capacitance of the Gamma reference bus, determine the precharge time constant. The precharge level and resistor values ​​can be determined based on the permissible disturbance of the Gamma reference bus, the source driver input range, and the available blank time.

[0088] The source driver interface J1 includes at least a positive Gamma reference terminal, a negative Gamma reference terminal, and a source output enable terminal. The positive Gamma reference bus and the negative Gamma reference bus are connected to the positive Gamma reference terminal and the negative Gamma reference terminal of J1, respectively. The OE_SRC output of U10 is connected to the source output enable terminal of J1. When OE_SRC is disabled, the source driver stops transmitting the reference switching process to the panel source line; after OE_SRC is enabled, the source driver resumes the data voltage output based on the stabilized Gamma reference voltage.

[0089] The input signals of the timing control unit U10 include CLK, RESET_N, FRAME_SYNC, ROW_END, POL, and LOAD_NEXT_DONE. CLK is used for the state machine, address counting, and setup time counting; RESET_N is used to initialize the working library, address counting, and output control status; FRAME_SYNC is used to determine the frame start point and reset or correct the line band address; ROW_END is used to indicate the end of the current line band scan; POL is used to indicate the current drive polarity; and LOAD_NEXT_DONE is used to indicate that the N×K standby holding nodes for the next line band have been pre-loaded.

[0090] U10 records the completion status of the current polarity pairing unit based on the state and changes of POL. For example, a polarity state counter can be set to record the completion of one positive polarity drive and one negative polarity drive, respectively, and form an internal PAIR_DONE state when both are completed. PAIR_DONE is used to participate in the database swap condition judgment and does not need to be used as a database swapping condition. Figure 2 The external input terminal in the process. The new PAIR_COMMIT is used to allow U1 to latch new target code before the next complete polarity pairing unit begins.

[0091] Specifically, the U10 internally allows setting a positive polarity completion flag POS_DONE and a negative polarity completion flag NEG_DONE. When ROW_END or a scan completion event corresponding to the end of the current line band arrives, the U10 reads the POL: POS_DONE is set when the completed drive cycle is positive polarity, and NEG_DONE is set when the completed drive cycle is negative polarity; PAIR_DONE is only formed when POS_DONE and NEG_DONE correspond to the same set of submitted parameters and are both set. PAIR_DONE is cleared after a database change and new working database confirmation. Therefore, a single POL transition does not directly equate to polarity pairing completion, avoiding misjudgments during resets, dropped lines, or abnormal scan states.

[0092] Specifically, the U10 can also be configured with a column group counter, a binding point counter, and a write completion flag. After each target holding node completes its analog-to-digital conversion, demultiplexing selection, and sample-and-hold operation, the corresponding count status is updated. When all nodes requiring writing in the current operation within the range c = 1 to N and k = 1 to K have been completed, LOAD_NEXT_DONE is set. When using sparse updates, the range is the set of nodes whose mask identifiers are updated. LOAD_NEXT_DONE is cleared after a library swap and is re-counted when the next round of pre-installation of the pending library begins.

[0093] The output signals of U10 include PAIR_COMMIT, DAC_CLK, DAC_LATCH, COL_GROUP_ADDR, BIND_ADDR, SEL_CK, LOAD_A, LOAD_B, BANK_SEL, ISO_GAMMA, PRE, and OE_SRC. PAIR_COMMIT controls U1; DAC_CLK and DAC_LATCH control U2; COL_GROUP_ADDR, BIND_ADDR, and SEL_CK control U4; LOAD_A and LOAD_B control SW1 and SW2 respectively; BANK_SEL controls SW3; ISO_GAMMA jointly controls SW4 and SW5; PRE jointly controls SW6 and SW7; and OE_SRC controls the enable output of the source driver corresponding to J1. U3, U5, U6, U7, U8, and U9 are analog buffers or operational circuits and do not require independent switching control terminals from U10.

[0094] See Figure 3 During the current row band scan (r), the working library continuously provides the current row band reference voltage to the positive and negative Gamma generation circuits. Simultaneously, U10 sequentially sets COL_GROUP_ADDR and BIND_ADDR, sending the target code for each column group and Gamma binding point of the next row band (r+1) to U1 and U2, and writing the corresponding analog reference voltage to the hold library via LOAD_A or LOAD_B. Once all predetermined hold nodes have been written, LOAD_NEXT_DONE is formed.

[0095] Generally, the pre-loading of the pending library should be completed before the library needs to be replaced. For full pre-loading, the available pre-loading time TLOAD for the current row band should satisfy that TLOAD is not less than N×K×tWRITE, where tWRITE includes at least the time required for target code loading, analog-to-digital conversion setup, demultiplexing gating, and sample-and-hold. For sparse updates, N×K can be replaced with the number of nodes to be written in the update mask. The above relationship is used to illustrate the pre-loading scheduling principle and does not limit the specific speed of each circuit element.

[0096] Upon receiving ROW_END, U10 further determines whether a complete positive and negative polarity pairing is achieved based on POL. A library swap permission can be represented as a logical AND of ROW_END, PAIR_DONE, and LOAD_NEXT_DONE. If any condition is not met, U10 maintains the current BANK_SEL, does not change the working library, and continues to wait for the unmet condition. Accordingly, the current reference voltage will not be prematurely switched due to a single line band end signal.

[0097] Optionally, U10 employs a state machine to implement the joint judgment and database switching control. The state machine includes display state, pre-installation state, waiting for permission state, source output disabled state, bus isolation state, pre-charge state, database switching state, reference establishment state, new reference access state, bus stable state, end pre-charge state, and resume output state. The display state and pre-installation state can run in parallel; the remaining states follow a specific time frame. Figure 3 The sequence of actions shown is as follows. Except for reset or fault protection, the state machine switches directly from the old work library to the new work library without skipping the pre-charge state.

[0098] When all three switching conditions are met, U10 first disables OE_SRC to prevent the source driver output; then it isolates ISO_GAMMA, disconnecting SW4 and SW5; then it enables PRE, closing SW6 and SW7, and pre-charging the positive and negative Gamma reference buses to the corresponding pre-charge levels through R3 and R4 respectively.

[0099] During the precharge period, U10 toggles BANK_SEL, making the original pending library the new working library, and waits for the preset reference voltage setup time tSET. tSET can be determined by a fixed counter or by comparing the output of the new working library with the target window. After the wait is complete, U10 enables ISO_GAMMA, closes SW4 and SW5, and connects the new positive and negative Gamma reference voltages to the corresponding Gamma reference buses.

[0100] Furthermore, after the new reference voltage is connected, U10 waits for the Gamma reference bus to stabilize; then, PRE is disabled, and SW6 and SW7 are disconnected to end the precharge; finally, OE_SRC is enabled again, and the source driver uses the new Gamma reference voltage to drive the next row with r+1. This sequence ensures that the precharge, library change, and new reference connection all occur within the window when the source output is disabled.

[0101] During the aforementioned library switching process, OE_SRC remains disabled from the source output disabled state until the new reference voltage is connected, the Gamma reference bus stabilizes, and the pre-charge ends; ISO_GAMMA remains invalid from the bus isolation state until the reference setup state ends; PRE remains valid from the pre-charge state, at least until the new reference voltage is connected and the bus stability determination is completed. Correspondingly, BANK_SEL toggles only when OE_SRC is disabled, ISO_GAMMA is isolated, and PRE is valid.

[0102] Optionally, the stability of the Gamma reference bus can be determined by a preset waiting time, or by a window comparator to determine whether the positive and negative Gamma reference buses have entered the corresponding target voltage windows. When a fixed waiting time is used, its duration can be determined based on the most unfavorable combination of buffer bandwidth, isolating switch on-resistance, pre-charge resistance, and bus equivalent capacitance. The two detection inputs of the window comparator are connected to the positive and negative Gamma reference buses, respectively; the corresponding target voltage windows are determined by the target positive Gamma reference voltage ±ΔVP and the target negative Gamma reference voltage ±ΔVN, respectively. A BUS_STABLE signal is generated when both detection results are within the corresponding target voltage window. The timeout counter starts when a new reference voltage is connected or pre-charge begins, and is cleared when BUS_STABLE is valid; if the system is still unstable after reaching the preset timeout value, the state machine maintains OE_SRC in the disabled state and re-enters the pre-charge state.

[0103] Optionally, U10 can be set with an establishment or stabilization wait timeout value. If stabilization is not achieved after the timeout value, U10 maintains OE_SRC in an inactive state, does not submit the next PAIR_COMMIT, and maintains the current fault state or returns to the precharge state to re-execute precharge, instead of directly restoring the source driver output. The fault protection can be implemented by an internal counter of the state machine, and is not required to be implemented within the state machine. Figure 2 An independent control device was added.

[0104] Furthermore, by using the same set of submitted parameters within a polarity pairing unit and generating corresponding reference voltages around VCOM_BUF using positive and negative Gamma generation circuits, the signed voltage-time accumulation in the same region within that polarity pairing unit can approach equilibrium. This equilibrium can be expressed as the absolute value of the signed residual not exceeding an allowable threshold εdc, where the signed residual is the algebraic sum of the products of the effective trans-voltage relative to the common voltage and the corresponding duration in each driving period. The allowable threshold can be determined based on the panel's DC residual specification.

[0105] Optionally, to reduce the pre-installation time of the shared digital-to-analog converter U2, U10 can only perform updates on column groups and Gamma binding points where the change in target code exceeds a preset threshold; for hold nodes where the change does not exceed the threshold, the existing voltage in the waiting library can be used. Regardless of whether a full update or a sparse update is used, LOAD_NEXT_DONE is valid after the required waiting hold nodes have been written.

[0106] Example 2: Dynamic Adjustment Method for Regional Penetration

[0107] This embodiment provides a method for dynamically adjusting the transmittance of a liquid crystal display screen area. This method can be executed by the display module and the area transmittance dynamic adjustment circuit described in Embodiment 1. See also... Figure 4 The method includes steps S101 to S107.

[0108] Step S101: Obtain the target transmittance parameters for the regions. Specifically, regions Z(r, c) are formed according to M row bands and N column groups, and the target transmittance parameters for each region during the corresponding display period are obtained based on image data and optional partition backlight driving intensity. The target transmittance parameters can be represented as normalized transmittance, transmittance level, or its corresponding calibration index.

[0109] Step S102: Generate Gamma binding point parameters for each column group. Specifically, based on the target penetration parameters of each region within the next row (r+1) and the panel calibration data, generate target codes for K Gamma binding points in N column groups, and address them according to the column group address COL_GROUP_ADDR and the binding point address BIND_ADDR.

[0110] Step S103 generates Gamma binding point parameters for each column group and latches them within the polarity pairing unit. Specifically, when the submission of the next set of region parameters is allowed, PAIR_COMMIT is enabled, and the target code generated in step S102 is latched by U1, ensuring that the same set of Gamma binding point parameters is used within the same complete positive and negative polarity pairing unit. It should be noted that step S103 adds a polarity pairing latching action compared to step S102, rather than repeatedly calculating the target code.

[0111] Step S104: Preload the next row with reference voltage into the standby holding library. While the current row with band r is outputting reference voltage from the working library, the target codes of the next row with band r+1 are sequentially sent to the shared digital-to-analog converter U2. The corresponding column group and Gamma binding point are selected by the analog demultiplexer U4, and the converted analog reference voltage is written into the standby holding library via LOAD_A or LOAD_B. After completing the required write of the standby holding nodes, LOAD_NEXT_DONE is generated.

[0112] Step S105: Determine whether the horizontal band scan has ended, polarity pairing has been completed, and pre-loading has been completed. Specifically, determine whether ROW_END, internal PAIR_DONE, and LOAD_NEXT_DONE are all valid. If at least one is invalid, maintain the current working library, continue outputting the current reference voltage, and wait for the switching condition; then execute step S105 again. If all three conditions are valid, proceed to step S106.

[0113] Step S106: Disable source output and precharge the Gamma reference bus. Specifically, first disable OE_SRC, then isolate ISO_GAMMA to stop the source driver output and disconnect SW4 and SW5 respectively; then enable PRE, close SW6 and SW7, and precharge the positive and negative Gamma reference buses to the levels corresponding to VPRE_P and VPRE_N through R3 and R4 respectively.

[0114] Step S107: Replace library, stabilize, and restore source output. Specifically, in the pre-charge state, toggle BANK_SEL to select the pre-installed holding library; wait for the reference voltage setup time tSET; enable ISO_GAMMA to connect the new positive and negative Gamma reference voltages to the corresponding Gamma reference buses; wait for the Gamma reference buses to stabilize; then disable PRE to end the pre-charge and enable OE_SRC to start the next row scan using the new reference voltage.

[0115] It is understood that the effective level in steps S106 and S107 can be configured in reverse according to the logic definition of the switching device and source driver interface used, as long as the action sequence of "disable source output - isolate Gamma bus - perform precharge - flip conversion library - wait for establishment - connect new reference voltage - wait for bus to stabilize - end precharge - restore source output" is maintained.

[0116] Furthermore, when scanning multiple line bands continuously, steps S104 to S107 are executed cyclically: after line band r+1 becomes the current line band, the original working library is converted into a standby library and used to preload the reference voltage of line band r+2, thereby forming a pipeline process in which the A / B holding libraries work alternately.

[0117] For example, when holding library A is the working library for row band r, holding library B pre-loads the reference voltage for row band r+1 according to the column group address and binding point address during row band r scanning. Once all three switching conditions are met and steps S106 and S107 are completed, holding library B becomes the working library for row band r+1, and holding library A becomes the standby library and begins pre-loading the reference voltage for row band r+2. For each library switch, PAIR_DONE and LOAD_NEXT_DONE are cleared upon completion to prevent the previous completion state from being reused in the next library switch.

[0118] In addition, when a frame ends or a reset occurs, the row band address, column group address, binding point address, polarity state counter and BANK_SEL can be restored to the preset initial state according to FRAME_SYNC or RESET_N, and the reference voltage loading of the initial working library is completed before the source driver output is restored.

[0119] Example 3: Collaborative Driving of Display Modules

[0120] This embodiment further illustrates... Figure 1 The diagram illustrates the synergistic relationship between the liquid crystal region transmittance and the partitioned backlight in the display module. After receiving image data, the timing controller generates a target transmittance parameter for region Z(r,c) and backlight driving parameters for one or more backlight partitions associated with that region. The region transmittance dynamic adjustment circuit updates the Gamma reference voltage of the source driver according to the target transmittance parameter, and the partitioned backlight driver adjusts the partitioned backlight according to the backlight driving parameters.

[0121] For example, but not limited to, when it is necessary to increase the brightness of a local bright area, the luminous intensity of the corresponding backlight zone can be increased, and the Gamma binding point reference voltage of the corresponding area can be set according to the target brightness and panel optical calibration results; when it is necessary to reduce the power consumption of a dark area, the luminous intensity of the corresponding backlight zone can be reduced, and the target transmittance parameters of that area can be redefined. Both control paths are based on FRAME_SYNC and the horizontal band scanning timing to ensure that the new Gamma reference voltage is switched before the corresponding horizontal band begins.

[0122] It should be noted that the mapping relationship between the partitioned backlight and the M×N liquid crystal area can be one-to-one, one-to-many, or many-to-one. The core of this invention lies in the pipelined pre-loading of the liquid crystal area reference voltage, polarity pairing locking, and boundary pre-charging and library replacement. The backlight diffusion model, the area boundary smoothing algorithm, and the specific image statistical methods do not constitute necessary limitations of this embodiment.

[0123] The circuit connections in Example 1, the method steps in Example 2, and the display module connection relationships in this example can be referenced to each other. Each control signal in the circuit can be generated by a dedicated logic circuit, a field-programmable gate array, the internal logic of a timing control chip, or a combination thereof. Analog buffers and analog switches can be integrated into the source driver chip, the timing control chip, or an independent reference voltage chip.

[0124] It should be pointed out that, Figure 1 The timing controller in the display module is a timing controller. Figure 2 The timing control unit U10 performs pre-installation, polarity pairing judgment, and inventory switching control functions. The timing control unit U10 can be set as an independent logic in the area penetration rate dynamic adjustment circuit, or it can be integrated into the module-level timing controller; when the two are integrated, they are still divided according to their functional connection relationship.

[0125] It should be noted that the terms "first", "second", "positive", "negative", "A", and "B" are used only to distinguish the corresponding devices, nodes, or states, and are not used to limit their absolute position or sequence; the term "connection" includes direct electrical connection as well as indirect electrical connection through intermediate devices that can achieve the same signal transmission function.

[0126] It should be noted that, unless contradictory, the technical features in the above embodiments can be combined with each other. All equivalent substitutions, improvements, or modifications made within the spirit and principles of this invention should fall within the protection scope of this invention.

Claims

1. A dynamic transmittance adjustment circuit for a liquid crystal display screen, applied to a liquid crystal display screen, the liquid crystal display screen comprising multiple row strips and multiple column groups, the multiple row strips and the multiple column groups intersecting to form multiple display areas, each column group corresponding to at least one Gamma binding point, characterized in that, The region transmittance dynamic adjustment circuit includes a reference voltage generation unit, a dual hold unit, a library selection unit, a positive and negative Gamma generation unit, a Gamma bus isolation and pre-charge unit, and a timing control unit. The reference voltage generation unit, dual hold unit, library selection unit, positive and negative Gamma generation unit, and Gamma bus isolation and precharge unit are connected in sequence. The Gamma bus isolation and precharge unit is connected to the positive Gamma reference input terminal and the negative Gamma reference input terminal of the source driver via the positive Gamma reference bus and the negative Gamma reference bus. The timing control unit is connected to the reference voltage generation unit, dual hold unit, library selection unit, Gamma bus isolation and precharge unit, and the source output enable terminal of the source driver, respectively. Under the control of the timing control unit, the same set of Gamma binding point parameters remain unchanged within the polarity pairing unit consisting of a positive polarity driving cycle and a negative polarity driving cycle; The two holding libraries of the dual holding unit alternately serve as the working library and the waiting library. During the period when the working library outputs the Gamma binding point reference voltage of the current row band, the reference voltage generation unit preloads the Gamma binding point reference voltage of the next row band into the waiting library according to the column group selection information and the binding point selection information. Only when the current row band scan ends, the polarity pairing unit completes, and the Gamma binding point reference voltage of the next row band is pre-loaded, the timing control unit sequentially disables the source driver output, disconnects the positive and negative Gamma generation unit from the positive and negative Gamma reference buses, pre-charges the positive and negative Gamma reference buses, switches the holding library, and connects the new positive and negative Gamma reference voltages to their respective Gamma reference buses after they are established. After the positive and negative Gamma reference buses stabilize, the precharge ends and the source driver output is restored.

2. The dynamic transmittance adjustment circuit for a liquid crystal display area according to claim 1, characterized in that, The reference voltage generation unit includes a target parameter latching unit, a shared digital-to-analog converter, a digital-to-analog converter output buffer, and an analog demultiplexer. The parameter input terminal of the target parameter latch unit receives the target parameter signal TARGET_CODE_CK, the latch control terminal receives the parameter submission signal PAIR_COMMIT, and the output terminal is connected to the digital input terminal of the shared digital-to-analog converter. The clock and update terminals of the shared digital-to-analog converter receive the digital-to-analog converter clock signal DAC_CLK and the digital-to-analog converter latch signal DAC_LATCH, respectively, and its analog output terminal is connected to the common analog input terminal of the analog demultiplexer through the digital-to-analog converter output buffer. The analog demultiplexer transmits the analog reference voltage output by the shared digital-to-analog converter to the write node of the corresponding column group and Gamma binding point according to the column group address COL_GROUP_ADDR and the binding point address BIND_ADDR.

3. The dynamic transmittance adjustment circuit for a liquid crystal display area according to claim 1, characterized in that, The dual hold unit is provided with a write node, a first sampling switch, a second sampling switch, a first hold capacitor, a second hold capacitor, a first hold buffer, and a second hold buffer for each Gamma binding point of each column group; The write node is connected to the first holding capacitor and the first holding buffer respectively through the first sampling switch, and is connected to the second holding capacitor and the second holding buffer respectively through the second sampling switch. The other ends of the first holding capacitor and the second holding capacitor are respectively connected to analog ground. The outputs of the first holding buffer and the second holding buffer are respectively connected to the two analog inputs of the library selection switch in the library selection unit; The first sampling switch and the second sampling switch are controlled by the first loading signal LOAD_A and the second loading signal LOAD_B, respectively, and the first loading signal LOAD_A and the second loading signal LOAD_B are not effective at the same time; the library selection switch is controlled by the library selection signal BANK_SEL, and adopts a switching method of disconnecting first and then turning on.

4. The dynamic transmittance adjustment circuit for a liquid crystal display area according to claim 1, characterized in that, The Gamma bus isolation and precharge unit includes a positive Gamma isolation switch, a negative Gamma isolation switch, a positive Gamma precharge switch, a negative Gamma precharge switch, a first precharge resistor, and a second precharge resistor. The positive Gamma isolation switch is connected between the positive Gamma output terminal of the positive and negative Gamma generation unit and the positive Gamma reference bus; The negative Gamma isolation switch is connected between the negative Gamma output terminal of the positive and negative Gamma generation unit and the negative Gamma reference bus; The positive precharge voltage terminal is connected to the positive Gamma reference bus through the first precharge resistor and the positive Gamma precharge switch, and the negative precharge voltage terminal is connected to the negative Gamma reference bus through the second precharge resistor and the negative Gamma precharge switch. The positive Gamma precharge switch and the negative Gamma precharge switch are controlled by the precharge control signal PRE.

5. The dynamic transmittance adjustment circuit for a liquid crystal display area according to claim 1, characterized in that, The timing control unit includes a Gamma bus stability detection unit and a timeout counter; The Gamma bus stability detection unit includes a window comparator, which detects whether the positive Gamma reference bus and the negative Gamma reference bus have entered the corresponding target voltage window. The timing control unit ends the precharge and resumes the source driver output only when both the positive Gamma reference bus and the negative Gamma reference bus enter the corresponding target voltage window; When the timeout counter reaches the preset timeout value and the positive Gamma reference bus or the negative Gamma reference bus does not enter the corresponding target voltage window, the timing control unit maintains the source driver in the output disabled state and re-executes the precharge.

6. The dynamic transmittance adjustment circuit for a liquid crystal display area according to claim 1, characterized in that, The timing control unit includes a polarity state counter, a column group counter, a binding point counter, and a state machine; The polarity state counter records the positive polarity drive completion state and negative polarity drive completion state corresponding to the same set of Gamma binding point parameters according to the polarity signal POL, and generates a polarity pairing completion flag when both completion states are valid. The column group counter and the binding point counter generate the column group selection information and the binding point selection information, and generate a pre-installation completion flag after the column group and Gamma binding point that need to be updated have been written. The state machine enters the database switching state only when the line band end flag, the polarity pairing completion flag, and the pre-installation completion flag are all valid; the polarity pairing completion flag and the pre-installation completion flag are cleared after a database switching is completed.

7. The dynamic transmittance adjustment circuit for a liquid crystal display area according to claim 1, characterized in that, During the library switching process, the timing control unit outputs the enable signal OE_SRC, the isolation control signal ISO_GAMMA, the precharge control signal PRE, and the library selection signal BANK_SEL. The source output enable signal OE_SRC remains disabled from the moment the source driver output is disabled until the precharge ends and the positive Gamma reference bus and the negative Gamma reference bus are stable. The isolation control signal ISO_GAMMA remains in an isolated state from the time the Gamma reference bus is isolated until a new positive Gamma reference voltage and negative Gamma reference voltage are established. The precharge control signal PRE remains valid from the start of precharge until the positive Gamma reference bus and the negative Gamma reference bus stabilize. The BANK_SEL signal toggles only when the source driver output is disabled, the Gamma reference bus is isolated, and the bus is in a precharge state.

8. A driving method for a liquid crystal display screen area transmittance dynamic adjustment circuit, applied to a liquid crystal display screen having multiple row strips and multiple column groups, wherein the multiple row strips and multiple column groups intersect to form multiple display areas, the area transmittance dynamic adjustment circuit is connected to a source driver, a positive Gamma reference bus, and a negative Gamma reference bus, and has two holding libraries that alternately serve as working libraries and standby libraries, characterized in that, include: S101, Obtain the target transmittance parameters for each display area; S102, Generate the Gamma binding point parameters for each column group based on the target penetration rate parameters; S103 ensures that the same set of Gamma binding point parameters remain unchanged within a polar pairing unit consisting of a positive polarity driving cycle and a negative polarity driving cycle. S104, during the output of the Gamma binding point reference voltage of the current row band in the working library, the Gamma binding point reference voltage of the next row band is pre-loaded into the standby library according to the column group selection information and the binding point selection information; S105, determine whether the current row band scan has ended, whether the polarity pairing unit has been completed, and whether the Gamma binding point reference voltage of the next row band has been pre-installed; if any condition is not met, maintain the working library output; if all three conditions are met, execute S106. S106, disable the source driver output, disconnect the connection between the positive Gamma reference voltage and the positive Gamma reference bus and the connection between the negative Gamma reference voltage and the negative Gamma reference bus respectively, and then precharge the positive Gamma reference bus and the negative Gamma reference bus. S107, switch the standby library to the new working library, after the new positive Gamma reference voltage and negative Gamma reference voltage are established, connect the new positive Gamma reference voltage and negative Gamma reference voltage to the positive Gamma reference bus and negative Gamma reference bus respectively, and end the precharge and restore the source driver output after the positive Gamma reference bus and negative Gamma reference bus are stable.

9. The driving method according to claim 8, characterized in that, In step S104, the Gamma binding point parameters of the next row are converted into analog reference voltages by a shared digital-to-analog converter, and the analog reference voltages are written sequentially to the holding nodes of the corresponding column group and Gamma binding point according to the column group address COL_GROUP_ADDR and the binding point address BIND_ADDR by an analog demultiplexer. After all the holding nodes that need to be updated have been written, a pre-loading completion flag LOAD_NEXT_DONE is generated. In step S105, the positive polarity drive completion state POS_DONE and the negative polarity drive completion state NEG_DONE are recorded according to the polarity signal POL, and a polarity pairing completion flag PAIR_DONE is generated when both the positive polarity drive completion state POS_DONE and the negative polarity drive completion state NEG_DONE correspond to the same set of Gamma binding point parameters. After step S107 is completed, the pre-installation completion flag LOAD_NEXT_DONE and the polarity pairing completion flag PAIR_DONE are cleared, and the original working library is set as the library to be used in the next round of pre-installation.

10. A display module, characterized in that, It includes a timing controller, a source driver, a gate driver, a zone backlight driver, a zone backlight, a zone liquid crystal panel, and a dynamic adjustment circuit for the zone transmittance of the liquid crystal display screen according to any one of claims 1 to 7. The timing controller is connected to the regional transmittance dynamic adjustment circuit, the source driver, the gate driver, and the partition backlight driver, respectively. The region transmittance dynamic adjustment circuit is connected to the positive Gamma reference input terminal, the negative Gamma reference input terminal, and the source output enable terminal of the source driver. The partition backlight driver is connected to the partition backlight, and the backlight partitions of the partition backlight have a preset mapping relationship with multiple display areas of the regional liquid crystal panel; The timing controller generates target transmittance parameters and backlight driving parameters for each display area based on image data, and synchronizes the Gamma reference voltage generated by the regional transmittance dynamic adjustment circuit, the data output of the source driver, the horizontal band scanning of the gate driver, and the emission timing of the partitioned backlight.

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