Silicon-two-dimensional hetero-embedded dynamic random access memory array and read-write refresh method

Abstract

The application discloses a silicon-two-dimensional hetero-embedded dynamic random memory array and a read-write refreshing method. In the array, each memory unit is composed of a two-dimensional semiconductor write transistor and a silicon read transistor. The source of the write transistor is connected with the gate of the read transistor to form a floating storage node, and the data is represented by the storage state of the node charge. The array is externally provided with a row decoding and word line driving unit, a write bit line driving unit, and a read-out amplification and write-back unit. When writing, the selected row write word line is added with an opening voltage, and the unselected row is added with a negative voltage to suppress crosstalk. The read-out is non-destructive, and the read bit line current is compared with a reference current to determine the data. The off-state leakage of the two-dimensional write transistor is low, the node charge retention time reaches the order of thousands of seconds, the refreshing period is relaxed to the order of seconds, and the refreshing power consumption is greatly reduced. The application has long retention time, large read-out margin and low refreshing power consumption, and is suitable for processor embedded cache.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory technology, and more specifically, to a silicon-two-dimensional heterogeneous embedded dynamic random access memory array and a read / write refresh method. Background Technology

[0002] The cache in a processor is used to temporarily store data that will be used soon. The larger the cache, the fewer times the processor accesses main memory, and the higher the overall performance of the system. Currently, on-chip caches mainly use six-transistor static random access memory (SRAM). Its disadvantages are large cell area, high static power consumption, and difficulty in further increasing the cache capacity. Although traditional dynamic random access memory (DRAM) has a small cell area, it requires a deep slot or stacked capacitors next to each cell, which is incompatible with the process and logic circuits. In addition, it must be completely refreshed every 64 milliseconds, resulting in high power consumption.

[0003] The dual-transistor gain cell is another dynamic memory scheme: the write transistor is responsible for writing, the gate capacitance of the read transistor acts as the storage capacitor, and the read transistor is responsible for amplification and readout. It requires no additional capacitors, does not corrupt data during readout, and is compatible with logic processes. However, this scheme faces the following three technical bottlenecks before it can be put into practical use:

[0004] First, it is difficult to achieve both retention time and driving capability. If both transistors are made of silicon, the write transistor has a large leakage current after being turned off, and the node charge is lost in a few milliseconds, resulting in a short retention time. If both transistors are made of two-dimensional semiconductors, the leakage current is small, but the conduction current that two-dimensional materials can currently provide is too small, resulting in a weak read signal, which is difficult to drive the peripheral circuit to quickly determine the data.

[0005] Second, there is the issue of write crosstalk. Multiple cells in the same column of the array share a single write bit line. When writing to a certain row, although the write transistors of other cells in the same column are not turned on, their weak leakage current will still gradually change the charge on their respective memory nodes. The larger the array, the more obvious the accumulated crosstalk becomes.

[0006] Third, there is a lack of operating methods that match the characteristics of the devices. Traditional dynamic memory refreshes at a uniform 64-millisecond cycle, which is designed for millisecond-level retention times. For new cells with retention times on the order of thousands of seconds, operating in the old way will cause a lot of unnecessary refreshes, wasting power.

[0007] Therefore, a new type of memory array and its operation method is needed that can take advantage of the near-zero leakage of two-dimensional semiconductor transistors to obtain long hold time, and take advantage of the large conduction current of silicon transistors to obtain strong read signals, while solving the problems of write crosstalk and refresh power consumption. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a silicon-two-dimensional heterogeneous embedded dynamic random access memory array and a read / write refresh method.

[0009] To achieve the above objectives, the present invention adopts the following technical solution:

[0010] A silicon-based two-dimensional heterogeneous embedded dynamic random access memory array includes:

[0011] A memory array includes multiple memory cells arranged in multiple rows and columns. Each memory cell consists of a write transistor and a read transistor. The source of the write transistor is electrically connected to the gate of the read transistor, and the connection point between the two forms a floating memory node. The memory node is held by the gate capacitance of the read transistor and the stored data is characterized by the charge storage state. The write transistor is a field-effect transistor with a two-dimensional semiconductor channel layer, which is a single-layer or few-layer molybdenum disulfide channel layer. The read transistor is a field-effect transistor with a top silicon channel layer on a silicon-on-insulator substrate. The read transistor is fabricated in the top silicon layer of the silicon-on-insulator substrate. The write transistor is vertically stacked and integrated above the read transistor. An interlayer dielectric layer is provided between the read transistor and the write transistor. The memory node achieves electrical connection between the source of the write transistor and the gate of the read transistor through interconnect vias passing through the interlayer dielectric layer.

[0012] The row decoding and word line driving unit connects the write word lines and read word lines of each row, and is used to provide an enable voltage to the write word lines of the selected row and a negative disable voltage to the write word lines of the unselected row during a write operation.

[0013] The write bit line driving unit connects the write bit lines of each column and is used to apply a level corresponding to the written data to the write bit lines during a write operation.

[0014] The read amplification and write-back unit connects the read bit lines of each column and is used to compare the current on the read bit lines with the reference current during the read operation to determine the stored data.

[0015] Furthermore, it also includes a timing control unit and a refresh control unit. The timing control unit is used to generate the operation timing for each stage of writing, holding, reading and refreshing. The refresh control unit is used to control the read amplification and write-back units to perform read-write-back refresh operations on each row in sequence according to the refresh cycle.

[0016] Furthermore, the refresh cycle of the refresh control unit is on the order of seconds, and the charge retention time of the storage node is on the order of kiloseconds.

[0017] Furthermore, the gate of the write transistor is connected to the write word line, the drain of the write transistor is connected to the write bit line, the source of the write transistor is connected to the gate of the read transistor to form a storage node, the drain of the read transistor is connected to the read bit line, and the source of the read transistor is connected to the read word line.

[0018] Furthermore, the read amplification and write-back unit stabilizes the read bit line at a fixed voltage and compares the channel current flowing through the read transistor with a preset reference current. If the channel current is greater than the reference current, it is determined to be a high level; otherwise, it is determined to be a low level.

[0019] Furthermore, the write lines and read lines of all memory cells in the same row are interconnected, and the write bit lines and read bit lines of all memory cells in the same column are interconnected.

[0020] Furthermore, the write transistor is vertically stacked above the read transistor using a low-temperature transfer or back-end compatible process.

[0021] Furthermore, the minimum area of ​​the storage cell is 8F. 2 , where F is the process feature dimension.

[0022] This invention also provides a read / write refresh method for a silicon-two-dimensional heterogeneous embedded dynamic random access memory array, comprising:

[0023] Writing steps: Apply an enable voltage to the write word lines of the selected row, apply a negative disable voltage to the write word lines of the remaining unselected rows, and apply a level corresponding to the data to be written to each column's write bit lines, so that each memory cell in the selected row charges or discharges the memory node according to the write bit line level.

[0024] Retention steps: All word lines and bit lines are set to the off level, and the storage node charge is retained through the off-state leakage of the write transistor;

[0025] Reading steps: Apply a read strobe voltage to the read word line of the selected row, keep the read bit lines of each column at a fixed voltage, compare the channel current of each column read transistor with the reference current to determine the stored data, and keep the write word line at the off level during the read process;

[0026] Refresh steps: Perform the read steps sequentially on the target row according to the refresh cycle, and write the judgment result back to the storage node through the write bit line and write word line pulses.

[0027] The beneficial effects of this invention are:

[0028] 1. This invention assigns the write and read functions to write transistors and read transistors respectively. A two-dimensional semiconductor material serves as the channel for the write transistor, and silicon as the channel for the read transistor. The ultra-low off-state leakage current of the two-dimensional material achieves kilosecond-level charge retention, while the high mobility of silicon achieves a read current margin of tens of microamps per micrometer. The two materials are heterogeneously integrated in the same memory cell, each performing its specific function, overcoming the dual technical bottlenecks of short retention time in all-silicon solutions and weak read signals in all-two-dimensional solutions.

[0029] 2. The present invention applies a negative shutdown voltage to the write word lines of unselected rows, so that the write transistors of unselected memory cells are in a deep shutdown state, further reducing leakage current and keeping crosstalk controllable when the array size is expanded.

[0030] 3. Based on the charge retention characteristics at the kilometer level, the refresh cycle is relaxed from the traditional 64 milliseconds to the second level, and the refresh frequency is reduced by more than three orders of magnitude; at the same time, the read is non-destructive, and daily read operations do not require write-back, further reducing power consumption.

[0031] 4. The peripheral circuit of this invention is manufactured using silicon-based technology, and the write transistor is vertically integrated above the read transistor through a back-end compatible process, which is compatible with the existing processor chip manufacturing process. Attached Figure Description

[0032] Figure 1 This is a structural block diagram of a silicon-two-dimensional heterogeneous embedded dynamic random access memory array in this embodiment;

[0033] Figure 2 This is a circuit structure diagram of a storage unit in this embodiment;

[0034] Figure 3 This is a diagram showing a stacked structure of the storage unit in this embodiment;

[0035] Figure 4 This is a circuit diagram of a storage array in this embodiment.

[0036] Reference numerals: 1. Memory array; 2. Row decoding and word line driving unit; 3. Write bit line driving unit; 4. Read amplification and write-back unit; 5. Timing control unit; 6. Refresh control unit. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] Example: A silicon-based two-dimensional heterogeneous embedded dynamic random access memory array, such as Figure 1 As shown, it includes a storage array 1, a row decoding and word line driving unit 2, a write bit line driving unit 3, a read amplification and write-back unit 4, a timing control unit 5, and a refresh control unit 6.

[0039] Storage array 1 comprises multiple storage units arranged in a multi-row, multi-column configuration. For example... Figure 2 As shown, each memory cell consists of a write transistor TW and a read transistor TR. The channel layer of the write transistor TW uses a single-layer or few-layer molybdenum disulfide. This two-dimensional semiconductor material has extremely low off-state leakage current at atomic-level thickness, which can effectively suppress charge loss. The read transistor TR uses a silicon-based field-effect transistor. Taking advantage of the high carrier mobility of silicon, a large on-state drive current and signal amplification capability can be obtained.

[0040] The source of the write transistor TW is electrically connected to the gate of the read transistor TR. The connection point between the two forms a floating memory node SN. This memory node utilizes the gate capacitance of the read transistor TR to store charge, and its equivalent capacitance is as follows: Figure 1 As shown by the dashed line, the charge state of the storage node SN determines the stored data. When it is in a high-level state (charged), it corresponds to the data "1", and when it is in a low-level state (discharged), it corresponds to the data "0". During the read operation, the potential of the storage node SN directly controls the conduction level of the read transistor TR, converting the amount of charge on the storage node into the magnitude of the channel current output of the read transistor TR, thereby achieving gain readout.

[0041] Furthermore, such as Figure 2 As shown, the gate of the write transistor TW is connected to the write word line WWL, and the drain is connected to the write bit line WBL. The drain of the read transistor TR is connected to the read bit line RBL, and the source is connected to the read word line RWL. It should be noted that the source and drain of the write transistor TW are defined according to the direction of the current during writing. During writing, charge flows from the write bit line WBL through the write transistor TW to the memory node SN. Therefore, the end connected to the memory node SN is the source, and the end connected to the write bit line WBL is the drain.

[0042] like Figure 3As shown, this embodiment employs a vertical stacked structure to achieve high-density integration of memory cells. The read transistor TR is fabricated in the top silicon layer of a silicon-on-insulator substrate, which, from bottom to top, consists of a bottom silicon layer, a buried oxide layer (BOX), and a top silicon layer. The molybdenum disulfide channel of the write transistor TW is vertically integrated directly above the read transistor TR using a low-temperature transfer process or a back-end compatible process, with an interlayer dielectric layer (ILD) between them. The connection relationship of the memory nodes SN is as follows: the gate of the read transistor TR is led out through a lower metal trace and electrically connected to the source of the write transistor TW via an interconnecting via passing through the interlayer dielectric layer (ILD). This vertical stacked structure ensures that the footprint of the memory cell is determined solely by the size of the read transistor TR, with a minimum size of 8F. 2 Where F is the process feature size, and this process step is compatible with standard complementary metal-oxide-semiconductor logic processes and can be directly embedded into existing processor chip manufacturing processes.

[0043] The interconnection of storage array 1 is as follows Figure 4 As shown, taking a 3x3 array as an example, all memory cells in the same row share the same write line and the same read line. Specifically: in row 0, the write lines WWL0 and read lines RWL0 of all memory cells are interconnected; in row 1, the write lines WWL1 and read lines RWL1 of all memory cells are interconnected; and in row 2, the write lines WWL2 and read lines RWL2 of all memory cells are interconnected.

[0044] All memory cells in the same column share the same write bit line and the same read bit line. Specifically: the write bit lines WBL0 and read bit lines RBL0 of all memory cells in column 0 are interconnected; the write bit lines WBL1 and read bit lines RBL1 of all memory cells in column 1 are interconnected; and the write bit lines WBL2 and read bit lines RBL2 of all memory cells in column 2 are interconnected.

[0045] The interconnection of rows and columns constitutes the complete addressing and data read / write path of storage array 1.

[0046] Furthermore, the output of the row decoding and word line driving unit 2 is connected to the write word line (WWL) and read word line (RWL) of each row, respectively. This unit decodes the externally input row address to select the word line corresponding to the target row. During the write operation, the row decoding and word line driving unit 2 provides an enable voltage (e.g., 2V) to the write word line of the selected row, while simultaneously providing a negative turn-off voltage (e.g., -1V) to the write word lines of all unselected rows. This negative turn-off voltage puts the write transistor TW of the unselected memory cell in a deeply turned-off state, further reducing its leakage current and effectively suppressing write crosstalk. During the read operation, this unit applies a read strobe voltage to the read word line of the selected row.

[0047] Furthermore, the output of the write bitline driver unit 3 is connected to the write bitlines of each column. During the write operation, the write bitline driver unit 3 applies a corresponding level to each column of write bitlines according to the data to be written: a high level is provided when writing data "1", and a low level is provided when writing data "0". After the write operation is completed, the write bitline driver unit 3 restores all write bitlines to the off level, turns off the write transistor TW, and cuts off the leakage path between the memory node SN and the write bitlines.

[0048] Furthermore, the input terminals of the read amplification and write-back unit 4 are connected to the read bit lines of each column. During the read operation, this unit first stabilizes the read bit lines at a fixed voltage, then detects the channel current flowing through the read transistor TR, and compares this current with a preset reference current: if the channel current is greater than the reference current, the stored data is determined to be "1", which is a high level; otherwise, it is determined to be "0", which is a low level. In this embodiment, since the read transistor TR uses a silicon channel, its on-state drive current is large, and the difference in read current corresponding to data "1" and data "0" can reach 35 microamps per micrometer, and the determination process can be completed within 5 nanoseconds. When a write-back operation needs to be performed (e.g., during the refresh process), this unit converts the determination result into a corresponding level signal to drive the write bit line, and, in conjunction with the write word line pulse, rewrites the data into the storage node.

[0049] Furthermore, the timing control unit 5 is used to generate operation timing signals for each stage of writing, holding, reading and refreshing according to external instructions, and to specify the level switching order and duration of each word line and bit line.

[0050] Furthermore, the refresh control unit 6 initiates refresh requests according to a preset refresh cycle, controlling the read amplification and write-back unit 4 to sequentially perform read-write-back refresh operations on each row of the memory array 1. Because the write transistor TW has extremely low off-state leakage current, the charge retention time of the memory node SN can reach over 6000 seconds, thus the refresh cycle can be set to the second level (e.g., 2 seconds). Compared to the 64-millisecond refresh cycle of traditional dynamic memory, the refresh frequency is reduced by more than three orders of magnitude, and refresh power consumption is significantly reduced.

[0051] This embodiment also provides a read / write refresh method for a silicon-two-dimensional heterogeneous embedded dynamic random access memory array, including:

[0052] Writing steps: Apply an enable voltage to the write word lines of the selected row, apply a negative disable voltage to the write word lines of the remaining unselected rows, and apply a level corresponding to the data to be written to each column's write bit lines, so that each memory cell in the selected row charges or discharges the memory node according to the write bit line level.

[0053] Specifically, such as Figure 4As shown, taking writing data to row 0 as an example, row decoding and word line driving unit 2 raises the level of write word line WWL0 to the turn-on voltage (e.g., 2V), while keeping the levels of other write word lines WWL1 and WWL2 at negative turn-off voltages (e.g., -1V). Write bit line driving unit 3 sets each column of write bit lines WBL0-WBL2 to a high or low level according to the data to be written. The write transistor TW in each memory cell of row 0 is turned on because its gate receives the turn-on voltage. The level signal on the write bit line charges or discharges the memory node SN through the write transistor TW, and the write pulse width can be as short as 5 nanoseconds. After writing is completed, the level of WWL0 falls back to the negative turn-off voltage, the write transistor TW is turned off, and the memory node SN enters a floating hold state. At this time, the write transistor TW of the unselected row memory cell in the same column is in a deeply turned-off state because its gate voltage is -1V, and the charge of its memory node SN is not affected by the current write operation.

[0054] Reading steps: Apply a read strobe voltage to the read word line of the selected row, keep the read bit lines of each column at a fixed voltage, compare the channel current of each column read transistor TR with the reference current to determine the stored data, and keep the write word line at the off level during the read process.

[0055] Specifically, such as Figure 4 As shown, taking the reading of row 0 data as an example, row decoding and word line driving unit 2 sets the read word line RWL0 to the read gate voltage, while the remaining read word lines RWL1 and RWL2 remain off. Read amplification and write-back unit 4 maintains each column of read bit lines RBL0-RBL2 at a fixed voltage and detects the channel current of each column of read transistors TR. For memory cells storing "1" data, memory node SN is at a high potential, read transistor TR is fully turned on, and the channel current is large; for memory cells storing "0" data, memory node SN is at a low potential, read transistor TR is not fully turned on, and the channel current is small. By comparing the detected channel current with the reference current, the stored data of each cell can be determined. The determination process can be completed within 5 nanoseconds. During the read operation, write word lines WWL0-WWL2 are all maintained at a negative off voltage, and the charge of memory node SN is unaffected. Therefore, the read operation is non-destructive, and no write-back is required after a normal read operation.

[0056] Retention Procedure: All word lines and bit lines are set to the off level, and the storage node charge is retained by the off-state leakage current of the write transistor TW.

[0057] Specifically, when the array is not performing read / write operations, all word lines and bit lines are at the off level. The charge on the memory node SN is slowly dissipated only through the off-state leakage current of the write transistor TW. Because the write transistor TW uses a two-dimensional semiconductor material as its channel, its off-state leakage current is extremely low, and the charge retention time of the memory node SN can reach more than 6000 seconds.

[0058] Refresh steps: Perform the read steps sequentially on the target row according to the refresh cycle, and write the judgment result back to the storage node through the write bit line and write word line pulses.

[0059] Specifically, the refresh control unit 6 initiates a refresh request according to a second-level refresh cycle (e.g., 2 seconds). After arbitration with external access operations, it performs a refresh operation on the target row. The specific process of the refresh operation is as follows: First, the data of each memory cell in the target row is detected according to the read steps, and the read amplification and write-back unit 4 completes the data determination; then, the level signal corresponding to the determination result is driven to the write bit lines of each column, and an enable pulse is applied to the write word line of the target row to rewrite the data into the memory node; finally, the write word line is restored to the off level, and the refresh address is incremented to the next row. Since the refresh cycle is in the second range, compared with the 64-millisecond unified refresh mechanism of traditional dynamic memory, the refresh frequency is reduced by more than three orders of magnitude, and the refresh power consumption is significantly reduced.

[0060] Through the coordinated operation of the above-described write, read, hold, and refresh steps, the silicon-based two-dimensional heterogeneous embedded dynamic random access memory array of this embodiment achieves 8F... 2 While achieving high-density integration, it also features a charge retention time of kiloseconds and a readout current margin of tens of microamps per micrometer, making it suitable for applications involving on-chip L3 or L4 caches in processors.

[0061] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A silicon-two-dimensional heterogeneous embedded dynamic random access memory array, characterized in that, include: The storage array (1) includes multiple storage cells arranged in multiple rows and columns. Each storage cell consists of a write transistor and a read transistor. The source of the write transistor is electrically connected to the gate of the read transistor. The connection point of the two transistors forms a floating storage node. The storage node is held by the gate capacitance of the read transistor and the stored data is characterized by the charge storage state. The write transistor is a field-effect transistor with a two-dimensional semiconductor channel layer, which is a single-layer or few-layer molybdenum disulfide channel layer. The read transistor is a field-effect transistor with a silicon-on-insulator substrate top silicon channel layer. The read transistor is fabricated in the top silicon layer of a silicon-on-insulator substrate, and the write transistor is vertically stacked and integrated above the read transistor. An interlayer dielectric layer is provided between the read transistor and the write transistor. The memory node achieves electrical connection between the source of the write transistor and the gate of the read transistor through interconnect vias passing through the interlayer dielectric layer. The row decoding and word line driving unit (2) connects the write word line and read word line of each row and is used to provide an enable voltage to the write word line of the selected row and a negative turn-off voltage to the write word line of the unselected row during the write operation. Write bit line driving unit (3) connects the write bit lines of each column and is used to apply the level corresponding to the written data to the write bit lines during the write operation; The read amplification and write-back unit (4) connects the read bit lines of each column and is used to compare the current on the read bit lines with the reference current during the read operation to determine the stored data.

2. The silicon-two-dimensional heterogeneous embedded dynamic random access memory array according to claim 1, characterized in that, It also includes a timing control unit (5) and a refresh control unit (6). The timing control unit (5) is used to generate the operation timing for each stage of writing, holding, reading and refreshing. The refresh control unit (6) is used to control the read amplification and write-back unit (4) to perform read-write-back refresh operations on each row in sequence according to the refresh cycle.

3. The silicon-two-dimensional heterogeneous embedded dynamic random access memory array according to claim 2, characterized in that, The refresh control unit (6) has a refresh cycle in the order of seconds, and the charge retention time of the storage node is in the order of kiloseconds.

4. The silicon-two-dimensional heterogeneous embedded dynamic random access memory array according to claim 1, characterized in that, The gate of the write transistor is connected to the write word line, the drain of the write transistor is connected to the write bit line, the source of the write transistor is connected to the gate of the read transistor to form a storage node, the drain of the read transistor is connected to the read bit line, and the source of the read transistor is connected to the read word line.

5. The silicon-two-dimensional heterogeneous embedded dynamic random access memory array according to claim 1, characterized in that, The read amplification and write-back unit (4) stabilizes the read bit line at a fixed voltage and compares the channel current flowing through the read transistor with a preset reference current. If the channel current is greater than the reference current, it is determined to be a high level; otherwise, it is determined to be a low level.

6. The silicon-two-dimensional heterogeneous embedded dynamic random access memory array according to claim 1, characterized in that, Write lines and read lines of all memory cells in the same row are interconnected, and write lines and read lines of all memory cells in the same column are interconnected.

7. The silicon-two-dimensional heterogeneous embedded dynamic random access memory array according to claim 1, characterized in that, The write transistor is vertically stacked above the read transistor using a low-temperature transfer or back-end compatible process.

8. The silicon-two-dimensional heterogeneous embedded dynamic random access memory array according to claim 1, characterized in that, The minimum area of ​​the storage unit is 8F. 2 , where F is the process feature dimension.

9. A read / write refresh method for a silicon-two-dimensional heterogeneous embedded dynamic random access memory array as described in any one of claims 1-8, characterized in that, include: Writing steps: Apply an enable voltage to the write word lines of the selected row, apply a negative disable voltage to the write word lines of the remaining unselected rows, and apply a level corresponding to the data to be written to each column's write bit lines, so that each memory cell in the selected row charges or discharges the memory node according to the write bit line level. Retention steps: All word lines and bit lines are set to the off level, and the storage node charge is retained through the off-state leakage of the write transistor; Reading steps: Apply a read strobe voltage to the read word line of the selected row, keep the read bit lines of each column at a fixed voltage, compare the channel current of each column read transistor with the reference current to determine the stored data, and keep the write word line at the off level during the read process; Refresh steps: Perform the read steps sequentially on the target row according to the refresh cycle, and write the judgment result back to the storage node through the write bit line and write word line pulses.

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