Method and apparatus for reconstructing a failure bitmap of a dram memory array and computer device

Abstract

The application relates to a DRAM storage array failure bitmap reconstruction method and device and computer equipment, and realizes the unity of sampling efficiency, detection completeness and reconstruction accuracy in DRAM storage array testing through a closed-loop architecture based on physical semantic dictionary sparse reconstruction, which is realized through structured coarse sampling, multi-dimensional abnormal score evaluation and adaptive multi-resolution refinement. The application guarantees that each row and each column has a sampling point through the cooperation of the sampling starting offset staggered distribution of the storage body row and the row and column sampling step length, and provides a deterministic detection basis for whole row and whole column failure. On this basis, the multi-dimensional abnormal score classifies the sampling area, and adaptive multi-resolution refinement sampling is performed, so that the sampling budget is preferentially allocated to the suspicious area, the effective sampling rate is reduced, and large-area cluster failure is avoided. Finally, the failure bitmap is reconstructed by means of the physical semantic dictionary sparse reconstruction, and a high-precision reconstruction result meeting the redundancy repair requirement is obtained at a sampling cost far lower than that of full testing.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory testing technology, and in particular to a method, apparatus, computer device, computer-readable storage medium, and computer program product for reconstructing a failure bitmap of a DRAM memory array. Background Technology

[0002] With the continuous miniaturization of semiconductor manufacturing processes, DDR5 SDRAM memory has fully entered the mass production stage of high frequency, large capacity, and high density. In this process, mass production testing of DRAM (Dynamic Random Access Memory) chips faces a fundamental contradiction between test coverage and test cost. On the one hand, in industrial practice, to ensure the data retention and read / write correctness of billions or even tens of billions of memory cells, it is necessary to perform multi-step March algorithms (a type of test algorithm specifically used for fault detection in memory such as DRAM and SRAM, such as March C-, March LR, etc.) on each cell. Each cell is accessed 6 to 14 times in the complete test process. On the other hand, test time directly determines manufacturing cost. With the exponential growth of DRAM capacity, if traditional linear test methodologies are used, test time will increase to an unacceptable level, severely restricting production capacity and yield. It is evident that while the traditional full March algorithm test has high coverage, its time complexity is O(n), the test time increases linearly with the capacity, and it can only provide binary pass / fail results, which cannot assist in root cause analysis and lacks dynamic adjustment capabilities.

[0003] To reduce the amount of test data, the industry has proposed a BIST (Built-In Self-Test) compression scheme based on MISR (Multiple-Input Signature Register) signatures. This scheme integrates a response compressor inside the chip to compress millions of bits of test responses into a fixed-length signature value of 16-64 bits. While this scheme reduces reliance on external ATE (Automatic Test Equipment) through signature compression, the compression process is irreversible, resulting in the complete loss of failure location information and making subsequent redundant repairs impossible.

[0004] The academic community has further explored the application of general compressed sensing (CS) theory to failure bitmap reconstruction in IC testing. This theory states that if a signal is sparsity in a certain transform domain, it can be accurately reconstructed from random measurements at a rate far less than the Nyquist sampling rate. However, directly applying the general CS framework to DRAM mass production testing has three fundamental drawbacks: First, the random sampling matrix ignores the physical access constraints of DRAM, and the pre-charging and row activation overhead caused by random jumps negates the sampling advantage; second, general CS provides probabilistic recovery guarantees, which cannot meet the stringent requirements of deterministic failure detection control in mass production scenarios; third, the sparse basis used in general CS (such as DCT basis, wavelet basis) is a general mathematical transformation, not designed for DRAM physical failure mechanisms (such as row failures caused by word line open circuits, column failures caused by bit line leakage, and cluster failures caused by silicon defects), lacking the ability to perceive the spatial structure of DRAM failure modes.

[0005] In summary, traditional DRAM testing techniques cannot achieve a balance between testing efficiency, failure location accuracy, and physical structure compatibility. Therefore, there is an urgent need for a new testing method that can take into account testing efficiency, physical constraints, and deterministic detection guarantees. Summary of the Invention

[0006] Therefore, it is necessary to provide a DRAM memory array failure bitmap reconstruction method, apparatus, computer equipment, computer-readable storage medium, and computer program product to address the above-mentioned technical problems.

[0007] In a first aspect, this application provides a method for reconstructing a failure bitmap of a DRAM memory array, the method comprising: A structured sampling matrix is ​​configured based on the physical hierarchy of the DRAM memory array to perform at least one round of structured coarse sampling on the DRAM memory array to obtain coarse sampling results. The physical hierarchy of the DRAM memory array includes four levels: memory bank, row, column, and memory subarray. The structured sampling matrix includes a first sampling step size in the row direction, a second sampling step size in the column direction, and a row sampling start offset configured for each memory bank. The row sampling start offset makes the sampling rows of different memory banks staggered in the row address space. The first sampling step size and the second sampling step size ensure that there is at least one sampling point in each row and each column of the DRAM memory array. Based on the coarse sampling results, calculate the multidimensional anomaly score for each predefined sampling region in the DRAM storage array; Based on the multidimensional anomaly score, multi-resolution refined sampling is adaptively performed on the sampling region to obtain multi-resolution sampling results; Based on a pre-trained physical semantic dictionary, sparse reconstruction is performed on the multi-resolution sampling results to obtain the failure bitmap of the DRAM memory array.

[0008] In one embodiment, the structured sampling matrix further includes a column offset parameter, which defines the starting position of the column sampling point for each sampled row. The column offset parameter is generated based on the number of the memory bank and the row address of the sampled row, such that the starting positions of the column sampling points of different sampled rows within the same memory bank are offset along the column direction, and the starting positions of the column sampling points between different memory banks are staggered along the column direction.

[0009] In one embodiment, the multidimensional anomaly score is a weighted sum of the density anomaly score, pattern anomaly score, context anomaly score, and edge vulnerability factor of the corresponding sampling region; The density anomaly fraction is: ,in, For the first Density anomaly score of each sampling region and These represent the mean and standard deviation of the failure counts, respectively, obtained from coarse sampling on the reference chip. For the first Failure count for each sampling area; The abnormality score of the pattern is: , in, For the first Pattern anomaly score for each sampling region For the first Row alignment of each sampling region For the first Column alignment of each sampling region For the first Clustering coefficients for each sampled region; The context anomaly score is: ,in, For the first Context anomaly score for each sampled region Indicates the first Empirical failure distribution of each sampling region Indicates the first The arithmetic mean of the failure distributions of the neighboring sampling regions of each sampling region; The edge vulnerability factor is: ,in, For the first Edge fragility factor of each sampling region Indicates the first The shortest distance from the center of each sampling region to the edge of the chip. Represents the attenuation constant. This represents the bias boundary weighting coefficient.

[0010] In one embodiment, the step of adaptively performing multi-resolution refinement sampling on the sampling region based on the multidimensional anomaly score to obtain a multi-resolution sampling result includes: For any of the sampling regions, if the multidimensional anomaly score is determined to be less than the first score threshold, the sampling region is determined to be a normal region, and the refined sampling is terminated. If the multidimensional anomaly score is determined to be greater than or equal to the first score threshold and less than or equal to the second score threshold, the sampling region is determined to be a suspected anomaly region; quadtree refinement sampling is performed on the suspected anomaly region a preset number of times to obtain the multi-resolution sampling result of the suspected anomaly region; the second score threshold is greater than the first score threshold; If the multidimensional anomaly score is determined to be greater than the second score threshold, the sampling region is determined to be an anomaly region. Quadtree refinement sampling is recursively performed on the anomaly region until the minimum resolution is reached, and the multi-resolution sampling result of the anomaly region is obtained.

[0011] In one embodiment, after recursively performing quadtree thinning sampling on the abnormal region until the minimum resolution is reached, the method further includes: If the system is still abnormal after reaching the minimum resolution, a full scan is performed to obtain the full scan results. Based on the full scan results, the multi-resolution sampling results of the abnormal region are determined.

[0012] In one embodiment, the recursive quadtree thinning sampling of the abnormal region until the minimum resolution is reached includes: The abnormal region is recursively divided using a quadtree structure to obtain corresponding sub-regions; For the currently divided sub-region, sampling is performed with half the row sampling step size of the corresponding parent region as the new row sampling step size and half the column sampling step size of the corresponding parent region as the new column sampling step size, and the multidimensional anomaly score of the sub-region is calculated. The process is recursively iterated based on the multidimensional anomaly scores of the sub-regions until the minimum resolution is reached.

[0013] In one embodiment, the physical semantic dictionary includes a plurality of dictionary atoms, each dictionary atom corresponding to a physical failure mode of a DRAM storage array; The pre-trained physical semantic dictionary is used to sparsely reconstruct the multi-resolution sampling results to obtain the failure bitmap of the DRAM storage array, including: The sampling area is divided into multiple regions to be reconstructed based on a preset row and column size, and the hierarchical status of each region to be reconstructed is determined. Based on the hierarchical status of the region to be reconstructed, a corresponding subset of the dictionary is determined from the physical semantic dictionary; Based on the dictionary subset and local sampling matrix of the region to be reconstructed, the failure bitmap of the region to be reconstructed is sparsely reconstructed to obtain the binary failure bitmap of the region to be reconstructed. By merging the binary failure bitmaps of all regions to be rebuilt in the DRAM memory array, a complete failure bitmap of the DRAM memory array is obtained.

[0014] In one embodiment, the sparse reconstruction is achieved by solving the following LASSO problem: in, This refers to the multi-resolution sampling observation vector of the region to be reconstructed. This is the local sampling matrix of the region to be reconstructed. This is a subset of the dictionary corresponding to the region to be reconstructed. The regularization coefficient is used. This represents the sparse coefficient vector obtained from the reconstruction. Representing vectors The L1 norm.

[0015] Secondly, this application also provides a DRAM memory array failure bitmap reconstruction apparatus, the apparatus comprising: A coarse sampling module is used to configure a structured sampling matrix based on the physical hierarchy of the DRAM storage array, and to perform at least one round of structured coarse sampling on the DRAM storage array to obtain coarse sampling results. The physical hierarchy of the DRAM storage array includes four levels: storage bank, row, column, and storage subarray. The structured sampling matrix includes a first sampling step size in the row direction, a second sampling step size in the column direction, and a row sampling start offset configured for each storage bank. The row sampling start offset makes the sampling rows of different storage banks staggered in the row address space. The first sampling step size and the second sampling step size ensure that there is at least one sampling point in each row and each column of the DRAM storage array. An anomaly score calculation module is used to calculate the multidimensional anomaly score of each predefined sampling region in the DRAM storage array based on the coarse sampling results. A refined sampling module is used to adaptively perform multi-resolution refined sampling on the sampling region based on the multi-dimensional anomaly score to obtain multi-resolution sampling results; The reconstruction module is used to perform sparse reconstruction on the multi-resolution sampling results based on a pre-trained physical semantic dictionary to obtain the failure bitmap of the DRAM storage array.

[0016] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in the first aspect.

[0017] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the first aspect.

[0018] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in the first aspect above.

[0019] The aforementioned DRAM memory array failure bitmap reconstruction method, apparatus, computer equipment, computer-readable storage medium, and computer program product achieve a balance between sampling efficiency, detection completeness, and reconstruction accuracy in DRAM memory array testing through a four-stage closed-loop architecture: structured coarse sampling, multi-dimensional anomaly score evaluation, adaptive multi-resolution refinement, and sparse reconstruction based on a physical semantic dictionary. It utilizes a four-level physical hierarchy structure (Bank / Row / Column / Segment) to configure a structured sampling matrix including row sampling step size, column sampling step size, and Bank row start offset. By leveraging the staggered distribution of different Bank sampling rows in the row address space and the coordination of row and column sampling step sizes, it ensures that each row and column of the array has at least one sampling point, thus providing a deterministic detection basis independent of probability recovery for whole-row and whole-column failures. Based on this, it performs hierarchical evaluation of predefined sampling regions through multi-dimensional anomaly scores and adaptively executes multi-resolution refinement sampling accordingly, thus improving sampling efficiency. It can prioritize the allocation to truly suspicious areas, significantly reducing the effective sampling rate while avoiding missed detections of large-area cluster failures. Finally, by using a pre-trained physical semantic dictionary to sparsely reconstruct the multi-resolution sampling results, the failure bitmap reconstruction is transformed from a purely mathematical inverse problem into a pattern matching problem under physical constraints. This allows for the acquisition of high-precision failure bitmaps with structural similarity that meet the redundancy repair requirements at a sampling cost far lower than that of full March testing. Overall, it solves the technical contradiction that the time cost of existing full testing increases linearly with capacity, while general compressed sensing schemes ignore the physical structure of DRAM and lack deterministic missed detection guarantees. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating a DRAM memory array failure bitmap reconstruction method in one embodiment; Figure 2 This is a flowchart illustrating the recursive execution of the quadtree refinement sampling step in one embodiment; Figure 3 This is a structural block diagram of a DRAM memory array failure bitmap reconstruction apparatus in one embodiment; Figure 4 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0023] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0024] In one exemplary embodiment, such as Figure 1 As shown, a method for reconstructing a DRAM memory array failure bitmap is provided, which may specifically include the following steps: Step 102: Configure a structured sampling matrix based on the physical hierarchy of the DRAM storage array, and perform at least one round of structured coarse sampling on the DRAM storage array to obtain the coarse sampling results.

[0025] The DRAM memory arrays include, but are not limited to, DDR4 / DDR5 SDRAM, LPDDR4 / LPDDR5 / LPDDR6 mobile DRAM, HBM2 / HBM3 / HBM4 high-bandwidth memory, GDDR6 / GDDR7 graphics memory, and memory expansion devices based on the CXL (ComputeExpress Link, an open high-speed interconnect standard) protocol. The DRAM memory array failure bitmap reconstruction method provided in this application is also applicable to failure detection scenarios for other large-scale memory arrays with row and column address structures (such as NANDFlash, MRAM, ReRAM, and other non-volatile memories); the testing scenarios cover wafer-level testing (CP), package-level finished product testing (FT), and built-in self-test (BIST).

[0026] The physical hierarchy of a DRAM memory array consists of four levels: Bank (a memory bank, i.e., a memory array partition in DRAM with independent row / column decoders), Row (a row, i.e., a horizontal row of memory cells in a Bank), Column (a vertical column in a Bank), and Segment (a local array segment within a Bank, i.e., a physical memory subarray further subdivided within a Bank). Because the memory array area of ​​a Bank in the actual layout of a DRAM chip is very large, in order to reduce bitline capacitance, shorten wordline RC delay, and improve the sensitivity of the sense amplifier, a Bank can be further divided into multiple relatively independent Segments (also called sub-arrays or mats). Each Segment contains localized row decoders, column decoders, and sense amplifier arrays, and is one of the smallest physical units within a Bank capable of independently performing some timing control and power management.

[0027] The structured sampling matrix is ​​a set of sampling points defined by deterministic parameters such as row sampling step size (i.e., the first sampling step size in the row direction), column sampling step size (i.e., the second sampling step size in the column direction), and bank-level row sampling start offset. Among them, the bank-level row sampling start offset ensures that the sampling rows of different banks are staggered in the row address space, and the first and second sampling step sizes ensure that there is at least one sampling point in each row and each column of the DRAM memory array.

[0028] For example, the structured sampling matrix can be configured as follows: For any memory cell (b, r, c) in a DRAM array, where b is the bank number, r is the row address, and c is the column address, the following structured sampling decision function F can be defined: F(b, r, c) = 1 if and only if and If the condition is met, then F(b, r, c) = 0; otherwise, F(b, r, c) = 0. This indicates that r is paired with... Find the remainder when the remainder is If c is within the range of column sampling points, then F(b, r, c) = 1, which satisfies the sampling condition.

[0029] in, This represents the first sampling step size (i.e., the row sampling step size), which determines the sampling sparsity in the row direction. A typical value in this embodiment is... =16, meaning 1 row is sampled every 16 rows; with 8192 rows per bank, 512 rows are sampled per bank.

[0030] The row sampling start offset, representing the row sampling start offset of Bank b, is generated by the following formula: ;in, To and The offset constants of coprime elements, and their typical values ​​in this embodiment. =3 (and = 16 coprime), b corresponds to the number of different banks (such as Bank 0, Bank 1, Bank 2, etc.). Because and Since they are coprime, the sampled rows of each Bank are staggered and do not overlap in the row address space, thus achieving an interleaved distribution of sampled rows from different Banks and maximizing the overall coverage efficiency of the row address space.

[0031] Let represent the set of column sampling points. For the row r being sampled, the set of column sampling points within that row is constructed as follows: .in, The second sampling step size (i.e., column sampling step size, a typical value in this embodiment) = 16), shift(b, r) is the column offset parameter related to the Bank number b and the row address r.

[0032] With the above configuration, the number of sampling points per bank is (8192 / 16) × (1024 / 16) = 512 × 64 = 32768, corresponding to an effective sampling rate of approximately 1 / 256 (approximately 0.39%).

[0033] Specifically, the column offset parameter defines the starting position of the column sampling point for each sampled row. The column offset parameter is generated based on the storage bank number b and the row address of the sampled row r, and its typical construction is as follows: ,in and Similarly, for the purpose of... Coprime offset constants, typical values = 3 (and = 16 coprime).

[0034] Since shift changes row by row as r increases, the starting position of column sampling points for different sampled rows r within the same Bank is shifted row by row along the column direction, avoiding repeated sampling of all sampled rows within the same Bank at the same batch of column addresses. Furthermore, since shift also changes with the Bank number b and the sampled rows of each Bank are already interleaved, the starting positions of column sampling points between different Banks are interleaved along the column direction, which together ensures the traversal of column offsets in the b×r parameter space.

[0035] This gives the structured sampling matrix the following key properties: Line coverage, when When = 16, one row out of every 16 rows in each Bank will be sampled, and at least 64 sampling points will be distributed within the sampled row. Therefore, the address space of each row is covered, providing a geometric basis for the deterministic detection of the failure of the entire row. Column covering, since shift(b, r) uniformly traverses the b×r two-dimensional parameter space, for any column address c, there must exist at least one pair (b, r) such that c ∈ That is, each column address is covered by at least one sampling point under the joint coverage of all {Bank, Row}, providing a geometric basis for the deterministic detection of the failure of the entire column; The mutual consistency bound is defined by the mutual consistency μ(ΦD) between the structured sampling matrix Φ and the physical semantic dictionary D (described later), which satisfies μ(ΦD) ≤ 1 / max( , );exist = Under the condition of 16, μ(ΦD) ≤ 0.0625, which is much lower than the typical value of random Gaussian sampling matrix (about 0.3~0.5), thus providing a better theoretical recovery bound for subsequent sparse reconstruction.

[0036] Based on this, this embodiment, without adding any sampling points, ensures that row and column sampling points are fully distributed in the address space, achieving deterministic coverage of any row and column address, thus including the failure of an entire row or column within the hard guarantee range. Furthermore, it can be implemented at the software or hardware / firmware level using only a simple counter and modulo adder, eliminating the need for a pseudo-random number generator and resulting in low implementation complexity.

[0037] For example, if we take = 16, = 3, then the column sampling start positions of the 0th, 16th and 32nd sampled rows of Bank 0 are 0, 1 and 2 (mod 16) respectively, and the column sampling start positions of the corresponding rows of Bank 1 are 3, 4 and 5 (mod 16) respectively, and so on.

[0038] During coarse sampling, the sampling rows of each bank are activated sequentially in ascending order of row address. Each activated row sequentially completes read and write tests of all 64 column sampling points within that row while it is held in the row buffer. Since the sampling process follows the access mode of sequential row activation and multiple column reuse within a row, it is naturally compatible with the DRAM row activation / precharge timing constraints, avoiding the tRP + tRCD (approximately 25~35ns in DDR5) time overhead introduced by each random row jump in the random addressing scheme. For each sampling point, Read(0) (meaning first write logic 0 to the target cell, then read back, and check if the read is equal to 0) and Read(1) (meaning first write logic 1 to the target cell, then read back, and check if the read is equal to 1) are performed once each. If any read operation fails, the cell is determined to be faulty and its address is recorded to form the coarse sampling result.

[0039] In one scenario, two independent rounds of structured coarse sampling can be performed on each device under test, with the two rounds using different methods. The shift parameter ensures that the two sets of sampling points do not intersect, thus creating sampling redundancy and providing probabilistic suppression of missed detections for isolated single-bit failures.

[0040] Step 104: Based on the coarse sampling results, calculate the multidimensional anomaly score for each predefined sampling region in the DRAM memory array.

[0041] Here, the predefined sampling region block is an equal-sized region divided into segments and banks within the physical hierarchy of the DRAM storage array during the coarse sampling stage. In this embodiment, a typical size can be 256×256 cells. The multidimensional anomaly score is a weighted sum of the density anomaly score, pattern anomaly score, context anomaly score, and edge fragility factor of the corresponding sampling region. Specifically, it is expressed as follows: ; in, Let represent the weight vector, where are numbers greater than or equal to 0 and less than or equal to 1. The sum of is 1, determined by grid search on the validation set, with the goal of maximizing the discriminative power of refinement or non-refinement (using the sampling region that triggers the full scan as the positive sample label).

[0042] This represents the density anomaly score, used to measure the degree of deviation of the density of failed sampling points within the sampling area from the normal baseline distribution. Specifically, it is expressed as: , in, For the first Density anomaly score of each sampling region For the failure count of the i-th sampling region, and These represent the mean and standard deviation of the failure counts, respectively, from coarse sampling on the reference chip. Under typical 8Gb DDR4 process conditions, ≈ 0.02, ≈ 0.15 (with random single-bit noise), therefore, the presence of two failed sampling points in any region constitutes a significant density anomaly. >3σ).

[0043] The mode anomaly score measures whether the spatial arrangement of failure sampling points within a region exhibits the geometric characteristics of a known failure mode. Specifically, it is represented as: ; in, This represents the normalized weights; typical values ​​in this embodiment are... It is 0.7. It is 0.7. It is 0.6.

[0044] The definitions are as follows: in, For the first Pattern anomaly score for each sampling region For the first The row alignment of each sampling region is a normalized measure of the degree to which failed sampling points are collinear in the row direction (typically, the number of row failures increases when there are ≥3 failed points in the same row, and the 3σ threshold is 1.3). For the first The column alignment of each sampling region, and symmetry; For the first Clustering coefficients for each sampled region, where the molecule The denominator represents the average of the reciprocals of the Euclidean spatial distances between each pair of failed sampling points. The expected value obtained from the offline test is cluster_coef>1.5, which indicates that the failure points are more clustered than the random distribution, and is a typical signal of cluster failure.

[0045] This represents the context anomaly score, used to measure the degree of inconsistency between the failure distribution of a sampled region and its spatial neighborhood. Specifically, it is expressed as: ; in, For the first Context anomaly score for each sampling region; This is the empirical failure distribution (normalized histogram) of the i-th sampling region at the sampling points. For the first The arithmetic mean of the failure distribution of the 8 neighboring sampling regions of each sampling region. The divergence is Kullback-Leibler. = 0 indicates that the failure mode of this region is completely consistent with that of the neighboring region (e.g., if the bad region has been identified, no additional attention is needed); A value >1.0 (this is an empirical threshold) indicates significant inconsistency. An isolated normal region surrounded by a clean region is often a weak early failure signal and should be prioritized for refinement.

[0046] The edge vulnerability factor quantifies the proximity of the sampling region to process-sensitive areas such as chip physical edges and bias regions (e.g., VBBwell boundaries). A higher value indicates that the region is closer to a process-sensitive area and has a higher prior risk of failure. Specifically, it is expressed as: ; Where B is within the known bias boundary region, =1, otherwise It is 0. For the first Edge fragility factor of each sampling region It represents the shortest distance from the center of the i-th sampling region to the chip edge (typically using Chebyshev distance, in block units). α is the attenuation constant (typically 4, assuming the edge effect is significant within about 4 block widths), and α is the bias boundary weighting coefficient (typically 0.5).

[0047] This embodiment captures information from four complementary aspects through four dimensions: density anomaly (measuring the number of failures), pattern anomaly (measuring the arrangement of failures), context anomaly (measuring whether failures are consistent with their surroundings), and edge prior (measuring whether failures occur in physically vulnerable areas). Any single-dimensional failure pattern can be captured by at least one dimension, thereby significantly reducing the missed trigger rate in abnormal areas. At the same time, the four-dimensional weighted fusion, through validation set optimization, suppresses false triggers caused by single-dimensional noise, enabling the refined sampling budget to be accurately targeted at truly suspicious areas.

[0048] Step 106: Adaptively perform multi-resolution refinement sampling on the sampling region based on the multi-dimensional anomaly score to obtain multi-resolution sampling results.

[0049] In this embodiment, the sampling area can be sampled and split at different resolutions based on the multidimensional anomaly score of each sampling area to obtain multi-resolution sampling results.

[0050] For example, for any sampling region, if the multidimensional anomaly score is determined to be less than the first score threshold, the sampling region is determined to be a normal region (splitting to CLEAN), and the refined sampling is terminated, directly entering the subsequent reconstruction process.

[0051] In one scenario, if the multidimensional anomaly score of any sampling region is determined to be greater than or equal to a first score threshold and less than or equal to a second score threshold, the sampling region is identified as a suspected anomaly region (splitting the stream as SUSPICIOUS). Quadtree refinement sampling is then performed on this suspected anomaly region a preset number of times (e.g., 1-2 times, refining stops after reaching the preset number of times regardless of the result) to obtain the multi-resolution sampling results of the suspected anomaly region, and the process proceeds to the subsequent reconstruction process. The second score threshold is greater than the first score threshold. For example, in this embodiment, the first score threshold can be 0.35, and the second score threshold can be 0.7.

[0052] In one scenario, if the multidimensional anomaly score of any sampling region is greater than the second score threshold, the sampling region is determined to be an anomaly region (HOT). Quadtree refinement sampling is recursively performed on the anomaly region until the minimum resolution is reached, the multi-resolution sampling results of the anomaly region are obtained, and the subsequent reconstruction process is initiated.

[0053] In one exemplary embodiment, such as Figure 2 As shown, quadtree refinement sampling is recursively performed on the abnormal region until the minimum resolution is reached. Specifically, this may include: Step 202: The abnormal region is recursively divided using a quadtree structure to obtain the corresponding sub-regions.

[0054] For example, taking a block with a sampling area, i.e. an abnormal area, of 256×256 as an example, it can be divided into four 128×128 sub-regions based on the quadtree structure (in the subsequent recursive process, it can be further divided into 64×64, 32×32, and 16×16 sub-regions as needed), and each sub-region is sampled based on the subsequent steps.

[0055] Step 204: Perform sampling on the sub-region obtained by the current division, using half of the row sampling step length of the corresponding parent region as the new row sampling step length and half of the column sampling step length of the corresponding parent region as the new column sampling step length, and calculate the multidimensional anomaly score of the sub-region.

[0056] The row sampling step size corresponding to the initial parent region is the first sampling step size of the structured sampling matrix. The column sampling step size is the second sampling step size of the structured sampling matrix. .

[0057] For example, for the four 128×128 sub-regions obtained above, their row sampling step size and column sampling step size are respectively... / 2 and The resolution is doubled progressively by 2. Based on this, each sub-region is sampled, and the multidimensional anomaly score for the corresponding sub-region is calculated.

[0058] Step 206: Recursively iterate based on the multidimensional anomaly scores of the sub-regions until the minimum resolution is reached.

[0059] The process is recursively iterated based on the multidimensional anomaly scores of the sub-regions. For example, if the sub-region is split into CLEAN, the process terminates immediately; if it is split into SUSPICIOUS, the process is refined a preset number of times and then terminates; if it is split into HOT, the process continues to recursively down the range until the minimum resolution (typically 16×16, i.e., the edge of cell-level resolution) is reached.

[0060] In one possible implementation, after recursively performing quadtree refinement sampling on the abnormal region until the minimum resolution is reached, if it is determined that the region is still abnormal (i.e., the flow is split into HOT) after reaching the minimum resolution (16×16), then a full scan (FULL_SCAN) is performed on the region. That is, a complete multi-step March algorithm test (e.g., March C-, 10 visits per cell) is performed on all cells in the region to obtain the full scan result, and the multi-resolution sampling result of the region is determined based on the full scan result.

[0061] Under typical mass production data distribution, the trigger rate of FULL_SCAN is approximately 0.15%. The full failure data obtained from the full scan area can also serve as training samples for subsequent online incremental dictionary learning, achieving a dual utilization of a safety net and a data closed loop. Through full scanning, it provides a deterministic safety net with zero missed detections for extreme failure scenarios (such as areas exhibiting diffuse anomalies even at minimum resolution), thereby ensuring the absolute correctness of the reconstructed bitmap for such areas. Simultaneously, the ground truth data generated by the full scan flows back to the dictionary training stage, forming a closed loop where test data continuously feeds back into the reconstruction model, combining security and data asset value.

[0062] In one exemplary implementation, the budget allocation for refined sampling can employ a multi-armed bandit framework, treating each block to be refined as an "arm," with its "reward" being the number of suspected faulty cells revealed after refinement. The next batch of blocks to be refined is selected using a UCB (Upper Confidence Bound) strategy. This can be represented as follows: in, for The average number of failures found per sampling to date, n i This represents the number of refined rounds that have been executed for this block. For the total number of refinements, To explore parameters. Because blocks with high anomaly scores naturally have higher... Based on the prior mean, the UCB strategy automatically prioritizes the sampling budget to the HOT region while exploring and utilizing the balance between the SUSPICIOUS regions to maximize the number of failed cells detected under the total sampling budget constraint.

[0063] This embodiment is based on a sampling budget allocation strategy that terminates the CLEAN region, which accounts for the largest proportion (typically over 80%), in advance, concentrating sampling resources on a few suspicious regions and keeping the overall effective sampling rate in the range of 1% to 5%. By using quadtree recursion, the granularity of refinement is adaptively matched with the degree of anomaly, and the abnormal region can be refined to the cell-level resolution, providing accurate failure addresses for subsequent redundancy repair. The three-level flow splitting is implemented with two-level thresholds, resulting in extremely low computational overhead, and can be executed online in real time during the ATE test process.

[0064] Step 108: Based on the pre-trained physical semantic dictionary, sparse reconstruction is performed on the multi-resolution sampling results to obtain the failure bitmap of the DRAM memory array.

[0065] The physical semantic dictionary is an overcomplete dictionary trained from historical failure bitmap data through dictionary learning. Each dictionary atom corresponds to a physical failure mode of the DRAM memory array. The failure bitmap is a binary matrix representation of the test results recording the pass / fail status of each memory cell in the memory array.

[0066] In one exemplary embodiment, obtaining the physical semantic dictionary may include the following stages: Training data preparation phase: Collect complete March test failure bitmaps from at least 10,000 historical dies (bare chips), and cut each bitmap into non-overlapping 16×16 (256-dimensional) sample blocks. Each sample block is labeled as one of the following types: isolated failure (d_isolated, 1~2 isolated failures). Cell failures, typically caused by alpha particle flipping or single-cell leakage (approximately 5%), row failures (d_row, continuous failures along the row direction, typically caused by word line open / short circuits, approximately 25%), column failures (d_col, continuous failures along the column direction, typically caused by bit line leakage or sensitive amplifier failure, approximately 20%), cluster failures (d_cluster, circular / elliptical clusters of failures, typically caused by silicon defects or gate oxide pinholes, approximately 30%), coupling failures (d_coupled, cross-shaped row + column intersection failures, typically caused by decoder coupling failures, approximately 12%), periodic failures (d_periodic, periodically spaced failures, typically caused by address scramble mapping errors, approximately 3%), and normal regions (d_clean, full pass, approximately 5%).

[0067] K-SVD dictionary learning phase: Specifically, this can be achieved by solving the following optimization problem: This indicates that for each sample block, only a maximum of [number] samples can be used. Given a certain number of dictionary atoms, minimize the reconstruction error between the original training sample Y and the dictionary reconstruction result DX.

[0068] in, The training sample matrix is ​​defined by N, where N is the dimension of the sample block (e.g., 256 dimensions), and K is the number of training samples (sim 10). 6 (magnitude) M is the overcomplete dictionary to be learned, which is equal to the dimension of the sample block to ensure overcompleteness; X is the sparse coefficient matrix (each column... The number of non-zero elements in the middle does not exceed T0 = 5). is the L0 pseudonorm, representing the number of non-zero elements in the counting vector; This represents the Frobenius norm.

[0069] K-SVD employs sparse coding (OMP algorithm), which is an alternating optimization strategy of updating atoms one by one. In the atom update phase, for the k-th atom, a sample index set using that atom is defined. Construct the error matrix after removing the contribution of this atom. and intercept exist submatrix on ,right Perform SVD decomposition and update the atoms with the first left singular vector. The corresponding sparse coefficients are updated by the product of the first right singular vector and the first singular value, which is the rank-1 approximation of the error matrix. After training converges, each atom is visualized as a 16×16 grayscale image and its physical semantic morphology is verified (row failure atoms are horizontal stripes, column failure atoms are vertical stripes, cluster atoms are patchy, etc.) to ensure that each dictionary atom corresponds to a physical failure mode of the DRAM memory array.

[0070] During the reconstruction phase, the multi-resolution sampling results are processed as follows: Based on a preset row and column size (e.g., 16×16), each sampling area is divided into multiple regions to be reconstructed, and the hierarchical status of each region to be reconstructed (e.g., CLEAN / SUSPICIOUS / HOT or FULL_SCAN) is determined according to the above refined flow results.

[0071] Then, based on the hierarchical status, the corresponding dictionary subset is determined from the physical semantic dictionary. For example, for the CLEAN region, D_clean ∪ D_isolated is selected (clean regions only need to distinguish between the two modes of all good and isolated bits); for the SUSPICIOUS region, the full dictionary D_full is selected (the failure type is uncertain and full coverage is required); for the HOT / FULL_SCAN region, D_row ∪ D_col ∪ D_cluster ∪ D_coupled is selected (hot areas are likely structural failures).

[0072] Based on the dictionary subset and local sampling matrix of the region to be reconstructed, a sparse reconstruction of the failure bitmap of the region to be reconstructed is performed (specific parameters can be provided in the subsequent sparse reconstruction section) to obtain a binary failure bitmap of the region to be reconstructed. Finally, the binary failure bitmaps of all regions to be reconstructed in the DRAM memory array are merged, and a consensus voting correction is performed on the boundaries of adjacent regions to be reconstructed (typically 2-cell wide stripes) (in case of a tie, a conservative fail is determined) to obtain the complete failure bitmap of the DRAM memory array.

[0073] In the above embodiments, the dictionary atoms have clear physical semantics. By transforming sparse reconstruction from a purely mathematical problem into a pattern matching problem under physical constraints, the reconstruction results have strong physical interpretability and can directly support root cause analysis of failures. By selecting a subset of the dictionary according to hierarchical states, the basic dimension of the problem to be solved is compressed by about 50% to 75% while ensuring coverage, which significantly reduces the computational load of online reconstruction. Moreover, the structural similarity (SSIM) of the reconstructed bitmap relative to the full March reference bitmap can reach more than 0.99, which can ensure that the reconstructed bitmap can directly replace the original full test results in the redundancy repair process.

[0074] In one exemplary embodiment, sparse reconstruction is achieved by solving the following LASSO problem: in, For the multi-resolution sampled observation vectors of the region to be reconstructed, This is the local sampling matrix of the region to be reconstructed (each row contains only one non-zero element 1, corresponding to the position of a sampling point). This is a subset of the dictionary corresponding to the region to be reconstructed. is the regularization coefficient (determined by cross-validation, typically 0.1). Representing vectors L1 norm; Let x represent the sparse coefficient vector obtained from the reconstruction. This function is an optimization problem. The first part minimizes the error, and the second part makes the dictionary template dk smaller, thus making x sparser.

[0075] In the specific solution, the FISTA (Fast Iterative Shrinkage-Thresholding Algorithm) is used for iterative solution: , in, , Soft threshold operator, according to calculate; t represents the iteration step, which increases from 0, 1, 2, and so on. It is the sparse coefficient vector at step t. Initialize to all zeros. It is the output of the previous step; This represents the FISTA momentum sequence. , In this embodiment, the convergence rate of FISTA is O(1 / t²), which is significantly faster than that of ordinary ISTA (O(1 / t)).

[0076] After reconstruction, the continuous value reconstruction results are mapped to a binary failure bitmap through thresholding: when (τ is the judgment threshold, typically 0.5) If the threshold is τ, the product is judged as a fail; otherwise, it is judged as a pass. Understandably, the choice of τ follows the principle of conservatively judging failure, that is, it is better to judge more failures and generate false positives (which can be remedied by redundancy repair resources) than to miss judgments and generate false negatives (leading to customer complaints and returns).

[0077] In this embodiment, LASSO is a convex optimization problem with a globally optimal solution, avoiding combinatorial explosion and local optimum traps in L0-constrained problems, and ensuring the reproducibility of region-by-region reconstruction results in mass production environments. FISTA's O(1 / t²) convergence speed, combined with the skip strategy of directly outputting all zero regions when all observation points pass, keeps the reconstruction time of all regions of a single die within tens of milliseconds, which can be embedded into the mass production test cycle. The sparsity induced by L1 regularization makes the solution naturally fall on the low-dimensional combination of physical failure modes, forming a dual constraint with the physical semantics of the dictionary, further suppressing reconstruction artifacts.

[0078] In an exemplary embodiment, to address the degradation of pre-trained dictionary representation capabilities caused by process drift, equipment aging, and inter-lot fluctuations in a mass production environment (manifested as a continuous increase in the FULL_SCAN trigger rate and a decrease in reconstructed SSIM), the above method may further include an online incremental dictionary update step to achieve continuous dictionary updates. This step utilizes only the full March test data of the block that triggers FULL_SCAN in the current lot as incremental training samples, performs incremental K-SVD updates on the dictionary in the background, with an update latency not exceeding one lot's test cycle, zero downtime during the update process, does not compete for computing resources with the foreground ATE test process, and the incrementally updated dictionary is not inferior to the offline training version in terms of mutual consistency metrics.

[0079] The above method can provide two layers of detection guarantees with different properties within a unified framework: a hard guarantee and a soft guarantee.

[0080] The hard guarantee (100% deterministic detection) is reflected in its ability to cover entire row failures, entire column failures, and large-area cluster failures with a continuous area ≥ 8 cells. Due to the design constraint of at least one sampling point per row in the structured sampling matrix, if all cells in a row fail, there must be at least one failed sampling point in that row. This row is marked as an anomaly and will inevitably trigger refinement. Refinement to the cell level achieves 100% detection, i.e., coverage of entire row failures. The traversal guarantee of the column offset parameter—that is, for any column address c, there exists at least one pair (b, r) such that the column is sampled and covered—depends on the traversal of shift(b, r) in the b×r parameter space. and When coprime, the traversal period is lcm ( , This means coverage of entire cluster failures. Segment-level coverage and quadtree refinement ensure that contiguous clusters larger than 8 cells will inevitably fall within the monitoring range of at least one sampling block. Quadtree refinement guarantees precise location within a depth ≤ 4 (corresponding to a 16×16 block), and spatial continuity ensures that missed detections are impossible, thus covering large-area cluster failures. Based on historical statistical data from 8Gb / 16Gb DDR4, the hardware guarantees coverage of approximately 95% of actual mass-production failure modes, and this part of the detection does not rely on any probability recovery.

[0081] Soft guarantees (controllable probability bounds) provide the following upper bound for the missed detection probability for isolated single-bit failures and small cluster failures (2~7 cells): P_miss ≤ P1 (Phase 1, i.e., coarse sampling, not detected) × P2 (Phase 2, refinement not triggered) × P3 (Phase 3, reconstruction failed).

[0082] Under single-round coarse sampling (sampling rate 1 / 256), the missed detection probability of isolated bits is about 6%, which is unacceptable. After introducing two rounds of independent redundant sampling (sampling point sets are non-overlapping), P_miss ≤ 0.06² ≈ 3.6×10 - ³; After expanding to three rounds of redundant sampling, P_miss can be reduced to 10. -9 The risk level is acceptable, considering that isolated single-bit failures account for only about 5% of all failures, and that single-bit failures can usually be corrected by ECC.

[0083] In an exemplary embodiment, taking an 8Gb DDR4 SDRAM chip (×8 data width) as the test object, the above-mentioned DRAM memory array failure bitmap reconstruction method is further explained. Wherein: The chip specifications include: the tested DDR4 chip has a capacity of 8Gb, uses a 1x nm process node, contains 8 banks, each bank has a storage array of 8192 rows × 1024 columns, a single bank contains 8,388,608 storage cells, and the total number of cells in the entire chip is 67,108,864. The ATE test rate is 1.6Gbps.

[0084] Configure structured sampling parameters: row sampling step size =16, column sampling step size =16, Bank offset coprime constant =3, column offset coprime constant =3, column offset function In the coarse sampling stage, the predefined sampling area (block) size is 256×256 cells, and each bank is divided into (8192 / 256)×(1024 / 256)=32×4=128 blocks.

[0085] During the offline training phase, training samples were extracted from the full range of March test failure bitmaps of no less than 10,000 historical dies. Each bitmap was cut into non-overlapping 16×16=256 dimensional sample blocks, and each sample block was labeled with a failure type, including: isolated point failure (approximately 5%), row failure (approximately 25%), column failure (approximately 20%), cluster failure (approximately 30%), coupling failure (approximately 12%), periodic failure (approximately 3%), and normal region (approximately 5%). The K-SVD algorithm was used to train the physical semantic dictionary D∈R^(256×256), with a sparsity constraint T0=5, meaning that each sample block was represented by a maximum of 5 linear combinations of dictionary atoms.

[0086] Phase 1 Structured Coarse Sampling: Configure the row sampling start offset for each bank. The offsets for Bank 0 to Bank 7 are 0, 3, 6, 9, 12, 15, 2, and 5, respectively.

[0087] For Bank 0, the sampled row set R_sample = {r | r≡0 (mod 16), 0≤r<8192} contains 512 sampled rows. For each sampled row r, the starting column is determined by the column offset shift(0,r) = (0·3+r) mod 16. =16 is the step size, sampling 64 points in the column direction. The column sampling set is C_sample(r,0)={c | c=j·16+shift(0,r),j=0,1,...,63}. The total number of coarse sampling points in Bank 0 is 512×64=32,768.

[0088] Banks 1 through 7 perform the same operation in parallel, with each bank using its own row sampling start offset. The total number of coarse sampling points across the eight banks is 262,144, representing a coarse sampling rate of approximately 0.39% relative to the total 67,108,864 cells in the chip.

[0089] During coarse sampling, Read(0) and Read(1) operations are performed once for each target sampling point. If either Read operation fails, the sampling point is marked as a failure point. During the read operation, ATE accesses the sampling row addresses in order to avoid the pre-charging and row activation time overhead (tRP+tRCD approximately 25~35ns) introduced by random row skipping.

[0090] Phase 2 adaptive refinement sampling: For each 256×256 block (predefined sampling region), calculate the multidimensional anomaly score. , where the weight vector w ( = [0.20, 0.35, 0.30, 0.15], determined by the validation set grid search.

[0091] Taking a tested die as an example, the failure count distribution of each block after coarse sampling is as follows: most blocks have a fail_count of 0, blocks with a fail_count of 1 account for approximately 8%, and blocks with a fail_count ≥ 2 account for approximately 1.8%. For blocks with a fail_count of 0, ≈-0.13, ≈0, ≈0, The overall anomaly score is approximately 0.1 to 0.3, and the comprehensive anomaly score is approximately 0.02 to 0.07. Since this score is lower than the first score threshold θ_low=0.3, it is determined to be a CLEAN region, and the refinement is terminated.

[0092] For an isolated block with fail_count=1 and surrounded by a clean region ≈6.5 (exceeding the 10σ threshold). Since the difference from the neighborhood can reach 0.8~1.2, the comprehensive score S≈0.50~0.55, which is between θ_low=0.3 and θ_high=1.0, it is determined to be a SUSPICIOUS region, and 1~2 quadtree refinements are performed.

[0093] For blocks with fail_count ≥ 2, the overall score S > 1.0, indicating a HOT region, triggering recursive quadtree refinement. First split: Divide the 256×256 block into four 128×128 sub-blocks, and refine each sub-block using... =8、 =8 times the resolution sampling, and recalculate the anomaly score. If the sub-block is still HOT, continue splitting to 64×64, 32×32, and 16×16. Sub-blocks that are still HOT at 16×16 (depth 4) are marked as FULL_SCAN, and a full March C-test (10 visits / cell) is performed on the sub-block. In this embodiment, the FULL_SCAN trigger rate is approximately 0.15%.

[0094] The sampling budget for the refinement phase adopts a "total budget - on-demand allocation" strategy, with a total effective sampling rate target of r_target=2.3%. Coarse sampling consumes 0.39% (approximately 17% of the total budget), and refinement sampling consumes approximately 1.91% (approximately 83% of the total budget). During the refinement sampling process, a multi-armed slot machine (UCB) strategy is used to dynamically allocate the sampling budget among various SUSPICIOUS and HOT regions to explore parameters. .

[0095] Phase 3 sparse reconstruction execution: The array of all 8 banks (memory units) is divided into 16×16, resulting in a total of (8192 / 16)×(1024 / 16)×8=512×64×8=16,384 regions to be reconstructed.

[0096] For each region to be reconstructed, process in parallel: acquire the multi-resolution sampled observations y_k (including the joint sampling results of Phase 1 and Phase 2) within that region. If all observed points in the region to be reconstructed are pass, directly output the region to be reconstructed with all zeros, skipping the LASSO solution.

[0097] For regions to be reconstructed with failed observations, a subset of the dictionary is selected based on the state of the block containing the region. For example, D_clean∪D_isolated is used for CLEAN regions; D_full (all 256 atoms) is used for SUSPICIOUS regions; and D_row∪D_col∪D_cluster∪D_coupled is used for HOT / FULL_SCAN regions.

[0098] Solve the following LASSO problem: Where λ=0.1 is determined by cross-validation. The FISTA algorithm is used for solving the problem, with a maximum of 200 iterations and a convergence tolerance of 10. -4 The gradient Lipschitz constant L = ||Φ_kD_k||2² is estimated by power iteration. Nesterov momentum extrapolation and soft thresholding are performed in each iteration.

[0099] After reconstruction, thresholding is performed to obtain a binary bitmap of the region to be reconstructed. After merging the binary bitmaps of all regions to be reconstructed, a consensus voting correction is performed on the boundaries of adjacent regions (2-cell wide stripes), and a conservative fail is made in case of a tie.

[0100] Test results output: The test results of this embodiment on the 8Gb DDR4 chip include: the total time for coarse sampling + fine sampling is about 1.7ms, the reconstruction calculation time is about 16ms (parallel processing of multi-core CPUs on the ATE workstation), and the total time for the array test is about 18ms. Compared with the full March C- test of about 53.7 seconds, it achieves an acceleration of about 2983 times.

[0101] The effective sampling rate is approximately 2.3%, with a FULL_SCAN trigger rate of 0.15% providing a safety net for extreme cases. At the hard guarantee level, the structured sampling matrix ensures at least one sampling point per row and column, achieving 100% deterministic detection of entire row and column failures; quadtree refinement to 16×16 resolution ensures 100% detection of cluster failures ≥8 cells. The hard guarantee covers approximately 95% of actual mass-production failure modes.

[0102] At the soft guarantee level, two rounds of independent structured coarse sampling (different) (and the shift parameter) controls the upper bound of the isolated single-bit missed detection probability at 10. -9 The reconstructed bitmap SSIM reached 0.995, almost identical to the reference bitmap in the full March test. The redundancy repair success rate was approximately 98.1%, with no significant difference from the full test baseline (98.2%).

[0103] This embodiment verifies the compatibility of the structured sampling matrix with DRAM physical addressing constraints by executing the complete three-stage method flow on an 8Gb DDR4 chip, demonstrates the effectiveness of the quadtree adaptive refinement mechanism in sampling budget allocation, and shows that the physical semantic dictionary achieves an SSIM index of 0.995 in sparse reconstruction. This embodiment demonstrates that the method can reduce the array test time from approximately 54 seconds to the order of 18 milliseconds while maintaining the redundancy repair success rate, resulting in a test cost saving of over 90%.

[0104] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0105] Based on the same inventive concept, this application also provides an apparatus for implementing the DRAM memory array failure bitmap reconstruction method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more apparatus embodiments provided below can be found in the limitations of the DRAM memory array failure bitmap reconstruction method described above, and will not be repeated here.

[0106] In one exemplary embodiment, such as Figure 3 As shown, a DRAM memory array failure bitmap reconstruction device is provided, including: a coarse sampling module 302, an anomaly score calculation module 304, a fine sampling module 306, and a reconstruction module 308, wherein: The coarse sampling module 302 is used to configure a structured sampling matrix based on the physical hierarchy of the DRAM storage array, and to perform at least one round of structured coarse sampling on the DRAM storage array to obtain coarse sampling results. The physical hierarchy of the DRAM storage array includes four levels: Bank, Row, Column, and Segment. The structured sampling matrix includes a first sampling step size in the row direction, a second sampling step size in the column direction, and a row sampling start offset configured for each storage Bank. The row sampling start offset makes the sampling rows of different Banks staggered in the row address space. The first sampling step size and the second sampling step size ensure that there is at least one sampling point in each row and each column of the DRAM storage array. Anomaly score calculation module 304 is used to calculate the multidimensional anomaly score of each predefined sampling region in the DRAM storage array based on the coarse sampling results; The refined sampling module 306 is used to adaptively perform multi-resolution refined sampling on the sampling region according to the multi-dimensional anomaly score to obtain multi-resolution sampling results; The reconstruction module 308 is used to perform sparse reconstruction on the multi-resolution sampling results based on a pre-trained physical semantic dictionary to obtain the failure bitmap of the DRAM storage array.

[0107] In an exemplary embodiment, the structured sampling matrix further includes a column offset parameter, which defines the starting position of the column sampling point for each sampled row. The column offset parameter is generated based on the number of the storage bank and the row address of the sampled row, such that the starting positions of the column sampling points of different sampled rows within the same bank are offset along the column direction, and the starting positions of the column sampling points between different banks are staggered along the column direction.

[0108] In an exemplary embodiment, the multidimensional anomaly score is a weighted sum of the density anomaly score, pattern anomaly score, context anomaly score, and edge vulnerability factor of the corresponding sampling region; The density anomaly fraction is: ,in, For the first Density anomaly score of each sampling region and These represent the mean and standard deviation of the failure counts, respectively, obtained from coarse sampling on the reference chip. For the first Failure count for each sampling area; The abnormality score of the pattern is: , in, For the first Pattern anomaly score for each sampling region For the first Row alignment of each sampling region For the first Column alignment of each sampling region For the first Clustering coefficients for each sampled region; The context anomaly score is: ,in, For the first Context anomaly score for each sampled region Indicates the first Empirical failure distribution of each sampling region Indicates the first The arithmetic mean of the failure distributions of the neighboring sampling regions of each sampling region; The edge vulnerability factor is: ,in, For the first Edge fragility factor of each sampling region Indicates the first The shortest distance from the center of each sampling region to the edge of the chip. Represents the attenuation constant. This represents the bias boundary weighting coefficient.

[0109] In an exemplary embodiment, the step of adaptively performing multi-resolution refinement sampling on the sampling region based on the multidimensional anomaly score to obtain a multi-resolution sampling result includes: For any of the sampling regions, if the multidimensional anomaly score is determined to be less than the first score threshold, the sampling region is determined to be a normal region, and the refined sampling is terminated. If the multidimensional anomaly score is determined to be greater than or equal to the first score threshold and less than or equal to the second score threshold, the sampling region is determined to be a suspected anomaly region; quadtree refinement sampling is performed on the suspected anomaly region a preset number of times to obtain the multi-resolution sampling result of the suspected anomaly region; the second score threshold is greater than the first score threshold; If the multidimensional anomaly score is determined to be greater than the second score threshold, the sampling region is determined to be an anomaly region. Quadtree refinement sampling is recursively performed on the anomaly region until the minimum resolution is reached, and the multi-resolution sampling result of the anomaly region is obtained.

[0110] In an exemplary embodiment, after recursively performing quadtree thinning sampling on the abnormal region until the minimum resolution is reached, the method further includes: If the system is still abnormal after reaching the minimum resolution, a full scan is performed to obtain the full scan results. Based on the full scan results, the multi-resolution sampling results of the abnormal region are determined.

[0111] In one exemplary embodiment, the recursive quadtree thinning sampling of the abnormal region until the minimum resolution is reached includes: The abnormal region is recursively divided using a quadtree structure to obtain corresponding sub-regions; For the currently divided sub-region, sampling is performed with half the row sampling step size of the corresponding parent region as the new row sampling step size and half the column sampling step size of the corresponding parent region as the new column sampling step size, and the multidimensional anomaly score of the sub-region is calculated. The process is recursively iterated based on the multidimensional anomaly scores of the sub-regions until the minimum resolution is reached.

[0112] In one exemplary embodiment, the physical semantic dictionary includes a plurality of dictionary atoms, each dictionary atom corresponding to a physical failure mode of a DRAM storage array; The pre-trained physical semantic dictionary is used to sparsely reconstruct the multi-resolution sampling results to obtain the failure bitmap of the DRAM storage array, including: The sampling area is divided into multiple regions to be reconstructed based on a preset row and column size, and the hierarchical status of each region to be reconstructed is determined. Based on the hierarchical status of the region to be reconstructed, a corresponding subset of the dictionary is determined from the physical semantic dictionary; Based on the dictionary subset and local sampling matrix of the region to be reconstructed, the failure bitmap of the region to be reconstructed is sparsely reconstructed to obtain the binary failure bitmap of the region to be reconstructed. By merging the binary failure bitmaps of all regions to be rebuilt in the DRAM memory array, a complete failure bitmap of the DRAM memory array is obtained.

[0113] In one exemplary embodiment, the sparse reconstruction is achieved by solving the following LASSO problem: in, This refers to the multi-resolution sampling observation vector of the region to be reconstructed. This is the local sampling matrix of the region to be reconstructed. This is a subset of the dictionary corresponding to the region to be reconstructed. The regularization coefficient is used. This represents the sparse coefficient vector obtained from the reconstruction. Representing vectors The L1 norm.

[0114] Each module in the aforementioned DRAM memory array failure bitmap reconstruction device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0115] In one exemplary embodiment, a computer device is provided, the internal structure of which can be as shown in the figure. Figure 4As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When executed by the processor, the computer program implements a DRAM memory array failure bitmap reconstruction method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0116] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0117] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0118] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.

[0119] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0120] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0121] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0122] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0123] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for reconstructing a failure bitmap of a DRAM memory array, characterized in that, The method includes: A structured sampling matrix is ​​configured based on the physical hierarchy of the DRAM memory array to perform at least one round of structured coarse sampling on the DRAM memory array to obtain coarse sampling results. The physical hierarchy of the DRAM memory array includes four levels: memory bank, row, column, and memory subarray. The structured sampling matrix includes a first sampling step size in the row direction, a second sampling step size in the column direction, and a row sampling start offset configured for each memory bank. The row sampling start offset makes the sampling rows of different memory banks staggered in the row address space. The first sampling step size and the second sampling step size ensure that there is at least one sampling point in each row and each column of the DRAM memory array. Based on the coarse sampling results, calculate the multidimensional anomaly score for each predefined sampling region in the DRAM storage array; Based on the multidimensional anomaly score, multi-resolution refined sampling is adaptively performed on the sampling region to obtain multi-resolution sampling results; Based on a pre-trained physical semantic dictionary, sparse reconstruction is performed on the multi-resolution sampling results to obtain the failure bitmap of the DRAM memory array.

2. The method according to claim 1, characterized in that, The structured sampling matrix also includes a column offset parameter, which defines the starting position of the column sampling point for each sampled row. The column offset parameter is generated based on the number of the memory bank and the row address of the sampled row, so that the starting positions of the column sampling points of different sampled rows in the same memory bank are offset along the column direction, and the starting positions of the column sampling points of different memory banks are staggered along the column direction.

3. The method according to claim 1, characterized in that, The multidimensional anomaly score is a weighted sum of the density anomaly score, pattern anomaly score, context anomaly score, and edge vulnerability factor of the corresponding sampling region; The density anomaly fraction is: ,in, For the first Density anomaly score of each sampling region and These represent the mean and standard deviation of the failure counts, respectively, obtained from coarse sampling on the reference chip. For the first Failure count for each sampling area; The abnormality score of the pattern is: ， in, For the first Pattern anomaly score for each sampling region For the first Row alignment of each sampling region For the first Column alignment of each sampling region For the first Clustering coefficients for each sampled region; The context anomaly score is: ,in, For the first Context anomaly score for each sampled region Indicates the first Empirical failure distribution of each sampling region Indicates the first The arithmetic mean of the failure distributions of the neighboring sampling regions of each sampling region; The edge vulnerability factor is: ,in, For the first Edge fragility factor of each sampling region Indicates the first The shortest distance from the center of each sampling region to the edge of the chip. Represents the attenuation constant. This represents the bias boundary weighting coefficient.

4. The method according to claim 1, characterized in that, The step of adaptively performing multi-resolution refined sampling on the sampling region based on the multidimensional anomaly score to obtain multi-resolution sampling results includes: For any of the sampling regions, if the multidimensional anomaly score is determined to be less than the first score threshold, the sampling region is determined to be a normal region, and the refined sampling is terminated. If the multidimensional anomaly score is determined to be greater than or equal to the first score threshold and less than or equal to the second score threshold, the sampling region is determined to be a suspected anomaly region; quadtree refinement sampling is performed on the suspected anomaly region a preset number of times to obtain the multi-resolution sampling result of the suspected anomaly region; the second score threshold is greater than the first score threshold; If the multidimensional anomaly score is determined to be greater than the second score threshold, the sampling region is determined to be an anomaly region. Quadtree refinement sampling is recursively performed on the anomaly region until the minimum resolution is reached, and the multi-resolution sampling result of the anomaly region is obtained.

5. The method according to claim 4, characterized in that, After recursively performing quadtree thinning sampling on the abnormal region until the minimum resolution is reached, the method further includes: If the system is still abnormal after reaching the minimum resolution, a full scan is performed to obtain the full scan results. Based on the full scan results, the multi-resolution sampling results of the abnormal region are determined.

6. The method according to claim 4, characterized in that, The recursive quadtree refinement sampling of the abnormal region until the minimum resolution is reached includes: The abnormal region is recursively divided using a quadtree structure to obtain corresponding sub-regions; For the currently divided sub-region, sampling is performed with half the row sampling step size of the corresponding parent region as the new row sampling step size and half the column sampling step size of the corresponding parent region as the new column sampling step size, and the multidimensional anomaly score of the sub-region is calculated. The process is recursively iterated based on the multidimensional anomaly scores of the sub-regions until the minimum resolution is reached.

7. The method according to any one of claims 1 to 6, characterized in that, The physical semantic dictionary includes multiple dictionary atoms, each of which corresponds to a physical failure mode of the DRAM storage array; The pre-trained physical semantic dictionary is used to sparsely reconstruct the multi-resolution sampling results to obtain the failure bitmap of the DRAM storage array, including: The sampling area is divided into multiple regions to be reconstructed based on a preset row and column size, and the hierarchical status of each region to be reconstructed is determined. Based on the hierarchical status of the region to be reconstructed, a corresponding subset of the dictionary is determined from the physical semantic dictionary; Based on the dictionary subset and local sampling matrix of the region to be reconstructed, the failure bitmap of the region to be reconstructed is sparsely reconstructed to obtain the binary failure bitmap of the region to be reconstructed. By merging the binary failure bitmaps of all regions to be rebuilt in the DRAM storage array, a complete failure bitmap of the DRAM storage array is obtained.

8. The method according to claim 7, characterized in that, The sparse reconstruction is achieved by solving the following LASSO problem: in, This refers to the multi-resolution sampling observation vector of the region to be reconstructed. This is the local sampling matrix of the region to be reconstructed. This is a subset of the dictionary corresponding to the region to be reconstructed. The regularization coefficient is used. This represents the sparse coefficient vector obtained from the reconstruction. Representing vectors The L1 norm.

9. A DRAM memory array failure bitmap reconstruction apparatus, characterized in that, The device includes: A coarse sampling module is used to configure a structured sampling matrix based on the physical hierarchy of the DRAM storage array, and to perform at least one round of structured coarse sampling on the DRAM storage array to obtain coarse sampling results. The physical hierarchy of the DRAM storage array includes four levels: storage bank, row, column, and storage subarray. The structured sampling matrix includes a first sampling step size in the row direction, a second sampling step size in the column direction, and a row sampling start offset configured for each storage bank. The row sampling start offset makes the sampling rows of different storage banks staggered in the row address space. The first sampling step size and the second sampling step size ensure that there is at least one sampling point in each row and each column of the DRAM storage array. An anomaly score calculation module is used to calculate the multidimensional anomaly score of each predefined sampling region in the DRAM storage array based on the coarse sampling results. A refined sampling module is used to adaptively perform multi-resolution refined sampling on the sampling region based on the multi-dimensional anomaly score to obtain multi-resolution sampling results; The reconstruction module is used to perform sparse reconstruction on the multi-resolution sampling results based on a pre-trained physical semantic dictionary to obtain the failure bitmap of the DRAM storage array.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

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