A laminated chip inductor and a method for manufacturing the same
Patent Information
- Application Number
- CN202611219019.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-12
- Publication Date
- 2026-11-03
AI Technical Summary
Existing surface-mount inductors are prone to breakage when subjected to external impacts, especially those along the width of the inductor. This is particularly true at the external electrode or the junction between the external electrode and the insulator, where the connection reliability is poor and the service life is affected.
The external electrode structure design of the multilayer chip inductor includes embedding two first external electrodes and two second external electrodes in the multilayer body, with part of their surfaces exposed on the outer surface of the multilayer body. The two external electrodes do not contact each other and are respectively connected to the inner electrode patterns of the lead-in layer and the lead-out layer to form a spirally extending coil.
It improves the soldering strength and connection reliability between the inductor and the circuit board, reduces the use of electrode materials, increases the Q value of the inductor, and enhances the inductor's shock resistance.
Smart Images
Figure CN123033879A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of inductor technology, specifically to a multilayer chip inductor and its fabrication method. Background Technology
[0002] Existing chip inductors typically consist of two parts: a multilayer inductor and external electrodes. The multilayer inductor comprises multiple conductive layers and an insulating package. The conductive layers are interconnected and embedded within the insulating package, and are connected to two external electrodes. A portion of each external electrode is exposed outside the insulator, serving as a connection point for electrical connection between the internal conductor and another circuit. The two L-shaped external electrodes are soldered to and electrically connected to a circuit board. In practical applications, stress tends to concentrate on the external electrodes of the multilayer inductor. When the inductor is subjected to external impact, especially along its width, it is prone to breakage. The breakage usually occurs at the external electrodes or at the junction of the external electrodes and the insulator.
[0003] Therefore, how to improve the external electrode structure of multilayer chip inductors, enhance connection reliability, and increase the service life of inductors under harsh conditions is an urgent problem to be solved. Summary of the Invention
[0004] Based on the deficiencies of the existing technology, the purpose of this application is to provide a multilayer chip inductor and its fabrication method.
[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: In a first aspect, this application provides a multilayer chip inductor, which includes a multilayer body, the multilayer body including a first cover plate, an inlet layer, a coil conductor region, an outlet layer and a second cover plate arranged sequentially along its width direction; The inlet layer is provided with a first inner electrode pattern, the coil conductor area is provided with at least one second inner electrode pattern, and the outlet layer is provided with a third inner electrode pattern. The first inner electrode pattern, at least one second inner electrode pattern, and the third inner electrode pattern are connected by an electrode connection portion to form a spirally extending coil. The stacked body further includes two first external electrodes and two second external electrodes. The first external electrodes are embedded in the stacked body, and a portion of the surface of the first external electrode is exposed on the outer surface of the stacked body. The second external electrodes are embedded in the stacked body, and a portion of the surface of the second external electrode is exposed on the outer surface of the stacked body. The two first external electrodes and the two second external electrodes do not contact each other. Any one of the two first external electrodes is connected to the first inner electrode pattern of the introduction layer, and any one of the two second external electrodes is connected to the third inner electrode pattern of the lead-out layer.
[0006] Preferably, the laminate has a first surface, a second surface, a third surface, a fourth surface, a fifth surface, and a sixth surface. The first surface and the second surface are disposed opposite each other along the length direction of the laminate, the third surface and the fourth surface are disposed opposite each other along the height direction of the laminate, and the fifth surface and the sixth surface are disposed opposite each other along the width direction of the laminate. The first external electrode has a first exposed surface, a second exposed surface, and a third exposed surface. The first exposed surface is exposed on the first surface, the second exposed surface is exposed on the third surface, and in the two first external electrodes, the third exposed surface of one first external electrode is exposed on the fifth surface, and the third exposed surface of the other first external electrode is exposed on the sixth surface. The second external electrode has a fourth exposed surface, a fifth exposed surface, and a sixth exposed surface. The fourth exposed surface is exposed on the second surface, and the fifth exposed surface is exposed on the third surface. In the two second external electrodes, the sixth exposed surface of one second external electrode is exposed on the fifth surface, and the sixth exposed surface of the other second external electrode is exposed on the sixth surface.
[0007] More preferably, the length of the stacked body is L, the width of the stacked body is W, and the height of the stacked body is H; The dimension of the first exposed surface in the width direction of the laminate is equal to the dimension of the second exposed surface in the width direction of the laminate, and is denoted as w1; the dimension of the first exposed surface in the height direction of the laminate is denoted as h1, and the dimension of the second exposed surface in the length direction of the laminate is denoted as h1. l 1; The dimension of the fourth exposed surface in the width direction of the laminate is equal to the dimension of the fifth exposed surface in the width direction of the laminate, and is denoted as w2; the dimension of the fourth exposed surface in the height direction of the laminate is denoted as h2, and the dimension of the fifth exposed surface in the length direction of the laminate is denoted as h2. l 2; The stacked body satisfies: L / ( l 1+ l 2) is 3~8, and / or, W / (w1+w2) is 3~8, and / or, H / (h1+h2) is 2~4.
[0008] Further preferred, L / ( l 1+ l 2) is 4~6, and / or, W / (w1+w2) is 4~6.
[0009] More preferably, the first exposed surface is square, the second exposed surface is square, the fourth exposed surface is square, and the fifth exposed surface is square.
[0010] More preferably, the two first external electrodes and the two second external electrodes are respectively disposed in the four apex regions of the stack.
[0011] More preferably, the third and sixth exposed surfaces have inwardly concave arc-shaped edges.
[0012] Preferably, the number of the first cover sheets is no less than two layers, and the first cover sheets of no less than two layers are stacked sequentially along the width direction of the stacked body.
[0013] Preferably, the number of the second cover sheets is no less than two layers, and the two or more layers of the second cover sheets are stacked sequentially along the width direction of the stacked body.
[0014] Preferably, the coil conductor region includes at least one first dielectric layer and at least two second dielectric layers, the first dielectric layer and the second dielectric layer are alternately stacked along the width direction, each first dielectric layer is provided with a second inner electrode pattern, and the electrode connection portion passes through the through hole corresponding to the second dielectric layer.
[0015] Secondly, this application provides a method for fabricating a multilayer chip inductor as described in the first aspect, comprising the following steps: S1. Print photosensitive ceramic pastes separately to obtain several ceramic paste layers used to prepare the first cover plate, the lead-in layer, the first dielectric layer, the second dielectric layer, the lead-out layer, and the second cover plate; S2. Lay out the corresponding patterned mask on each ceramic slurry layer and expose it to solidify the exposed parts of each ceramic slurry layer and form a solidified layer; remove the mask, wash away the uncured coating with developer, and independently form patterned grooves corresponding to the desired electrode pattern on each solidified layer. S3. Print electrode paste on each cured layer to form an electrode paste layer and fill the pattern groove with electrode paste. Then, place a mask plate corresponding to the shape of the pattern groove on the electrode paste layer and expose it to cure the exposed part of the electrode paste and form the corresponding electrode pattern. Remove the mask plate and wash away the uncured electrode paste layer with developer to obtain the corresponding printed film. S4. Stack the printed sheets according to the structure of the stacked body, then press and cut them into green blanks; S5. The green blank is sintered to obtain the multilayer chip inductor.
[0016] Preferably, the sintering process is carried out in an air atmosphere at a temperature of 800-860°C for 60-90 minutes.
[0017] Compared with the prior art, the beneficial effects of this application are as follows: This application embeds two first external electrodes and two second external electrodes into the stacked body of a multilayer inductor, with a portion of the surface of the first external electrode exposed on the outer surface of the stacked body, and a portion of the surface of the second external electrode exposed on the outer surface of the stacked body. The two first external electrodes and the two second external electrodes do not contact each other. Any one of the two first external electrodes is connected to the first inner electrode pattern of the lead-in layer, and any one of the two second external electrodes is connected to the third inner electrode pattern of the lead-out layer. This external electrode structure can provide a larger soldering area, thereby effectively improving the soldering strength and connection reliability between the inductor and the circuit board. The external electrode configuration method adopted in this application can save electrode material and enable the inductor to have a higher Q value. Attached Figure Description
[0018] Figure 1 A split schematic diagram of the multilayer chip inductor provided in this application; Figure 2 A perspective view of the multilayer chip capacitor provided in this application; Figure 3 A perspective view of the multilayer chip capacitor provided in this application from another angle; Figure 4 This is a perspective view of the multilayer chip capacitor provided in Comparative Example 2 of this application; Figure 5 This is a perspective view of the multilayer chip capacitor provided in Comparative Example 3 of this application; Figure 6 This is a perspective view of the multilayer chip capacitor provided in Comparative Example 4 of this application; Figure 7 This is a perspective view of the multilayer chip capacitor provided in Comparative Example 5 of this application; Figure 8 This is a perspective view of the multilayer chip capacitor provided in Comparative Example 6 of this application; Figure 9 This is a perspective view of the multilayer chip capacitor provided in Comparative Example 7 of this application; Figure 10 This is a perspective view of the multilayer chip capacitor provided in Comparative Example 8 of this application.
[0019] In the figure, 1 is the first cover plate, 2 is the lead-in layer, 3 is the coil conductor area, 31 is the first dielectric layer, 32 is the second dielectric layer, 4 is the lead-out layer, 5 is the second cover plate, 6 is the first external electrode, 61 is the first exposed surface, 62 is the second exposed surface, 63 is the third exposed surface, 7 is the second external electrode, 71 is the fourth exposed surface, 72 is the fifth exposed surface, 73 is the sixth exposed surface, 81 is the first internal electrode pattern, 82 is the second internal electrode pattern, 83 is the third internal electrode pattern, and 84 is the electrode connection part. Detailed Implementation
[0020] To better illustrate the purpose, technical solution, and advantages of this application, the following detailed description, in conjunction with specific embodiments, aims to provide a thorough understanding of the application's content, rather than limiting it. All other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.
[0021] In the description of the embodiments herein, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the embodiments herein and for simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments herein.
[0022] In the description of the embodiments herein, unless otherwise explicitly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments herein according to the specific circumstances.
[0023] In the description of the embodiments herein, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments herein, "multiple" means two or more, unless otherwise explicitly defined.
[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this applies; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this document; the terms “comprising” and “having”, and any variations thereof, in the description, claims, and accompanying drawings herein are intended to cover non-exclusive inclusion.
[0025] In this document, the term "implementation" means that a particular feature, structure, or characteristic described in connection with an implementation can be included in at least one implementation described herein. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same implementation, nor is it a separate or alternative implementation mutually exclusive with other implementations. It will be explicitly and implicitly understood by those skilled in the art that the implementations described herein can be combined with other implementations.
[0026] In the description of the embodiments herein, "several groups" refers to two or more groups (including two groups), and "several individuals" refers to two or more individuals (including two individuals).
[0027] Firstly, please refer to Figures 1-3 This application provides a multilayer chip inductor, which includes a multilayer body, wherein the multilayer body includes a first cover plate 1, an inlet layer 2, a coil conductor region 3, an outlet layer 4 and a second cover plate 5 arranged sequentially along its width direction; The inlet layer 2 is provided with a first inner electrode pattern 81, the coil conductor region 3 is provided with at least one second inner electrode pattern 82, and the outlet layer 3 is provided with a third inner electrode pattern 83. The first inner electrode pattern 81, at least one second inner electrode pattern 82 and the third inner electrode pattern 83 are connected by an electrode connection portion 84 to form a spirally extending coil. The stacked body further includes two first external electrodes 6 and two second external electrodes 7. The first external electrodes 6 are embedded in the stacked body, and a portion of the surface of the first external electrode 6 is exposed on the outer surface of the stacked body. The second external electrodes 7 are embedded in the stacked body, and a portion of the surface of the second external electrode 7 is exposed on the outer surface of the stacked body. The two first external electrodes 6 and the two second external electrodes 7 do not contact each other. Any one of the two first external electrodes 6 is connected to the first inner electrode pattern 81 of the introduction layer 2, and any one of the two second external electrodes 7 is connected to the third inner electrode pattern 83 of the lead-out layer 4.
[0028] Compared to the L-shaped external electrode structure in existing inductors, this application embeds two first external electrodes 6 and two second external electrodes 7 into the stacked body of a multilayer inductor, with a portion of the surface of the first external electrode 6 and a portion of the surface of the second external electrode 7 exposed on the outer surface of the stacked body. The two first external electrodes 6 and the two second external electrodes 7 do not contact each other. Any one of the two first external electrodes 6 is connected to the first inner electrode pattern 81 located in the lead-in layer 2, and any one of the two second external electrodes 7 is connected to the third inner electrode pattern 83 located in the lead-out layer 4. This external electrode structure can provide a larger soldering area, thereby effectively improving the soldering strength and connection reliability between the inductor and the circuit board.
[0029] In existing inductors, each layer has an external electrode, and the external electrodes of adjacent layers are connected together or form a fence-type external electrode. This significantly increases the area between the electrodes, resulting in a large parasitic capacitance, which affects the Q value of the inductor and leads to increased losses at high frequencies. Compared with the above-mentioned external electrode arrangement, the external electrode arrangement of this application can save electrode material and enable the inductor to have a higher Q value.
[0030] In this application, any one of the two first external electrodes 6 is connected to the first internal electrode pattern 81 located in the lead-in layer 2, and any one of the two second external electrodes 7 is connected to the third internal electrode pattern 83 located in the lead-out layer 4. The second internal electrode pattern in the coil conductor area does not contact the first external electrode 6 and the second external electrode 7, which can avoid short circuit.
[0031] In some embodiments, the laminate has a first surface, a second surface, a third surface, a fourth surface, a fifth surface, and a sixth surface, wherein the first surface and the second surface are disposed opposite to each other along the length direction of the laminate, the third surface and the fourth surface are disposed opposite to each other along the height direction of the laminate, and the fifth surface and the sixth surface are disposed opposite to each other along the width direction of the laminate. The first external electrode 6 has a first exposed surface 61, a second exposed surface 62 and a third exposed surface 63. The first exposed surface 61 is exposed on the first surface, the second exposed surface 62 is exposed on the third surface, and in the two first external electrodes 6, the third exposed surface 63 of one first external electrode 6 is exposed on the fifth surface, and the third exposed surface 63 of the other first external electrode 6 is exposed on the sixth surface. The second external electrode 7 has a fourth exposed surface 71, a fifth exposed surface 72, and a sixth exposed surface 73. The fourth exposed surface 71 is exposed on the second surface, and the fifth exposed surface 72 is exposed on the third surface. In the two second external electrodes 7, the sixth exposed surface 73 of one second external electrode 7 is exposed on the fifth surface, and the sixth exposed surface 73 of the other second external electrode 7 is exposed on the sixth surface.
[0032] In some embodiments, the length of the stack is L, the width of the stack is W, and the height of the stack is H; The dimension of the first exposed surface 61 in the width direction of the laminate is equal to the dimension of the second exposed surface 62 in the width direction of the laminate, and is denoted as w1; the dimension of the first exposed surface 61 in the height direction of the laminate is denoted as h1, and the dimension of the second exposed surface 62 in the length direction of the laminate is denoted as h1. l 1; The dimension of the fourth exposed surface 71 in the width direction of the laminate is equal to the dimension of the fifth exposed surface 72 in the width direction of the laminate, and is denoted as w2. The dimension of the fourth exposed surface 71 in the height direction of the laminate is denoted as h2, and the dimension of the fifth exposed surface 72 in the length direction of the laminate is denoted as h2. l 2; The stacked body satisfies: L / ( l 1+ l 2) is 3~8, and / or, W / (w1+w2) is 3~8, and / or, H / (h1+h2) is 2~4.
[0033] For example, L / ( l 1+ l 2) It can be a range of values consisting of any one or any two of the following: 3, 3.2, 3.5, 3.8, 4, 4.2, 4.5, 4.8, 5, 5.2, 5.5, 5.8, 6, 6.2, 6.5, 6.8, 7, 7.2, 7.5, 7.8, 8.
[0034] For example, W / (w1+w2) can be a range of values consisting of any one or any two of the following: 3, 3.2, 3.5, 3.8, 4, 4.2, 4.5, 4.8, 5, 5.2, 5.5, 5.8, 6, 6.2, 6.5, 6.8, 7, 7.2, 7.5, 7.8, 8.
[0035] For example, H / (h1+h2) can be a range of values consisting of any one or any two of the following: 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6, 3.7, 3.8, 3.9, and 4.
[0036] The inventor discovered through research that if L / ( l 1+ l 2) When W / (w1+w2) and H / (h1+h2) exceed their respective ranges, the area available for welding the inductor decreases, significantly reducing the strength of subsequent welds. Consequently, the welded inductor fails to meet national standards in tensile, shear, and bending tests. If L / ( l 1+ l 2) When W / (w1+w2) and H / (h1+h2) are lower than their respective ranges, the parasitic parameters formed between the external and internal electrodes of the inductor increase, causing the Q value to decrease and the loss to increase.
[0037] In some of these implementations, L / ( l 1+ l 2) is 4~6, and / or, W / (w1+w2) is 4~6.
[0038] In some of these implementations, l 1 and l 2 are equal, w1 and w2 are equal.
[0039] In some embodiments, the first exposed surface 61 is square, the second exposed surface 62 is square, the fourth exposed surface 71 is square, and the fifth exposed surface 72 is square.
[0040] In some embodiments, two first external electrodes 6 and two second external electrodes 7 are respectively disposed in the four apex regions of the stack.
[0041] Through research, the inventors discovered that the two first external electrodes 6 and the two second external electrodes 7 are not in contact with each other and are respectively set in four different apex regions of the laminate, forming a four-pin structure. This provides four symmetrical external electrode positions for welding and fixing the inductor, which can evenly distribute the physical stress in all directions of the inductor, making the inductor more impact-resistant, more accurate in reflow soldering positioning, and less prone to displacement.
[0042] In some embodiments, the dimension of the third exposed surface 63 in the height direction of the stack is equal to the dimension of the first exposed surface 61 in the height direction of the stack, and the dimension of the third exposed surface 63 in the length direction of the stack is the same as the dimension of the second exposed surface 62 in the length direction of the stack.
[0043] In some embodiments, the sixth exposed surface 73 has the same dimension in the height direction of the stack as the fourth exposed surface 71 in the height direction of the stack, and the third exposed surface 63 has the same dimension in the length direction of the stack as the fifth exposed surface 72 in the length direction of the stack.
[0044] In some embodiments, both the third exposed surface 63 and the sixth exposed surface 73 have inwardly recessed arc-shaped edges.
[0045] The exposed surfaces on the fifth and sixth surfaces also provide area for solder bonding. The curved edge design reduces the impact of parasitic parameters on the inductor, thus enabling the inductor to achieve a higher Q value.
[0046] In some embodiments, the number of first cover sheets 1 is not less than two layers, and the first cover sheets 1 of not less than two layers are stacked sequentially along the width direction of the stacked body.
[0047] In some embodiments, the number of second cover sheets 5 is not less than two layers, and the two layers of second cover sheets 5 are stacked sequentially along the width direction of the stacked body.
[0048] In some embodiments, the coil conductor region 3 includes at least one first dielectric layer 31 and at least two second dielectric layers 32, with the first dielectric layer 31 and the second dielectric layer 32 alternately stacked along the width direction. Each first dielectric layer 31 is provided with a second inner electrode pattern 82, and the electrode connection portion 84 passes through the through hole corresponding to the second dielectric layer 32.
[0049] When the number of first dielectric layers 31 is not less than two, any two adjacent second inner electrode patterns 82 are connected by an electrode connection part 84. The second inner electrode pattern 82 at the beginning is connected to the first inner electrode pattern 81 by an electrode connection part 84, and the second inner electrode pattern 82 at the end is connected to the third inner electrode pattern 83 by an electrode connection part 84.
[0050] Secondly, this application provides a method for fabricating a multilayer chip inductor as described in the first aspect, comprising the following steps: S1. Print photosensitive ceramic paste separately to obtain a ceramic paste layer for preparing the first cover plate, the lead-in layer, the first dielectric layer, the second dielectric layer, the lead-out layer and the second cover plate; S2. Lay out the corresponding patterned mask on each ceramic slurry layer and expose it to solidify the exposed parts of each ceramic slurry layer and form a solidified layer; remove the mask and wash away the uncured coating with developer, and the washed-away parts form patterned grooves. S3. Print electrode paste on each cured layer to form an electrode paste layer and fill the pattern groove with electrode paste. Then, place a mask plate corresponding to the shape of the pattern groove on the electrode paste layer and expose it to solidify the exposed part of the electrode paste and form an electrode pattern. Remove the mask plate and wash away the uncured electrode paste layer with developer to obtain the printed film. S4. Stack the printed sheets according to the structure of the stacked body, then press and cut them into green blanks; S5. The green blank is sintered to obtain the multilayer chip inductor.
[0051] In some embodiments, the sintering process is carried out in an air atmosphere at a temperature of 800-860°C for 60-90 minutes.
[0052] The following embodiments are provided to facilitate understanding of the present application. These embodiments are provided not to limit the scope of the claims.
[0053] Unless otherwise specified, all components and raw materials used in the embodiments and comparative examples of this application are commercially available, and the same type of components and raw materials are used in each parallel experiment.
[0054] Examples 1-9 Examples 1-9 each provide a multilayer chip inductor; please refer to [link / reference]. Figures 1-3The multilayer chip inductor includes a multilayer body, which includes a first cover plate 1, an inlet layer 2, a coil conductor region 3, an outlet layer 4, and a second cover plate 5 arranged sequentially along its width direction. The multilayer body also includes two first external electrodes 6 and two second external electrodes 7. The inlet layer 2 is provided with a first inner electrode pattern 81, the coil conductor region 3 is provided with at least one second inner electrode pattern 82, and the outlet layer 3 is provided with a third inner electrode pattern 83. The first inner electrode pattern 81, at least one second inner electrode pattern 82 and the third inner electrode pattern 83 are connected by an electrode connection portion 84 to form a spirally extending coil. The stacked body further includes two first external electrodes 6 and two second external electrodes 7. The first external electrodes 6 are embedded in the stacked body, and a portion of the surface of the first external electrodes 6 is exposed on the outer surface of the stacked body. The second external electrodes 7 are embedded in the stacked body, and a portion of the surface of the second external electrodes 7 is exposed on the outer surface of the stacked body. The two first external electrodes 6 and the two second external electrodes 7 are located in four different apex regions of the stacked body, and the two first external electrodes 6 and the two second external electrodes 7 do not contact each other. Any one of the two first external electrodes 6 is connected to the first inner electrode pattern 81 of the introduction layer 2, and any one of the two second external electrodes 7 is connected to the third inner electrode pattern 83 of the lead-out layer 4.
[0055] The laminate has a first surface, a second surface, a third surface, a fourth surface, a fifth surface, and a sixth surface. The first surface and the second surface are arranged opposite each other along the length direction of the laminate, the third surface and the fourth surface are arranged opposite each other along the height direction of the laminate, and the fifth surface and the sixth surface are arranged opposite each other along the width direction of the laminate. The first external electrode 6 has a first exposed surface 61, a second exposed surface 62 and a third exposed surface 63. The first exposed surface 61 is exposed on the first surface, the second exposed surface 62 is exposed on the third surface, and in the two first external electrodes 6, the third exposed surface 63 of one first external electrode 6 is exposed on the fifth surface, and the third exposed surface 63 of the other first external electrode 6 is exposed on the sixth surface. The second external electrode 7 has a fourth exposed surface 71, a fifth exposed surface 72, and a sixth exposed surface 73. The fourth exposed surface 71 is exposed on the second surface, and the fifth exposed surface 72 is exposed on the third surface. In the two second external electrodes 7, the sixth exposed surface 73 of one second external electrode 7 is exposed on the fifth surface, and the sixth exposed surface 73 of the other second external electrode 7 is exposed on the sixth surface.
[0056] The length of the stack is L, the width of the stack is W, and the height of the stack is H. The dimension of the first exposed surface 61 in the width direction of the laminate is equal to the dimension of the second exposed surface 62 in the width direction of the laminate, and is denoted as w1; the dimension of the first exposed surface 61 in the height direction of the laminate is denoted as h1, and the dimension of the second exposed surface 62 in the length direction of the laminate is denoted as h1. l 1; The dimension of the fourth exposed surface 71 in the width direction of the laminate is equal to the dimension of the fifth exposed surface 72 in the width direction of the laminate, and is denoted as w2. The dimension of the fourth exposed surface 71 in the height direction of the laminate is denoted as h2, and the dimension of the fifth exposed surface 72 in the length direction of the laminate is denoted as h2. l 2; L=1.8mm, W=0.9mm, H=0.9mm, l 1= l 2, w1=w2, h1=h2, the width of the lead-in layer and the width of the lead-out layer are 0.09mm, the width of the first cover plate, the width of the second cover plate, and the width of each layer in the coil conductor area are all 0.08mm, L / ( l 1+ l 2) W / (w1+w2) and H / (h1+h2) are shown in Table 1.
[0057] The first exposed surface 61 is square, the second exposed surface 62 is square, the fourth exposed surface 71 is square, and the fifth exposed surface 72 is square.
[0058] The dimension of the third exposed surface 63 in the height direction of the laminate is equal to the dimension of the first exposed surface 61 in the height direction of the laminate, and the dimension of the third exposed surface 63 in the length direction of the laminate is the same as the dimension of the second exposed surface 62 in the length direction of the laminate.
[0059] The sixth exposed surface 73 has the same dimension in the height direction of the laminate as the fourth exposed surface 71 in the height direction of the laminate, and the third exposed surface 63 has the same dimension in the length direction of the laminate as the fifth exposed surface 72 in the length direction of the laminate.
[0060] Both the third exposed surface 63 and the sixth exposed surface 73 have inwardly recessed arc-shaped edges with an arc radius of π / 2. The coil conductor region includes three first dielectric layers 31 and four second dielectric layers 32. The first dielectric layers 31 and the second dielectric layers 32 are alternately stacked along the width direction. Each first dielectric layer 31 is provided with a second inner electrode pattern 82, and the electrode connection portion 84 passes through the through hole corresponding to the second dielectric layer 32.
[0061] The dimensions of the first dielectric layer 31 in the width direction of the stack are equal to the dimensions of the second dielectric layer 32 in the width direction of the stack.
[0062] The method for fabricating the multilayer chip inductor includes the following steps: S1. Print photosensitive ceramic pastes separately to obtain several ceramic paste layers used to prepare the first cover plate, the lead-in layer, the first dielectric layer, the second dielectric layer, the lead-out layer, and the second cover plate; S2. A patterned mask is laid on each ceramic slurry layer, and ultraviolet light is used for exposure to cure the exposed parts of each ceramic slurry layer and form a cured layer; the mask is removed, and the uncured coating is washed away with a developer, thereby forming a patterned groove corresponding to the desired electrode pattern independently on each cured layer (for example, a patterned groove corresponding to the first inner electrode pattern is formed on the cured layer used to prepare the introduction layer, and a patterned groove corresponding to the electrode connection portion is formed on the cured layer used to prepare the second dielectric layer). S3. Print electrode paste on each cured layer. The electrode paste used is a commercially available metal paste. Form an electrode paste layer and fill the pattern groove with electrode paste. Then, place a mask plate corresponding to the shape of the pattern groove on the electrode paste layer. Expose the electrode paste with ultraviolet light to cure the exposed part of the electrode paste and form the corresponding electrode pattern. Remove the mask plate and wash away the uncured electrode paste layer with developer to obtain the corresponding printed film. S4. Stack the printed sheets according to the structure of the stacked body, then press and cut them into green blanks; S5. The green blank is sintered in an air atmosphere at a temperature of 850°C for 80 minutes to obtain the inductor.
[0063] Examples 10-11 The difference between Embodiments 10-11 and Embodiment 1 is that the coil conductor region of Embodiments 10-11 includes six first dielectric layers 31 and seven second dielectric layers 32. The width of the lead-in layer and the width of the lead-out layer are both 0.075 mm. The width of the first cover plate, the width of the second cover plate and the width of each layer of the coil conductor region are all 0.05 mm.
[0064] Comparative Example 1 The difference between this comparative example and Example 1 is that this comparative example does not have a first cover plate and a second cover plate.
[0065] Comparative Example 2 The difference between this comparative example and Example 1 is that, in this comparative example, as Figure 4 As shown, the first external electrode does not have a third exposed surface, and the second external electrode does not have a sixth exposed surface.
[0066] Comparative Example 3 The difference between this comparative example and Example 1 is that, Figure 5As shown, in this comparative example, the first outer electrode does not contact the first inner electrode pattern, and the second outer electrode does not contact the third inner electrode pattern.
[0067] Comparative Example 4 The difference between this comparative example and Example 1 is that, Figure 6 As shown in this comparative example, both the first external electrode 6 and the second external electrode 7 have only one exposed surface. The first external electrode 6 is not exposed on the first surface and the third surface, and the second external electrode 7 is not exposed on the second surface and the third surface.
[0068] Comparative Example 5 The difference between this comparative example and Example 1 is that, Figure 7 As shown, in this comparative example, there is one first external electrode 6 and one second external electrode 7. Both the first external electrode 6 and the second external electrode 7 extend from the fifth surface of the laminate to the sixth surface of the laminate along the width direction of the laminate, such that w1=w2=W. The exposed surfaces of the first external electrode 6 on the fifth surface and the exposed surfaces on the sixth surface of this comparative example have the same shape and size as the third exposed surface of Example 1. The exposed surfaces of the second external electrode 7 on the fifth surface and the exposed surfaces on the sixth surface of this comparative example have the same shape and size as the sixth exposed surface of Example 1.
[0069] Comparative Example 6 The difference between this comparative example and Example 1 is that, Figure 8 As shown, in this comparative example, there are four first external electrodes 6 and four second external electrodes 6. The four first external electrodes are evenly distributed in the width direction of the laminate. The two first external electrodes 6 in the middle have only the first exposed surface and the second exposed surface. The four second external electrodes are evenly distributed in the width direction of the laminate. The two second external electrodes 7 in the middle have only the fourth exposed surface and the fifth exposed surface.
[0070] Comparative Example 7 The difference between this comparative example and Example 1 is that, Figure 9 As shown, in this comparative example, one first external electrode 6 is arranged diagonally opposite to another first external electrode, and another first external electrode 6 is arranged diagonally opposite to another first external electrode. The fourth exposed surfaces 71 of both second external electrodes 7 are exposed on the second surface, the fifth exposed surfaces of both second external electrodes 7 are exposed on the fourth surface, the sixth exposed surface 73 of one first external electrode 7 is exposed on the fifth surface, and the sixth exposed surface of the other external electrode 7 is exposed on the sixth surface.
[0071] Comparative Example 8 The difference between this comparative example and Example 1 is that, Figure 10As shown, in this comparative example, one first external electrode 6 is arranged diagonally opposite to another first external electrode, and the other first external electrode 6 is arranged diagonally opposite to another first external electrode. The first exposed surfaces of both first external electrodes 6 are exposed on the first surface of the laminate, and the third exposed surfaces 63 of both first external electrodes are exposed on the fifth surface of the laminate. Among the two first external electrodes 6, the second exposed surface 62 of one first external electrode 6 is exposed on the third surface of the laminate, and the second exposed surface of the other first external electrode 6 is exposed on the fourth surface of the laminate. The fourth exposed surface 71 of both external electrodes 7 is exposed on the second surface of the laminate, and the sixth exposed surface of both external electrodes 7 is exposed on the sixth surface of the laminate. Among the two second external electrodes 7, the fifth exposed surface 72 of one second external electrode 7 is exposed on the third surface of the laminate, and the fifth exposed surface 72 of the other second external electrode 7 is exposed on the fourth surface of the laminate.
[0072] Comparative Examples 9-14 The difference between Comparative Examples 9-14 and Example 1 is that in Comparative Examples 9-14, L / ( l 1+ l 2) W / (w1+w2) and H / (h1+h2) are shown in Table 1.
[0073] Table 1 Example of effect The inductors obtained in the above embodiments and comparative examples were reflow soldered onto a test board for performance testing. The test methods are shown in Table 2 below, and the test results are shown in Table 3.
[0074] Table 2 Table 3 As can be seen from Table 3, the embodiments of this application embed two first external electrodes and two second external electrodes into the stacked body of the multilayer inductor, with a portion of the surface of the first external electrode exposed on the outer surface of the stacked body, and a portion of the surface of the second external electrode exposed on the outer surface of the stacked body. The two first external electrodes and the two second external electrodes do not contact each other. Any one of the two first external electrodes is connected to the first inner electrode pattern of the lead-in layer, and any one of the two second external electrodes is connected to the third inner electrode pattern of the lead-out layer. This external electrode structure can not only provide a larger welding area, thereby effectively improving the welding strength and connection reliability of the inductor, making the tensile test value not less than 5.66N, the shear test value not less than 2.57N, and the weld seam not cracking during the bending test, but also improve the L value and Q value of the multilayer chip inductor, with the L value not less than 4.248 and the Q value not less than 17.9.
[0075] Compared with Example 1, Comparative Example 1 does not have a first cover and a second cover, and the internal electrodes of the inductor are exposed and have no electrical properties.
[0076] Compared with Example 1, Comparative Example 2 uses a first external electrode that does not have a third exposed surface and a second external electrode that does not have a sixth exposed surface, which reduces the welding strength of the inductor.
[0077] Compared with Example 1, in Comparative Example 3, the second outer electrode does not contact the first inner electrode pattern, and the third outer electrode does not contact the third inner electrode pattern, thus failing to realize the function of the inductor itself.
[0078] Compared with Example 1, in Comparative Example 4, the first external electrode is not exposed on the first and third surfaces, and the second external electrode is not exposed on the second and third surfaces, which significantly deteriorates the welding strength and connection reliability of the inductor.
[0079] Compared with Example 1, in Comparative Example 5, both the first and second external electrodes extend from the fifth surface of the laminate to the sixth surface of the laminate along the width direction of the laminate, making w1=w2=W, which significantly reduces the Q value of the inductor.
[0080] Compared to Example 1, Comparative Example 6 uses a fence-type external electrode, which significantly reduces the Q value of the inductor.
[0081] Compared with Example 1, the distribution of the first external electrode and the second external electrode in Comparative Examples 7-8 is unreasonable, which significantly reduces the welding strength and connection reliability of the inductor.
[0082] Compared with Example 1, in Comparative Example 9, L / ( l 1+ l 2) Excessive values: In Comparative Example 11, W / (w1+w2) is too large; in Comparative Example 13, H / (h1+h2) is too large, significantly reducing the welding strength and connection reliability of the inductor; in Comparative Example 10, L / ( l 1+ l 2) Too small. In Comparative Example 12, W / (w1+w2) is too small, and in Comparative Example 14, H / (h1+h2) is too small, causing the L value and Q value of the inductor to decrease significantly.
[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit the scope of protection of this application. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the substance and scope of the technical solutions of this application.
Claims
1. A multilayer chip inductor, characterized in that, The stack includes a multilayer body, which comprises a first cover plate, an inlet layer, a coil conductor region, an outlet layer, and a second cover plate arranged sequentially along its width direction. The inlet layer is provided with a first inner electrode pattern, the coil conductor area is provided with at least one second inner electrode pattern, and the outlet layer is provided with a third inner electrode pattern. The first inner electrode pattern, at least one second inner electrode pattern, and the third inner electrode pattern are connected by an electrode connection portion to form a spirally extending coil. The stacked body further includes two first external electrodes and two second external electrodes. The first external electrodes are embedded in the stacked body, and a portion of the surface of the first external electrode is exposed on the outer surface of the stacked body. The second external electrodes are embedded in the stacked body, and a portion of the surface of the second external electrode is exposed on the outer surface of the stacked body. The two first external electrodes and the two second external electrodes do not contact each other. Any one of the two first external electrodes is connected to the first inner electrode pattern of the introduction layer, and any one of the two second external electrodes is connected to the third inner electrode pattern of the lead-out layer.
2. The multilayer chip inductor as described in claim 1, characterized in that, The laminate has a first surface, a second surface, a third surface, a fourth surface, a fifth surface, and a sixth surface. The first surface and the second surface are arranged opposite each other along the length direction of the laminate, the third surface and the fourth surface are arranged opposite each other along the height direction of the laminate, and the fifth surface and the sixth surface are arranged opposite each other along the width direction of the laminate. The first external electrode has a first exposed surface, a second exposed surface, and a third exposed surface. The first exposed surface is exposed on the first surface, the second exposed surface is exposed on the third surface, and in the two first external electrodes, the third exposed surface of one first external electrode is exposed on the fifth surface, and the third exposed surface of the other first external electrode is exposed on the sixth surface. The second external electrode has a fourth exposed surface, a fifth exposed surface, and a sixth exposed surface. The fourth exposed surface is exposed on the second surface, and the fifth exposed surface is exposed on the third surface. In the two second external electrodes, the sixth exposed surface of one second external electrode is exposed on the fifth surface, and the sixth exposed surface of the other second external electrode is exposed on the sixth surface.
3. The multilayer chip inductor as described in claim 2, characterized in that, The length of the stack is L, the width of the stack is W, and the height of the stack is H. The dimension of the first exposed surface in the width direction of the laminate is equal to the dimension of the second exposed surface in the width direction of the laminate, and is denoted as w1; the dimension of the first exposed surface in the height direction of the laminate is denoted as h1, and the dimension of the second exposed surface in the length direction of the laminate is denoted as h1. l 1; The dimension of the fourth exposed surface in the width direction of the laminate is equal to the dimension of the fifth exposed surface in the width direction of the laminate, and is denoted as w2; the dimension of the fourth exposed surface in the height direction of the laminate is denoted as h2, and the dimension of the fifth exposed surface in the length direction of the laminate is denoted as h2. l 2; The stacked body satisfies: L / ( l 1+ l 2) is 3~8, and / or, W / (w1+w2) is 3~8, and / or, H / (h1+h2) is 2~4.
4. The multilayer chip inductor as described in claim 3, characterized in that, L / ( l 1+ l 2) is 4~6, and / or, W / (w1+w2) is 4~6.
5. The multilayer chip inductor as described in claim 2, characterized in that, Two first external electrodes and two second external electrodes are respectively disposed in the four vertices of the stack.
6. The multilayer chip inductor as described in claim 2, characterized in that, The third and sixth exposed surfaces have inwardly concave arc-shaped edges.
7. The multilayer chip inductor as described in claim 1, characterized in that, The number of the first cover sheet is no less than two layers, and the first cover sheet of no less than two layers is stacked sequentially along the width direction of the stacked body; and / or, the number of the second cover sheet is no less than two layers, and the second cover sheet of no less than two layers is stacked sequentially along the width direction of the stacked body.
8. The multilayer chip inductor as described in claim 1, characterized in that, It includes at least one first dielectric layer and at least two second dielectric layers, wherein the first dielectric layer and the second dielectric layer are stacked alternately along the width direction, each first dielectric layer is provided with a second inner electrode pattern, and the electrode connection portion passes through the through hole corresponding to the second dielectric layer.
9. A method for fabricating a multilayer chip inductor as described in any one of claims 1 to 8, characterized in that, Includes the following steps: S1. Print photosensitive ceramic pastes separately to obtain several ceramic paste layers used to prepare the first cover plate, the lead-in layer, the first dielectric layer, the second dielectric layer, the lead-out layer, and the second cover plate; S2. Lay out the corresponding patterned mask on each ceramic slurry layer and expose it to solidify the exposed parts of each ceramic slurry layer and form a cured layer; remove the mask, wash away the uncured coating with developer, and independently form patterned grooves corresponding to the desired electrode pattern on each cured layer. S3. Print electrode paste on each cured layer to form an electrode paste layer and fill the pattern groove with electrode paste. Then, lay a mask plate corresponding to the shape of the pattern groove on the electrode paste layer and expose it to cure the exposed part of the electrode paste and form the corresponding electrode pattern. Remove the mask and wash away the uncured electrode paste layer with developer to obtain the corresponding printed film; S4. Stack the printed sheets according to the structure of the stacked body, then press and cut them into green blanks; S5. The green blank is sintered to obtain the multilayer chip inductor.
10. The method for fabricating a multilayer chip inductor as described in claim 9, characterized in that, The sintering process is carried out in an air atmosphere at a temperature of 800-860°C for 60-90 minutes.