Junction field effect transistor cascode circuit and corresponding control circuit

Abstract

Junction field effect transistor common source common gate circuits and corresponding control circuits are provided. A JFET common source common gate circuit includes a gate driver powered according to a unipolar power supply scheme including a supply potential and a reference potential sufficient to meet a controlled overdrive value, the gate driver generating a gate drive signal including a first gate drive signal during a turn-on condition and a second gate drive signal during a turn-off condition; a JFET having a JFET gate terminal, the JFET gate terminal controlling conduction of current through the JFET according to a gate-source voltage; a voltage-controlled transistor coupled to the JFET in a common source common gate configuration at a common source common gate node, the voltage-controlled transistor including a transistor gate terminal coupled to the gate driver to control conduction of current through the voltage-controlled transistor based on the first gate drive signal or the second gate drive signal; and an overdrive voltage circuit including a supply terminal providing the supply potential, a reference terminal providing the reference potential, and an output terminal coupled to the JFET gate terminal.

Description

Technical Field

[0001] This invention relates to a common-source, common-gate junction field-effect transistor (JFET) circuit and the corresponding control circuit. Background Technology

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as driving electric motors or generators, rely on power semiconductor devices. For example, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes are used in a variety of applications, including but not limited to switches in power supplies, power converters, and power distribution.

[0003] Solid-state switches use electronic components (such as transistors, thyristors, or solid-state relays) instead of mechanical switches or contactors to control the flow of electrical power. Unlike traditional switches that physically move parts to establish or break a circuit, solid-state switches use semiconductor materials to achieve this without moving any parts.

[0004] In power distribution systems, solid-state switches typically need to block the flow of current in both directions (positive and negative voltage) and conduct current in both directions (positive and negative current flow). To achieve this, two semiconductor switches are usually connected source-to-source (sometimes called a back-to-back configuration). This source-to-source configuration is a key difference from typical power converter topologies (e.g., inverters or rectifiers), where the goal is usually unidirectional conduction or controlled energy transfer, rather than purely bidirectional interruption.

[0005] A transistor typically comprises a semiconductor structure configured to conduct load current along a load current path between two load terminal structures of the transistor. Furthermore, the load current can be controlled by the transistor's control electrode (sometimes called the gate electrode). For example, upon receiving a corresponding control signal from, for example, a gate driver, the control electrode can set its transistor to one of two states: on or off. Thus, the semiconductor structure behaves similarly to a switch with on and off states (i.e., on and off states, respectively). The load current can be controlled by driving two complementary transistors. The amplitude of the control signal received from the gate driver for each transistor can be varied to drive the two complementary transistors between switching states. For example, the gate-source voltage VGS of a MOSFET is typically driven down to near zero to turn off the MOSFET and typically driven to its maximum value to fully turn on the MOSFET. Therefore, the gate-source voltage VGS can be referred to as the control voltage. Summary of the Invention

[0006] In some implementations, a junction field-effect transistor (JFET) cascode circuit includes: a gate driver configured to be powered according to a unipolar supply scheme including a supply potential and a reference potential sufficient to satisfy a controlled overdrive value; the gate driver configured to generate a gate drive signal including a first gate drive signal during an on-state and a second gate drive signal during an off-state; a JFET having a JFET gate terminal configured to control the conduction of current through the JFET according to a gate-source voltage; and a voltage-controlled transistor coupled to the JFET in a cascode configuration at a cascode node, the voltage-controlled transistor including... The device includes a transistor gate terminal coupled to a gate driver, and the transistor gate terminal is configured to control the conduction of current through the voltage-controlled transistor based on a first gate drive signal or a second gate drive signal; and an overdrive voltage circuit including a power supply terminal providing a power supply potential, a reference terminal providing a reference potential, and an output terminal coupled to the gate terminal of the JFET, wherein the overdrive voltage circuit is configured to generate a controlled overdrive value as part of the power supply potential and output the controlled overdrive value from the output terminal to the gate terminal of the JFET, and wherein the cascode node is configured to float to a potential higher than the JFET gate potential during the off state to set the JFET to a blocking mode.

[0007] In some implementations, a JFET cascode circuit includes: a gate driver configured to be powered according to a unipolar supply scheme including a supply potential and a reference potential sufficient to satisfy a controlled overdrive voltage; the gate driver being configured to generate a gate drive signal including a first gate drive signal during an on-state and a second gate drive signal during an off-state; a JFET having a JFET gate terminal configured to control the conduction of current through the JFET according to a gate-source voltage; and a voltage-controlled transistor coupled to the JFET in a cascode configuration at a cascode node. The transistor includes a transistor gate terminal coupled to a gate driver, and the transistor gate terminal is configured to control the conduction of current through the voltage-controlled transistor based on a first gate drive signal or a second gate drive signal; and an overdrive voltage circuit including a power supply terminal providing a supply potential, a reference terminal providing a reference potential, and an output terminal coupled to the JFET gate terminal and providing a controlled overdrive voltage, wherein the overdrive voltage circuit is configured to set the controlled overdrive voltage to a predetermined amount in the supply potential, and wherein the cascode node is configured to float to a potential higher than the JFET gate potential during a turn-off state to set the JFET to a blocking mode.

[0008] A cascode control circuit for a junction field-effect transistor (JFET) is provided. The JFET cascode control circuit is configured to control a JFET cascode circuit. The JFET cascode circuit includes a voltage-controlled transistor coupled to the JFET in a cascode configuration. In some implementations, the JFET cascode control circuit includes: a gate driver configured to be powered according to a unipolar power supply scheme including a supply potential and a reference potential sufficient to satisfy a controlled overdrive value; the gate driver is configured to generate a gate drive signal based on a control signal, including a first gate drive signal during an on-state and a second gate drive signal during an off-state, and output the first gate drive signal or the second gate drive signal at a gate drive terminal configured to be coupled to the gate terminal of a transistor of a voltage-controlled transistor; and an overdrive voltage circuit including a supply terminal providing the supply potential, a reference terminal providing the reference potential, and an output terminal configured to be coupled to the gate terminal of the JFET, wherein the overdrive voltage circuit is configured to generate a controlled overdrive value as part of the supply potential and output the controlled overdrive value from the output terminal to the gate terminal of the JFET. Attached Figure Description

[0009] This article describes the implementation method with reference to the accompanying drawings.

[0010] Figure 1 The graph shows the relationship between the drain-to-source on-resistance (RDSon) and VGS of an n-channel high-voltage (HV) JFET.

[0011] Figure 2 The assembly of the power switch and clamping element is shown.

[0012] Figure 3 This is a schematic block diagram illustrating a JFET cascode circuit according to one or more implementations.

[0013] Figure 4A An overdrive voltage circuit is shown according to one or more implementations.

[0014] Figure 4B An overdrive voltage circuit is shown according to one or more implementations.

[0015] Figure 5 This is a schematic block diagram illustrating a JFET cascode circuit according to one or more implementations. Detailed Implementation

[0016] The following text elaborates on details to provide a more thorough explanation of the illustrative implementations. However, it will be apparent to those skilled in the art that these implementations can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagrams or schematics rather than in detail to avoid obscuring the implementation. Furthermore, unless otherwise specifically indicated, features of the different implementations described below can be combined with each other.

[0017] Furthermore, in the following description, equivalent or similar elements, or elements having equivalent or similar functions, are indicated by equivalent or similar reference numerals. Since identical or functionally equivalent elements are given the same reference numerals in the drawings, repeated descriptions of elements with the same reference numerals can be omitted. Therefore, the descriptions provided for elements with the same or similar reference numerals are interchangeable.

[0018] It should be understood that when an element is referred to as “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, there are no intermediate elements. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).

[0019] In the implementations described herein or illustrated in the accompanying drawings, any direct electrical connection or coupling (e.g., any connection or coupling without additional intermediate elements) may also be implemented by an indirect connection or coupling (e.g., a connection or coupling with one or more additional intermediate elements, and vice versa), as long as the general purpose of the connection or coupling is substantially maintained (e.g., transmitting a signal or transmitting information). Features from different implementations may be combined to form other implementations. For example, unless otherwise stated, variations or modifications described with respect to one implementation may also be applicable to other implementations.

[0020] As used herein, the terms “substantially” and “approximately” mean “within reasonable tolerances of manufacturing and measurement.” For example, the terms “substantially” and “approximately” may be used herein to describe small manufacturing tolerances or other factors (e.g., within 5%) that are considered acceptable in the industry, without departing from aspects of the implementation described herein. For example, a resistor with an approximate resistance value may actually have a resistance within 5% of the approximate resistance value. As another example, a signal with an approximate signal value may actually have a signal value within 5% of the approximate signal value.

[0021] In this disclosure, expressions including ordinal numbers such as "first" and "second" may modify various elements. However, such elements are not limited by such expressions. For example, such expressions do not limit the order and / or importance of elements. Rather, such expressions are used only for the purpose of distinguishing an element from other elements. For example, a first box and a second box indicate different boxes, although both are boxes. As a further example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure.

[0022] A transistor, also known as a power switch, power semiconductor, logic switch, or transistor switch, is used to drive current such as load current. Specifically, a power transistor is a power semiconductor device that can be used to drive load current. A power transistor includes a first load terminal (e.g., source or emitter) and a second load terminal (e.g., drain or collector). Additionally, the load current path of a power transistor can be controlled by a control electrode (sometimes called the gate) connected to the control terminal of the power transistor. The load current path of a power transistor is a gate-controlled conductive channel whose conductivity can be controlled by a control voltage applied to the control electrode of the power transistor. For example, a power transistor can be turned on or off by activating and deactivating its control electrode. For example, applying a positive voltage across the gate and source of a MOSFET will keep the MOSFET in its "on" state, while applying a near-zero or slightly negative voltage across the gate and source of a MOSFET will "off" the MOSFET. As used herein, the terms "on state," "on condition," "steady-state on condition," "current on state," and "on mode" are used interchangeably to refer to the on state of a transistor. In addition, terms such as "off state," "off condition," "current blocking state," and "blocking mode" can be used interchangeably to refer to the off state of a transistor.

[0023] There are turn-on and turn-off processes for turning on and off transistors. During the turn-on process of an n-channel transistor, the gate driver can be used to supply a (source) gate current (e.g., a turn-on current) to the gate of the n-channel transistor to charge the gate voltage to a voltage sufficient to turn on the n-channel transistor. Conversely, during the turn-off process of an n-channel transistor, the gate driver is used to draw (sink) a gate current (e.g., a turn-off current) from the gate of the n-channel transistor to fully discharge the gate voltage to turn off the n-channel transistor. A voltage pulse can be output from the gate driver as a control signal according to a pulse width modulation (PWM) scheme. Therefore, the control signal can be switched between the turn-on voltage level and the turn-off voltage level during the PWM cycle to control the n-channel transistor. This, in turn, charges and discharges the gate capacitance to correspondingly modulate the gate voltage to turn on and off the n-channel transistor, respectively.

[0024] For p-channel transistors, the situation is exactly the opposite. A gate driver can be used to draw (sink) gate current (e.g., on-state current) from the gate of a p-channel transistor to discharge the gate voltage sufficiently to turn the p-channel transistor on. Conversely, during the turn-off process of a p-channel transistor, the gate driver is used to supply (source) gate current (e.g., turn-off current) to the gate of the p-channel transistor to fully charge the gate voltage to turn it off. A control signal applied to the gate of the p-channel transistor can be switched between on-state and off-state voltage levels during the PWM cycle to control the p-channel transistor. This, in turn, charges and discharges the gate voltage to turn the p-channel transistor on and off, respectively.

[0025] For both n-channel and p-channel transistors, when the gate-source voltage VGS is approximately zero or below the threshold voltage, both n-channel and p-channel transistors are turned off, while when the gate-source voltage VGS is equal to or greater than the threshold voltage, both n-channel and p-channel transistors are turned on.

[0026] Another type of transistor is the junction field-effect transistor (JFET). An n-channel JFET as a standalone component is a normally-on device. To turn off an n-channel JFET, a negative voltage (e.g., negative VGS, where the source has a higher potential than the gate) must be applied between the gate and source contacts. In some applications, normally-off behavior of the power stage is required (e.g., the drain-source connection is in a high-impedance state, and no active control signal is applied at the gate). In other applications, the introduction of the negative control voltage required to put the n-channel JFET into a high-impedance state (off state) is impractical or undesirable. In both cases, the JFET can be used in series with a normally-off device, such as a standard enhancement-mode MOSFET, to meet design requirements. The circuit topology of connecting a JFET in series with a normally-off device is called a cascode JFET. However, to optimize the performance of a cascode JFET, certain characteristics of the cascode JFET must be considered.

[0027] In solid-state power distribution applications, the total path resistance of the power stage (e.g., drain-to-source on-resistance (RDSon)) is important. In this case, the minimum possible RDSon of the JFET can be achieved through gate control circuitry. For example, the RDSon of the JFET can be controlled by controlling the gate-to-source voltage of the JFET during the on-state.

[0028] Figure 1Graph 100 shows the relationship between RDSon and VGS for an n-channel high-voltage (HV) JFET. Some n-channel power JFETs exhibit a significant gate-source voltage (VGS) dependence of RDSon values ​​near VGS = 0 V. Applying a positive VGS further reduces the channel RDSon compared to the RDSon value present at VGS = 0 V. In the example shown in Graph 100, a 17% reduction in RDSon can be achieved by applying a positive VGS compared to the RDSon at VGS = 0 V. Therefore, a positive VGS can be referred to as overdrive voltage, overdrive gate voltage, overdrive VGS, or overdrive value. In other words, the overdrive voltage is the positive voltage between the gate and source of the JFET at which RDSon is further reduced compared to VGS equal to 0 V. Due to the structure of the n-channel JFET, the maximum applicable gate voltage is limited by the intrinsic gate-to-source pn junction and gate-to-drain pn junction of the JFET. For example, once VGS or the gate-drain voltage VGD exceeds a certain voltage of the corresponding intrinsic pn junction, such as the inflection point voltage, the intrinsic gate-to-source pn junction and the gate-to-drain pn junction begin to conduct high-level gate currents. The inflection point voltage (also known as the threshold voltage) of an intrinsic pn junction is the minimum forward voltage at which the pn junction begins to conduct significantly. For example, for silicon pn junctions, the inflection point voltage is typically between 0.6 V and 0.7 V, and for silicon carbide (SiC) pn junctions, it is typically between approximately 2.5 V and 3 V (note that the inflection point voltage of a particular intrinsic pn junction can depend on device characteristics such as doping level and temperature). Conducting high-level gate currents through the intrinsic gate-to-source pn junction and the gate-to-drain pn junction is undesirable because the current flowing through these intrinsic pn junction structures increases power dissipation in the JFET and burdens the power supply to the gate driver. Furthermore, once the VGS voltage level exceeds the inflection point voltages of the gate-to-source pn junction and the gate-to-drain pn junction, a saturation effect of d(RDSon) / d(VGS) will be observed. Therefore, it is preferable that during the steady-state conduction of the JFET (e.g., when the JFET is in the on state), the VGS level driving the JFET (e.g., the overdrive voltage) is close to the inflection point voltage level of the intrinsic pn junction to achieve a minimum RDSon while keeping the steady-state gate current at a low level.

[0029] In some applications (e.g., solid-state power distribution), transistor chip sizes can be large to achieve the desired low RDSon (e.g., <1 mOhm at a VBDss rating of 1200 V, where VBDss refers to the drain-source breakdown voltage). Therefore, the total gate charge of a JFET device (primarily the gate-drain charge (Qgd)) can be very high, easily exceeding 1000 nanocoulombs (nC). To achieve reasonably fast switching behavior (dV / dt > 1 kV / µs) in a JFET device, high transient gate currents, potentially exceeding 10 A, are required. Crucially, the high transient current capability of the gate drive circuitry must be enabled to maintain safe control of the power device during voltage transients applied across the drain-source contacts of the JFET (e.g., during switching transients of external air-gap devices). Therefore, implementing a very low impedance drive circuitry for the JFET gate may be necessary.

[0030] While transient gate drive currents can be large due to the large transistor size, average gate drive current consumption can be very low in solid-state power distribution applications because JFETs operate at low switching frequencies (e.g., operating frequency << 1 Hz). Therefore, it is important to minimize the leakage current continuously fed to the JFET gate in order to reduce the workload of the power supply scheme used for the gate drive circuitry.

[0031] In solid-state power distribution applications, the turn-off current level (current density) can be very high, approaching the specified absolute maximum pulse current level of the power device. Furthermore, energy stored in the remaining line / load inductance of the external circuitry is absorbed by clamping elements and partially by the JFET itself.

[0032] In the event of overcurrent shutdown, the power semiconductor must support the switching of the shutdown current to the clamping element (e.g., a variable resistor (MOV), a transient voltage suppressor (TVS), a resistor-capacitor (RC) network, etc.). Once the switching is complete, the power semiconductor must block the clamping voltage of the clamping element.

[0033] Figure 2 An assembly 200 comprising a power switch (e.g., a JFET) and a clamping element is shown. The JFET and clamping element each have a series parasitic stray inductance L. stray,Switch and L Stray,Clamp For successful commutation, the JFET must provide a blocking voltage higher than the steady-state clamping voltage of the clamping element. The blocking voltage during commutation can be calculated using Equation 1.

[0034] While conventional switching devices such as MOSFETs use control measures (e.g., increasing the gate resistance) to set the switching speed of the output stage to avoid exceeding the specified maximum VBDss of the power device, n-channel power JFET devices can operate in an unclamped inductor switching (UIS) mode. In this mode, an internal drain-gate diode is used to drive the JFET into linear mode, providing a controlled VDS voltage at or above the specified maximum VBDss. This clamped mode must be enabled via a dedicated gate control scheme. Linear mode is achieved by the voltage drop induced in the gate resistor network by the avalanche breakdown current of the drain-gate pn junction.

[0035] Some implementations disclosed herein involve JFET cascode circuits, which provide an efficient way to drive discrete JFET cascode circuits, offering the best possible RDSon with minimal circuit complexity, required gate drive strength, and minimized steady-state supply current consumption. A JFET cascode circuit includes a JFET and a voltage-controlled transistor, such as a MOSFET, coupled to the JFET in a cascode configuration. For example, in a cascode configuration, the source terminal of the JFET can be coupled to the drain terminal of the voltage-controlled transistor at the cascode node. The voltage-controlled transistor can be driven to control the potential at the cascode node to place the JFET in current-conducting or blocking mode. For example, when the voltage-controlled transistor is in blocking mode, the cascode node can be configured to float to a potential higher than the JFET gate potential (e.g., making VGS negative) to set the JFET to blocking mode. Conversely, when the voltage-controlled transistor is in current-conducting mode, the potential at the cascode node can be pulled low by the voltage-controlled transistor such that VGS is sufficient to set the JFET to current-conducting mode. Therefore, the on / off state of the JFET is indirectly controlled by controlling the on / off state of the voltage-controlled transistor, where the JFET's on is based on the on of the voltage-controlled transistor, and the JFET's off is based on the off of the voltage-controlled transistor. When the voltage-controlled transistor is in current conduction mode, if an overdrive signal (e.g., an overdrive potential) is applied to the gate of the JFET, the VGS of the JFET will be positive, thereby achieving overdrive VGS and reducing the RDSon of the JFET.

[0036] In some implementations, the JFET gate drive voltage is obtained from the supply potential configured to power the gate driver via an overdrive voltage circuit. The voltage supplied to the JFET gate by the overdrive voltage circuit elements is limited by the overdrive voltage circuit or otherwise adjusted to a level below the inflection point voltage of the intrinsic GS pn junction of the JFET. Due to the control of the JFET gate drive voltage, the applied VGS overdrive voltage can be set such that a reduced or minimal RDSon can be achieved at the JFET (e.g., to a predefined reduced RDSon value), while the forward current entering the intrinsic GS pn junction of the JFET is limited to a predefined current value. A current-limiting element R is disposed between the output of the overdrive voltage circuit and the JFET gate. JGATE Instead of limiting the current fed to the JFET gate under steady-state conduction conditions, it can be provided and sized to optimize the switching performance of the JFET and maintain stable operation under external distortion.

[0037] The gate driver includes a buffer configured to generate a gate drive signal. The buffer may include a pair of complementary FETs for generating the gate drive signal. For example, one FET (e.g., a source FET) may be connected to a positive supply potential and, when enabled, pulls the gate drive signal up toward the positive supply potential (e.g., a high level). The other FET (e.g., a sink FET) may be connected to a reference potential (e.g., ground potential) and, when enabled, pulls the gate drive signal toward the reference potential (e.g., a low level). When enabled, the source FET may generate a turn-on current Io+ (e.g., a source current) to charge the gate of the transistor to turn it on. When enabled, the sink FET may generate a turn-off current Io- (e.g., a sink current) to discharge the gate of the transistor to turn it off.

[0038] Therefore, the gate driver is powered by a unipolar supply scheme using only one power rail (e.g., +12 V) and a single ground / reference (e.g., 0 V). All voltages in the system are positive (or zero) relative to the ground of the unipolar supply scheme. In other words, all voltage potentials in the circuit swing with only one polarity (e.g., positive) relative to ground. Thus, the JFET cascode circuit is simplified compared to gate driver circuits using multi-supply schemes with two or more positive power supplies and / or two or more reference power supplies (one of which can be negative).

[0039] A JFET cascode circuit can be turned off by the gate driver by setting the voltage-controlled transistor to blocking mode. Due to the blocking channel of the voltage-controlled transistor, the source potential of the JFET floats high, resulting in the negative VGS voltage required to switch the JFET to blocking mode.

[0040] The steady-state drive current of the JFET cascode circuit arrangement is minimized to the gate of the voltage-controlled transistor and the leakage current of the JFET gate. Because the switching frequency of typical solid-state power distribution applications is very low, the JFET cascode circuit allows coreless transformers to be used as power supply elements, which may be important for reducing the size and cost of solid-state circuit breaker (SSCB) implementations.

[0041] Furthermore, the JFET cascode circuitry provides a very low-ohm gate drive solution, enabling safe and stable operation of the JFET while minimizing gate drive current requirements and still achieving the best possible RDSon in conduction mode (e.g., during the steady-state conduction of the JFET).

[0042] Figure 3 This is a schematic block diagram illustrating a JFET cascode circuit 300 according to one or more implementations. The JFET cascode circuit 300 may include a gate driver 702, a JFET 704, a voltage-controlled transistor 706, and an overdrive voltage circuit 708. The JFET 704 may be an n-channel HV JFET, and the voltage-controlled transistor 706 may be an n-channel LV MOSFET.

[0043] The gate driver 702 is configured to be powered according to a unipolar power supply scheme. The unipolar power supply scheme includes a supply potential V sufficient to satisfy a controlled overdrive value (e.g., a controlled overdrive voltage). DRV (For example, a single supply potential, such as +12 V) and a reference potential V REF (For example, a single reference potential, such as 0 V or ground). Gate driver 702 is configured to generate gate drive signals, including a first gate drive signal during an on-state and a second gate drive signal during an off-state. For example, gate driver 702 may generate the first gate drive signal at a first gate drive terminal Out+ and the second gate drive signal at a second gate drive terminal Out-. In some implementations, the first gate drive signal may be an on-current Io+ (e.g., a source current), and the second gate drive signal may be an off-current Io- (e.g., a sink current). The gate drive signals may be based on one or more control signals received from a controller. For example, gate driver 702 may receive a first PWM control signal at a first input terminal IN+ and a second PWM control signal at a second input terminal IN-. The first PWM control signal can be used to control the source FET of gate driver 702 to generate the first gate drive signal, and the second PWM control signal can be used to control the sink FET of gate driver 702 to generate the second gate drive signal.

[0044] JFET 704 includes a JFET gate terminal (G) configured to control the conduction of current through the JFET based on the gate-source voltage VGS. Voltage-controlled transistor 706 is coupled to JFET 704 in a cascode configuration. For example, the source terminal (S) of JFET 704 can be coupled to the drain terminal (D) of voltage-controlled transistor 706 at cascode node 710 to form a cascode configuration. The source terminal (S) of voltage-controlled transistor 706 can be coupled to the common source node 712 of the JFET cascode circuit 300, wherein the common source node 712 is coupled to a reference potential VGS. REF Therefore, the source terminal (S) of the voltage-controlled transistor 706 can be grounded.

[0045] The voltage-controlled transistor 706 includes a transistor gate terminal (G) coupled to a first gate drive terminal Out+ and a second gate drive terminal Out- of a gate driver 702. The transistor gate terminal of the voltage-controlled transistor 706 is configured to control the conduction of current through the voltage-controlled transistor 706 based on a first gate drive signal or a second gate drive signal. For example, during the on-state, an on-current Io+ may flow through a gate resistor RGon to charge the gate of the voltage-controlled transistor 706. Alternatively, during the off-state, an off-current Io- may flow through a gate resistor RGoff to discharge the gate of the voltage-controlled transistor 706. In other words, the gate driver 702 may output a first gate drive signal from the first gate drive terminal Out+ to the transistor gate terminal of the voltage-controlled transistor 706 during the on-state, and may absorb a second gate drive signal from the transistor gate terminal of the voltage-controlled transistor 706 to the second gate drive terminal Out- during the off-state.

[0046] The overdrive voltage circuit 708 may include providing a power supply potential V DRV The power supply terminal provides a reference potential V. REF The reference terminal and the output terminal OUT coupled to the JFET gate terminal of the JFET 704. OD The overdrive voltage circuit 708 can generate a supply potential V. DRV A portion of the controlled overdrive value, and the controlled overdrive value is output from the OUT terminal. OD The output is sent to the JFET gate terminal. In some implementations, the overdrive voltage circuit 708 can generate a controlled overdrive value as a fixed preset value (e.g., a predetermined amount of supply potential V). DRV Therefore, the controlled overdrive potential V provided by the overdrive voltage circuit 708 can be used as a reference. ODThis limits the JFET gate potential. In some implementations, the overdrive voltage circuit 708 can be configured to generate a controlled overdrive value such that the JFET gate terminal of JFET 704 is always biased to a positive potential during operation (e.g., during the on and off states).

[0047] The overdrive voltage circuit 708 may include a plurality of passive and / or active elements arranged in a specific manner to provide a controlled overdrive voltage. Exemplary passive elements are resistors or diodes. Exemplary active elements are transistors or thyristors. For example, the overdrive voltage circuit 708 may be implemented as a voltage divider using resistors and / or diodes. Alternatively, the overdrive voltage circuit 708 may be implemented as a voltage regulator, such as a low-dropout regulator or a switching regulator.

[0048] The cascode node 710 can be configured to float to a potential higher than the JFET gate potential of JFET 704 during the off-state to set JFET 704 to a blocking mode. For example, gate driver 702 can set voltage-controlled transistor 706 to a blocking mode during the off-state, such that cascode node 710 is at a potential higher than the JFET gate potential, and the gate-source voltage VGS of JFET 704 is sufficiently negative to set JFET 704 to a blocking mode. In some implementations, gate driver 702 can set voltage-controlled transistor 706 to a blocking mode during the off-state, such that cascode node 710 is at a potential higher than the controlled overdrive value, and the gate-source voltage VGS of JFET 704 is sufficiently negative to set JFET 704 to a blocking mode.

[0049] Additionally, the gate driver 702 can set the voltage-controlled transistor 706 to conduction mode during the conduction state, such that the cascode node 710 is at a potential lower than the JFET gate potential, so that the gate-source voltage VGS of the JFET 704 is sufficient to set the JFET 704 to conduction mode. The overdrive voltage circuit 708 can control the output terminal OUT. OD The controlled overdrive value at the output terminal OUT is limited to a positive value that reduces or minimizes the drain-to-source on-resistance RDSon of the JFET 704. In some implementations, the overdrive voltage circuit 708 can limit the controlled overdrive value to a positive value less than the gate-to-source pn junction inflection point of the JFET 704. Therefore, the overdrive voltage circuit 708 can limit the output terminal OUT... ODThe controlled overdrive value is limited to a positive value that minimizes or sets the drain-to-source on-resistance RDSon of the JFET 704 to a predefined value, while the controlled overdrive VGS does not exceed the gate-to-source pn junction inflection point voltage of the JFET 704. Therefore, the controlled overdrive value can be a positive value less than the gate-to-source pn junction inflection point voltage of the JFET 704. In some implementations, the controlled overdrive value can be the voltage level at which the RDSon of the JFET 704 is minimized, while not exceeding the gate-to-source pn junction inflection point voltage. The overdrive voltage circuit 708 can limit the forward current flowing into the gate-to-source pn junction of the JFET 704 to a predefined value during the on-state.

[0050] In some implementations, the overdrive voltage circuit 708 can bias the JFET gate terminal according to a controlled overdrive value during the on and off states. For example, the overdrive voltage circuit 708 can be a voltage divider configured to continuously provide a desired overdrive value (e.g., a controlled overdrive value) during the on and off states, thereby creating a permanent positive bias at the JFET gate terminal during the on and off states. Alternatively, the overdrive voltage circuit 708 can be a voltage regulator configured to continuously provide a controlled overdrive value during the on and off states, thereby creating a permanent positive bias at the JFET gate terminal during the on and off states.

[0051] In some implementations, the reference terminal of the overdrive voltage circuit 708 can be coupled to the common source node 712 of the JFET cascode circuit 300, where a reference potential V is provided. REF The common source node 712 may correspond to the source terminal of the voltage-controlled transistor 706. Alternatively, in some implementations, the reference terminal of the overdrive voltage circuit 708 may be coupled to the common source cascode node 710 of the JFET cascode circuit 300.

[0052] As described above, the gate driver 702 is configured to be powered according to a unipolar power supply scheme. The unipolar power supply scheme may include a transformer 720 having a primary-side coil connected to the supply potential Vsup and the ground potential GND, and a secondary coil connected to the supply potential Vsup. DRV and reference potential V REF The secondary coil. The primary and secondary coils may have a turns ratio, wherein the secondary coil has a predetermined number of turns. Of course, the unipolar power supply scheme may include additional circuitry with active and / or passive components (not shown), for example for rectifying signals transmitted via transformer 720.

[0053] As mentioned above, Figure 3Provided as an example only. Other examples may differ from those provided. Figure 3 Example of the description.

[0054] Figure 4A An overdrive voltage circuit 400A according to one or more implementations is shown. The overdrive voltage circuit 400A can be implemented in combination with... Figure 3 The overdrive voltage circuit 708 is described. The overdrive voltage circuit 400A may include providing a supply potential V. DRV The power supply terminal provides a reference potential V. REF The reference terminal and the output terminal. As described above, the output terminal can be coupled to the JFET gate terminal. The overdrive voltage circuit 400A can generate a supply potential V. DRV A portion of the controlled overdrive potential V OD And output a controlled overdrive potential V from the output terminal. OD The overdrive voltage circuit 400A may include two or more resistors (e.g., resistors R1 and R2) arranged in a voltage divider configuration to generate a supply potential V. DRV A portion of the controlled overdrive potential V OD .

[0055] As mentioned above, Figure 4A Provided as an example only. Other examples may differ from those provided. Figure 4A Example of the description.

[0056] Figure 4B An overdrive voltage circuit 400B according to one or more implementations is shown. The overdrive voltage circuit 400B can be implemented in combination with... Figure 3 The overdrive voltage circuit 708 is described. The overdrive voltage circuit 400B may include providing a supply potential V. DRV The power supply terminal provides a reference potential V. REF The reference terminal and the output terminal. As described above, the output terminal can be coupled to the JFET gate terminal. The overdrive voltage circuit 400B can generate a supply potential V. DRV A portion of the controlled overdrive potential V OD And output a controlled overdrive potential V from the output terminal. OD The overdrive voltage circuit 400B can be a voltage regulator, such as a low-dropout regulator or a switching regulator, which generates the supply potential V. DRV A portion of the controlled overdrive potential V OD .

[0057] As mentioned above, Figure 4B Provided as an example only. Other examples may differ from those provided. Figure 4BExample of the description.

[0058] Figure 5 This is a schematic block diagram illustrating a JFET cascode circuit 500 according to one or more implementations. The JFET cascode circuit 500 can be similar to a combination of... Figure 3 The JFET cascode circuit 300 is described. However, instead of using the overdrive voltage circuit 708 to limit the output terminal OUT,... OD Controlled overdrive value at the output terminal OUT OD A center tap connected to transformer 720 (e.g., a center tap on the secondary winding) is used to provide a controlled overdrive potential V. OD Therefore, transformer 720 can be an overdrive voltage circuit, which generates the supply potential V. DRV A portion of the controlled overdrive potential V OD And from the output terminal OUT OD Output controlled overdrive potential V OD For example, the center tap of the secondary coil can be used to directly provide the desired overdrive potential V. OD Controlled overdrive potential V OD A tap can be taken at the middle position of the secondary side coil corresponding to the lower number of turns. In some implementations, the middle position can be adjustable to obtain the overdrive potential V. OD .

[0059] Therefore, transformer 720 can supply power to gate driver 702 according to a unipolar power supply scheme. Transformer 720 includes a primary-side coil and a secondary-side coil, wherein the power supply terminal, reference terminal, and output terminal are coupled to the secondary-side coil, and the output terminal OUT... OD The transformer 720 is coupled to the secondary winding at the center tap position between the power supply terminal and the reference terminal. The transformer 720 can generate the power supply potential V. DRV A portion of the controlled overdrive value (e.g., overdrive potential V) OD ), and the controlled overdrive value is transferred from the output terminal OUT OD Output to the JFET gate terminal.

[0060] In some implementations, the gate driver 702 can set the voltage-controlled transistor 706 to a blocking mode during the off-state, such that the cascode node 710 is at a potential higher than the controlled overdrive value, and the gate-source voltage VGS of the JFET 704 is negative enough to set the JFET 704 to a blocking mode. Alternatively, the gate driver 702 can set the voltage-controlled transistor 706 to a conducting mode during the on-state, such that the cascode node 710 is at a potential lower than the JFET gate potential, so that the gate-source voltage VGS of the JFET 704 is sufficient to set the JFET 704 to a conducting mode.

[0061] Transformer 720 can be configured to output terminal OUT OD The controlled overdrive value is limited or otherwise provided as a positive value, which reduces or minimizes the drain-to-source on-resistance RDSon of the JFET 704. In some implementations, the transformer 720 can be configured to limit the controlled overdrive value to a positive value less than the gate-to-source pn junction inflection point of the JFET 704. Therefore, the transformer 720 can be configured to limit the controlled overdrive value to a positive value less than the gate-to-source pn junction inflection point of the JFET 704. OD The controlled overdrive value is limited to a positive value that minimizes or sets the drain-to-source on-resistance RDSon of the JFET 704 to a predefined value, while the controlled overdrive VGS does not exceed the gate-to-source pn junction inflection point voltage of the JFET 704. Therefore, the controlled overdrive value can be a positive value less than the gate-to-source pn junction inflection point voltage of the JFET 704. In some implementations, the controlled overdrive value can be the voltage level at which the RDSon of the JFET 704 is minimized, provided that this voltage level does not exceed the gate-to-source pn junction inflection point voltage. The transformer 720 can be configured to limit the forward current flowing into the gate-to-source pn junction of the JFET 704 to a predefined value during the on-state.

[0062] In some implementations, transformer 720 can be configured to bias the JFET gate terminal according to a controlled overdrive value during the on and off states. For example, transformer 720 can be configured to continuously provide a controlled overdrive value during the on and off states, thereby creating a permanent positive bias at the JFET gate terminal during the on and off states.

[0063] As mentioned above, Figure 5 Provided as an example only. Other examples may differ from those provided. Figure 5 Example of the description.

[0064] The following provides an overview of some aspects of this disclosure:

[0065] Aspect 1: A JFET cascode circuit, comprising: a gate driver configured to be powered according to a unipolar power supply scheme including a supply potential sufficient to satisfy a controlled overdrive value and a reference potential, the gate driver being configured to generate a gate drive signal including a first gate drive signal during an on-state and a second gate drive signal during an off-state; a JFET having a JFET gate terminal configured to control the conduction of current through the JFET according to a gate-source voltage; and a voltage-controlled transistor coupled to the JFET in a cascode configuration at a cascode node, the voltage-controlled transistor including a connection to the gate driver. The device includes a transistor gate terminal, configured to control the conduction of current through the voltage-controlled transistor based on a first gate drive signal or a second gate drive signal; and an overdrive voltage circuit including a power supply terminal providing a power supply potential, a reference terminal providing a reference potential, and an output terminal coupled to the gate terminal of the JFET, wherein the overdrive voltage circuit is configured to generate a controlled overdrive value as part of the power supply potential and output the controlled overdrive value from the output terminal to the gate terminal of the JFET, and wherein the cascode node is configured to float to a potential higher than the JFET gate potential during the off state to set the JFET to a blocking mode.

[0066] Aspect 2: The JFET cascode circuit according to aspect 1, wherein the gate driver is configured to set the voltage-controlled transistor to a blocking mode during the off state, such that: the cascode node is at a potential higher than the JFET gate potential, and the gate-source voltage is sufficiently negative to set the JFET to a blocking mode.

[0067] Aspect 3: The JFET cascode circuit according to Aspect 2, wherein the gate driver is configured to set the voltage-controlled transistor to conduction mode during conduction, such that the cascode node is at a potential lower than the JFET gate potential, so that the gate-source voltage is sufficient to set the JFET to conduction mode, and wherein the overdrive voltage circuit is configured to limit the controlled overdrive value to a positive value, which minimizes the drain-to-source on-resistance of the JFET.

[0068] Aspect 4: The JFET cascode circuit according to Aspect 2, wherein the gate driver is configured to set the voltage-controlled transistor to conduction mode during conduction, such that the cascode node is at a potential lower than the JFET gate potential, so that the gate-source voltage is sufficient to set the JFET to conduction mode, wherein the JFET includes a gate-to-source pn junction, and wherein the overdrive voltage circuit is configured to limit the controlled overdrive value to a positive value, which is less than the inflection point voltage of the gate-to-source pn junction.

[0069] Aspect 5: A JFET cascode circuit according to any one of Aspects 1 to 4, wherein the gate driver is configured to set the voltage-controlled transistor to a blocking mode during the off state, such that: the cascode node is at a potential higher than the controlled overdrive value, and the gate-source voltage is sufficiently negative to set the JFET to a blocking mode.

[0070] Aspect 6: A JFET cascode circuit according to any one of Aspects 1 to 5, wherein the JFET includes a gate-to-source pn junction, and wherein the controlled overdrive value is a positive value less than the inflection point voltage of the gate-to-source pn junction.

[0071] Aspect 7: The JFET cascode circuit according to aspect 6, wherein the controlled overdrive value is the voltage level at which the drain-to-source on-resistance of the JFET is minimized, and the voltage level does not exceed the inflection point voltage of the gate-to-source pn junction.

[0072] Aspect 8: The JFET common-source cascode circuit according to aspect 6, wherein the overdrive voltage circuit is configured to bias the JFET gate terminal according to a controlled overdrive value during the on and off states.

[0073] Aspect 9: The JFET cascode circuit according to aspect 6, wherein the JFET includes a gate-to-source pn junction formed by the gate and source of the JFET, and wherein the overdrive voltage circuit is configured to limit the forward current flowing into the gate-to-source pn junction to a predefined value during the on-state.

[0074] Aspect 10: The JFET cascode circuit according to any one of Aspects 1 to 9, wherein the overdrive voltage circuit is a voltage divider configured to continuously provide a controlled overdrive value during the on and off states, thereby generating a permanent positive bias at the JFET gate terminal during the on and off states.

[0075] Aspect 11: The JFET cascode circuit according to any one of Aspects 1 to 10, wherein the overdrive voltage circuit is a voltage regulator configured to continuously provide a controlled overdrive value during the on-state and off-state, thereby generating a permanent positive bias at the JFET gate terminal during the on-state and off-state.

[0076] Aspect 12: A JFET cascode circuit according to any one of Aspects 1 to 11, wherein a reference terminal is coupled to a common source node of the JFET cascode circuit, and a reference potential is provided at the common source node, the common source node corresponding to the source terminal of the voltage-controlled transistor.

[0077] Aspect 13: A JFET cascode circuit according to any one of Aspects 1 to 12, wherein the gate driver includes a first gate drive terminal and a second gate drive terminal, the first gate drive terminal and the second gate drive terminal being coupled to a transistor gate terminal, and wherein the gate driver is configured to output a first gate drive signal from the first gate drive terminal to the transistor gate terminal during an on-state, and to absorb a second gate drive signal from the transistor gate terminal to the second gate drive terminal during an off-state.

[0078] Aspect 14: A JFET common-source cascode circuit according to any one of Aspects 1 to 13, wherein the overdrive voltage circuit includes a transformer configured to supply power to the gate driver according to a unipolar power supply scheme, wherein the transformer includes a primary-side coil and a secondary-side coil, and wherein a power supply terminal, a reference terminal and an output terminal are coupled to the secondary-side coil, wherein the output terminal is coupled to the secondary-side coil at an intermediate tap position between the power supply terminal and the reference terminal.

[0079] Aspect 15: A JFET cascode circuit comprising: a gate driver configured to be powered according to a unipolar power supply scheme including a supply potential sufficient to satisfy a controlled overdrive voltage and a reference potential, the gate driver being configured to generate a gate drive signal including a first gate drive signal during an on-state and a second gate drive signal during an off-state; a JFET having a JFET gate terminal configured to control the conduction of current through the JFET according to a gate-source voltage; and a voltage-controlled transistor coupled to the JFET in a cascode configuration at a cascode node. The body transistor includes a transistor gate terminal coupled to a gate driver, and the transistor gate terminal is configured to control the conduction of current through the voltage-controlled transistor based on a first gate drive signal or a second gate drive signal; and an overdrive voltage circuit including a power supply terminal providing a supply potential, a reference terminal providing a reference potential, and an output terminal coupled to the JFET gate terminal and providing a controlled overdrive voltage, wherein the overdrive voltage circuit is configured to set the controlled overdrive voltage to a predetermined supply potential, and wherein the cascode node is configured to float to a potential higher than the JFET gate potential during the off state to set the JFET to a blocking mode.

[0080] Aspect 16: A junction field-effect transistor (JFET) cascode control circuit configured to control a JFET cascode circuit including a voltage-controlled transistor coupled to the JFET in a cascode configuration, the JFET cascode control circuit including: a gate driver configured to be powered according to a unipolar power supply scheme including a supply potential sufficient to satisfy a controlled overdrive value and a reference potential, the gate driver being configured to generate, based on a control signal, a first gate drive signal during an on-state and a second gate drive signal during an off-state. The second gate drive signal is a gate drive signal between the two gates, and the first gate drive signal or the second gate drive signal is output at a gate drive terminal configured to be coupled to the gate terminal of the voltage-controlled transistor; the overdrive voltage circuit includes a power supply terminal providing a power supply potential, a reference terminal providing a reference potential, and an output terminal configured to be coupled to the gate terminal of the JFET, wherein the overdrive voltage circuit is configured to generate a controlled overdrive value as part of the power supply potential, and output the controlled overdrive value from the output terminal to the gate terminal of the JFET.

[0081] Aspect 17: The JFET common-source cascode control circuit according to aspect 16, wherein the overdrive voltage circuit includes a transformer configured to supply power to the gate driver according to a unipolar power supply scheme, wherein the transformer includes a primary-side coil and a secondary-side coil, and wherein a power supply terminal, a reference terminal and an output terminal are coupled to the secondary-side coil, wherein the output terminal is coupled to the secondary-side coil at an intermediate tap position between the power supply terminal and the reference terminal.

[0082] Aspect 18: A JFET common-source cascode control circuit according to any one of Aspects 16 or 17, wherein the overdrive voltage circuit is a voltage divider configured to continuously provide a controlled overdrive value during the on and off states, thereby generating a permanent positive bias at the JFET gate terminal during the on and off states.

[0083] Aspect 19: A JFET common-source cascode control circuit according to any one of Aspects 16 to 18, wherein the overdrive voltage circuit is a voltage regulator configured to continuously provide a controlled overdrive value during the on-state and off-state, thereby generating a permanent positive bias at the JFET gate terminal during the on-state and off-state.

[0084] Aspect 20: A system configured to perform one or more of the operations described in one or more of aspects 1 to 19.

[0085] Aspect 21: An apparatus comprising means for performing one or more of the operations described in one or more of aspects 1 to 19.

[0086] Aspect 22: A non-transitory computer-readable medium storing an instruction set comprising one or more instructions that, when executed by a device, cause the device to perform one or more operations described in one or more of Aspects 1 to 19.

[0087] Aspect 23: A computer program product comprising instructions or code for performing one or more of the operations described in one or more of aspects 1 to 19.

[0088] The foregoing disclosure provides explanations and descriptions, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations can be made based on the foregoing disclosure, or modifications and variations can be derived from the practice of implementation.

[0089] This article can use thresholds to describe some implementation methods. As used in this article, the "satisfying" threshold can refer to values ​​such as greater than the threshold, more than the threshold, higher than the threshold, greater than or equal to the threshold, less than the threshold, less than the threshold, lower than the threshold, less than or equal to the threshold, and equal to the threshold.

[0090] As used herein, the term "component" is intended to be interpreted broadly as hardware, firmware, or a combination of hardware and software. The systems and / or methods described herein can be implemented in various forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods is not a limitation on the implementation method. Therefore, while this document describes the operation and behavior of the systems and / or methods without reference to specific software code, it should be understood that software and hardware can be designed to implement the systems and / or methods based on the descriptions herein.

[0091] Any processing unit can be implemented as a central processing unit (CPU) or other processor that reads and executes software programs from a non-transitory computer-readable recording medium such as a hard disk or semiconductor memory device. For example, instructions can be executed by one or more processors, such as one or more CPUs, digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPLAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuits. Therefore, as used herein, the term "processor" refers to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. Software can be stored on a non-transitory computer-readable medium such that the non-transitory computer-readable medium includes program code or program algorithms stored thereon, which, when executed, cause the processor to perform the steps of a method via a computer program.

[0092] The controller, including hardware, may also perform one or more of the techniques described in this disclosure. A controller including one or more processors may use electrical signals and digital algorithms to perform its receiving, analysis, and control functions, and may also include correction functions. Such hardware, software, and firmware may be implemented within the same device or in separate devices to support the various techniques described in this disclosure.

[0093] Signal processing circuitry and / or signal conditioning circuitry can receive one or more signals (e.g., measurement signals) from one or more components in the form of raw measurement data, and can derive additional information from the measurement signals. As used herein, “signal conditioning” refers to manipulating an analog signal in such a way that the signal meets the requirements of the next stage for further processing. Signal conditioning may include analog-to-digital conversion (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other processing required to make the signal suitable for processing after conditioning.

[0094] Even though specific combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the implementations described herein. Many of these features can be combined in ways not specifically recited in the claims and / or not disclosed in the specification. For example, this disclosure includes combinations of each dependent claim in the claim set with each other individual claim in the claim set and each combination of multiple claims in the claim set. As used herein, the phrase “at least one” in a list of items refers to any combination of these items, including individual components. As an example, “at least one of a, b, or c” is intended to cover a, b, c, a and b, a and c, b and c, and a, b, and c, as well as any combination with multiple identical elements (e.g., a + a, a + a + a, a + a + b, a + a + c, a + b + b, a + c + c, b + b, b + b + b, b + b + c, c + c, and c + c + c, or any other ordering of a, b, and c).

[0095] Furthermore, it should be understood that the disclosure of multiple actions or functions in the specification or claims is not to be construed as being in a particular order. Therefore, the disclosure of multiple actions or functions will not be limited to a specific order unless such actions or functions are technically non-interchangeable. Additionally, in some implementations, a single action may include or be divided into multiple sub-actions. Unless expressly excluded, such sub-actions may be included as part of the disclosure of that single action.

[0096] Unless explicitly stated otherwise, no element, action, or instruction used herein should be construed as critical or necessary. Furthermore, as used herein, the articles “a” and “one” are intended to include one or more items and may be used interchangeably with “one or more.” Additionally, as used herein, the article “the” is intended to include one or more items referenced by the article “the” and may be used interchangeably with “one or more.” Where only one item is intended, the phrases “only one,” “single,” or similar language are used. Furthermore, as used herein, the terms “has,” “have,” “having,” etc., are intended to be open-ended terms that do not limit the element they modify (e.g., element “having” A may also have B). Furthermore, unless explicitly stated otherwise, the phrase “based on” is intended to mean “at least partially based on.” As used herein, the term “multiple” may be replaced with “multiple” and vice versa. Furthermore, as used herein, the term “or” is intended to be inclusive when used in series and may be used interchangeably with “and / or” unless otherwise expressly stated (e.g., if used in combination with “any one” or “only one”).

Claims

1. A junction field-effect transistor (JFET) cascode circuit, comprising: A gate driver configured to be powered according to a unipolar power supply scheme including a power supply potential and a reference potential sufficient to satisfy a controlled overdrive value, the gate driver being configured to generate a gate drive signal including a first gate drive signal during an on-state and a second gate drive signal during an off-state. A JFET having a JFET gate terminal, the JFET gate terminal being configured to control the conduction of current through the JFET according to the gate-source voltage; A voltage-controlled transistor, the voltage-controlled transistor being coupled to the JFET in a cascode configuration at a cascode node, the voltage-controlled transistor including a transistor gate terminal coupled to the gate driver, and the transistor gate terminal being configured to control the conduction of current through the voltage-controlled transistor based on a first gate drive signal or a second gate drive signal; as well as An overdrive voltage circuit, the overdrive voltage circuit including a power supply terminal providing the power supply potential, a reference terminal providing the reference potential, and an output terminal coupled to the gate terminal of the JFET. The overdrive voltage circuit is configured to generate a controlled overdrive value as part of the supply potential, and output the controlled overdrive value from the output terminal to the JFET gate terminal. The common-source cascode node is configured to float to a potential higher than the JFET gate potential during the off state, so as to set the JFET to a blocking mode.

2. The JFET cascode circuit according to claim 1, wherein, The JFET includes a gate-to-source pn junction, and The controlled overdrive value is a positive value that is less than the inflection point voltage of the gate-to-source pn junction.

3. The JFET cascode circuit according to claim 2, wherein, The controlled overdrive value is the voltage level at which the drain-to-source on-resistance of the JFET is minimized, and the voltage level does not exceed the inflection point voltage of the gate-to-source pn junction.

4. The JFET cascode circuit according to claim 2, wherein, The overdrive voltage circuit is configured to bias the JFET gate terminal according to the controlled overdrive value during the on-state and the off-state.

5. The JFET cascode circuit according to claim 2, wherein, The JFET includes a gate-to-source pn junction formed by the gate and source of the JFET, and The overdrive voltage circuit is configured to limit the forward current flowing into the gate-to-source pn junction to a predefined value during the conduction state.

6. The JFET cascode circuit according to claim 1, wherein, The reference terminal is coupled to the common source node of the JFET cascode circuit, and the reference potential is provided at the common source node, which corresponds to the source terminal of the voltage-controlled transistor.

7. The JFET cascode circuit according to claim 1, wherein, The overdrive voltage circuit includes a transformer configured to supply power to the gate driver according to the unipolar power supply scheme. The transformer includes a primary winding and a secondary winding, and The power supply terminal, the reference terminal, and the output terminal are coupled to the secondary coil, wherein the output terminal is coupled to the secondary coil at the center tap position between the power supply terminal and the reference terminal.

8. The JFET cascode circuit according to any one of claims 1 to 7, wherein, The overdrive voltage circuit is a voltage divider configured to continuously provide the controlled overdrive value during the on-state and the off-state, thereby generating a permanent positive bias at the JFET gate terminal during the on-state and the off-state.

9. The JFET cascode circuit according to any one of claims 1 to 7, wherein, The overdrive voltage circuit is a voltage regulator configured to continuously provide the controlled overdrive value during the on-state and the off-state, thereby generating a permanent positive bias at the JFET gate terminal during the on-state and the off-state.

10. A junction field-effect transistor (JFET) cascode circuit, comprising: A gate driver configured to be powered according to a unipolar power supply scheme including a supply potential and a reference potential sufficient to satisfy a controlled overdrive voltage, the gate driver being configured to generate a gate drive signal including a first gate drive signal during an on-state and a second gate drive signal during an off-state. A JFET having a JFET gate terminal, the JFET gate terminal being configured to control the conduction of current through the JFET according to the gate-source voltage; A voltage-controlled transistor, the voltage-controlled transistor being coupled to the JFET in a cascode configuration at a cascode node, the voltage-controlled transistor including a transistor gate terminal coupled to the gate driver, and the transistor gate terminal being configured to control the conduction of current through the voltage-controlled transistor based on a first gate drive signal or a second gate drive signal; as well as An overdrive voltage circuit, comprising a power supply terminal providing the power supply potential, a reference terminal providing the reference potential, and an output terminal coupled to the JFET gate terminal and providing the controlled overdrive voltage. The overdrive voltage circuit is configured to set the controlled overdrive voltage to a predetermined amount of the supply voltage, and The common-source cascode node is configured to float to a potential higher than the JFET gate potential during the off state, so as to set the JFET to a blocking mode.

11. A junction field-effect transistor (JFET) cascode control circuit configured to control a JFET cascode circuit, the JFET cascode circuit including a voltage-controlled transistor coupled to the JFET in a cascode configuration, the JFET cascode control circuit comprising: A gate driver configured to be powered according to a unipolar power supply scheme including a power supply potential and a reference potential sufficient to satisfy a controlled overdrive value, the gate driver being configured to generate a gate drive signal based on a control signal, including a first gate drive signal during an on-state and a second gate drive signal during an off-state, and output the first gate drive signal or the second gate drive signal at a gate drive terminal configured to be coupled to the gate terminal of the voltage-controlled transistor; An overdrive voltage circuit, the overdrive voltage circuit including a power supply terminal providing the power supply potential, a reference terminal providing the reference potential, and an output terminal configured to be coupled to the gate terminal of the JFET. The overdrive voltage circuit is configured to generate the controlled overdrive value as part of the supply potential and output the controlled overdrive value from the output terminal to the JFET gate terminal.

12. The JFET cascode control circuit according to claim 11, wherein, The overdrive voltage circuit includes a transformer configured to supply power to the gate driver according to the unipolar power supply scheme. The transformer includes a primary winding and a secondary winding, and The power supply terminal, the reference terminal, and the output terminal are coupled to the secondary coil, wherein the output terminal is coupled to the secondary coil at the center tap position between the power supply terminal and the reference terminal.

13. The JFET cascode control circuit according to claim 11 or 12, wherein, The overdrive voltage circuit is a voltage divider configured to continuously provide the controlled overdrive value during the on-state and the off-state, thereby generating a permanent positive bias at the JFET gate terminal during the on-state and the off-state.

14. The JFET cascode control circuit according to claim 11 or 12, wherein, The overdrive voltage circuit is a voltage regulator configured to continuously provide the controlled overdrive value during the on-state and the off-state, thereby generating a permanent positive bias at the JFET gate terminal during the on-state and the off-state.

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