Junction field effect transistor cascode circuit and corresponding control circuit

Abstract

Junction field effect transistor common source common gate circuits and corresponding control circuits are provided. A junction field effect transistor (JFET) common source common gate circuit includes a gate driver configured to be powered according to a unipolar power supply scheme, the gate driver configured to output a gate drive signal from a gate drive terminal; a JFET having a JFET gate terminal configured to control conduction of current through the JFET according to a JFET gate potential; a voltage controlled transistor coupled to the JFET in a common source common gate configuration, the voltage controlled transistor including a transistor gate terminal coupled to the gate drive terminal and configured to control conduction of current through the voltage controlled transistor; and a voltage limiting circuit coupled to the gate drive terminal and the JFET gate terminal, a voltage limiting element configured to adjust the JFET gate potential based on the gate drive signal such that, during a turn-on condition of the JFET, the JFET gate potential is limited to a controlled overdrive value.

Description

Technical Field

[0001] This invention relates to a common-source, common-gate junction field-effect transistor (JFET) circuit and its corresponding control circuit. Background Technology

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as driving electric motors or generators, rely on power semiconductor devices. For example, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes are used in a variety of applications, including but not limited to switches in power supplies, power converters, and power distribution.

[0003] Solid-state switches use electronic components (such as transistors, thyristors, or solid-state relays) instead of mechanical switches or contactors to control the flow of electrical power. Unlike traditional switches that physically move parts to establish or break a circuit, solid-state switches use semiconductor materials to achieve this without moving any parts.

[0004] In power distribution systems, solid-state switches typically need to block the flow of current in both directions (positive and negative voltage) and conduct current in both directions (positive and negative current flow). To achieve this, two semiconductor switches are usually connected source-to-source (sometimes called a back-to-back configuration). This source-to-source configuration is a key difference from typical power converter topologies (e.g., inverters or rectifiers), where the goal is usually unidirectional conduction or controlled energy transfer, rather than purely bidirectional interruption.

[0005] A transistor typically comprises a semiconductor structure configured to conduct load current along a load current path between two load terminal structures of the transistor. Furthermore, the load current can be controlled by the transistor's control electrode (sometimes called the gate electrode). For example, upon receiving a corresponding control signal from, for example, a gate driver, the control electrode can set its transistor to one of two states: on or off. Thus, the semiconductor structure behaves similarly to a switch with on and off states (i.e., on and off states, respectively). The load current can be controlled by driving two complementary transistors. The amplitude of the control signal received from the gate driver for each transistor can be varied to drive the two complementary transistors between switching states. For example, the gate-source voltage VGS of a MOSFET is typically driven down to near zero to turn off the MOSFET and typically driven to its maximum value to fully turn on the MOSFET. Therefore, the gate-source voltage VGS can be referred to as the control voltage. Summary of the Invention

[0006] In some implementations, a junction field-effect transistor (JFET) cascode circuit includes: a gate driver configured to be powered according to a unipolar power supply scheme, the gate driver being configured to output a gate drive signal from a gate drive terminal of the gate driver; a JFET having a JFET gate terminal configured to control the conduction of current through the JFET based on a JFET gate potential based on the gate drive signal; a voltage-controlled transistor coupled to the JFET in a cascode configuration, the voltage-controlled transistor including a transistor gate terminal coupled to the gate drive terminal and configured to control the conduction of current through the voltage-controlled transistor based on the gate drive signal; and a voltage limiting circuit coupled to the gate drive terminal and the JFET gate terminal, the voltage limiting circuit including a voltage limiting element configured to adjust the JFET gate potential based on the gate drive signal such that during the steady-state conduction of the JFET, the maximum value of the JFET gate potential is limited to a controlled overdrive value, wherein the voltage limiting element is an active device.

[0007] A cascode control circuit for a junction field-effect transistor (JFET) is provided. The JFET cascode control circuit is configured to control a JFET cascode circuit including a voltage-controlled transistor coupled to the JFET in a cascode configuration. In some implementations, the JFET cascode control circuit includes: a gate driver configured to be powered according to a unipolar power supply scheme, the gate driver being configured to receive a control signal and output a gate drive signal from a gate drive terminal configured to be coupled to the gate terminal of the voltage-controlled transistor based on the control signal; and a voltage limiting circuit coupled to the gate drive terminal and including an overdrive terminal configured to be coupled to the JFET gate terminal, the voltage limiting circuit including a voltage limiting element configured to output an adjusted signal at the overdrive terminal based on the gate drive signal, such that during the steady-state conduction of the JFET, the maximum value of the JFET gate potential is limited to a controlled overdrive value, wherein the voltage limiting element is an active device. Attached Figure Description

[0008] This article describes the implementation method with reference to the accompanying drawings.

[0009] Figure 1 The graph shows the relationship between the drain-to-source on-resistance (RDSon) and VGS of an n-channel high-voltage (HV) JFET.

[0010] Figure 2 The assembly of the power switch and clamping element is shown.

[0011] Figure 3This is a schematic block diagram illustrating a JFET cascode circuit according to one or more implementations.

[0012] Figure 4 This is a schematic block diagram illustrating a JFET cascode circuit according to one or more implementations.

[0013] Figure 5 This is a schematic block diagram illustrating a JFET cascode circuit according to one or more implementations.

[0014] Figure 6 This is a schematic block diagram illustrating a JFET cascode circuit according to one or more implementations. Detailed Implementation

[0015] The following text elaborates on details to provide a more thorough explanation of the illustrative implementations. However, it will be apparent to those skilled in the art that these implementations can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagrams or schematics rather than in detail to avoid obscuring the implementation. Furthermore, unless otherwise specifically indicated, features of the different implementations described below can be combined with each other.

[0016] Furthermore, in the following description, equivalent or similar elements, or elements having equivalent or similar functions, are indicated by equivalent or similar reference numerals. Since identical or functionally equivalent elements are given the same reference numerals in the drawings, repeated descriptions of elements with the same reference numerals can be omitted. Therefore, the descriptions provided for elements with the same or similar reference numerals are interchangeable.

[0017] It should be understood that when an element is referred to as “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, there are no intermediate elements. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).

[0018] In the implementations described herein or illustrated in the accompanying drawings, any direct electrical connection or coupling (e.g., any connection or coupling without additional intermediate elements) may also be implemented by an indirect connection or coupling (e.g., a connection or coupling with one or more additional intermediate elements, and vice versa), as long as the general purpose of the connection or coupling is substantially maintained (e.g., transmitting a signal or transmitting information). Features from different implementations may be combined to form other implementations. For example, unless otherwise stated, variations or modifications described with respect to one implementation may also be applicable to other implementations.

[0019] As used herein, the terms “substantially” and “approximately” mean “within reasonable tolerances of manufacturing and measurement.” For example, the terms “substantially” and “approximately” may be used herein to describe small manufacturing tolerances or other factors (e.g., within 5%) that are considered acceptable in the industry, without departing from aspects of the implementation described herein. For example, a resistor with an approximate resistance value may actually have a resistance within 5% of the approximate resistance value. As another example, a signal with an approximate signal value may actually have a signal value within 5% of the approximate signal value.

[0020] In this disclosure, expressions including ordinal numbers such as "first" and "second" may modify various elements. However, such elements are not limited by such expressions. For example, such expressions do not limit the order and / or importance of elements. Rather, such expressions are used only for the purpose of distinguishing an element from other elements. For example, a first box and a second box indicate different boxes, although both are boxes. As a further example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure.

[0021] A transistor, also known as a power switch, power semiconductor, logic switch, or transistor switch, is used to drive current such as load current. Specifically, a power transistor is a power semiconductor device that can be used to drive load current. A power transistor includes a first load terminal (e.g., source or emitter) and a second load terminal (e.g., drain or collector). Additionally, the load current path of a power transistor can be controlled by a control electrode (sometimes called the gate) connected to the control terminal of the power transistor. The load current path of a power transistor is a gate-controlled conductive channel whose conductivity can be controlled by a control voltage applied to the control electrode of the power transistor. For example, a power transistor can be turned on or off by activating and deactivating its control electrode. For example, applying a positive voltage across the gate and source of a MOSFET will keep the MOSFET in its "on" state, while applying a near-zero or slightly negative voltage across the gate and source of a MOSFET will "off" the MOSFET. As used herein, the terms "on state," "on condition," "steady-state on condition," "current on state," and "on mode" are used interchangeably to refer to the on state of a transistor. In addition, terms such as "off state," "off condition," "current blocking state," and "blocking mode" can be used interchangeably to refer to the off state of a transistor.

[0022] There are turn-on and turn-off processes for turning on and off transistors. During the turn-on process of an n-channel transistor, the gate driver can be used to supply a (source) gate current (e.g., a turn-on current) to the gate of the n-channel transistor to charge the gate voltage to a voltage sufficient to turn on the n-channel transistor. Conversely, during the turn-off process of an n-channel transistor, the gate driver is used to draw (sink) a gate current (e.g., a turn-off current) from the gate of the n-channel transistor to fully discharge the gate voltage to turn off the n-channel transistor. A voltage pulse can be output from the gate driver as a control signal according to a pulse width modulation (PWM) scheme. Therefore, the control signal can be switched between the turn-on voltage level and the turn-off voltage level during the PWM cycle to control the n-channel transistor. This, in turn, charges and discharges the gate capacitance to correspondingly modulate the gate voltage to turn on and off the n-channel transistor, respectively.

[0023] For p-channel transistors, the situation is exactly the opposite. A gate driver can be used to draw (sink) gate current (e.g., on-state current) from the gate of a p-channel transistor to discharge the gate voltage sufficiently to turn the p-channel transistor on. Conversely, during the turn-off process of a p-channel transistor, the gate driver is used to supply (source) gate current (e.g., turn-off current) to the gate of the p-channel transistor to fully charge the gate voltage to turn it off. A control signal applied to the gate of the p-channel transistor can be switched between on-state and off-state voltage levels during the PWM cycle to control the p-channel transistor. This, in turn, charges and discharges the gate voltage to turn the p-channel transistor on and off, respectively.

[0024] For both n-channel and p-channel transistors, when the gate-source voltage VGS is approximately zero or below the threshold voltage, both n-channel and p-channel transistors are turned off, while when the gate-source voltage VGS is equal to or greater than the threshold voltage, both n-channel and p-channel transistors are turned on.

[0025] Another type of transistor is the junction field-effect transistor (JFET). An n-channel JFET as a standalone component is a normally-on device. To turn off an n-channel JFET, a negative voltage (e.g., negative VGS, where the source has a higher potential than the gate) must be applied between the gate and source contacts. In some applications, normally-off behavior of the power stage is required (e.g., the drain-source connection is in a high-impedance state, and no active control signal is applied at the gate). In other applications, the introduction of the negative control voltage required to put the n-channel JFET into a high-impedance state (off state) is impractical or undesirable. In both cases, the JFET can be used in series with a normally-off device, such as a standard enhancement-mode MOSFET, to meet design requirements. The circuit topology of connecting a JFET in series with a normally-off device is called a cascode JFET. However, to optimize the performance of a cascode JFET, certain characteristics of the cascode JFET must be considered.

[0026] In solid-state power distribution applications, the total path resistance of the power stage (e.g., drain-to-source on-resistance (RDSon)) is important. In this case, the minimum possible RDSon of the JFET can be achieved through gate control circuitry. For example, the RDSon of the JFET can be controlled by controlling the gate-to-source voltage of the JFET during the on-state.

[0027] Figure 1Graph 100 shows the relationship between RDSon and VGS for an n-channel high-voltage (HV) JFET. Some n-channel power JFETs exhibit a significant gate-source voltage (VGS) dependence of RDSon values ​​near VGS = 0 V. Applying a positive VGS further reduces the channel RDSon compared to the RDSon value present at VGS = 0 V. In the example shown in Graph 100, a 17% reduction in RDSon can be achieved by applying a positive VGS compared to the RDSon at VGS = 0 V. Therefore, a positive VGS can be referred to as overdrive voltage, overdrive gate voltage, overdrive VGS, or overdrive value. In other words, the overdrive voltage is the positive voltage between the gate and source of the JFET at which RDSon is further reduced compared to VGS equal to 0 V. Due to the structure of the n-channel JFET, the maximum applicable gate voltage is limited by the intrinsic gate-to-source pn junction and gate-to-drain pn junction of the JFET. For example, once VGS or the gate-drain voltage VGD exceeds a certain voltage of the corresponding intrinsic pn junction, such as the inflection point voltage, the intrinsic gate-to-source pn junction and the gate-to-drain pn junction begin to conduct high-level gate currents. The inflection point voltage (also known as the threshold voltage) of an intrinsic pn junction is the minimum forward voltage at which the pn junction begins to conduct significantly. For example, for silicon pn junctions, the inflection point voltage is typically between 0.6 V and 0.7 V, and for silicon carbide (SiC) pn junctions, it is typically between approximately 2.5 V and 3 V (note that the inflection point voltage of a particular intrinsic pn junction can depend on device characteristics such as doping level and temperature). Conducting high-level gate currents through the intrinsic gate-to-source pn junction and the gate-to-drain pn junction is undesirable because the current flowing through these intrinsic pn junction structures increases power dissipation in the JFET and burdens the power supply to the gate driver. Furthermore, once the VGS voltage level exceeds the inflection point voltages of the gate-to-source pn junction and the gate-to-drain pn junction, a saturation effect of d(RDSon) / d(VGS) will be observed. Therefore, it is preferable that during the steady-state conduction of the JFET (e.g., when the JFET is in the on state), the VGS level driving the JFET (e.g., the overdrive voltage) is close to the inflection point voltage level of the intrinsic pn junction to achieve a minimum RDSon while keeping the steady-state gate current at a low level.

[0028] In some applications (e.g., solid-state power distribution), transistor chip sizes can be large to achieve the desired low RDSon (e.g., <1 mOhm at a VBDss rating of 1200 V, where VBDss refers to the drain-source breakdown voltage). Therefore, the total gate charge of a JFET device (primarily the gate-drain charge (Qgd)) can be very high, easily exceeding 1000 nanocoulombs (nC). To achieve reasonably fast switching behavior (dV / dt > 1 kV / µs) in a JFET device, high transient gate currents, potentially exceeding 10 A, are required. Crucially, the high transient current capability of the gate drive circuitry must be enabled to maintain safe control of the power device during voltage transients applied across the drain-source contacts of the JFET (e.g., during switching transients of external air-gap devices). Therefore, implementing a very low impedance drive circuitry for the JFET gate may be necessary.

[0029] While transient gate drive currents can be large due to the large transistor size, average gate drive current consumption can be very low in solid-state power distribution applications because JFETs operate at low switching frequencies (e.g., operating frequency << 1 Hz). Therefore, it is important to minimize the leakage current continuously fed to the JFET gate in order to reduce the workload of the power supply scheme used for the gate drive circuitry.

[0030] In solid-state power distribution applications, the turn-off current level (current density) can be very high, approaching the specified absolute maximum pulse current level of the power device. Furthermore, energy stored in the remaining line / load inductance of the external circuitry is absorbed by clamping elements and partially by the JFET itself.

[0031] In the event of overcurrent shutdown, the power semiconductor must support the switching of the shutdown current to the clamping element (e.g., a variable resistor (MOV), a transient voltage suppressor (TVS), a resistor-capacitor (RC) network, etc.). Once the switching is complete, the power semiconductor must block the clamping voltage of the clamping element.

[0032] Figure 2 An assembly 200 comprising a power switch (e.g., a JFET) and a clamping element is shown. The JFET and clamping element each have a series parasitic stray inductance L. stray,Switch and L Stray,Clamp For successful commutation, the JFET must provide a blocking voltage higher than the steady-state clamping voltage of the clamping element. The blocking voltage during commutation can be calculated using Equation 1.

[0033] While conventional switching devices such as MOSFETs use control measures (e.g., increasing the gate resistance) to set the switching speed of the output stage to avoid exceeding the specified maximum VBDss of the power device, n-channel power JFET devices can operate in an unclamped inductor switching (UIS) mode. In this mode, an internal drain-gate diode is used to drive the JFET into linear mode, providing a controlled VDS voltage at or above the specified maximum VBDss. This clamped mode must be enabled via a dedicated gate control scheme. Linear mode is achieved by the voltage drop induced in the gate resistor network by the avalanche breakdown current of the drain-gate pn junction.

[0034] Some implementations disclosed herein involve JFET cascode circuits, which provide an efficient way to drive discrete JFET cascode circuits, offering the best possible RDSon with minimal circuit complexity, required gate drive strength, and minimized steady-state supply current consumption. A JFET cascode circuit includes a JFET and a voltage-controlled transistor, such as a MOSFET, coupled to the JFET in a cascode configuration. For example, in a cascode configuration, the source terminal of the JFET can be coupled to the drain terminal of the voltage-controlled transistor at the cascode node. The voltage-controlled transistor can be driven to control the potential at the cascode node to place the JFET in current-conducting or blocking mode. For example, when the voltage-controlled transistor is in blocking mode, the cascode node can be configured to float to a potential higher than the JFET gate potential (e.g., making VGS negative) to set the JFET to blocking mode. Conversely, when the voltage-controlled transistor is in current-conducting mode, the potential at the cascode node can be pulled low by the voltage-controlled transistor such that VGS is sufficient to set the JFET to current-conducting mode. Therefore, the on / off state of the JFET is indirectly controlled by controlling the on / off state of the voltage-controlled transistor, where the JFET's on is based on the on of the voltage-controlled transistor, and the JFET's off is based on the off of the voltage-controlled transistor. When the voltage-controlled transistor is in current conduction mode, if an overdrive signal (e.g., an overdrive potential) is applied to the gate of the JFET, the VGS of the JFET will be positive, thereby achieving overdrive VGS and reducing the RDSon of the JFET.

[0035] In some implementations, the JFET gate drive voltage is derived from the output voltage of the gate driver via a voltage limiter. The voltage limiter includes a voltage-limiting element that is an active device. Example active devices are transistors or thyristors, while example passive devices are resistors or diodes. The voltage supplied to the JFET gate by the voltage limiter is limited by the voltage limiter or otherwise adjusted to a level below the inflection point voltage of the intrinsic GS pn junction of the JFET. Due to the control of the JFET gate drive voltage, the applied VGS overdrive voltage can be set such that a reduced or minimal RDSon (e.g., to a predefined reduced RDSon value) can be achieved at the JFET, while the forward current entering the intrinsic GS pn junction of the JFET is limited to a predefined current value. A current-limiting element R is positioned between the output of the voltage limiter and the JFET gate. JGATE Instead of limiting the current fed to the JFET gate under steady-state conduction conditions, it can be provided and sized to optimize the switching performance of the JFET and maintain stable operation under external distortion.

[0036] The gate driver includes a buffer configured to generate a gate drive signal. The buffer may include a pair of complementary FETs for generating the gate drive signal. For example, one FET (e.g., a source FET) may be connected to a positive supply potential and, when enabled, pulls the gate drive signal up toward the positive supply potential (e.g., a high level). The other FET (e.g., a sink FET) may be connected to a reference potential (e.g., ground potential) and, when enabled, pulls the gate drive signal toward the reference potential (e.g., a low level). When enabled, the source FET may generate a turn-on current Io+ (e.g., a source current) to charge the gate of the transistor to turn it on. When enabled, the sink FET may generate a turn-off current Io- (e.g., a sink current) to discharge the gate of the transistor to turn it off.

[0037] Therefore, the gate driver is powered by a unipolar supply scheme using only one power rail (e.g., +12 V) and a single ground / reference (e.g., 0 V). All voltages in the system are positive (or zero) relative to the ground of the unipolar supply scheme. In other words, all voltage potentials in the circuit swing with only one polarity (e.g., positive) relative to ground. Thus, the JFET cascode circuit is simplified compared to gate driver circuits using multi-supply schemes with two or more positive power supplies and / or two or more reference power supplies (one of which can be negative).

[0038] When the JFET cascode circuit is turned off by the gate driver, the JFET gate can be pulled low to the gate driver level. Due to the blocking channel of the voltage-controlled transistor, the source potential of the JFET floats high, resulting in the negative VGS voltage required to switch the JFET to blocking mode.

[0039] The steady-state drive current of the JFET cascode circuit arrangement is minimized to the gate of the voltage-controlled transistor and the leakage current of the JFET gate. Because the switching frequency of typical solid-state power distribution applications is very low, the JFET cascode circuit allows coreless transformers to be used as power supply elements, which may be important for reducing the size and cost of solid-state circuit breaker (SSCB) implementations.

[0040] Furthermore, the JFET cascode circuitry provides a very low-ohm gate drive solution, enabling safe and stable operation of the JFET while minimizing gate drive current requirements and still achieving the best possible RDSon in conduction mode (e.g., during the steady-state conduction of the JFET).

[0041] Figure 3 This is a schematic block diagram illustrating a JFET cascode circuit 300 according to one or more implementations. The JFET cascode circuit 300 may include a gate driver 302, a JFET 304, a voltage-controlled transistor 306, and a voltage limiting circuit 308 (e.g., an overdrive voltage circuit). The JFET 304 may be an n-channel high-voltage (HV) JFET, and the voltage-controlled transistor 306 may be an n-channel low-voltage (LV) MOSFET.

[0042] The gate driver 302 is configured to be powered according to a unipolar power supply scheme. The unipolar power supply scheme includes a supply potential V sufficient to satisfy a controlled overdrive value (e.g., a controlled overdrive voltage). DRV (For example, a single supply potential, such as +12 V) and a reference potential V REF (For example, a single reference potential, such as 0 V or ground). Gate driver 302 is configured to output a gate drive signal from the gate drive terminal of gate driver 302 based on one or more control signals. For example, gate driver 302 may receive a PWM control signal from a controller and generate a gate drive signal based on the PWM control signal. In some implementations, gate driver 302 may receive two or more PWM control signals from a controller. For example, a first PWM control signal may be used to control the source FET of gate driver 302, and a second PWM control signal may be used to control the sink FET of gate driver 302. During the on-state of JFET cascode circuit 300, gate driver 302 may set the gate drive signal to the supply potential V. DRV And / or provide on-current, and during the off-state of the JFET cascode circuit 300, the gate driver 302 can set the gate drive signal to the reference potential V. REF And / or provide shutdown current.

[0043] JFET 304 includes a JFET gate terminal (G) configured to control the conduction of current through the JFET based on the JFET gate potential based on the gate drive signal.

[0044] The voltage-controlled transistor 306 is coupled to the JFET in a cascode configuration. For example, the source terminal (S) of the JFET 304 can be coupled to the drain terminal (D) of the voltage-controlled transistor 306 at the cascode node 310 to form a cascode configuration. The source terminal of the voltage-controlled transistor 306 can be coupled to the common source node 312 of the JFET cascode circuit 300, wherein the common source node 312 is coupled to a reference potential V. REF Therefore, the source terminal of the voltage-controlled transistor 306 can be grounded.

[0045] The voltage-controlled transistor 306 includes a transistor gate terminal (G) coupled to a gate drive terminal of a gate driver 302 and is configured to control the conduction of current through the voltage-controlled transistor 306 based on a gate drive signal.

[0046] A voltage limiting circuit 308 is coupled to the gate drive terminal and the JFET gate terminal. The voltage limiting circuit 308 includes at least one voltage limiting element configured to adjust the JFET gate potential based on the gate drive signal, such that during the steady-state conduction of the JFET 304, the maximum value of the JFET gate potential is limited to a controlled overdrive value. For example, the controlled overdrive potential V provided by the voltage limiting circuit 308 can be used as a reference. OD To limit the JFET gate potential. In some implementations, during the steady-state conduction of JFET 304, the voltage limiting circuit 308 sets the JFET gate potential to a controlled overdrive value. Therefore, during the steady-state conduction of JFET 304, a controlled overdrive voltage (e.g., controlled overdrive VGS) can be established between the gate and source terminals of JFET 304. The gate-to-source pn junction 314 of JFET 304 is... Figure 3 The diode is represented in the image. The gate-to-source pn junction 314 is an intrinsic gate-to-source pn junction formed by the gate and source of the JFET 304. The JFET 304 also includes a gate-to-drain pn junction inherently formed by the gate and drain of the JFET 304. The voltage limiting element is an active device. For example, the voltage limiting element can be a transistor or an operational amplifier.

[0047] In some implementations, the voltage limiting circuit 308 can be configured to provide a controlled overdrive value at the JFET gate that is a positive value less than the gate-to-source pn junction voltage 314 (e.g., the controlled overdrive VGS is less than the gate-to-source pn junction voltage 314). In some implementations, the controlled overdrive value can be a voltage level at which the RDSon of the JFET 304 is minimized or set to a predefined value, provided that this voltage level does not exceed the gate-to-source pn junction voltage. In other words, the controlled overdrive value can be a positive value at which the controlled overdrive VGS causes the RDSon of the JFET 304 to be minimized or set to a predetermined value, provided that the controlled overdrive VGS does not exceed the gate-to-source pn junction voltage.

[0048] In some implementations, the voltage limiting element of the voltage limiting circuit 308 can bias the JFET gate terminal according to a controlled overdrive value during the steady-state conduction of the JFET, wherein the controlled overdrive value is a voltage level at which the RDSon of the JFET 304 is minimized or set to a predefined value.

[0049] In some implementations, the voltage limiting element of the voltage limiting circuit 308 can limit the forward current flowing into the gate-to-source pn junction 314 to a predetermined value during the steady-state conduction of the JFET.

[0050] During operation, the gate driver 302 sets the gate drive signal to the supply potential V. DRV The voltage-controlled transistor 306 is turned on, thereby setting the JFET 304 to a current-conducting state. Alternatively, the gate driver 302 can set the gate drive signal to a reference potential V. REF The voltage-controlled transistor 306 is turned off, thereby setting JFET 304 to the blocking state. In some implementations, the voltage-limiting element of the voltage-limiting circuit 308 can set the JFET gate potential to the reference potential V during the turn-off state of JFET 304. REF This can help turn off JFET 304 by making its VGS more negative. For example, the cascode node 310 can be configured to float to a potential higher than the JFET gate potential during the turn-off state of JFET 304, thus setting JFET 304 to a blocking state. For example, when the voltage-controlled transistor 306 is placed in a blocking state by a gate drive signal, the blocking state of the voltage-controlled transistor 306 can cause the cascode node 310 to float to a potential higher than the JFET gate potential, making the VGS of JFET 304 sufficiently negative to turn off JFET 304.

[0051] In some implementations, the voltage limiting element is configured to receive the gate drive signal as a power supply input, and to limit the gate drive signal at the output of the voltage limiting element, thereby limiting the JFET gate potential to a controlled overdrive value. Alternatively, in some implementations, the voltage limiting element is configured to receive the supply potential V. DRV As a power input, and limiting the power supply potential V at the output of the voltage limiting element. DRV This limits the JFET gate potential to a controlled overdrive value.

[0052] The JFET cascode circuit 300 may also include current-limiting elements (e.g., gate resistors) connected to the gates of the JFET 304 and the voltage-controlled transistor 306. For example, a first current-limiting element R... JGATE It can be coupled to the JFET gate terminal of JFET 304, and the second current limiting element R LVGATE It can be coupled to the gate terminal of the voltage-controlled transistor 306. The first current-limiting element R is placed between the output of the voltage-limiting circuit 308 and the gate of the JFET. JGATE It can be supplied and sized to optimize the switching performance of the JFET 304 and maintain stable operation under external distortion.

[0053] As mentioned above, Figure 3 Provided as an example only. Other examples may differ from those provided. Figure 3 The example described.

[0054] Figure 4 This is a schematic block diagram illustrating a JFET cascode circuit 400 according to one or more implementations. The JFET cascode circuit 400 can be similar to a combination of... Figure 3 The described JFET cascode circuit 300 includes, in more detail, an example implementation of a voltage limiting circuit 308. Therefore, the JFET cascode circuit 400 includes a gate driver 302, a JFET 304, a voltage-controlled transistor 306, and a voltage limiting circuit 308 (e.g., an overdrive voltage circuit), as described above. Figure 3 As stated above.

[0055] exist Figure 4 In the example shown, the voltage limiting element 316 of the voltage limiting circuit 308 is shown as a transistor. In some implementations, the voltage limiting element 316 may be an npn transistor. The voltage limiting element 316 may be configured to receive a gate drive signal as a power supply input and limit the gate drive signal at its output such that the JFET gate potential is limited to a controlled overdrive value. For example, the voltage limiting element 316 may receive the gate drive signal as a power supply input at its collector terminal and limit the gate drive signal at its emitter terminal.

[0056] When the gate driver 302 is driven high (e.g., V), DRV When ), Zener diode D1 is biased by resistor R. bias Bias and set the reference bias voltage V Bias During a turn-on event or negative voltage transient at the JFET drain contact, the limiting element 316 provides a very low impedance output to the JFET gate, enabling the JFET 304 to quickly turn on from the off state and a stable gate voltage during voltage transients. A charging resistor Rj can be implemented. charge To tune the conduction characteristics of the JFET 304 (e.g., negative dV / dt switching slope).

[0057] By pulling the gate drive line to the reference potential V REF The cas-source gate is turned off by gate driver 302. The JFET gate potential is controlled by discharge resistor Rj. Disc Rj formed by diode D2 Disc The / D2 discharge path discharges to the gate driver output voltage. Simultaneously, the voltage-controlled transistor 306 begins to block, causing the voltage at the cascode node 310 to rise. Once the VGS of the JFET 304 drops below its pinch-off voltage, the JFET 304 is set to the blocking state, and the cascode configuration is turned off.

[0058] In some implementations, JFET 304 can be used to absorb UIS energy within a high-voltage switching arrangement. The JFET cascode circuit 400 can enable controlled UIS operation in a cascode configuration by enabling stable linear mode operation. JFET 304 can be designed such that its drain-to-gate breakdown voltage is lower than its drain-to-source breakdown voltage. In this way, the VDS voltage of the JFET increases until the gate-to-drain pn junction 318 of the JFET 304 reaches its avalanche breakdown voltage. This is due to the avalanche current supplied at the JFET gate terminal causing a discharge path Rj. Disc The voltage drop across / D2 causes an increase in the effective VGS voltage at JFET 304. Simultaneously, the VDS voltage at voltage-controlled transistor 306 is controlled and limited to a fixed level determined by a diode feedback network D3 / D4, which consists of a pair of back-to-back coupled diodes D3 and D4. Diode D3 can be a Zener diode providing the reference voltage, and diode D4 can be a junction diode. In this way, both JFET 304 and voltage-controlled transistor 306 operate in linear mode at the defined VDS rating until the unclamped current decays. Once the VDS voltage collapses, the JFET gate is discharged to the reference potential V.REF Furthermore, the common-source cascode node 310 stabilizes at the voltage required to pinch off the JFET 304.

[0059] The voltage limiting circuit 308 may include a Zener diode D1, which has a cathode coupled to a reference node (e.g., common source node 312) of the JFET cascode circuit 400 and an anode coupled to a control terminal (e.g., base terminal) of the voltage limiting element 316. Therefore, the cathode of the Zener diode D1 is coupled to a reference potential V. REF (For example, ground potential). A voltage reference element can be coupled between the control terminal of the voltage limiting element 316 and the reference node. The voltage reference element can be configured to be biased by a gate drive signal such that the signal provided by the voltage reference element depends on the state of the gate drive signal. For example, the voltage reference element can be a Zener diode D1 having a first cathode coupled to the reference node of the JFET cascode circuit and a first anode coupled to the control terminal of the voltage limiting element. Bias resistor R bias The gate driver 302 is coupled at one end to the gate drive terminal and at the other end to the anode of the Zener diode D1. The gate driver 302 can drive the gate drive signal between high and low levels. Therefore, the Zener diode D1 can conduct current in reverse conduction mode based on the gate drive signal being high, and the voltage at the control terminal of the voltage limiting element 316 is set to the reverse bias reference voltage of the Zener diode D1 (e.g., the Zener breakdown voltage of the Zener diode D1). The gate driver 302 is coupled to the common source node 312, and the low level corresponds to the reference potential V at the common source node 312. REF .

[0060] Additionally, the voltage limiting circuit 308 may include a diode D2, such as a Schottky diode, having a cathode coupled to the gate drive terminal and an anode coupled to the output of the voltage limiting element 316 and the JFET gate terminal. Diode D2 can discharge the JFET gate terminal to a low level (e.g., to a reference potential V) based on a low gate drive signal. REF ).

[0061] Gate resistor R GMOS A pair of back-to-back coupled diodes D3 and D4 can be coupled between the gate drive terminal and the gate terminal of the voltage-controlled transistor 306 to provide a gate drive signal to the gate terminal of the voltage-controlled transistor 306. For the above reasons, a pair of back-to-back coupled diodes D3 and D4 can be coupled to the drain terminal and the gate terminal of the voltage-controlled transistor 306, respectively. The pair of back-to-back coupled diodes D3 and D4 can be arranged in the gate resistor R. GMOS Between the transistor gate terminal and the voltage-controlled transistor 306.

[0062] In some implementations, the discharge path can be coupled to a reference potential V. REF (e.g., ground potential) instead of being coupled to the gate drive terminal (e.g., coupled to the gate drive signal line), and diode D2 can be replaced by an active element such as a transistor.

[0063] As mentioned above, Figure 4 Provided as an example only. Other examples may differ from those provided. Figure 4 Example of the description.

[0064] Figure 5 This is a schematic block diagram illustrating a JFET cascode circuit 500 according to one or more implementations. The JFET cascode circuit 500 can be similar to a combination of... Figure 3 The described JFET cascode circuit 300 includes an example implementation of a voltage limiting circuit 308 in more detail. Furthermore, the JFET cascode circuit 500 can be similarly combined with... Figure 4 The described JFET cascode circuit 400, except that the voltage limiting element 316 is configured to receive the supply potential V, DRV As a power supply input (instead of a gate drive signal, such as...) Figure 4 (as shown), and limits the supply potential V at the output of the voltage limiting element 316. DRV This limits the JFET gate potential to a controlled overdrive value. Therefore, the supply current for the voltage limiting element 316 can be directly obtained from the power supply pin of the gate driver 302 or the positive power supply rail of the gate driver 302. Consequently, the gate drive strength for driving the JFET 304 can be further enhanced relative to the JFET cascode circuit 400 because the output of the gate driver 302 does not limit the total current to be supplied to the JFET gate terminal during transients, but only the base current of the voltage limiting element 316 (e.g., an npn transistor). In other words, by connecting the collector of the voltage limiting element 316 to the power supply pin of the gate driver 302, the gate drive signal is no longer responsible for supplying current to the collector terminal of the voltage limiting element 316, but only for supplying current to the control terminal of the voltage limiting element 316. The voltage limiting element 316 can be a current-controlled transistor (such as a bipolar junction transistor (BJT)) or a voltage-controlled transistor.

[0065] When the gate drive signal is high, the bias resistor R biasThis causes an increase in the potential at the anode of Zener diode D1, and consequently an increase in the potential at the control terminal of voltage limiting element 316. Therefore, Zener diode D1 is configured to conduct current in reverse conduction mode based on a high gate drive signal, and the voltage at the control terminal of the voltage limiting element is set to the reverse bias reference voltage of Zener diode D1 (e.g., the Zener breakdown voltage of Zener diode D1). Zener diode D1 also has a cathode coupled to a reference node (e.g., at common source node 312) of the JFET cascode circuit 500. Therefore, the cathode of Zener diode D1 is coupled to the reference potential V. REF (For example, ground potential).

[0066] As mentioned above, Figure 5 Provided as an example only. Other examples may differ from those provided. Figure 5 Example of the description.

[0067] Figure 6 This is a schematic block diagram illustrating a JFET cascode circuit 600 according to one or more implementations. The JFET cascode circuit 600 can be similar to a combination of... Figure 4 The described JFET cascode circuit 400 differs from the one to which the cathode of the Zener diode D1 is coupled to a reference node 310 (e.g., instead of being coupled to a common source node 312). In this case, a diode blocking any forward current through the Zener diode D1 can be additionally provided in series with the Zener diode D1. Alternatively, the JFET cascode circuit 600 can be similarly combined with... Figure 5 The described JFET cascode circuit 500, except that the reference node to which the cathode of the Zener diode D1 is coupled is the cascode node 310 (e.g., not coupled to the common source node 312). Therefore, the Zener diode D1 can have a cathode coupled to the reference node (e.g., the cascode node 310) of the JFET cascode circuit 600 and an anode coupled to the control terminal of the voltage limiting element 316. In this case, a diode blocking any forward current through the Zener diode D1 can be additionally provided in series with the Zener diode D1. However, implementations other than using a Zener diode are also possible. For example, any other element suitable for providing a voltage reference, besides a Zener diode, can be used to connect the voltage limiting circuit 308 to the cascode node 310, thereby providing a predefined bias voltage V_Bias, such as... Figure 6 As depicted in the text.

[0068] In some examples, a high voltage drop can be generated across the voltage-controlled transistor 306, which can reduce the VGS overdrive voltage of the JFET 304, thereby increasing the RDSon of the JFET. Therefore, in the case of a high voltage drop across the voltage-controlled transistor 306, using the cascode node 310 as the reference node for the voltage limiting circuit 308 can be beneficial in maintaining the VGS overdrive voltage of the JFET 304 at the desired level and reducing the RDSon of the JFET 304 to the desired level, while the VGS overdrive voltage does not exceed the inflection point voltage of the gate-to-source pn junction of the JFET 304.

[0069] As mentioned above, Figure 6 Provided as an example only. Other examples may differ from those provided. Figure 6 Example of the description.

[0070] The following provides an overview of some aspects of this disclosure:

[0071] Aspect 1: A JFET cascode circuit comprising: a gate driver configured to be powered according to a unipolar power supply scheme, the gate driver being configured to output a gate drive signal from a gate drive terminal of the gate driver; a JFET having a JFET gate terminal configured to control the conduction of current through the JFET based on a JFET gate potential based on the gate drive signal; a voltage-controlled transistor coupled to the JFET in a cascode configuration, the voltage-controlled transistor including a transistor gate terminal coupled to the gate drive terminal and configured to control the conduction of current through the voltage-controlled transistor based on the gate drive signal; and a voltage limiting circuit coupled to the gate drive terminal and the JFET gate terminal, the voltage limiting circuit including a voltage limiting element configured to adjust the JFET gate potential based on the gate drive signal such that during the steady-state conduction of the JFET, the maximum value of the JFET gate potential is limited to a controlled overdrive value, wherein the voltage limiting element is an active device.

[0072] Aspect 2: The JFET cascode circuit according to aspect 1, wherein the JFET includes a gate-to-source pn junction, and wherein the controlled overdrive value is a positive value less than the inflection point voltage of the gate-to-source pn junction.

[0073] Aspect 3: According to the JFET cascode circuit of aspect 2, the controlled overdrive value is the voltage level at which the drain-to-source on-resistance of the JFET is minimized, and the voltage level does not exceed the inflection point voltage of the gate-to-source pn junction.

[0074] Aspect 4: The JFET cascode circuit according to any one of Aspects 1 to 3, wherein the voltage limiting element is configured to bias the JFET gate terminal according to a controlled overdrive value during the steady-state conduction of the JFET, and wherein the controlled overdrive value is the voltage level at which the drain-to-source on-resistance of the JFET is minimized.

[0075] Aspect 5: A JFET cascode circuit according to any one of Aspects 1 to 4, wherein the JFET includes a gate-to-source pn junction formed by the gate and source of the JFET, and wherein a voltage limiting element is configured to limit the forward current flowing to the gate-to-source pn junction to a predetermined value during the steady-state conduction of the JFET.

[0076] Aspect 6: A JFET cascode circuit according to any one of Aspects 1 to 5, wherein the unipolar power supply scheme includes a supply potential and a reference potential sufficient to satisfy a controlled overdrive value, wherein the gate driver is configured to set the gate drive signal to the supply potential to turn on the voltage-controlled transistor, such that the JFET is set to a current-conducting state, wherein the gate driver is configured to set the gate drive signal to the reference potential to turn off the voltage-controlled transistor, such that the JFET is set to a blocking state, and wherein the voltage limiting element is configured to set the JFET gate potential to the reference potential during the JFET's off state.

[0077] Aspect 7: The JFET cascode circuit according to aspect 6, wherein the source terminal of the JFET and the drain terminal of the voltage-controlled transistor are coupled at a cascode node to form a cascode configuration, and wherein the cascode node is configured to float to a potential higher than the JFET gate potential during the JFET's off state to set the JFET to a blocking state.

[0078] Aspect 8: The JFET common-source cascode circuit according to any one of Aspects 1 to 7, wherein the voltage limiting element is configured to receive the gate drive signal as a power supply input and to limit the gate drive signal at the output of the voltage limiting element such that the JFET gate potential is limited to a controlled overdrive value.

[0079] Aspect 9: The JFET cascode circuit according to Aspect 8, wherein the voltage limiting element is a transistor, and wherein the voltage limiting circuit further includes: a voltage reference element coupled between a control terminal of the voltage limiting element and a reference node, wherein the voltage reference element is configured to be biased by a gate drive signal such that the signal provided by the voltage reference element depends on the state of the gate drive signal, wherein the gate driver is configured to drive the gate drive signal between a high level and a low level, and wherein the voltage reference element is configured to conduct current in reverse conduction mode based on the gate drive signal being at a high level, and to set the voltage at the control terminal of the voltage limiting element to a reverse bias reference voltage.

[0080] Aspect 10: The JFET cascode circuit according to aspect 9, wherein the voltage reference element is a Zener diode having a first cathode coupled to a reference node of the JFET cascode circuit and a first anode coupled to a control terminal of a voltage limiting element, and wherein a bias resistor is coupled to a gate drive terminal and the first anode of the Zener diode.

[0081] Aspect 11: The JFET cascode circuit according to aspect 9, wherein the reference node is the common source node of the JFET cascode circuit, and the common source node corresponds to the source terminal of the voltage-controlled transistor.

[0082] Aspect 12: The JFET common-source cascode circuit according to aspect 11, wherein the gate driver is coupled to a common source node, and wherein a low level corresponds to a reference potential at the common source node.

[0083] Aspect 13: The JFET cascode circuit according to aspect 9, wherein the JFET and the voltage-controlled transistor are coupled at a cascode node, and wherein the reference node is a cascode node.

[0084] Aspect 14: The JFET common-source cascode circuit according to aspect 9, wherein the voltage limiting circuit further includes: a diode having a second cathode coupled to a gate drive terminal and a second anode coupled to the output of the voltage limiting element and coupled to the JFET gate terminal, wherein the diode is configured to discharge the JFET gate terminal to a low level based on the gate drive signal being at a low level.

[0085] Aspect 15: The JFET common-source common-gate circuit according to Aspect 8 further includes: a gate resistor coupled between a gate drive terminal and a transistor gate terminal of a voltage-controlled transistor for providing a gate drive signal to the transistor gate terminal of the voltage-controlled transistor; and a pair of back-to-back coupled diodes coupled to a drain terminal of a voltage-controlled transistor and a transistor gate terminal of the voltage-controlled transistor, the pair of back-to-back coupled diodes being arranged between the gate resistor and the transistor gate terminal of the voltage-controlled transistor, wherein one of the back-to-back coupled diodes is a Zener diode providing a reference voltage.

[0086] Aspect 16: A JFET common-source cascode circuit according to any one of Aspects 1 to 15, wherein the drain-to-gate breakdown voltage of the JFET is lower than the drain-to-source breakdown voltage of the JFET.

[0087] Aspect 17: The JFET cascode circuit according to any one of Aspects 1 to 16, wherein the unipolar power supply scheme includes a power supply potential and a reference potential sufficient to satisfy a controlled overdrive value, and wherein a voltage limiting element is configured to receive the power supply potential as a power supply input and limit the power supply potential at the output of the voltage limiting element such that the JFET gate potential is limited to a controlled overdrive value.

[0088] Aspect 18: The JFET cascode circuit according to aspect 17, wherein the voltage limiting element is a transistor, and wherein the voltage limiting circuit further includes: a voltage reference element coupled between a control terminal of the voltage limiting element and a reference node, wherein the voltage reference element is configured to be biased by a gate drive signal such that the signal provided by the voltage reference element depends on the state of the gate drive signal, wherein the gate driver is configured to drive the gate drive signal between a high level and a low level, and wherein the voltage reference element is configured to conduct current in reverse conduction mode based on the gate drive signal being at a high level, and to set the voltage at the control terminal of the voltage limiting element to a reverse bias reference voltage.

[0089] Aspect 19: The JFET cascode circuit according to aspect 18, wherein the reference node is the common source node of the JFET cascode circuit, and the common source node corresponds to the source terminal of the voltage-controlled transistor.

[0090] Aspect 20: The JFET common-source cascode circuit according to aspect 19, wherein the gate driver is coupled to a common source node, and wherein a low level corresponds to a reference potential at the common source node.

[0091] Aspect 21: The JFET common-source cascode circuit according to aspect 18, wherein the voltage limiting circuit further includes: a diode having a second cathode coupled to a gate drive terminal and a second anode coupled to the output of the voltage limiting element and coupled to the JFET gate terminal, wherein the diode is configured to discharge the JFET gate terminal to a low level based on the gate drive signal being at a low level.

[0092] Aspect 22: A JFET cascode circuit according to any one of aspects 1 to 21, wherein the voltage limiting element is configured to set the JFET gate potential to a low voltage level of the unipolar power supply scheme during the JFET's off state.

[0093] Aspect 23: A junction field-effect transistor (JFET) cascode control circuit configured to control a JFET cascode circuit including a voltage-controlled transistor coupled to the JFET in a cascode configuration, the JFET cascode control circuit including: A gate driver, configured to be powered according to a unipolar power supply scheme, is configured to receive a control signal and, based on the control signal, output a gate drive signal from a gate drive terminal configured to be coupled to the gate terminal of a voltage-controlled transistor. A voltage limiting circuit, coupled to a gate drive terminal and including an overdrive terminal configured to be coupled to the JFET gate terminal, includes a voltage limiting element configured to output an adjusted signal at the overdrive terminal based on a gate drive signal, such that during the steady-state conduction of the JFET, the maximum value of the JFET gate potential is limited to a controlled overdrive value. Among them, the voltage limiting element is an active device.

[0094] Aspect 24: The junction field-effect transistor (JFET) cascode control circuit according to aspect 23, wherein the unipolar power supply scheme includes a power supply potential and a reference potential sufficient to satisfy the controlled overdrive value, wherein when the control signal indicates the JFET cascode circuit to be turned on: The gate driver is configured to set the gate drive signal to the supply potential to turn on the voltage-controlled transistor, and the voltage limiting element is configured to output an adjusted signal according to the controlled overdrive value, wherein, when the control signal indicates that the JFET cascode circuit is turned off: The gate driver is configured to set the gate drive signal to a reference potential to turn off the voltage-controlled transistor, and the voltage limiting element is configured to set the overdrive terminal to a reference potential.

[0095] Aspect 25: According to the junction field-effect transistor (JFET) common-source cascode control circuit of aspect 23, wherein a voltage limiting element is configured to receive a gate drive signal as a power supply input, and the gate drive signal is limited at the output of the voltage limiting element such that the adjusted signal at the overdrive terminal is limited to a controlled overdrive value.

[0096] Aspect 26: The JFET cascode control circuit according to aspect 25, wherein the voltage limiting element is a transistor, and wherein the voltage limiting circuit further includes: A voltage reference element is coupled between the control terminal of the voltage limiting element and a reference node, wherein the voltage reference element is configured to be biased by a gate drive signal such that the signal provided by the voltage reference element depends on the state of the gate drive signal. The gate driver is configured to drive the gate drive signal between high and low levels, and The voltage reference element is configured to conduct current in reverse conduction mode based on the gate drive signal being at a high level, and the voltage at the control terminal of the voltage limiting element is set as a reverse bias reference voltage.

[0097] Aspect 27: The JFET cascode control circuit according to aspect 26, wherein the voltage limiting circuit further includes: A diode having a second cathode coupled to a gate drive terminal and a second anode coupled to the output of a voltage limiting element and to an overdrive terminal. The diode is configured to draw current from the overdrive terminal to discharge the JFET gate terminal to a low level based on the gate drive signal being at a low level.

[0098] Aspect 28: According to the JFET cascode control circuit of aspect 23, wherein the unipolar power supply scheme includes a supply potential and a reference potential sufficient to satisfy the controlled overdrive value, and The voltage limiting element is configured to receive the power supply potential as the power supply input, and to limit the power supply potential at the output of the voltage limiting element, so that the adjusted signal at the overdrive terminal is limited to a controlled overdrive value.

[0099] Aspect 29: The JFET cascode control circuit according to aspect 28, wherein the voltage limiting element is a transistor, and wherein the voltage limiting circuit further includes: A voltage reference element is coupled between the control terminal of the voltage limiting element and a reference node, wherein the voltage reference element is configured to be biased by a gate drive signal such that the signal provided by the voltage reference element depends on the state of the gate drive signal. The gate driver is configured to drive the gate drive signal between high and low levels, and The voltage reference element is configured to conduct current in reverse conduction mode based on the gate drive signal being at a high level, and the voltage at the control terminal of the voltage limiting element is set as a reverse bias reference voltage.

[0100] Aspect 30: A system configured to perform one or more of the operations described in one or more of aspects 1 to 29.

[0101] Aspect 31: An apparatus comprising means for performing one or more of the operations described in one or more of aspects 1 to 30.

[0102] Aspect 32: A non-transitory computer-readable medium storing an instruction set comprising one or more instructions that, when executed by a device, cause the device to perform one or more operations described in one or more of aspects 1 to 29.

[0103] Aspect 33: A computer program product comprising instructions or code for performing one or more of the operations described in one or more of aspects 1 to 29.

[0104] The foregoing disclosure provides explanations and descriptions, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations can be made based on the foregoing disclosure, or modifications and variations can be derived from the practice of implementation.

[0105] This article can use thresholds to describe some implementation methods. As used in this article, the "satisfying" threshold can refer to values ​​such as greater than the threshold, more than the threshold, higher than the threshold, greater than or equal to the threshold, less than the threshold, less than the threshold, lower than the threshold, less than or equal to the threshold, and equal to the threshold.

[0106] As used herein, the term "component" is intended to be interpreted broadly as hardware, firmware, or a combination of hardware and software. The systems and / or methods described herein can be implemented in various forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods is not a limitation on the implementation method. Therefore, while this document describes the operation and behavior of the systems and / or methods without reference to specific software code, it should be understood that software and hardware can be designed to implement the systems and / or methods based on the descriptions herein.

[0107] Any processing unit can be implemented as a central processing unit (CPU) or other processor that reads and executes software programs from a non-transitory computer-readable recording medium such as a hard disk or semiconductor memory device. For example, instructions can be executed by one or more processors, such as one or more CPUs, digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPLAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuits. Therefore, as used herein, the term "processor" refers to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. Software can be stored on a non-transitory computer-readable medium such that the non-transitory computer-readable medium includes program code or program algorithms stored thereon, which, when executed, cause the processor to perform the steps of a method via a computer program.

[0108] The controller, including hardware, may also perform one or more of the techniques described in this disclosure. A controller including one or more processors may use electrical signals and digital algorithms to perform its receiving, analysis, and control functions, and may also include correction functions. Such hardware, software, and firmware may be implemented within the same device or in separate devices to support the various techniques described in this disclosure.

[0109] Signal processing circuitry and / or signal conditioning circuitry can receive one or more signals (e.g., measurement signals) from one or more components in the form of raw measurement data, and can derive additional information from the measurement signals. As used herein, “signal conditioning” refers to manipulating an analog signal in such a way that the signal meets the requirements of the next stage for further processing. Signal conditioning may include analog-to-digital conversion (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other processing required to make the signal suitable for processing after conditioning.

[0110] Even though specific combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the implementations described herein. Many of these features can be combined in ways not specifically recited in the claims and / or not disclosed in the specification. For example, this disclosure includes combinations of each dependent claim in the claim set with each other individual claim in the claim set and each combination of multiple claims in the claim set. As used herein, the phrase “at least one” in a list of items refers to any combination of these items, including individual components. As an example, “at least one of a, b, or c” is intended to cover a, b, c, a and b, a and c, b and c, and a, b, and c, as well as any combination with multiple identical elements (e.g., a + a, a + a + a, a + a + b, a + a + c, a + b + b, a + c + c, b + b, b + b + b, b + b + c, c + c, and c + c + c, or any other ordering of a, b, and c).

[0111] Furthermore, it should be understood that the disclosure of multiple actions or functions in the specification or claims is not to be construed as being in a particular order. Therefore, the disclosure of multiple actions or functions will not be limited to a specific order unless such actions or functions are technically non-interchangeable. Additionally, in some implementations, a single action may include or be divided into multiple sub-actions. Unless expressly excluded, such sub-actions may be included as part of the disclosure of that single action.

[0112] Unless explicitly stated otherwise, no element, action, or instruction used herein should be construed as critical or necessary. Furthermore, as used herein, the articles “a” and “one” are intended to include one or more items and may be used interchangeably with “one or more.” Additionally, as used herein, the article “the” is intended to include one or more items referenced by the article “the” and may be used interchangeably with “one or more.” Where only one item is intended, the phrases “only one,” “single,” or similar language are used. Furthermore, as used herein, the terms “has,” “have,” “having,” etc., are intended to be open-ended terms that do not limit the element they modify (e.g., element “having” A may also have B). Furthermore, unless explicitly stated otherwise, the phrase “based on” is intended to mean “at least partially based on.” As used herein, the term “multiple” may be replaced with “a plurality of” and vice versa. Furthermore, as used herein, the term “or” is intended to be inclusive when used in series and may be used interchangeably with “and / or” unless otherwise expressly stated (e.g., if used in combination with “any one” or “only one”).

Claims

1. A junction field-effect transistor (JFET) cascode circuit, comprising: A gate driver configured to be powered according to a unipolar power supply scheme, the gate driver being configured to output a gate drive signal from the gate drive terminal of the gate driver; A JFET having a JFET gate terminal, the JFET gate terminal being configured to control the conduction of current through the JFET according to the JFET gate potential based on the gate drive signal; A voltage-controlled transistor coupled to the JFET in a common-source, common-gate configuration, the voltage-controlled transistor including a transistor gate terminal coupled to the gate drive terminal and configured to control the conduction of current through the voltage-controlled transistor based on the gate drive signal; as well as A voltage limiting circuit, coupled to the gate drive terminal and the JFET gate terminal, includes a voltage limiting element configured to adjust the JFET gate potential based on the gate drive signal, such that during the steady-state conduction of the JFET, the maximum value of the JFET gate potential is limited to a controlled overdrive value. The voltage limiting element is an active device.

2. The JFET cascode circuit according to claim 1, wherein, The JFET includes a gate-to-source pn junction, and The controlled overdrive value is a positive value that is less than the inflection point voltage of the gate-to-source pn junction.

3. The JFET cascode circuit according to claim 2, wherein, The controlled overdrive value is the voltage level at which the drain-to-source on-resistance of the JFET is minimized, and the voltage level does not exceed the inflection point voltage of the gate-to-source pn junction.

4. The JFET cascode circuit according to claim 1, wherein, The voltage limiting element is configured to bias the JFET gate terminal according to the controlled overdrive value during the steady-state conduction of the JFET, and The controlled overdrive value is the voltage level at which the drain-to-source on-resistance of the JFET is minimized.

5. The JFET cascode circuit according to claim 1, wherein, The JFET includes a gate-to-source pn junction formed by the gate and source of the JFET, and The voltage limiting element is configured to limit the forward current flowing into the gate-to-source pn junction to a predefined value during the steady-state conduction of the JFET.

6. The JFET cascode circuit according to claim 1, wherein, The unipolar power supply scheme includes a power supply potential and a reference potential sufficient to satisfy the controlled overdrive value. The gate driver is configured to set the gate drive signal to the supply potential to turn on the voltage-controlled transistor, thereby setting the JFET to a current-conducting state. The gate driver is configured to set the gate drive signal to the reference potential to turn off the voltage-controlled transistor, thereby setting the JFET to a blocking state. The voltage limiting element is configured to set the JFET gate potential to the reference potential during the JFET's off state.

7. The JFET cascode circuit according to claim 1, wherein, The voltage limiting element is configured to receive the gate drive signal as a power supply input and to limit the gate drive signal at the output of the voltage limiting element, such that the JFET gate potential is limited to the controlled overdrive value.

8. The JFET cascode circuit according to claim 7, wherein, The voltage limiting element is a transistor, and The voltage limiting circuit further includes: A voltage reference element is coupled between the control terminal of the voltage limiting element and the reference node of the JFET cascode circuit, wherein the voltage reference element is configured to be biased by the gate drive signal such that the signal provided by the voltage reference element depends on the state of the gate drive signal. The gate driver is configured to drive the gate drive signal between a high level and a low level, and The voltage reference element is configured to conduct current in reverse conduction mode based on the gate drive signal being at the high level, and to set the voltage at the control terminal of the voltage limiting element as a reverse bias reference voltage.

9. The JFET cascode circuit according to claim 8, wherein, The voltage reference element is a Zener diode having a first cathode coupled to the reference node of the JFET cascode circuit and a first anode coupled to the control terminal of the voltage limiting element, wherein a bias resistor is coupled to the gate drive terminal and the first anode of the Zener diode.

10. The JFET cascode circuit according to claim 8, wherein, The voltage limiting circuit also includes: A diode having a second cathode coupled to the gate drive terminal and a second anode coupled to the output terminal of the voltage limiting element and to the gate terminal of the JFET. The diode is configured to discharge the JFET gate terminal to the low level based on the gate drive signal being at the low level.

11. The JFET cascode circuit according to claim 1, wherein, The unipolar power supply scheme includes a power supply potential and a reference potential sufficient to satisfy the controlled overdrive value, and The voltage limiting element is configured to receive the power supply potential as a power supply input and to limit the power supply potential at the output of the voltage limiting element, such that the JFET gate potential is limited to the controlled overdrive value.

12. The JFET cascode circuit according to claim 11, wherein, The voltage limiting element is a transistor, and The voltage limiting circuit further includes: A voltage reference element is coupled between the control terminal of the voltage limiting element and the reference node of the JFET cascode circuit, wherein the voltage reference element is configured to be biased by the gate drive signal such that the signal provided by the voltage reference element depends on the state of the gate drive signal. The gate driver is configured to drive the gate drive signal between a high level and a low level, and The voltage reference element is configured to conduct current in reverse conduction mode based on the gate drive signal being at the high level, and to set the voltage at the control terminal of the voltage limiting element as a reverse bias reference voltage.

13. The JFET cascode circuit according to claim 1, wherein, The voltage limiting element is configured to set the JFET gate potential to a low voltage level of the unipolar power supply scheme during the JFET's off state.

14. A junction field-effect transistor (JFET) cascode control circuit configured to control a JFET cascode circuit, the JFET cascode circuit including a voltage-controlled transistor coupled to the JFET in a cascode configuration, the JFET cascode control circuit comprising: A gate driver, configured to be powered according to a unipolar power supply scheme, is configured to receive a control signal and, based on the control signal, output a gate drive signal from a gate drive terminal configured to be coupled to the gate terminal of the voltage-controlled transistor. A voltage limiting circuit, coupled to the gate drive terminal and including an overdrive terminal configured to be coupled to the JFET gate terminal, the voltage limiting circuit including a voltage limiting element configured to output an adjusted signal at the overdrive terminal based on the gate drive signal, such that during the steady-state conduction of the JFET, the maximum value of the JFET gate potential is limited to a controlled overdrive value. The voltage limiting element is an active device.

15. The JFET cascode control circuit according to claim 14, wherein, The unipolar power supply scheme includes a power supply potential and a reference potential sufficient to satisfy the controlled overdrive value. Specifically, when the control signal indicates that the JFET cascode circuit is turned on: The gate driver is configured to set the gate drive signal to the supply potential to turn on the voltage-controlled transistor, and the voltage limiting element is configured to output the adjusted signal according to the controlled overdrive value. Specifically, when the control signal instructs the JFET cascode circuit to be turned off: The gate driver is configured to set the gate drive signal to the reference potential to turn off the voltage-controlled transistor, and the voltage limiting element is configured to set the overdrive terminal to the reference potential.

16. The JFET cascode control circuit according to claim 14, wherein, The voltage limiting element is configured to receive the gate drive signal as a power supply input and to limit the gate drive signal at the output of the voltage limiting element such that the adjusted signal at the overdrive terminal is limited to the controlled overdrive value.

17. The JFET cascode control circuit according to claim 16, wherein, The voltage limiting element is a transistor, and The voltage limiting circuit further includes: A voltage reference element is coupled between the control terminal of the voltage limiting element and the reference node of the JFET cascode circuit, wherein the voltage reference element is configured to be biased by the gate drive signal such that the signal provided by the voltage reference element depends on the state of the gate drive signal. The gate driver is configured to drive the gate drive signal between a high level and a low level, and The voltage reference element is configured to conduct current in reverse conduction mode based on the gate drive signal being at the high level, and to set the voltage at the control terminal of the voltage limiting element as a reverse bias reference voltage.

18. The JFET cascode control circuit according to claim 17, wherein, The voltage limiting circuit also includes: A diode having a cathode coupled to the gate drive terminal and an anode coupled to the output terminal of the voltage limiting element and to the overdrive terminal. The diode is configured to draw current from the overdrive terminal to discharge the JFET gate terminal to the low level based on the gate drive signal being at the low level.

19. The JFET cascode control circuit according to claim 14, wherein, The unipolar power supply scheme includes a power supply potential and a reference potential sufficient to satisfy the controlled overdrive value, and The voltage limiting element is configured to receive the power supply potential as a power supply input and to limit the power supply potential at the output of the voltage limiting element, such that the adjusted signal at the overdrive terminal is limited to the controlled overdrive value.

20. The JFET cascode control circuit according to claim 19, wherein, The voltage limiting element is a transistor, and The voltage limiting circuit further includes: A voltage reference element is coupled between the control terminal of the voltage limiting element and the reference node of the JFET cascode circuit, wherein the voltage reference element is configured to be biased by the gate drive signal such that the signal provided by the voltage reference element depends on the state of the gate drive signal. The gate driver is configured to drive the gate drive signal between a high level and a low level, and The voltage reference element is configured to conduct current in reverse conduction mode based on the gate drive signal being at the high level, and to set the voltage at the control terminal of the voltage limiting element as a reverse bias reference voltage.

Images