A high-speed viterbi decoding method, device and equipment based on multi-frame interleaving pipeline and a medium

Abstract

A high-speed Viterbi decoding method, device and equipment based on multi-frame interleaving flow, and a medium, relating to the technical field of digital communication channel decoding, comprising: obtaining F frames to be decoded, each frame being divided into multiple input groups containing M soft decision quantities; constructing a frame context containing path metric, surviving path and frame control for each frame, F >= L, L being path metric feedback delay; rotating frame selection in a continuous clock cycle, the interval between adjacent selections of the same frame being >= L; reading state path metric, performing Radix-M grouped grid processing per beat, starting a group per cycle, and synchronously outputting updated path metric, surviving path decision and delay tag; writing path metric and surviving path back according to delay tag; when the delay frame identifier is the same as the current frame to be decoded, using updated path metric as the starting point of recursion; if the backtracking condition is met, outputting backtracking, otherwise continuing. The method solves the problems of ACS feedback delay limiting start interval, deep flow being unable to fill, and throughput being limited.

Description

Technical Field

[0001] This invention relates to the field of digital communication channel decoding technology, specifically to a high-speed Viterbi decoding method, apparatus, device, and medium based on multi-frame interleaving pipeline. Background Technology

[0002] Viterbi decoding achieves maximum likelihood estimation of the transmitted information sequence by recursively calculating path metrics on a convolutional code grid and preserving surviving paths. A typical hardware decoder includes a branch metric calculation unit, an adder-comparator-selector unit, a path metric storage unit, a surviving path storage unit, and a backtracking unit. The adder-comparator-selector unit generates the path metric for the next grid time based on the path metric from the previous grid time, thus forming a data-dependent feedback loop.

[0003] Currently, related technologies typically employ hardware Viterbi decoders with branch metric computation, additive selection (ACS), path metric storage, surviving path storage, and backtracking units. They also improve the operating frequency and the number of decoded information bits per pass by inserting multi-stage pipeline registers into the ACS recursive loop and using Radix-M grouped grid processing.

[0004] However, this related technology has the following problems: When processing a single frame continuously, the next input group must wait for the updated path metric of the previous input group to return. The ACS feedback loop delay L makes the pipeline startup interval usually no less than L system clock cycles, and the deep pipeline Radix-M processing unit cannot be continuously filled by a single frame. Existing multi-channel shared or multi-data input structures also cannot solve problems such as configuring independent frame contexts according to feedback delay, accurately aligning frame identifiers with deep pipeline results, handling the related hazards of writing back to the same frame and reading the same frame again, and ensuring that surviving path writing and backtracking do not block the front end startup step by step, thus limiting the improvement of the steady-state throughput of decoded information after decoding.

[0005] Therefore, we propose a Viterbi decoding method that can hide ACS feedback delay and achieve high-throughput decoding through multi-frame interleaving and Radix-M grouped pipeline collaboration. Summary of the Invention

[0006] The purpose of this invention is to provide a high-speed Viterbi decoding method, apparatus, device, and medium based on multi-frame interleaved pipeline, which solves the problem that in traditional Viterbi decoding, the delay of the ACS feedback loop limits the pipeline start interval and the deep pipeline Radix-M processing unit cannot be continuously filled by a single frame, resulting in limited steady-state throughput of decoded information bits.

[0007] This invention is achieved through the following technical solution: A high-speed Viterbi decoding method based on multi-frame interleaved pipeline includes: Obtain F frames to be decoded, divide each frame's soft decision quantity into multiple input groups containing M soft decision quantities, and configure each group with a frame identifier, intra-frame group number, and frame end identifier; A frame context is constructed for each frame to be decoded. The frame context includes a path metric context for storing state path metrics, a surviving path context for storing surviving path decision vectors, and a frame control context for storing intra-frame group numbers and frame state information; and F≥L, where L is the path metric feedback delay. The frame to be decoded is selected in a cyclic rotation within a continuous system clock cycle, and the interval between two adjacent selections of the same frame is not less than L. Read the state path metric of the current frame to be decoded, perform Radix-M grouped grid processing on its input group step by step, start one input group every cycle, and synchronously output the updated state path metric vector, surviving path decision vector, delayed frame identifier, intra-frame group number and frame end identifier. Write the updated state path metric vector back to the corresponding path metric context according to the delayed frame identifier, and write the surviving path decision vector into the surviving path context according to the delayed frame identifier and intra-frame group number. When the delayed frame identifier is the same as the current frame to be decoded, the updated state path metric vector is used as the recursive starting point of the current input group. Determine whether the current frame to be decoded meets the backtracking condition. If it does, read the surviving path decision vector backtracking and output the decoding information bits according to the frame identifier and intra-frame group number; otherwise, continue to perform Radix-M grouped grid processing on subsequent input groups.

[0008] Furthermore, the path metric feedback latency is the number of system clock cycles from the start of reading the path metric to the point where the updated path metric can be reused.

[0009] Furthermore, the cyclic selection of frames to be decoded adopts a frame pool cyclic scheduling mechanism; When the number of valid frames to be decoded in the frame pool is insufficient, an invalid time slot is inserted to wait for new frames to be decoded to enter the frame pool, ensuring that the same frame to be decoded will not be repeatedly scheduled when the path metric is not ready to be updated.

[0010] Furthermore, the Radix-M grouped mesh processing is completed by a Radix-M grouped mesh processing pipeline; The Radix-M grouped mesh processing includes grouped branch metric calculation and multi-level ACS processing; The pipeline is configured with a tag pipeline level that corresponds one-to-one with each internal data pipeline level. The frame identifier, intra-frame group number, and frame end identifier are output synchronously with the data path via the tag pipeline level with a delay.

[0011] Furthermore, when writing the updated state path metric vector back to the corresponding path metric context, the frame context performs intra-frame path metric normalization. The normalization reference metric is taken from the updated path metric of this frame and does not reference the path metric data of other frames to be decoded.

[0012] Furthermore, when the delayed frame identifier is the same as the current frame to be decoded, the updated state path metric vector is used as the recursive starting point of the current input group, and the process is implemented through a bypass path composed of a frame identifier comparator and a path metric selector, specifically as follows: When the frame identifier written back matches the current scheduling frame identifier, the path metric selector selects the updated state path metric vector directly output by the pipeline to replace the state path metric that has not yet been updated in the path metric context storage.

[0013] Furthermore, the backtracking condition is: The surviving path decision vector stored in the surviving path context of the frame to be decoded reaches the preset backtracking depth, or all input groups of the frame to be decoded have completed Radix-M grouped mesh processing; The survival path context is implemented by a dual-port memory, a multi-database memory, or a ping-pong memory, and is used to enable the parallel execution of the survival path decision vector write operation and the backtracking read operation.

[0014] A high-speed Viterbi decoding device based on multi-frame interleaving pipeline, comprising: The data acquisition module is used to acquire F frames to be decoded, divide each frame's soft decision quantity into multiple input groups containing M soft decision quantities, and configure each group with a frame identifier, intra-frame group number, and frame end identifier. The frame context construction module is used to construct a frame context for each frame to be decoded. The frame context includes a path metric context for storing state path metrics, a surviving path context for storing surviving path decision vectors, and a frame control context for storing intra-frame group numbers and frame state information; and F≥L, where L is the path metric feedback delay. The frame selection module is used to select frames to be decoded in a cyclic rotation within a continuous system clock cycle, with the interval between two adjacent selections of the same frame not less than L. The grouped grid processing module is used to read the state path metric of the current frame to be decoded, perform Radix-M grouped grid processing on its input group frame by frame, start one input group per cycle, and synchronously output the updated state path metric vector, surviving path decision vector, delayed frame identifier, intra-frame group number and frame end identifier. The update vector write-back module is used to write back the updated state path metric vector to the corresponding path metric context according to the delayed frame identifier, and to write the surviving path decision vector to the surviving path context according to the delayed frame identifier and intra-frame group number. The recursive update module is used to take the updated state path metric vector as the recursive starting point of the current input group when the delayed frame identifier is the same as the current frame to be decoded. The backtracking judgment module is used to determine whether the current frame to be decoded meets the backtracking conditions. If it does, the surviving path decision vector is read backtracked and the decoding information bits are output according to the frame identifier and the intra-frame group number; otherwise, Radix-M grouped grid processing is continued for subsequent input groups.

[0015] An electronic device, comprising: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which enables the at least one processor to perform the high-speed Viterbi decoding method based on multi-frame interleaving pipeline described above.

[0016] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described high-speed Viterbi decoding method based on multi-frame interleaving pipeline.

[0017] The technical solution of the present invention has at least the following advantages and beneficial effects: This invention discloses a high-speed Viterbi decoding method, apparatus, device, and medium based on multi-frame interleaving pipeline. By establishing independent path metric contexts, surviving path contexts, and frame control contexts for multiple frames to be decoded, and ensuring that the number of frames participating in interleaving is no less than the number of feedback delay cycles, the recursive operations of different frames are interleaved step-by-step in a deep pipeline while the recursive order of the same frame remains unchanged. By scheduling by frame round-robin and ensuring that the previous update results are available when the same frame is restarted, the high cardinality grouped grid processing unit can receive new input groups and continuously output decoding results in each system clock cycle. In addition, by synchronously transmitting frame identifiers, group numbers, and frame end information with the data path, and repositioning the results based on the delayed frame identifiers, the accurate correspondence and non-confusion of multi-frame calculation results are achieved; by directly using the latest updated result when the same frame is written back and read again, the correct continuation of the recursive chain is achieved; by independently reading the surviving path of frames that meet the backtracking conditions and outputting the decoding information, the parallel connection between front-end continuous decoding and back-end backtracking output is achieved.

[0018] Furthermore, by defining the feedback latency as the number of clock cycles required from reading the state metric to its updated value being usable again, accurate matching between the number of interleaved frames and the feedback timing is achieved. By employing frame pool cyclic scheduling and inserting invalid time slots when there are insufficient valid frames, the start interval constraint of the same frame is not violated even when frames arrive unevenly. By normalizing path metrics for each frame, independent maintenance of state metrics for different frames and avoidance of cross-frame interference are achieved. By using a bypass path composed of frame identifier comparison and result selection, priority is given to the latest state metric in the same-shot write-back read scenario. By employing dual-port, sharded, or ping-pong surviving path storage, parallel execution of surviving path writing and backtracking reading is achieved. By using backtracking depth or frame processing completion as backtracking trigger conditions, timely output of decoding results and recycling of storage resources are achieved. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a high-speed Viterbi decoding method based on multi-frame interleaving pipeline according to the present invention; Figure 2 This is a schematic diagram of a high-speed Viterbi decoding device based on multi-frame interleaving pipeline according to the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Example 1 like Figure 1 As shown, a high-speed Viterbi decoding method based on multi-frame interleaving pipeline includes: S1. Obtain F frames to be decoded, divide each frame's soft decision quantity into multiple input groups containing M soft decision quantities, and configure each group with a frame identifier, intra-frame group number, and frame end identifier; First, the input to Viterbi decoding is typically the soft decision variables output by the demodulator. The number of soft decision variables in each frame to be decoded is generally much larger than the width that a processing unit can handle at one time. Therefore, the soft decision variables within a frame need to be divided into multiple input groups in chronological order, with each input group containing M soft decision variables. In the preferred 1 / 2 code rate binary convolutional code mode, M is 16. In this case, one input group corresponds to 8 consecutive decoding information bits, meaning that one processing operation advances M·r decoding information bits, where r is the coding rate. Frame identifiers are used to distinguish different frames to be decoded throughout the pipeline. Intra-frame group numbers are configured to identify the order of the input group within its frame, and frame end identifiers are configured to indicate whether the input group is the last input group of the frame. By pre-grouping and attaching labels, it can adapt to the vectorized input interface of Radix-M grouped grids, laying the data foundation for interleaved execution of multi-frame operations within the same pipeline.

[0022] S2. Construct a frame context for each frame to be decoded. The frame context includes a path metric context for storing state path metrics, a surviving path context for storing surviving path decision vectors, and a frame control context for storing intra-frame group numbers and frame state information; and F≥L, where L is the path metric feedback delay. Specifically, the path metric feedback latency is the number of system clock cycles from the start of reading the path metric to the point where the updated path metric can be reused.

[0023] Each frame to be decoded has a logically independent frame context. The path metrics, surviving path decision vectors, and frame states between different frames are completely isolated. The The state path metric update corresponding to the input group satisfies:

[0024] In the formula, Representing the Frame number State path metric before input group operations. The function represents the merged branch metric corresponding to this input group. This represents the ACS addition-comparison-selection operation under Radix-M grouped grids. This operation depends only on the previous set of path metrics and the current set of branch metrics, and is independent of the data in the context of other frames. The number of frames participating in the interleaving is set to meet the following requirements. This is to provide enough frames to fill the pipeline gaps introduced by the ACS feedback loop, preventing pipeline bubbles caused by waiting for single-frame feedback and ensuring continuous utilization of hardware resources. The frame control context synchronously maintains frame state information such as group number, start state, and end state of each frame, enabling parallel processing of multiple frames in transit without interference.

[0025] S3. Select frames to be decoded in a round-robin manner within consecutive system clock cycles, and the interval between two adjacent selections of the same frame is no less than L; In addition, the round-robin selection of frames to be decoded adopts a frame pool cyclic scheduling mechanism; when the number of valid frames to be decoded in the frame pool is insufficient, invalid time slots are inserted to wait for new frames to be decoded to enter the frame pool, so as to ensure that the same frame to be decoded will not be rescheduled when the updated path metric is not ready.

[0026] The scheduler cyclically selects frames to be decoded from the frame pool at the beat of the system clock, and marks the th group of the frame sent into the pipeline as the moment when it is sent into the pipeline as , the scheduling constraint satisfies:

[0027] This timing constraint ensures that when the next input group of the same frame is scheduled again, the updated path metric obtained by the previous group through pipeline operation has been completely calculated and output, eliminating operation errors caused by unready feedback data. When the number of valid frames to be decoded in the frame pool is less than the feedback delay , there are not enough new frames available for round-robin scheduling, so invalid time slots are inserted without starting the operation of valid input groups, so as to maintain the timing constraint from being broken and be compatible with service scenarios with uneven frame arrival rates. This scheduling method does not need to modify the internal logic of the ACS pipeline, and relies on inter-frame time interleaving to hide the waiting overhead brought by the feedback loop.

[0028] S4. Read the state path metric of the current frame to be decoded, perform Radix-M grouped trellis processing on its input groups beat by beat, start one input group per cycle, and synchronously output the updated state path metric vector, the survivor path decision vector, as well as the delayed frame identifier, intra-frame group number and frame end identifier; Specifically, the Radix-M grouped trellis processing is completed by a Radix-M grouped trellis processing pipeline; the Radix-M grouped trellis processing includes grouped branch metric calculation and multi-stage ACS processing; the pipeline is configured with label pipeline stages corresponding one-to-one to each internal data pipeline stage, and the frame identifier, intra-frame group number and frame end identifier are output through the label pipeline stages with synchronous pipeline delay following the data path.

[0029] Radix-M grouped grid processing merges M soft decision quantities into grid operations, advancing multiple grid times in one go, thereby increasing the number of bits output per operation. The branch metric unit calculates the branch metric based on the received soft decision quantity and the grid transition relationship of the convolutional code. For branches with symbol complementarity, it reduces the overhead of repeated addition operations by reusing parts. Subsequent multi-stage ACS pipeline stages sequentially complete path expansion, addition, and comparison selection, outputting the updated state path metric and the surviving path decision vector for backtracking and recovering bits. The pipeline is set up with a tag pipeline stage that is completely equivalent to the number of data path stages. The frame identifier, intra-frame group number, and frame end identifier attached to the input follow the tag pipeline stage to be synchronously delayed. The operation results of the tag and the corresponding group are strictly synchronized and output, so there will be no data and tag misalignment. This ensures that the operation results can be correctly assigned to the corresponding frame to be decoded in multi-frame interleaving scenarios, avoiding data confusion between different frames. The pipeline can receive a new set of inputs every clock cycle, giving full play to the highest operating frequency supported by the deep pipeline hardware.

[0030] S5. Write the updated state path metric vector back to the corresponding path metric context according to the delayed frame identifier, and write the surviving path decision vector into the surviving path context according to the delayed frame identifier and intra-frame group number. In addition, when the updated state path metric vector is written back to the corresponding path metric context, the intra-frame path metric normalization is completed within the frame context. The normalization reference metric is taken from the updated path metric of this frame and does not reference the path metric data of other frames to be decoded.

[0031] The results of the computation are not written back based on the currently scheduled frame. Instead, the labels output by the pipeline delay are used as the addressing basis to adapt to the data-scheduling time misalignment problem caused by multi-stage pipeline delays. Path metrics tend to accumulate and increase over long iterations; therefore, intra-frame normalization is required after each computation. The total state path metric of the frame minus the reference metric obtained within this frame. :

[0032] After normalization, the first The path metric for each state is taken only from the current frame. Reading path metrics from other frames across frames is prohibited to participate in the calculation. This protects the independence of the context values ​​of each frame and avoids cross-frame metric contamination that could lead to decoding performance degradation. For the first Frame number The state path metric is updated after the input group operation. The surviving path decision vector is written into the surviving path context using a joint addressing of "frame identifier + intra-frame group number" to save all decision information for subsequent backtracking operations.

[0033] S6. When the delayed frame identifier is the same as the current frame to be decoded, the updated state path metric vector is used as the recursive starting point of the current input group. This is achieved through a bypass path composed of the frame identifier comparator and the path metric selector, specifically: When the frame identifier being written back matches the current scheduling frame identifier, the path metric selector selects the updated state path metric vector directly output by the pipeline to replace the state path metric that has not yet been updated in the path metric context storage.

[0034] exist In this configuration, if the updated path metric for the same frame completes pipelined output within the same clock cycle, and the scheduler happens to schedule the next input group for that frame, the memory may not have completed its write operation. Directly reading from the memory unit would result in reading an old path metric value, creating a read-after-write data hazard. The frame identifier comparator compares the pipeline output tag with the currently scheduled frame identifier in real time. When they match, the path metric selector directly selects the latest updated path metric from the pipeline output as the recursive input for this group's ACS operation, bypassing the memory read path that hasn't been updated. This ensures that the recursive operation uses the latest calculation result without increasing the number of interleaved frames, saving storage resources and guaranteeing the integrity and correctness of the recursive chain of path metrics within the frame.

[0035] As shown in Table 1, when L=8 and F=8, the g0 group of F0 is started in the 0th frame, the g0 group of F1 is started in the 1st frame, and so on, the g0 group of F7 is started in the 7th frame; in the 8th frame, the path metric updated by the g0 group of F0 reaches the feedback end, and at the same time the scheduler starts the g1 group of F0. Other frames are processed in the same way. It should be noted that in the 8th frame, the updated path metric of the input group 0 of the write-back frame 0 is completed, and at the same time the input group 1 of the frame is started; the latest path metric is obtained by write-first storage or bypass.

[0036] Table 1. Timing of Multi-Frame Interleaving, Frame-by-Frame Rotation, and ACS Write-back when L=8 and F=8

[0037] S7. Determine whether the current frame to be decoded meets the backtracking condition. If it does, read the surviving path decision vector backtracking output decoding information bits according to the frame identifier and intra-frame group number; otherwise, continue to perform Radix-M grouped grid processing on subsequent input groups.

[0038] Specifically, the backtracking conditions are: the number of survivor path decision vectors stored in the survivor path context of the frame to be decoded reaches a preset backtracking depth, or all input groups of the frame to be decoded complete Radix-M grouped grid processing; the survivor path context is implemented by a dual-port memory, a library-based memory, or a ping-pong memory, and is used to enable the parallel execution of survivor path decision vector writing operations and backtracking reading operations.

[0039] When a frame has accumulated enough surviving path decision vectors, or when all input groups for that frame have completed grouped mesh operations, the backtracking process for that frame is triggered. The surviving path context adopts a storage architecture that supports parallel read and write operations. While the ACS pipeline continuously writes surviving path decision vectors to memory, the backtracking unit can independently read the decision vectors under the corresponding frame and group number, and reverse the mesh backtracking to recover the decoded information bits. The back-end backtracking read operation will not block the front-end pipeline from receiving new input groups. This achieves complete decoupling between the front-end grouped mesh processing and the back-end bit recovery, avoiding backtracking tasks from occupying pipeline processing slots and ensuring that the overall steady-state throughput is not affected by the backtracking operation.

[0040] Example 2 like Figure 2 As shown, a high-speed Viterbi decoding device based on multi-frame interleaving pipeline includes: The data acquisition module is used to acquire F frames to be decoded, divide each frame's soft decision quantity into multiple input groups containing M soft decision quantities, and configure each group with a frame identifier, intra-frame group number, and frame end identifier. This module consists of a multi-frame input buffer and an input grouping unit. The multi-frame input buffer simultaneously maintains soft decision values ​​for F valid frames, and sets independent write pointers, read pointers, group sequence number counters, validity flags, start state configurations, and end state configurations for each frame. The input grouping unit retrieves M soft decision values ​​from the buffer area of ​​the same frame to form an input group, and ensures that data from different frames are not mixed within the same input group through intra-group selection logic. The frame identifier is given by the frame number register or the frame pool allocator, the intra-frame group sequence number is generated by incrementing the group sequence number counter, and the frame end flag is set by the frame length comparator in the last group. This module outputs labeled vectorized soft decision input groups, providing data to the grouped mesh processing module, and simultaneously providing the frame identifier and intra-frame group sequence number to the frame context construction module to establish or update the context of the corresponding frame.

[0041] The frame context construction module is used to construct a frame context for each frame to be decoded. The frame context includes a path metric context for storing state path metrics, a surviving path context for storing surviving path decision vectors, and a frame control context for storing intra-frame group numbers and frame state information; and F≥L, where L is the path metric feedback delay. This module is implemented using a register group partitioned by frame identifier, a random access memory partitioned by frame identifier, or a multi-bank structure addressed by both frame identifier and status number. The path metric context is divided into F independent storage areas, each corresponding to a frame identifier and storing the path metrics for all states of that frame. When the number of states is large, the path metrics for each frame can be further divided into multiple storage banks according to the status number to support parallel reading of multiple state path metrics within a single clock cycle. The surviving path context is also partitioned by frame identifier, with storage addresses organized by intra-frame group number and status number within each partition. The frame control context consists of a frame control register group, storing the intra-frame group number, frame validity identifier, frame end identifier, start status, end status, code rate mode, and backtracking depth count. The address decoder generates read / write addresses using the frame identifier as the high-order bit and the status number as the low-order bit, ensuring physical isolation of data from different frames. As frames to be decoded arrive successively, the frame pool allocator allocates idle frame contexts to new frames; when a frame completes its backtracking output, its frame context is released and made available for reuse by new frames.

[0042] The frame selection module is used to select frames to be decoded in a cyclic rotation within a continuous system clock cycle, with the interval between two adjacent selections of the same frame not less than L. This module consists of a frame pool, a loop counter, and readiness judgment logic. The loop counter increments under the system clock, and its count value is modulo F of the number of frame contexts to generate the identifier of the current frame to be decoded. The frame pool maintains valid and ready identifiers for each frame context. The readiness judgment logic checks whether the frame corresponding to the current frame to be decoded is valid and whether its preceding update path metric is ready. If valid and ready, the frame identifier is output as the current scheduled frame; if invalid or not ready, an invalid time slot is inserted, and the loop counter continues to increment without initiating valid computation. The frame pool can also be configured with a ready queue or a priority selector to select frames to be decoded according to arrival order or service priority when the number of valid frames is greater than F. This module outputs the current scheduled frame identifier, the current input group and its tag, and generates a read enable signal to the frame context construction module to read the status path metric of the current frame to be decoded.

[0043] The grouped grid processing module is used to read the state path metric of the current frame to be decoded, perform Radix-M grouped grid processing on its input group frame by frame, start one input group per cycle, and synchronously output the updated state path metric vector, surviving path decision vector, delayed frame identifier, intra-frame group number and frame end identifier. This module is implemented using a Radix-M grouped grid processing pipeline. Internally, it sequentially includes a branch metric sharing unit, a merged grid candidate path expansion unit, a hierarchical comparison and selection tree, and a path metric normalization unit, arranged according to the data pipeline stages. The branch metric sharing unit receives M soft decision variables, calculates the branch metric, and reuses partial sums with sign-symmetric or complementary relationships to reduce the number of redundant adders. The merged grid candidate path expansion unit generates candidate paths based on the transition relationships of the convolutional code grid. The hierarchical comparison and selection tree performs multi-level comparisons and selections on the candidate path metrics, outputting updated state path metric vectors and surviving path decision vectors. The path metric normalization unit sets up a subtractor array at the end of the pipeline or in the write-back path to normalize the state path metrics of the current frame according to the frame identifier. Data registers and tag registers are set between each stage of the pipeline. The tag register group corresponds one-to-one with the data register group. The frame identifier, intra-frame group number, frame end identifier, valid identifier, and frame start identifier shift progressively with the data. The tag register group consists of the same number of triggers as the data pipeline stage. Its outputs are aligned with the data outputs, ensuring that the corresponding delay tags arrive simultaneously when the updated path metric vector and the surviving path decision vector reach the output. This module can configure P identical Radix-M grouped mesh processing pipelines, where P is an integer greater than 1. Each pipeline can be configured with an independent set of frame contexts, or share the same set of frame contexts but allocate frames according to channel numbers. The outputs of multiple pipelines are written back to their respective frame contexts, thereby improving the overall throughput.

[0044] The update vector write-back module is used to write back the updated state path metric vector to the corresponding path metric context according to the delayed frame identifier, and to write the surviving path decision vector to the surviving path context according to the delayed frame identifier and intra-frame group number. This module consists of an address generator, write enable control logic, and a normalized subtractor. The address generator receives the delayed frame identifier and delayed intra-frame group number, using the frame identifier as the high-order address and the status number as the low-order address to generate the write address for the path metric context; simultaneously, it combines the frame identifier, intra-frame group number, and status number to generate the write address for the surviving path context. The write enable control logic generates a write pulse based on the delayed valid identifier and frame end identifier, ensuring that the path metric vector and surviving path decision vector are written to the corresponding memory area at the correct clock cycle. Before writing back, the normalized subtractor array subtracts the current frame's reference metric from the updated state path metric vector state by state. The reference metric is generated by the minimum path metric detection circuit or a fixed reference; the input to the subtractor comes only from the path metric corresponding to the same frame identifier, without selecting a reference value across frames. The surviving path context is divided into independent memory blocks according to the frame identifier, and each memory block is addressed by group number and status number; the write port and backtracking read port are configured independently.

[0045] The recursive update module is used to take the updated state path metric vector as the recursive starting point of the current input group when the delayed frame identifier is the same as the current frame to be decoded. This module consists of a frame identifier comparator, a path metric selector, and a bypass data path. One input of the frame identifier comparator receives the delayed frame identifier, and the other input receives the currently scheduled frame identifier. When they match, the comparator outputs a selection signal, controlling the path metric selector to select the updated state path metric vector directly from the pipeline output, instead of the old state path metric read from the path metric context. The output of the path metric selector serves as the recursive starting point for the ACS operation of the current input group. The bypass data path consists of a multiplexer array and a bus, with a bit width consistent with the state path metric vector. It can directly send the pipeline output to the ACS input within one system clock cycle, avoiding the latency of writing to and reading from memory. If the system uses a memory structure with write-priority semantics, the same effect can be achieved through timing control of memory write enable and read enable. If this bypass data path is not configured, the number of frame contexts is L+1, ensuring that updates are reliably written when the same frame is rescheduled.

[0046] The backtracking judgment module is used to determine whether the current frame to be decoded meets the backtracking conditions. If it does, the surviving path decision vector is read backtracked and the decoding information bits are output according to the frame identifier and the intra-frame group number; otherwise, Radix-M grouped grid processing is continued for subsequent input groups.

[0047] This module consists of a backtracking task queue, a backtracking controller, a backtracking read address generator, and an output reordering module. The backtracking task queue maintains a backtracking depth counter and a frame end identifier for each frame context. When the counter reaches a preset backtracking depth or the frame end identifier is valid, the corresponding frame identifier, termination status, and end group number are submitted to the backtracking task queue. The backtracking controller retrieves tasks from the queue and controls the backtracking read address generator to generate read addresses in reverse order according to the frame identifier and intra-frame group number, reading the surviving path decision vector from the surviving path context. The surviving path context uses a dual-port memory, a multi-database memory, or a ping-pong memory, allowing the ACS write port and the backtracking read port to simultaneously operate on different memory banks or different frame partitions. The backtracking controller recovers M·r decoded information bits each time it backtracks and sends the recovered decoded information bits to the output reordering module. The output reordering module distributes the decoding results to different output interfaces according to the frame identifier, or reorders the outputs of multiple frames according to the frame arrival order. The backtracking task queue works asynchronously with the front-end pipeline, so that backtracking reads do not occupy the front-end ACS write port, and the front-end continues to receive new input groups step by step.

[0048] Example 3 An electronic device, comprising: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which enables the at least one processor to perform the high-speed Viterbi decoding method based on multi-frame interleaving pipeline described above.

[0049] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described high-speed Viterbi decoding method based on multi-frame interleaving pipeline.

[0050] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-speed Viterbi decoding method based on multi-frame interleaving pipeline, characterized in that, include: Obtain F frames to be decoded, divide each frame's soft decision quantity into multiple input groups containing M soft decision quantities, and configure each group with a frame identifier, intra-frame group number, and frame end identifier; A frame context is constructed for each frame to be decoded. The frame context includes a path metric context for storing state path metrics, a surviving path context for storing surviving path decision vectors, and a frame control context for storing intra-frame group numbers and frame state information; and F≥L, where L is the path metric feedback delay. The frame to be decoded is selected in a cyclic rotation within a continuous system clock cycle, and the interval between two adjacent selections of the same frame is not less than L. Read the state path metric of the current frame to be decoded, perform Radix-M grouped grid processing on its input group step by step, start one input group every cycle, and synchronously output the updated state path metric vector, surviving path decision vector, delayed frame identifier, intra-frame group number and frame end identifier. Write the updated state path metric vector back to the corresponding path metric context according to the delayed frame identifier, and write the surviving path decision vector into the surviving path context according to the delayed frame identifier and intra-frame group number. When the delayed frame identifier is the same as the current frame to be decoded, the updated state path metric vector is used as the recursive starting point of the current input group. Determine whether the current frame to be decoded meets the backtracking condition. If it does, read the surviving path decision vector backtracking and output the decoding information bits according to the frame identifier and intra-frame group number; otherwise, continue to perform Radix-M grouped grid processing on subsequent input groups.

2. The high-speed Viterbi decoding method based on multi-frame interleaving pipeline as described in claim 1, characterized in that, The path metric feedback latency is the number of system clock cycles from the start of reading the path metric until the updated path metric can be reused.

3. The high-speed Viterbi decoding method based on multi-frame interleaving pipeline as described in claim 1, characterized in that, The cyclic selection of frames to be decoded adopts a frame pool cyclic scheduling mechanism. When the number of valid frames to be decoded in the frame pool is insufficient, an invalid time slot is inserted to wait for new frames to be decoded to enter the frame pool, ensuring that the same frame to be decoded will not be repeatedly scheduled when the path metric is not ready to be updated.

4. The high-speed Viterbi decoding method based on multi-frame interleaving pipeline as described in claim 1, characterized in that, The Radix-M grouped mesh processing is completed by the Radix-M grouped mesh processing pipeline; The Radix-M grouped grid processing includes grouped branch metric calculation and multi-level ACS processing; The pipeline is configured with a tag pipeline level that corresponds one-to-one with each internal data pipeline level. The frame identifier, intra-frame group number, and frame end identifier are output synchronously with the data path via the tag pipeline level with a delay.

5. The high-speed Viterbi decoding method based on multi-frame interleaving pipeline as described in claim 1, characterized in that, When the updated state path metric vector is written back to the corresponding path metric context, the intra-frame path metric normalization is completed within the frame context. The normalization reference metric is taken from the updated path metric of this frame and does not reference the path metric data of other frames to be decoded.

6. The high-speed Viterbi decoding method based on multi-frame interleaving pipeline as described in claim 1, characterized in that, When the delayed frame identifier is the same as the current frame to be decoded, the updated state path metric vector is used as the recursive starting point of the current input group, and the process is implemented through a bypass path composed of a frame identifier comparator and a path metric selector, specifically as follows: When the frame identifier written back matches the current scheduling frame identifier, the path metric selector selects the updated state path metric vector directly output by the pipeline to replace the state path metric that has not yet been updated in the path metric context storage.

7. The high-speed Viterbi decoding method based on multi-frame interleaving pipeline as described in claim 1, characterized in that, The backtracking conditions are: The surviving path decision vector stored in the surviving path context of the frame to be decoded reaches the preset backtracking depth, or all input groups of the frame to be decoded have completed Radix-M grouped mesh processing; The survival path context is implemented by a dual-port memory, a multi-database memory, or a ping-pong memory, and is used to enable the parallel execution of the survival path decision vector write operation and the backtracking read operation.

8. A high-speed Viterbi decoding device based on multi-frame interleaving pipeline, characterized in that, include: The data acquisition module is used to acquire F frames to be decoded, divide each frame's soft decision quantity into multiple input groups containing M soft decision quantities, and configure each group with a frame identifier, intra-frame group number, and frame end identifier. The frame context construction module is used to construct a frame context for each frame to be decoded. The frame context includes a path metric context for storing state path metrics, a surviving path context for storing surviving path decision vectors, and a frame control context for storing intra-frame group numbers and frame state information; and F≥L, where L is the path metric feedback delay. The frame selection module is used to select frames to be decoded in a cyclic rotation within a continuous system clock cycle, with the interval between two adjacent selections of the same frame not less than L. The grouped grid processing module is used to read the state path metric of the current frame to be decoded, perform Radix-M grouped grid processing on its input group frame by frame, start one input group per cycle, and synchronously output the updated state path metric vector, surviving path decision vector, delayed frame identifier, intra-frame group number and frame end identifier. The update vector write-back module is used to write back the updated state path metric vector to the corresponding path metric context according to the delayed frame identifier, and to write the surviving path decision vector to the surviving path context according to the delayed frame identifier and intra-frame group number. The recursive update module is used to take the updated state path metric vector as the recursive starting point of the current input group when the delayed frame identifier is the same as the current frame to be decoded. The backtracking judgment module is used to determine whether the current frame to be decoded meets the backtracking conditions. If it does, the surviving path decision vector is read backtracked and the decoding information bits are output according to the frame identifier and the intra-frame group number; otherwise, Radix-M grouped grid processing is continued for subsequent input groups.

9. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the high-speed Viterbi decoding method based on multi-frame interleaving pipeline as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the high-speed Viterbi decoding method based on multi-frame interleaving pipeline as described in any one of claims 1 to 7.

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