A bandwidth power consumption collaborative optimization method and system based on an HBF high-bandwidth chip

Abstract

The application relates to the technical field of power consumption optimization, and discloses a bandwidth power consumption collaborative optimization method based on an HBF high-bandwidth chip, which comprises the following steps: obtaining a task access request, extracting data throughput and bandwidth margin, and obtaining an initial physical channel number through feature mapping; calculating a power consumption increment to determine a sudden surge current of a power supply link; obtaining a current margin and a safety red line of the link, and if the difference between the sudden surge current and the current margin is greater than the safety red line, generating an out-of-limit identifier, combining physical environment parameters to generate a voltage sudden drop early warning; according to the voltage sudden drop early warning, reducing the initial channel number to obtain an updated channel number; extracting a node load capacity and a link impedance, and updating the sudden surge current value; and if the difference between the updated sudden surge current and the current margin is less than or equal to the red line, generating a transmission link configuration instruction. The method can realize dynamic balance optimization of bandwidth demand and power consumption impact.

Description

Technical Field

[0001] This invention relates to the field of power consumption optimization technology, and in particular to a bandwidth and power consumption co-optimization method and system based on HBF high-bandwidth chips. Background Technology

[0002] Currently, in the fields of high-performance computing and communications, HBF (High Bandwidth Chip) has become the core computing power foundation for scenarios such as artificial intelligence training and cloud computing data centers due to its superior data transmission capabilities. How to control peak power consumption while ensuring bandwidth requirements has become a critical issue that urgently needs to be addressed in the practical engineering applications of HBF chips.

[0003] In existing technologies, HBF chip physical channel scheduling often employs a static configuration scheme based on a fixed mapping table or a simple load balancing strategy executed by the microcontroller. This primarily focuses on the matching degree between data throughput and available bandwidth when a task is accessed, allocating resources through a pre-defined channel allocation table. When high-bandwidth tasks suddenly access the system, the microcontroller opens physical channels in batches according to preset rules to meet data throughput demands. However, this process lacks real-time awareness of the dynamic load-bearing capacity of the chip's power supply link, and fails to incorporate the transient current surges caused by channel opening into the scheduling decision-making scope. This leads to instantaneous overload or even voltage drop in the power supply link, resulting in abnormal chip operation or even task interruption.

[0004] In summary, existing technologies lack a coordinated consideration of the transient current carrying capacity of the power supply link when the microcontroller performs channel scheduling, making it difficult to achieve dynamic balance optimization between bandwidth requirements and power consumption impact in high-bandwidth task access scenarios. Summary of the Invention

[0005] This invention provides a bandwidth and power consumption co-optimization method and system based on HBF high-bandwidth chips to achieve dynamic balance optimization between bandwidth demand and power consumption impact.

[0006] In a first aspect, to address the aforementioned technical problems, this invention provides a bandwidth and power consumption co-optimization method based on an HBF high-bandwidth chip, comprising: The task access request of the target chip is obtained and extracted to obtain the data throughput value and bandwidth margin value. The data throughput value and bandwidth margin value are then feature-mapped to obtain the initial number of physical channels. The power consumption increment data is calculated using the initial number of physical channels, and the surge current value of the target chip's power supply link is determined based on the power consumption increment data. Obtain the current current margin value and safety red line value of the power supply link, calculate the difference between the sudden current value and the current current margin value, and if the difference is greater than the safety red line value, generate a voltage drop warning information based on the pre-obtained physical environment parameters. In response to the voltage drop warning information, the initial number of physical channels is reduced to obtain an updated number of physical channels; The link impedance data is extracted based on the updated physical channel count. The sudden current value is updated based on the link impedance data to obtain the updated current value. If the difference between the updated current value and the current current margin value is not less than the safety red line value, a transmission link configuration instruction is generated.

[0007] Secondly, the present invention provides a bandwidth and power consumption co-optimization system based on an HBF high-bandwidth chip, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the bandwidth and power consumption co-optimization method based on the HBF high-bandwidth chip as described above.

[0008] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the bandwidth and power consumption co-optimization method based on the HBF high-bandwidth chip as described above.

[0009] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention obtains the task access request of the target chip, extracts the data throughput value and bandwidth margin value of the target task, and performs feature mapping on the two to obtain the initial number of physical channels. This series of operations converts the bandwidth requirements of the task layer into the requirements of the underlying physical resources. By using temporal feature extraction and deep mapping network, it realizes the accurate mapping from task features to the number of channels, thereby solving the problem that the microcontroller in the prior art only relies on a fixed mapping table and lacks the ability to make adaptive channel number decisions.

[0010] (2) After obtaining the initial number of physical channels, the present invention calculates the corresponding power consumption increment data and determines the sudden current value of the power supply link accordingly, and then obtains the current current margin value and safety red line value. Through difference comparison and over-limit judgment, voltage drop warning information is generated. It can predict the impact on the power supply link before the channel is opened, make up for the lack of power supply perception in the traditional microcontroller scheduling strategy, and provide accurate triggering criteria for subsequent differentiated channel reduction.

[0011] (3) In response to voltage sag warning information, this invention reduces the initial number of physical channels and recalculates the surge current value by extracting link impedance data based on the updated number of channels until the current surge meets the safety red line constraint, at which point a transmission link configuration instruction is generated. This operation incorporates bandwidth requirement satisfaction and power supply link safety margin into a unified decision-making framework, enabling the microcontroller to proactively avoid power supply overload risks while ensuring data throughput performance, thereby improving the chip's operational reliability under high load scenarios.

[0012] (4) The transmission link configuration instruction finally generated by this invention carries both the configuration information of the data transmission link and the scheduling information of the power supply link, realizing the synchronous and coordinated scheduling of the two links. This mechanism breaks through the limitation of the separation between data transmission and power supply management in the traditional scheme. It avoids the risk of voltage drop caused by excessive channel opening and ensures the real-time requirements of high bandwidth tasks. It effectively solves the problem of insufficient chip power supply stability caused by the lack of bandwidth and power consumption co-optimization capability of microcontrollers in the prior art, and improves the overall availability and energy efficiency of HBF chips in complex task scenarios. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the bandwidth and power consumption collaborative optimization method based on HBF high-bandwidth chip provided in the first embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the change in power consumption increment with the number of channels provided in the first embodiment of the present invention; Figure 3 This is a schematic diagram of the sudden current and voltage drop response provided in the first embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Reference Figure 1 The first embodiment of the present invention provides a bandwidth and power consumption co-optimization method based on HBF high-bandwidth chips, including the following steps: Step S11: Obtain and extract the task access request of the target chip to obtain the data throughput value and bandwidth margin value. Perform feature mapping on the data throughput value and the bandwidth margin value to obtain the initial number of physical channels. Step S12: Calculate the power consumption increment data using the initial number of physical channels, and determine the surge current value of the target chip's power supply link based on the power consumption increment data; Step S13: Obtain the current current margin value and safety red line value of the power supply link, calculate the difference between the sudden current value and the current current margin value, and if the difference is greater than the safety red line value, generate voltage drop warning information based on the pre-obtained physical environment parameters. Step S14: For the voltage drop warning information, the initial number of physical channels is reduced to obtain the updated number of physical channels; Step S15: Extract link impedance data based on the updated physical channel quantity, update the surge current value based on the link impedance data to obtain an updated current value, and generate a transmission link configuration instruction if the difference between the updated current value and the current current margin value is not less than the safety red line value.

[0016] In step S11, the task access request of the target chip is obtained and extracted to obtain the data throughput value and bandwidth margin value. The data throughput value and bandwidth margin value are then feature-mapped to obtain the initial number of physical channels.

[0017] In one implementation, the method includes: Obtain the task access request of the target chip, and parse the task access request to obtain a request parse tree; Initial throughput data is extracted from the request parse tree to obtain data throughput values, and a task load graph is obtained based on the data throughput values; Initial bandwidth data is extracted from the task load graph. If the initial bandwidth data is greater than a preset threshold, the bandwidth margin value is determined.

[0018] In one implementation, the method further includes: The data throughput value and the bandwidth margin value are concatenated in time series to obtain an initial time series feature sequence; Long Short-Term Memory (LSTM) network is used to extract features from the initial temporal feature sequence to obtain the hidden layer state vector; Principal component analysis is performed on the hidden layer state vector to reduce its dimensionality, resulting in a dimensionality-reduced feature matrix. The reduced feature matrix is ​​linearly transformed by a feature mapping network to determine the channel mapping weights. The preset baseline channel values ​​are then weighted and summed according to the channel mapping weights to obtain the initial number of physical channels.

[0019] The task access request is generated by the target chip's main controller when it detects an external task trigger signal. It includes structured fields such as task type identifier, priority, data packet size, and latency constraints, and the transmission format follows the PCIe or AXI bus protocol. An abstract syntax tree (AST) parsing algorithm is used to hierarchically decompose the original message of the task access request, organizing the text-based request fields into a tree-like data structure according to semantic structure. The root node stores the task type, and the leaf nodes store specific parameter values. It should be noted that the AST parsing algorithm is a mature compiler principle technology in this field. The input is the original request message, and the output is a structured request parse tree. This request parse tree can accurately identify the hierarchical dependencies of complex tasks, improving the accuracy of subsequent feature extraction. For example, for a high-definition video stream decoding task, the root node of its request parse tree is the decoding task, the second-level nodes include the input bitstream and the output image, and the third-level nodes further refine the details to the specific bitstream format and resolution parameters.

[0020] Specifically, the leaf nodes of the request parse tree are traversed, and fields representing data volume are extracted as initial throughput data. For example, for a high-definition video stream decoding task, the extracted initial throughput data is 500MB / s, meaning the data throughput value is 500MB / s. Based on this, a graph neural network algorithm is used to construct a task load graph. The input is the data throughput value and the connection relationships between the computing units within the target chip. The output is a graph structure reflecting the load status of each computing unit in the chip. This graph structure uses computing units as nodes, data flow directions as edges, and the distribution ratio of data throughput values ​​as edge weights. The graph neural network uses a two-layer graph convolutional network (GCN) with a hidden layer dimension of 64 and the activation function ReLU. The update rule for each GCN layer is as follows: Where A is the adjacency matrix, D is the degree matrix, and W is the trainable weights. By updating the node features through neighbor aggregation, the load embedding vector of each computing unit is finally output, forming the task load graph. The pre-training process of the GCN is as follows: During the chip design verification stage, the Cadence Voltus power consumption simulation tool (Synopsys PrimePower as an alternative) is used to complete the gate-level power consumption simulation in combination with the target chip's gate-level netlist and parasitic parameters, generating a large number of (task flow, load distribution) sample pairs, forming a training set of no less than 3000 sets of samples, of which 1000 sets have accurate load distribution labels, and the remaining 2000 sets are unlabeled data. A pseudo-label self-training strategy is used to utilize this data. First, the GCN is pre-trained with 1000 sets of labeled samples, and then the pre-trained model is used to infer pseudo-labels from the 2000 sets of unlabeled samples. Pseudo-labeled samples with a confidence level higher than 0.9 are merged into the training set to participate in the second round of training. This process is repeated for 3 rounds until the comprehensive training evaluation index meets the preset conditions and the model parameters are solidified. The comprehensive training evaluation index includes The model includes node-level task category prediction accuracy and embedding vector reconstruction error. Node-level task categories are divided into three types based on bandwidth requirements: low-bandwidth tasks (less than 800 MB / s), medium-bandwidth tasks (greater than or equal to 800 MB / s but less than 1600 MB / s), and high-bandwidth tasks (greater than or equal to 1600 MB / s). The training loss function is a weighted sum of cross-entropy classification loss and embedding vector reconstruction loss, with weights of 0.7 and 0.3, respectively. Model parameters are fixed when the node-level task category prediction accuracy is greater than 90% and the embedding vector reconstruction error is less than 0.05.

[0021] Finally, initial bandwidth data is extracted from the task load graph. If the initial bandwidth data is greater than a preset threshold, a bandwidth margin value is determined. Specifically, initial bandwidth data is extracted from the edge weight features of the task load graph, for example, the initial bandwidth data is extracted to be 800MB / s. The preset threshold of 600MB / s is obtained by statistically taking 70% of the upper limit of the chip's internal bus bandwidth during the target chip manufacturing stage, that is, reserving a 30% margin as a safety margin. This ratio is determined by engineering experience regarding the ratio of peak bandwidth to sustained bandwidth in the chip design specifications. When the initial bandwidth data of 800MB / s is greater than the preset threshold of 600MB / s, it is determined that the current task has a high bandwidth occupation risk, and then a greedy algorithm is used to dynamically determine the bandwidth margin value as 200MB / s. The strategy of the greedy algorithm is to successively deduct the bandwidth requirement corresponding to the highest-load computing unit in the task load graph from the currently available total bandwidth until the deduction amount meets the total throughput requirement of the task. The remaining unallocated bandwidth is used as the bandwidth margin value, which is set to 200MB / s in this embodiment. The final data throughput of the target task was 500MB / s, with a corresponding bandwidth margin of 200MB / s. This resource assessment and extraction mechanism effectively prevents data packet loss in high-concurrency scenarios, significantly improving the overall resource utilization and task throughput performance of the chip.

[0022] The data throughput and bandwidth margin values ​​are concatenated over time to obtain an initial time-series feature sequence. Specifically, data throughput and bandwidth margin values ​​are continuously recorded using a preset sliding time window (e.g., a window length of 10 sampling points, corresponding to 10 consecutive historical moments, with an interval of 1ms between adjacent sampling points), with each sampling point corresponding to a timestamp. The data throughput and bandwidth margin values ​​of the current moment and the previous 9 moments are combined in chronological order to output an initial time-series feature sequence containing a time dimension. The dimension of the initial time-series feature sequence is 10×2, where 10 is the time step and 2 is the feature dimension (data throughput and bandwidth margin). This time-series concatenation method aims to preserve the dynamic characteristics of the task data stream fluctuating over time, providing necessary input for subsequent time-series models. It should be noted that the length of the sliding time window of 10 is determined based on the joint analysis of the minimum response period of task scheduling and the dependence depth of LSTM on historical information. Too short a window will lose historical trend information, while too long a window will introduce irrelevant historical noise.

[0023] Subsequently, a Long Short-Term Memory (LSTM) network is used to extract features from the initial temporal feature sequence to obtain the hidden layer state vector. Specifically, the LSTM network is a recurrent neural network suitable for processing temporal sequences. In this embodiment, the hidden layer dimension of the LSTM is set to 128, with two layers. Each LSTM unit contains three gating mechanisms: a forget gate, an input gate, and an output gate, as well as a cell state. The forget gate uses the sigmoid function to determine how much information to retain from the cell state at the previous time step. The input gate uses the sigmoid and tanh functions to determine how much of the current input to write into the cell state. The output gate uses the sigmoid function to determine how much to output from the updated cell state to the hidden layer state. The hidden layer state vector corresponding to the last time step is the output, with a dimension of 128. The pre-training process of the LSTM involves collecting historical temporal data of the target chip under various workloads under laboratory conditions, using the final actual number of allocated physical channels as labels to form a training set of no less than 5000 samples.

[0024] The label generation method involves using an exhaustive simulation approach on an FPGA verification platform to sequentially enable 1 to 28 physical channels for each set of historical time-series data, measuring the transient voltage drop and data throughput completion rate of the corresponding power supply links. The minimum number of channels selected from the set of feasible channels that meet the dual constraints of a voltage drop not exceeding 30mV and a data throughput completion rate not less than 95% is chosen as the optimal channel number label (i.e., the minimum feasible channel number, ensuring normal task execution while minimizing power consumption). At least three chip architects independently review the labels provided by the exhaustive simulation; in case of discrepancies, the median is used to solidify the label generation method, ensuring its reproducibility and consistency. The Adam optimizer is used, with a learning rate of 0.001, a batch size of 32, and 100 training epochs. The loss function is the mean squared error (MSE). Training stops and model parameters are solidified when the validation set loss no longer decreases after 10 consecutive epochs. The final model's coefficient of determination (R²) on the test set is greater than 0.92.

[0025] Subsequently, principal component analysis (PCA) is performed on the hidden layer state vector to reduce its dimensionality, resulting in a dimensionality-reduced feature matrix. Specifically, PCA is an unsupervised linear dimensionality reduction method that transforms the original feature space through orthogonal transformation, converting potentially correlated high-dimensional variables into linearly uncorrelated low-dimensional variables, while retaining the top principal components with the largest variance. In this embodiment, the original 128-dimensional hidden layer state vector is reduced to 16-dimensional. The process involves first calculating the covariance matrix Σ (128×128) of the hidden layer state vector across the entire training set, then performing eigenvalue decomposition on this covariance matrix, and using the eigenvectors corresponding to the 16 largest eigenvalues ​​to form a projection matrix W (128×16). The real-time acquired 128-dimensional hidden layer state vector is multiplied by the projection matrix W to obtain the 16-dimensional dimensionality-reduced feature matrix. The projection matrix W is calculated and stored once during initialization, requiring only one matrix multiplication during runtime, resulting in minimal computational overhead. The cumulative variance contribution rate retained after dimensionality reduction is greater than 95%, ensuring that information loss is within an acceptable range.

[0026] Finally, the reduced-dimensional feature matrix is ​​linearly transformed using a feature mapping network to determine the channel mapping weights. Based on these weights, a weighted sum of preset baseline channel values ​​is obtained to determine the initial number of physical channels. Specifically, the feature mapping network comprises two fully connected layers: the first layer maps the 16-dimensional input to 32 dimensions using ReLU activation; the second layer maps the 32-dimensional input to 2 dimensions, outputting a channel mapping weight vector with non-negative normalization constraints. The preset reference channel value These are two sets of basic channel numbers preset during the chip hardware design phase based on bus bandwidth specifications. Their physical meaning is related to data throughput values, serving as a low-load baseline. Corresponding total bandwidth It can support no more than The continuous data throughput just covers this embodiment. Medium to low load tasks; high load baseline Corresponding total bandwidth This is used to cover high-throughput tasks in future expanded scenarios. The physical meaning of the channel mapping weight is the weighting coefficient for channel allocation between the low-load and high-load benchmarks. The weighted summation process is as follows: Due to the weights output by the feature mapping network The weighted summation is obtained from continuous real values. Typically a non-integer (e.g.) hour (Number of channels), and the number of physical channels must be an integer to correspond to discrete hardware channel resources, therefore it is necessary to... Rounding is performed. This embodiment uses the round-down rule. That is, take no more than The largest integer is used as the final initial number of physical channels. The physical rationale for choosing to round down rather than round to the nearest integer is that when the bandwidth requirement is near the critical point of two integer channel numbers, it is better to allocate one less channel than to exceed the power supply link's carrying capacity, thereby avoiding the potential risk of voltage drop introduced by moving up the channel count. In this embodiment... hour That is, the initial number of physical channels is 28. The feature mapping network and LSTM are jointly pre-trained, and the weight parameters are updated synchronously during the LSTM training phase. The loss gradient updates the parameters of both networks simultaneously through backpropagation.

[0027] In step S12, power consumption increment data is calculated based on the initial number of physical channels, and the surge current value of the target chip power supply link is determined based on the power consumption increment data, including: The first voltage drop amplitude is obtained based on the initial dynamic current sequence corresponding to the power consumption increment data; The first voltage drop amplitude is filtered to obtain the second voltage drop amplitude. If the second voltage drop amplitude is greater than a preset voltage threshold, the node voltage distribution is determined. Peak current characteristics are extracted from the node voltage distribution, and the surge current value faced by the power supply link of the target chip is determined based on the peak current characteristics.

[0028] First, based on the initial number of physical channels and the topology of the target chip's internal bus, a two-dimensional matrix of dimension N×T is generated, where N is the initial number of physical channels and T is the preset time window length. The rows of the matrix represent different physical channels, and the columns represent consecutive time windows. Matrix elements consist of 0 and 1, where 1 indicates a channel is in an active working state, and 0 indicates a channel is in a dormant state. In this embodiment, the initial number of physical channels is 28, and the time window T is 10, so the dimension of the channel activation state matrix is ​​28×10. This matrix representation transforms the discrete channel allocation results into a computable spatiotemporal state map, facilitating subsequent indexing and matching with the hardware feature library. The 0s and 1s in the channel activation state matrix are written by the task scheduler at the beginning of each time window according to the channel allocation strategy, reflecting whether a channel is occupied by a task within that time window.

[0029] Subsequently, the target toggle rate sequence and static leakage current sequence are obtained by matching the channel activation state matrix. The target toggle rate sequence and the static leakage current sequence are then concatenated to obtain the basic power consumption feature vector. Specifically, the target chip pre-stores a hardware feature library, which records the logic gate toggle probability and inherent leakage parameters of each physical channel at different operating frequencies. These parameters are obtained through silicon testing during the chip tape-out stage. The specific testing method includes applying a test stimulus of known frequency to each channel, measuring its dynamic current consumption through an on-chip power monitoring circuit, and calculating the number of logic gate toggles and leakage current per unit time using a gate-level netlist. It should be noted that, considering the aging effects of NBTI (Negative Bias Temperature Instability) and HCI (Hot Carrier Injection) during long-term chip operation, which can cause transistor threshold voltage drift and thus slow drift in flip-flop probability and leakage current parameters, the writing strategy of the hardware feature library in this embodiment is as follows: based on the initial parameters written in one go during the tape-out stage, a 15% full-lifecycle aging margin is reserved for the flip-flop probability and leakage current of each channel (i.e., the written value is the actual measured value of silicon testing multiplied by 1.15). This margin is determined based on the upper bound of parameter drift obtained from the simulation of the NBTI and HCI joint aging model under the nominal 10-year lifespan of the target chip. Since the reserved aging margin covers the entire lifecycle, the hardware feature library does not need to be calibrated online or updated periodically after leaving the factory, which can ensure that the power consumption calculation deviation does not exceed the acceptable range (less than 10%) throughout the entire lifecycle.

[0030] The field format of each record in the hardware feature library is ( ),in The channel number (values ​​range from 1 to 28). The channel operating frequency (in GHz). The logic gate flip probability (dimensionless, ranging from 0 to 1). This represents the static leakage current (in μA). For example, the record for channel 1 at a 2GHz operating frequency is ( This indicates that the switching probability of channel 1 at 2GHz is 0.35 and the static leakage current is 45μA; the record for channel 2 at 2GHz is ( The record for channel 15 at 2GHz is ( ); The activation markers (i.e., positions with a value of 1) in the channel activation state matrix are traversed, and index matching is performed in the hardware feature library to extract the switching probability and leakage current parameters of the corresponding active channel at the current operating frequency. After time-dimensional alignment, the target switching rate sequence and the static leakage current sequence are output. In this embodiment, the target switching rate sequence contains 28 discrete values, ranging from 0.1 to 0.8; the static leakage current sequence contains 28 reference current values, in μA, ranging from 30μA to 80μA. A vector concatenation algorithm is used to concatenate the two sequences with different physical meanings along the feature dimension to generate a one-dimensional basic power consumption feature vector of length 56.

[0031] Finally, based on the basic power consumption feature vector, ridge regression is used to calculate the power consumption increment data of the target chip when the corresponding channel is activated. Specifically, the ridge regression algorithm is a linear regression method that introduces an L2 regularization term on the basis of least squares, which can effectively handle the multicollinearity problem that may exist in the feature vector and establish a mapping relationship between the basic power consumption feature vector and the power consumption increment. In this embodiment, the ridge regression model takes the form of: Where X is the 56-dimensional basic power consumption feature vector, W is the weight vector (56 dimensions), b is the bias term, and ΔP is the output power consumption increment data (in mW). The regularization coefficient λ is set to 0.1, and the regularization term is... The pre-training process of the ridge regression model involves, under laboratory conditions, collecting the basic power consumption feature vector (input) of the target chip under different channel activation combinations and the power consumption increment data (output) measured by a precision power analyzer (e.g., Keysight N6705C), forming a training set of no less than 2000 samples; and using the least squares method to solve for the weight vector W and the bias b, as shown in the formula. The optimal regularization coefficient was selected through 5-fold cross-validation (grid search among λ values ​​of 0.01, 0.1, 1.0, and 10), and model training was completed when the final determination coefficient R² was greater than 0.95. In this embodiment, when all 28 physical channels are activated simultaneously, the static leakage current of each channel is taken as a calibrated value in the range of 30μA to 80μA, corresponding to a total static power consumption of approximately 1.4mW; combined with the operating frequency of 2GHz, equivalent load capacitance, and logic gate switching activity, the dynamic power consumption is calculated to be approximately 118.6mW, and the total power consumption increment after the two are added together is approximately 120mW.

[0032] It should be noted that the power consumption increment data ΔP is first converted into an initial dynamic current sequence, with the conversion formula being I(t) = ΔP / Vdd, where Vdd is the supply voltage of the target chip (1.0V in this embodiment). The initial dynamic current sequence is obtained by expanding the sequence across 64 sampling points at a preset sampling interval (e.g., 1 ns). That is, the sequence time The value range is [0, 63ns], the step size is 1ns, and the number of sampling points is 64. The selection of the 1ns sampling interval is based on the fact that the shortest switching time of the target chip's internal switching transistor is approximately 500ps, and according to the Nyquist sampling theorem, sampling needs to be performed at a frequency higher than twice that. Subsequently, the power distribution network impedance convolution algorithm is used to perform a time-domain convolution operation with the preset chip power supply network impedance model, outputting the first voltage drop amplitude sequence. The power supply network impedance model is obtained during the chip design stage using the RLGC parasitic parameter extraction tool (e.g., Ansys RedHawk), recording the complete impedance frequency response from the package to the on-chip power supply grid inside the chip. The model form is as follows: The storage format is a complex impedance table at discrete frequency points, covering a frequency range from DC to 1 GHz, with a logarithmically equidistant distribution. In this embodiment... Key characteristic parameters include: DC impedance First resonant frequency Resonant peak impedance Second resonant frequency The voltage drop in the frequency domain is ,in The Fourier transform of the initial dynamic current sequence is followed by the inverse Fourier transform to obtain the voltage drop sequence in the time domain. In this embodiment, the maximum transient current is 120mA, and the maximum drop value of the first voltage drop amplitude sequence output after convolution calculation is 45mV.

[0033] Subsequently, the first voltage drop amplitude is filtered to obtain the second voltage drop amplitude. If the second voltage drop amplitude is greater than a preset voltage threshold, the node voltage distribution is determined. Specifically, a Butterworth low-pass filter algorithm is used to filter out high-frequency noise from the first voltage drop amplitude sequence. The cutoff frequency is set to 100MHz, the filter order is 4, and a smoothed second voltage drop amplitude sequence is output. The cutoff frequency of 100MHz is determined based on the upper limit of the resonant frequency of the target chip's power supply network. Components above this frequency are parasitic parameter noise and do not reflect the true voltage drop risk. The preset voltage threshold of 30mV is obtained by taking 80% of the power supply network IR drop margin during the chip design stage, i.e., 3% of the chip's rated operating voltage of 1.0V as a safety margin. When the maximum value in the second voltage drop amplitude sequence (e.g., 35mV) is greater than the preset voltage threshold of 30mV, the solution mechanism for the node voltage distribution is triggered. The input is the physical topology of the power supply grid inside the chip (containing a grid of about 10,000 nodes) and the current boundary current conditions. The Gauss-Seidel iterative algorithm is used to solve the voltage of all nodes in the network. The iteration terminates when the difference between two iterations is less than 1μV or the number of iterations reaches 10,000. The output is a two-dimensional node voltage distribution matrix, which records the real-time power supply voltage values ​​at each physical coordinate point of the chip.

[0034] Finally, peak current features are extracted from the node voltage distribution, and the surge current value faced by the target chip's power supply link is determined based on these peak current features. Specifically, principal component analysis is used to reduce the dimensionality and extract features from the voltage depression features in the node voltage distribution matrix, outputting a peak current feature vector with a dimension of 8 that characterizes the local current accumulation state. This peak current feature vector is then input into a pre-trained support vector regression model (SVR). The SVR uses a radial basis function (RBF) kernel function with a penalty parameter C=1.0 and a kernel parameter γ=0.1, establishing a mapping relationship between the feature vector and the actual link current. The pre-training process of the SVR model is as follows: During the chip design verification stage, a large number of node voltage distribution matrices and corresponding peak current feature vectors under different load distributions are generated using electromagnetic simulation tools, and measured link current values ​​are labeled to form a training set of no less than 1000 samples. Optimal hyperparameters (C in the range of [0.1, 1, 10, 100] and γ in the range of [0.01, 0.1, 1, 10]) are determined using grid search and 5-fold cross-validation. The final model's mean square error on the test set is less than 5 mA². In this embodiment, the sudden current value output by the SVR model is 120 mA.

[0035] In step S13, the current current margin and safety threshold of the power supply link are obtained, and the difference between the sudden current surge and the current current margin is calculated. If the difference is greater than the safety threshold, a voltage drop warning is generated based on pre-acquired physical environment parameters, including: Based on the sudden current value and load power consumption status, the Kalman filter algorithm is used to estimate the transient current throughput capability of the power supply link and obtain the current current margin value of the power supply link. Based on the current current margin value, a fuzzy logic reasoning algorithm is used to quantify and evaluate the disturbance immunity margin of the power supply link to obtain the safety red line value. Calculate the difference between the sudden current value and the current current margin value. If the difference is greater than the safety red line value, generate an over-limit trigger flag. Based on the over-limit triggering identifier and the physical environment parameters of the target chip, a decision tree classification algorithm is used to classify the risk level and generate voltage drop warning information.

[0036] It should be noted that the Kalman filter algorithm comprises two stages: prediction and update. The prediction stage predicts the transient current throughput capacity of the power supply link at the current moment based on the state estimate and state equation from the previous moment. The update stage corrects the predicted value by combining the currently measured surge current value and the load power state provided by the load power state matrix built into the target chip. The state equation is as follows: The observation equation is ,in Transient current throughput capability of the power supply link (unit: mA). The state transition matrix is ​​set to 0.95, reflecting the decay characteristics of link thermal inertia, meaning that 95% of the margin at the previous time step is still valid at the current time step. The control matrix is ​​set to 0.05, reflecting that 5% of the new input is reflected in the state at the current moment. This represents the value of the sudden increase in input current. H represents the observation value, and H is the observation matrix. In this embodiment, the observation value and the state quantity are the same physical quantity (instantaneous link current). Therefore, the observation matrix is ​​taken as a unit scalar H=1 (dimensionless), representing a 1:1 linear mapping from the state quantity to the observation quantity. , These represent process noise and observation noise (covariances of 0.5 and 2.0, respectively, obtained through field calibration experiments).

[0037] The values ​​of the state transition matrix A and control matrix B are based on the link thermal time constant of 0.19 ms and a sampling period of 10 μs, derived from the first-order exponential decay relationship of thermal inertia. Accordingly, B = 1 - A = 0.05. The process noise covariance Q = 0.5 and the observation noise covariance R = 2.0 were obtained through on-site calibration tests. The specific calibration process was as follows: Under calibration conditions (50% rated load, ambient temperature uniformly distributed from 25°C to 85°C, nominal supply voltage 1.0V), N = 500 sets of sample pairs (predicted current margin, measured current margin) were recorded, where the measured values ​​were read by a precision current probe (e.g., Tektronix TCP303); the variance of the predicted residual sequence was used as the process noise covariance Q, and the variance of the observed residual sequence was used as the observation noise covariance R. Maximum likelihood estimation was used to solve the problem, and the final calibration result was... In this embodiment, after inputting a sudden current surge value of 120mA and a load power consumption state matrix, the current current margin is output as 150mA after Kalman filtering recursion. The Kalman filtering recursion process includes five steps: predicting the state, predicting the covariance, calculating the Kalman gain, updating the state, and updating the covariance, which are executed once per sampling period.

[0038] Subsequently, based on the current current margin value, a fuzzy logic inference algorithm is used to quantify and evaluate the disturbance immunity margin of the power supply link, obtaining a safety red line value. Specifically, the fuzzy logic inference algorithm adopts a Mamdani-type fuzzy inference architecture, defining three fuzzy sets {low (L), medium (M), high (H)} for the input current current margin value, and using a triangular membership function with parameters [ [20, 0, 60], [40, 100, 160], [140, 200, 260] (unit mA); three fuzzy sets {relaxed, standard, strict} are defined for the output safety red line value, using triangular membership functions with parameters [10, 20, 30], [25, 40, 55], and [50, 70, 90] respectively. The fuzzy rule base contains three IF-THEN rules: low IF margin for the THEN red line (relaxed, avoiding frequent false alarms); medium IF margin for the THEN red line (standard); and high IF margin for the THEN red line (strict, providing sufficient protection). Inference uses the maximum-minimum synthesis method, that is, the trigger strength of each rule is taken as the minimum value of the input membership degree, and then the output membership degree is truncated; defuzzification uses the center of gravity method, that is, the center of gravity of the area of ​​the synthesized membership function of the inference result is obtained on the output interval. In this embodiment, the input current margin value is 150mA (belonging to the "medium" fuzzy set, with a membership degree of 0.83), and the inference output safety red line value is 40mA.

[0039] It should be noted that the membership function parameters and fuzzy rule base of the fuzzy inference are calibrated and fixed during the chip design stage, and will not be adjusted with changes in the current margin during operation. The safety red line value itself is the output value of the fuzzy inference, and its magnitude changes dynamically with the current margin value input in each sampling cycle (for example, outputting 40mA when the input is 150mA, and outputting 55mA when the input is 200mA). The basis for fixing is that the membership function parameters reflect the physical design boundary of the target chip's power supply link (i.e., the piecewise mapping relationship of the maximum allowable current surge determined by the package decoupling capacitor capacity, the transient response capability of the voltage regulator, and the noise margin of the most vulnerable logic gate). This boundary is determined by the chip's physical structure rather than its operating state, and therefore remains unchanged throughout its entire life cycle once calibrated. The specific calibration process for the fuzzy rule base and membership function parameters is as follows: For the expert experience part, at least three senior engineers with five years of experience in HBF chip architecture design independently derive the initial membership function boundary parameters and rule base weights based on the noise tolerance standard in the chip design specifications (i.e., 60% of the noise tolerance of the most vulnerable logic gate is used as the safety red line threshold). The median of the parameters given by the three engineers is used as the initial expert value to avoid subjective bias from a single expert. For the historical operating data part, data is collected for 12 consecutive months during the mass production testing phase of the target chip, covering temperatures from... At least 500 sets of historical fault data (including voltage drop alarm events and corresponding operating parameters) under various operating conditions such as 40°C to 125°C, voltage from 0.9V to 1.1V, and load rate from 10% to 100%, were used to fine-tune the triangle vertex parameters of the membership function using grid search (search step size 2mA). The optimization goal was to achieve a fault detection rate of greater than 95% and a false alarm rate of less than 5%. Finally, the fuzzy inference parameters for online operation were solidified.

[0040] Next, the difference between the sudden current value and the current current margin value is calculated. If the difference is greater than the safety red line value, an over-limit trigger flag is generated. Specifically, an algebraic difference algorithm is used to calculate the absolute deviation between the sudden current value and the current current margin value to obtain the difference. Then, this difference is compared with the safety red line value. If the difference is greater than the safety red line value, the state machine is triggered to jump, and a specific encoded over-limit trigger flag is output (in this embodiment, an 8-bit binary code 0xAB is used as the flag value). The encoding format of the over-limit trigger flag is predefined in the initialization stage and includes four fields: over-limit level (2 bits), occurrence timestamp (32 bits), trigger link identifier (16 bits), and difference magnitude (16 bits), which facilitates subsequent traceability and analysis. When the difference is less than the safety red line value, the state machine does not jump, skips the over-limit trigger flag generation step, and directly enters step S15.

[0041] Finally, based on the over-limit triggering identifier and the physical environment parameters of the target chip, a decision tree classification algorithm is used to classify the risk level and generate voltage drop warning information. Specifically, the decision tree classification algorithm uses the CART algorithm, with a maximum depth of 5, a minimum number of samples per leaf node of 20, and the Gini coefficient as the splitting criterion. The model input features are a 4-dimensional vector. The first dimension is the original difference calculated before generating the over-limit trigger flag (i.e., the algebraic difference between the surge current value and the current current margin value, in mA, floating-point precision, without any quantization truncation; the 16-bit integer quantization value stored in the "difference amplitude" field of the over-limit trigger flag encoding format is not used here to avoid the impact of quantization error on the accuracy of the decision tree splitting threshold). The second dimension is the current temperature of the target chip (read by the on-chip temperature sensor, in °C). The third dimension is the current voltage of the target chip (read by the on-chip voltage monitor, in mV). The fourth dimension is the current load rate of the target chip (read by the task scheduler, as a percentage). The output is a risk level label, divided into four levels: {Level 1 Red, Level 2 Orange, Level 3 Yellow, Level 4 Blue}, corresponding to different emergency response strategies. The pre-training process of the decision tree involves applying various operating conditions to the target chip under laboratory conditions (temperature from...). The system records the above four-dimensional input features (40°C to 125°C, voltage from 900mV to 1100mV, load rate from 10% to 100%, and difference from 0mA to 100mA) and the risk level labeled by experts, forming a training set of no less than 3000 samples. A 5-fold cross-validation model is used to train the model, and the model is solidified when the classification accuracy is greater than 95%. For example, when the input difference is 50mA, the current temperature is 75°C, the current voltage is 980mV, and the current load rate is 85%, the decision tree outputs a Level 1 red warning, generating a voltage drop warning message containing a Level 1 red warning instruction. This warning message also carries metadata such as the difference magnitude and the time of occurrence, providing input for the subsequent channel reduction in S15.

[0042] like Figure 2As shown in the figure, this diagram illustrates the mapping relationship between the initial number of physical channels and the power consumption increment, as well as the calibration of the safety red line judgment threshold. A comparison clearly shows that as the number of physical channels increases from 0 to 35, the power consumption increment exhibits an approximately linear growth trend (blue simulated data points). After ridge regression fitting, a red regression line is obtained, the slope of which represents the marginal power consumption increment caused by the activation of a single channel. When the number of physical channels reaches the initial calibration value of 28 (marked by the green dashed line), the corresponding power consumption increment is approximately 120mW (marked by the yellow dashed line). At this point, the calculation from step S12... The obtained surge current value is 120mA. The difference between this value and the current margin value of 150mA estimated by Kalman filtering is calculated. The difference of 30mA just touches the warning boundary of 40mA, which is the safety red line value output by fuzzy logic inference. This result intuitively proves that this solution can accurately predict the transient current carrying capacity of the power supply link before the channel is opened. The three-level recursive evaluation mechanism of "power consumption-current-margin" effectively identifies the risk of voltage drop, and provides a solid quantitative basis and over-limit judgment for triggering the differentiated channel reduction strategy.

[0043] In step S14, for the voltage sag warning information, the initial number of physical channels is reduced to obtain an updated number of physical channels, including: Analyze the voltage drop warning information and extract the channel state matrix corresponding to the initial number of physical channels; Based on the channel state matrix, a channel feature vector is constructed, and the channel feature vector is processed using a random forest algorithm to obtain a feature importance score. If the feature importance score is less than a preset reduction threshold, the initial number of physical channels is reduced to obtain an updated number of physical channels.

[0044] The voltage descent warning information is decoded using a message parsing algorithm to extract the initial number of physical channels allocated in the current power supply network (28 in this embodiment) and the real-time operating parameters of each channel, including on-resistance (mΩ), parasitic inductance (nH), and transient current carrying capacity (mA). These operating parameters are collected in real time by the channel's built-in monitoring circuit with a sampling period of 10μs and aggregated to the main controller via an on-chip sensor network. These parameters are organized into a channel state matrix with dimensions of 28×3, where each row corresponds to a physical channel and each column corresponds to a physical feature. This matrix-based state representation facilitates subsequent multi-dimensional joint analysis and maintains a format consistent with the hardware feature library to support direct index matching.

[0045] Subsequently, channel feature vectors are constructed based on the channel state matrix, and the random forest algorithm is used to process these feature vectors to obtain feature importance scores. The complete processing flow consists of three sequential steps: channel state matrix standardization, PCA dimensionality reduction, and random forest multi-output regression. The first step involves standardizing the 28×3 channel state matrix column-wise (subtracting the mean of each column and dividing by its standard deviation), outputting a standardized channel state matrix, still with a 28×3 dimension. The second step uses globally shared principal component analysis on the standardized 28×3 channel state matrix, meaning all 28 channels share the same set of principal component projection directions, rather than performing PCA independently on each channel. Specifically, the entire 28×3 matrix is ​​used as input, its 3×3 covariance matrix is ​​calculated, and eigenvalue decomposition is performed. The first principal component direction vector corresponding to the largest eigenvalue is then selected. (Shared by all channels), the 3D normalized feature vector of each channel is combined with... Project the inner product onto a 1-dimensional scalar Output 28 channel feature scores, arranged in order of channel number as a 28-dimensional channel feature vector. The rationale for using a globally shared projection direction is that all 28 channels are physically isomorphic (from the same chip hardware design), and the statistical distributions of their 3D physical characteristics (on-resistance, parasitic inductance, and transient current carrying capacity) are homogeneous. Therefore, they should share the same set of principal component directions to ensure that the feature scores of the 28 channels can be compared fairly in the same coordinate system. If PCA is performed independently on each channel, the projection directions of each channel will be different and the dimensions will be incomparable, which will undermine the ability of the subsequent random forest multi-output regressor to fairly rank the 28 channels. In the third step, the 28-dimensional channel feature vector is used as the overall input to the pre-trained random forest multi-output regressor. The regressor simultaneously outputs a 28-dimensional feature importance score vector, where the i-th element is the feature importance score of the i-th channel. The random forest algorithm is an ensemble learning model composed of multiple decision trees. In this embodiment, it includes 100 decision trees, each with a maximum depth of 6. During training, each tree randomly samples samples and features (with replacement), and the feature importance score is finally obtained by averaging the outputs of all trees. The pre-training process of the random forest is as follows: during the chip design verification stage, a large number of sample pairs (channel features, importance labels) are constructed for each physical channel, and the labels are obtained through accelerated aging experiments.

[0046] The specific method involves running the channel under accelerated aging conditions for 1000 hours, and measuring its support capability for the power supply network (i.e., the magnitude of output impedance change) every 100 hours using a precision impedance analyzer. (unit mΩ), then normalized by min-max to Convert to The importance label s of the interval, the conversion rule is as follows ,in and The boundary parameters were determined based on the minimum and maximum impedance changes measured in a 1000-hour accelerated aging test of 28 channels. The corresponding importance label s=0 (best support capability) Corresponding to s=100 (weakest support capability), this linear mapping relationship ensures the reproducibility of physical quantities to dimensionless scores. A training set of no less than 5000 samples is constructed; the model is trained using the RandomForestRegressor from the scikit-learn library, and feature importance is calculated by the reduction in Gini impurity. In this embodiment, the feature importance score for the 5th channel of the model output is 25 (corresponding to...). The feature importance score for channel 12 is 85 (corresponding to...) The first channel received a score of 72 out of 28.

[0047] Finally, if the feature importance score is less than a preset reduction threshold, the initial number of physical channels is reduced to obtain an updated number of physical channels. Specifically, the preset reduction threshold is 60, which is obtained through statistical analysis of the chip's power supply support capability under different loads under laboratory conditions. The specific process involves designing 12 load condition combinations covering the entire operating range of the target chip for testing, including 3 load rates (30%, 60%, 90%) × 2 temperatures (25°C, 85°C) × 2 voltages (0.95V, 1.05V), for a total of 12 condition combinations. Under each condition, channels with different importance scores are shut down (channels with scores below the thresholds of 20, 30, 40, 50, 60, 70, and 80 are shut down sequentially), and the change curve of the power supply network stability is recorded. The maximum score threshold that causes the stability to decrease by no more than 10% is taken as the reduction threshold. The stability index is measured using the standard deviation of the supply voltage; when the standard deviation exceeds 5mV, the stability is considered unsatisfactory. The feature importance score of each channel is iterated through, and channels with scores less than 60 (e.g., channel 5 with a score of 25) are removed, while channels with scores less than 60 are retained (e.g., channel 12 with a score of 85 and channel 1 with a score of 72). The final set of retained channels is the updated physical channel set. In this embodiment, 16 of the 28 initial channels with scores greater than or equal to 60 are removed, 12 channels are retained, and the number of updated physical channels is 12.

[0048] like Figure 3As shown in the figure, the comparison of the surge current and voltage drop response characteristics before and after channel reduction is evident. The comparison clearly shows that before reduction, the initial physical channel count of 28 corresponds to a peak transient current of 64.2 mA (blue curve peak), resulting in a voltage drop of 26.2 mV (red curve peak), approaching the critical boundary of the preset voltage threshold of 30 mV (gray dashed line), posing a significant threat to power supply stability. After the random forest feature importance scoring and threshold reduction process described in step S14, the physical channel count is reduced from 28 to 12, and the updated surge current value drops to below approximately 40 mA. The corresponding voltage drop converges to a safety margin of less than 15 mV, far below the preset voltage threshold of 30 mV. This result intuitively demonstrates that this solution can effectively reduce the current surge that originally threatened the power supply link safety to a controllable range through feature importance-driven channel selective elimination, providing a solid physical foundation and safety guarantee for the subsequent generation of transmission link configuration instructions that balance bandwidth requirements and power consumption constraints.

[0049] In step S15, link impedance data is extracted based on the updated physical channel count, and the surge current value is updated based on the link impedance data to obtain an updated current value. If the difference between the updated current value and the current current margin value is not less than the safety red line value, a transmission link configuration instruction is generated, including: Based on the updated number of physical channels, extract the link impedance data, determine the updated surge current value based on the link impedance data, and obtain the updated current value. Calculate the tolerance difference between the updated current value and the current current margin value; If the tolerance difference is greater than or equal to the safety red line value, then the corresponding routing allocation matrix is ​​extracted; The link activation status is obtained based on the routing allocation matrix, and a transmission link configuration instruction is generated based on the link activation status.

[0050] It should be noted that, based on the updated number of physical channels (12 in this embodiment) and the node topology of the chip's internal power supply network, the parameters of the power supply nodes associated with each channel are polled to read the load capacity of each node (i.e., the maximum current value that the node can carry, in mA). This load capacity is determined and stored in the chip design stage through current density simulation. Subsequently, a graph attention network (GAT) is used to aggregate the load capacity features of the nodes associated with each channel. The GAT contains two graph attention layers, four attention heads in each layer, and a hidden dimension of 32, which can adaptively learn the weights of different nodes on the impedance relationship.

[0051] The pre-training process of the GAT is as follows: the training graph data uses the physical nodes of the chip's power supply network as graph nodes. The node feature vector contains at least three fields: load capacity (in mA), connectivity (i.e., the number of neighboring nodes directly connected to that node), and physical location coordinates (in μm). Training labels (the standard answer for the equivalent impedance between nodes) are extracted using electromagnetic simulation tools through full-wave simulation for each channel configuration. It should be noted that the target chip has a total of 28 physical channels, and the total number of active combinations is... With billions of possible combinations, performing a full-wave electromagnetic simulation using Ansys HFSS for each combination (each simulation taking minutes to hours) is practically impossible in engineering. This embodiment employs a hybrid strategy of stratified sampling and Latin hypercube sampling. Training samples are selected from various combinations using stratified sampling, with 28 strata (k=1, 2, ..., 28) for each activation channel number. Sampling is performed independently within each stratum to ensure a balanced distribution of samples across all channel counts in the training set. Latin hypercube sampling is used: within each stratum (i.e., a fixed k value), all C(28,k) combinations in the 28-dimensional 0 / 1 channel state space are considered as candidate sets for that stratum. The Latin hypercube algorithm generates max(50, C(28,k)) sets of samples (taking the upper bound) on the normalized channel position indices to ensure uniform distribution of samples in the channel position space and avoid clustering. This hybrid strategy ultimately generates at least 10,000 training samples, covering all activation channel count levels and various typical channel position combinations. For each sampled channel configuration, Ansys HFSS is used to perform full-wave electromagnetic simulation of the chip's power supply network, extracting the equivalent impedance values ​​between all node pairs as monitoring labels. The loss function uses mean squared error. ,in Let Z_i be the inter-node impedance predicted by GAT, Z_i be the equivalent impedance label given by full-wave simulation, and M be the number of node pairs; the training sample size is no less than 10,000 sets, and the Adam optimizer is used (learning rate 0.001, batch size 64). The validation set MSE no longer decreases and is less than [value missing] for 20 consecutive rounds. The model parameters are then determined to have converged and solidified.

[0052] The GAT output is link impedance data characterizing the impedance relationship between nodes. For example, it generates an impedance distribution map containing the equivalent impedance values ​​between each node, with values ​​ranging from 45mΩ to 80mΩ. Based on this, the link impedance data and the current power supply network's reference voltage (1.0V) are input into a Kirchhoff network solving algorithm to perform transient current estimation of the power supply network. The Kirchhoff network solving algorithm constructs a system of linear equations based on Kirchhoff's Current Law (KCL) (the algebraic sum of node currents is zero) and Kirchhoff's Voltage Law (KVL) (the algebraic sum of loop voltages is zero). ,in Here is the nodal admittance matrix. Let be the node voltage vector to be determined. Given the current source vector, a sparse matrix solver (such as Cholesky decomposition or conjugate gradient method) is used to solve for the current in each branch, and the updated current value is output. In this embodiment, the updated current value obtained is 90mA.

[0053] Subsequently, the tolerance difference between the updated current value and the current current margin value is calculated. Specifically, an absolute difference statistical algorithm is used to calculate the difference between the updated current value and the current current margin value collected in real time by the underlying sensor to obtain the tolerance difference. The tolerance difference quantifies the current power supply network's carrying capacity margin; the smaller the value, the tighter the margin.

[0054] Subsequently, if the tolerance difference is greater than the preset safety red line value, the corresponding routing allocation matrix is ​​extracted. Specifically, when the tolerance difference is greater than the safety red line value, it indicates that there is still sufficient safety margin between the updated current value and the current margin value. At this time, the trigger condition is met, and the corresponding routing allocation matrix is ​​immediately retrieved from the preset policy library (see below for the retrieval strategy). When the tolerance difference is less than the safety red line value, it indicates that the margin is insufficient. An iterative adjustment strategy is used to dynamically update the reduction threshold. Each time the reduction process is re-executed in S14, the reduction threshold is increased by δ=10 based on the original value (i.e., the threshold is 60 for the first iteration, 70 for the second, and 80 for the third). Simultaneously, a proportional reduction strategy is used as an auxiliary criterion, based on the proportion of the current tolerance difference being lower than the safety red line value. (in For the current tolerance difference, To determine the additional number of channels to be reduced (based on the safety red line value). ( (The number of channels to be reserved at present). Through the above dual adjustment mechanism, the problem of infinite loop caused by repeated execution of S13 with no change in result under a fixed threshold is avoided.

[0055] It should be noted that, in order to prevent the iteration from failing to converge under extreme operating conditions, this embodiment sets the maximum number of iterations to 3 rounds as a fallback termination condition: a maximum of 3 rounds of iteration are executed. If the tolerance difference is still less than the safety red line value after the 3rd round of iteration, the new task access of the target chip is suspended and an overload alarm command is sent to the upper layer of the system. The upper layer of the system then performs task scheduling degradation or load migration to avoid the power supply link being subjected to over-limit impact for a long time.

[0056] For example, in the first iteration, the threshold is increased from 60 to 70, and four channels, including channel 5 (score 25) and channel 18 (score 62), are further eliminated, reducing the number of retained channels from 12 to 8. With 8 channels retained, the Kalman filter re-estimates the current margin value to 200mA, at which point the updated current value is reduced to 160mA, and the tolerance difference is... The value is exactly equal to the safety red line, satisfying the trigger condition. At this point, the corresponding routing matrix is ​​retrieved from the preset strategy library. This strategy library is a lookup table pre-built during the chip design phase. Its index key uses a binary composite index of "number of activated channels N and bitmap of activated channel position B" (B is a 28-bit 0 / 1 bitmap indicating which channels are activated), rather than indexing only by the number of channels N. The basis for using a composite index is that the power supply topology of channels at different locations is different. Even if the number of activated channels is the same, the spatial distribution of channels on the power supply grid is different (for example, for the same 8 channels, the spatial distribution of power supply nodes corresponding to activated channels 1-8 is completely different from that corresponding to activated channels 21-28), resulting in significantly different optimal current allocation weight matrices. If only indexed by the number of channels N, the same matrix would be looked up whenever the number of channels is the same, losing channel position information and causing the current allocation weights to deviate from the optimal solution. Each record in the strategy library corresponds to a specific (N, B) combination, and the optimal current allocation weight matrix under that combination is obtained through offline convex optimization. The objective function is to minimize the maximum voltage drop of the power supply network. .

[0057] in Assign a route to be determined (N is the number of currently active channels). Let the node voltage be a function of the routing weight, the specific relationship of which is derived from Kirchhoff's equations. Then, let the node admittance matrix... (Constructed from link impedance data output by GAT), node voltage vector With known current source vector Substitute into the KCL equation , where the current source vector ( For total current, (As a vector of all 1s), the solution is obtained. That is, the voltage of each node It is a linear function of the routing weight matrix R, therefore (where e_i is a unit vector), after substituting into the objective function, the entire optimization problem becomes a linear convex optimization problem with respect to R, which can be efficiently solved offline using the interior-point method; constraints include total quantity conservation constraints. That is, the sum of the current allocation weights of each channel is 1; capacity constraint That is, the single-channel current does not exceed its rated value; domain constraint That is, the weight values ​​are limited to the range [0,1]. In this embodiment, an 8×8 routing allocation matrix is ​​extracted. The matrix element values ​​are between 0 and 1, representing the current distribution ratio between each physical channel. The diagonal elements represent the self-powered ratio of this channel, and the off-diagonal elements represent the ratio of power borrowed from other channels.

[0058] Finally, the link activation status is obtained according to the routing allocation matrix, and a transmission link configuration instruction is generated based on the link activation status. Specifically, a matrix mapping algorithm is used to parse the non-zero elements in the routing allocation matrix, marking the links corresponding to the non-zero elements as high-level active states and the links corresponding to the zero elements as low-level sleep states, outputting a link activation status sequence. In this embodiment, links 3 and 8 are determined to be in high-level active states, while the remaining links are in low-level sleep states. Subsequently, an instruction encoding algorithm is used to encapsulate the link activation status using a protocol. The encapsulation format follows the hardware control protocol of the target chip, including a frame header (4 bytes, fixed at 0xDEADBEEF), a link activation bitmap (4 bytes, each bit corresponding to one channel, where bits 0 to 27 correspond to 28 physical channels respectively, and bits 28 to 31 are reserved and set to 0), a control field (2 bytes, including synchronization flag and checksum), and a frame trailer (4 bytes, fixed at 0xCAFEBABE). Finally, a transmission link configuration instruction is generated and sent to the underlying hardware controller to execute the physical switching of the links. The transmission link configuration instruction carries both the configuration information of the data transmission link and the scheduling information of the power supply link, thereby achieving synchronous scheduling of the two links. This avoids the risk of sudden voltage drop caused by traditional fragmented scheduling and effectively ensures the power supply stability and data throughput performance of the target chip when high-bandwidth tasks are accessed.

[0059] In summary, this invention discloses a bandwidth and power consumption collaborative optimization method based on HBF high-bandwidth chips, comprising: acquiring and extracting task access requests from a target chip to obtain data throughput and bandwidth margin values; performing feature mapping on the data throughput and bandwidth margin values ​​to obtain an initial number of physical channels; calculating power consumption increment data using the initial number of physical channels; determining the surge current value of the power supply link of the target chip based on the power consumption increment data; acquiring the current margin value and safety red line value of the power supply link; calculating the difference between the surge current value and the current margin value; if the difference is greater than the safety red line value, generating voltage drop warning information based on pre-acquired physical environment parameters; reducing the initial number of physical channels for the voltage drop warning information to obtain an updated number of physical channels; extracting link impedance data based on the updated number of physical channels; updating the surge current value based on the link impedance data to obtain an updated current value; if the difference between the updated current value and the current margin value is not less than the safety red line value, generating a transmission link configuration instruction. This invention achieves a dynamic balance between bandwidth requirements and power consumption impact through power consumption optimization.

[0060] The second embodiment of the present invention provides a bandwidth and power consumption co-optimization system based on an HBF high-bandwidth chip, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the bandwidth and power consumption co-optimization method based on the HBF high-bandwidth chip as described above.

[0061] It should be noted that the bandwidth and power consumption co-optimization system based on HBF high-bandwidth chip provided in this embodiment of the invention is used to execute all the process steps of the bandwidth and power consumption co-optimization method based on HBF high-bandwidth chip in the above embodiment. The working principle and beneficial effect of the two are one-to-one, so they will not be described again.

[0062] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0063] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A bandwidth and power consumption co-optimization method based on HBF high-bandwidth chips, characterized in that, include: The task access request of the target chip is obtained and extracted to obtain the data throughput value and bandwidth margin value. The data throughput value and bandwidth margin value are then feature-mapped to obtain the initial number of physical channels. The power consumption increment data is calculated using the initial number of physical channels, and the surge current value of the target chip's power supply link is determined based on the power consumption increment data. Obtain the current current margin value and safety red line value of the power supply link, calculate the difference between the sudden current value and the current current margin value, and if the difference is greater than the safety red line value, generate a voltage drop warning information based on the pre-obtained physical environment parameters. In response to the voltage drop warning information, the initial number of physical channels is reduced to obtain an updated number of physical channels; The link impedance data is extracted based on the updated physical channel count. The sudden current value is updated based on the link impedance data to obtain the updated current value. If the difference between the updated current value and the current current margin value is not less than the safety red line value, a transmission link configuration instruction is generated.

2. The bandwidth and power consumption co-optimization method based on HBF high-bandwidth chip according to claim 1, characterized in that, The process of acquiring and extracting the task access request from the target chip to obtain data throughput and bandwidth margin values ​​includes: Obtain the task access request of the target chip, and parse the task access request to obtain a request parse tree; Initial throughput data is extracted from the request parse tree to obtain data throughput values, and a task load graph is obtained based on the data throughput values; Initial bandwidth data is extracted from the task load graph. If the initial bandwidth data is greater than a preset threshold, then the bandwidth margin value is determined.

3. The bandwidth and power consumption co-optimization method based on HBF high-bandwidth chip according to claim 1, characterized in that, The step of performing feature mapping on the data throughput value and the bandwidth margin value to obtain the initial number of physical channels includes: The data throughput value and the bandwidth margin value are concatenated in time series to obtain an initial time series feature sequence; Long Short-Term Memory (LSTM) network is used to extract features from the initial temporal feature sequence to obtain the hidden layer state vector; Principal component analysis is performed on the hidden layer state vector to reduce its dimensionality, resulting in a dimensionality-reduced feature matrix. The reduced feature matrix is ​​linearly transformed by a feature mapping network to determine the channel mapping weights. The preset baseline channel values ​​are then weighted and summed according to the channel mapping weights to obtain the initial number of physical channels.

4. The bandwidth and power consumption co-optimization method based on HBF high-bandwidth chip according to claim 1, characterized in that, The power consumption increment data calculated using the initial number of physical channels includes: Construct a channel activation state matrix based on the initial number of physical channels; The target toggle rate sequence and static leakage current sequence are obtained by matching the channel activation state matrix, and the target toggle rate sequence and the static leakage current sequence are concatenated to obtain the basic power consumption feature vector. Based on the aforementioned basic power consumption feature vector, ridge regression is used to calculate the power consumption increment data of the target chip when the corresponding channel is turned on.

5. The bandwidth and power consumption co-optimization method based on HBF high-bandwidth chip according to claim 1, characterized in that, Determining the surge current value of the target chip's power supply link based on the power consumption increment data includes: The first voltage drop amplitude is obtained based on the initial dynamic current sequence corresponding to the power consumption increment data; The first voltage drop amplitude is filtered to obtain the second voltage drop amplitude. If the second voltage drop amplitude is greater than a preset voltage threshold, the node voltage distribution is determined. Peak current characteristics are extracted from the node voltage distribution, and the surge current value faced by the power supply link of the target chip is determined based on the peak current characteristics.

6. The bandwidth and power consumption co-optimization method based on HBF high-bandwidth chip according to claim 1, characterized in that, The process involves acquiring the current current margin and safety threshold of the power supply link, calculating the difference between the sudden current surge and the current current margin, and if the difference is greater than the safety threshold, generating a voltage drop warning based on pre-acquired physical environment parameters, including: Based on the sudden current value and load power consumption status, the Kalman filter algorithm is used to estimate the transient current throughput capability of the power supply link and obtain the current current margin value of the power supply link. Based on the current current margin value, a fuzzy logic reasoning algorithm is used to quantify and evaluate the disturbance immunity margin of the power supply link to obtain the safety red line value. Calculate the difference between the sudden current value and the current current margin value. If the difference is greater than the safety red line value, generate an over-limit trigger flag. Based on the over-limit triggering identifier and the physical environment parameters of the target chip, a decision tree classification algorithm is used to classify the risk level and generate voltage drop warning information.

7. The bandwidth and power consumption co-optimization method based on HBF high-bandwidth chip according to claim 1, characterized in that, The process of reducing the initial number of physical channels to obtain an updated number of physical channels in response to the voltage drop warning information includes: Analyze the voltage drop warning information and extract the channel state matrix corresponding to the initial number of physical channels; Based on the channel state matrix, a channel feature vector is constructed, and the channel feature vector is processed using a random forest algorithm to obtain a feature importance score. If the feature importance score is less than a preset reduction threshold, the initial number of physical channels is reduced to obtain an updated number of physical channels.

8. The bandwidth and power consumption co-optimization method based on HBF high-bandwidth chip according to claim 1, characterized in that, The process involves extracting link impedance data based on the updated physical channel count, updating the surge current value based on the link impedance data to obtain an updated current value, and generating a transmission link configuration instruction if the difference between the updated current value and the current current margin value is not less than the safety red line value. This instruction includes: Based on the updated number of physical channels, extract the link impedance data, determine the updated surge current value based on the link impedance data, and obtain the updated current value. Calculate the tolerance difference between the updated current value and the current current margin value; If the tolerance difference is greater than or equal to the safety red line value, then the corresponding routing allocation matrix is ​​extracted; The link activation status is obtained based on the routing allocation matrix, and a transmission link configuration instruction is generated based on the link activation status.

9. A bandwidth and power consumption co-optimization system based on an HBF high-bandwidth chip, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the bandwidth and power consumption co-optimization method based on the HBF high-bandwidth chip as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the bandwidth and power consumption co-optimization method based on the HBF high-bandwidth chip as described in any one of claims 1 to 8.

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