Circuit board processing method and computing power circuit board

Abstract

The application provides a circuit board processing method and a computing power circuit board. The method comprises the following steps: S1, designing a stack structure of a multilayer circuit board, the stack structure comprising a copper-clad core plate layer, a dielectric layer, and a semi-cured layer for interlayer adhesion, the dielectric layer comprising a hollow core plate and semi-cured sheets located on the upper and lower sides of the hollow core plate; S2, obtaining a copper-clad core plate with completed circuit production; S3, pre-treating the copper-clad core plate used for forming the dielectric layer to remove the copper layers on the opposite sides of the copper-clad core plate, thereby obtaining a hollow core plate; S4, measuring the thickness of the hollow core plate, and adjusting the specifications of the semi-cured sheets located on the upper and lower sides of the hollow core plate according to the measured data, so that the total thickness of the hollow core plate and the two semi-cured sheets is equal to the designed thickness of the dielectric layer; and S5, stacking the plates according to the stack structure, and performing compression treatment on the stack body formed after the stacking. The processing method can significantly improve the uniformity of the dielectric thickness of the inner layer of the circuit board, reduce the impedance tolerance, and effectively adapt to the transmission requirements of high-speed signals.

Description

Technical Field

[0001] This invention relates to the field of PCB manufacturing technology, and more specifically, to a circuit board processing method and a computing circuit board. Background Technology

[0002] With the rapid iteration of the artificial intelligence computing power industry, AI server motherboards need to support high-bandwidth interconnect signals between PCIe Gen6, DDR5, and AI chips, with signal transmission rates reaching a high level of 64Gbps and above. Characteristic impedance is a core parameter for high-speed signal transmission, and its consistency directly determines signal integrity, transmission bandwidth, and system operational stability. The higher the signal rate, the more stringent the requirements for impedance tolerance. The traditional ±10% impedance control accuracy is no longer suitable for the performance requirements of high-end AI computing power boards, and the uniformity of the inner dielectric layer thickness is a core factor determining the accuracy of the inner characteristic impedance.

[0003] AI computing boards typically have a thick dielectric layer in the middle. Currently, the industry commonly uses a method of stacking and laminating multiple prepreg (PP) sheets to form this thick dielectric layer, with a total thickness exceeding 40 mil. The aforementioned existing technology has the following significant technical drawbacks: The method of stacking multiple PP sheets to form a thick dielectric layer requires the resin of the prepreg to undergo the entire process of melting, flowing, filling and curing during the lamination process. The resin flow path of the thick dielectric layer is long, and the amount of resin flow is significantly affected by pressure distribution, copper surface undulations and resin content fluctuations. This can easily lead to uneven thickness and excessive thickness deviation in the final thick dielectric layer. Due to this limitation, the thickness tolerance of the inner thick dielectric layer under traditional processes can usually only be controlled at the ±10% level, and the corresponding impedance tolerance is difficult to exceed ±10%. For high-speed signals of 64Gbps and above, this level of impedance deviation will cause problems such as signal reflection, deterioration of return loss, and eye diagram closure, directly resulting in a decrease in the bandwidth of the AI ​​computing board and an increase in the transmission bit error rate, which can seriously affect the stable operation of the system.

[0004] In summary, the existing technology for controlling the thickness of the inner dielectric layer of AI computing boards has insufficient precision and cannot meet the high-precision impedance control requirements of next-generation high-speed interconnect signals. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a circuit board processing method and a computing circuit board to solve the technical problems existing in the background art.

[0006] The objective of this invention is achieved through the following technical solution: In a first aspect, the present invention provides a method for processing a circuit board, the method comprising the following steps: S1: Design a multilayer circuit board stack structure, the stack structure including a copper clad laminate layer, a dielectric layer, and a prepreg layer for interlayer bonding, the dielectric layer including a hollow core board and prepreg sheets located on the upper and lower sides of the hollow core board. S2: Obtain the copper-clad core board with completed circuit fabrication; S3: Pre-process the copper-clad laminate used to form the dielectric layer to remove the copper layers on both sides of the copper-clad laminate to obtain the hollow core board; S4: Measure the thickness of the hollow core board, and adjust the specifications of the prepregs located on the upper and lower sides of the hollow core board according to the measured data, so that the total thickness of the hollow core board and the two prepregs is equal to the design thickness of the dielectric layer. S5: Stack the plates according to the aforementioned stacking structure, and then press the resulting stacked body.

[0007] In the above scheme, in step S1, the circuit board stack structure is designed according to actual needs. The stack structure includes at least a copper-clad laminate layer, a dielectric layer, and a prepreg layer. The copper-clad laminate layer is a double-sided copper-clad laminate. The prepreg layer consists of prepreg sheets for bonding. The dielectric layer consists of a hollow core board and prepreg sheets located on the upper and lower sides of the hollow core board. The prepreg sheets on the upper and lower sides are used to bond with the surface copper layer of the adjacent copper-clad laminate layer. In step S2, the copper-clad laminate, i.e., the double-sided copper-clad laminate, is the basic unit for forming a multilayer circuit board. An appropriate number of copper-clad laminates are selected according to the number of layers in the designed circuit board stack structure. Step S3 is used to perform double-sided copper removal treatment on the copper-clad laminate constituting the dielectric layer to obtain a hollow core board with a pure dielectric structure. This can eliminate the thickness tolerance of the copper layer itself and avoid the copper thickness deviation from being superimposed on the dielectric. In terms of the total thickness tolerance of the dielectric layer, on the other hand, it can make the upper and lower surfaces of the hollow core board flat insulating dielectric surfaces. During lamination, the resin of the prepreg only fills the circuit area on one side (single-sided filling). The resin flow path is short and the filling is uniform, which further reduces the thickness deviation of the prepreg after curing. In step S4, by first measuring the actual thickness of the hollow core board and then adjusting the specifications of the prepreg accordingly, the thickness deviation of the incoming material of the hollow core board can be actively offset, so that the total thickness of the hollow core board and the upper and lower prepregs accurately matches the theoretical design thickness of the dielectric layer. This solves the pain point that the traditional fixed stacking process cannot correct the material deviation of the board and the large deviation of the median thickness of the finished product. In step S5, after the stacking is completed according to the designed stacking structure, the lamination process is carried out to allow the prepreg between the layers to flow and fill fully and to cure completely, finally forming a complete circuit board.

[0008] Optionally, in one embodiment, in S4, the thickness of the hollow core plate is measured, specifically including: measuring the thickness range and the average thickness of the hollow core plate.

[0009] In the above scheme, the thickness range is used to reflect the in-plane thickness uniformity of the hollow core board itself, which serves as a quantitative indicator for judging the quality of incoming materials and helps to screen out hollow core boards that meet the requirements for thickness uniformity; the average thickness avoids the interference of the randomness of single-point measurement and the local thickness deviation of the board surface, making the specification adjustment of the prepreg more in line with the true overall thickness of the hollow core board.

[0010] Optionally, in one embodiment, in step S4, after measuring the thickness of the hollow core board, the method further includes: comparing the thickness range and average thickness of the hollow core board with a preset acceptable range, and selecting the hollow core boards whose thickness range and average thickness are within the acceptable range to proceed to the next process.

[0011] In the above scheme, by using the two core parameters of thickness range and thickness average, the hidden defects caused by one indicator being qualified while the other exceeds the standard can be avoided, thus providing a consistent and stable processing substrate for subsequent pressing processes.

[0012] Optionally, in one embodiment, the acceptable range of the thickness difference of the hollow core plate is ±0.2 mil; the preset value of the average thickness of the hollow core plate is a, and the acceptable range of the average thickness of the hollow core plate is a±1.0 mil.

[0013] Optionally, in one embodiment, the copper layers on opposite sides of the hollow core board include process edges and in-board regions, with the process edges distributed around the in-board regions.

[0014] In the above scheme, process structures such as pressing alignment targets, positioning hole references, and optical identification marks can be made on the process edge to serve as a reference for processing positioning and interlayer alignment, so as to ensure the interlayer alignment accuracy in the stacking and pressing processes.

[0015] Optionally, in one embodiment, in S3, the copper-clad laminate used to form the dielectric layer is pre-processed, specifically including: etching the copper-clad laminate to remove the copper layer on both sides of the copper-clad laminate located in the area inside the board, while retaining the copper layer on the process edge.

[0016] In the above solution, the copper layer on the copper-clad laminate is removed by etching. During etching, only the copper layer in the inner area of ​​the board is removed, while the copper layer on the process edge is retained to avoid affecting the alignment during subsequent stacking and lamination.

[0017] Optionally, in one embodiment, in S1, the stacked structure further includes a top copper layer and a bottom copper layer, the top copper layer and the bottom copper layer being located at the top and bottom of the stacked structure, respectively.

[0018] In the above scheme, the top copper layer and the bottom copper layer are the surface conductive layers of the circuit board, used to make surface traces, component pads, positioning mounting holes and external connector pads, etc., which is the basic structure for multilayer circuit boards to have complete application functions.

[0019] Optionally, in one embodiment, after S5, the rough circuit board obtained after lamination is further subjected to electroplating to form electroplated layers on opposite sides of the rough circuit board.

[0020] In the above scheme, an electrical conduction between the top, bottom and inner signal layers is achieved by electroplating a conductive layer inside the holes of the circuit board. This provides a conductive path for the outgoing high-speed signals of the inner layer and the interconnection of components. At the same time, the uniform copper layer formed by electroplating is the processing benchmark for the subsequent etching of the outer circuit pattern and is a necessary process for the multilayer circuit board to have complete electrical functions.

[0021] Secondly, the present invention provides a computing power circuit board, which is manufactured using the aforementioned processing method. The computing power circuit board includes a hollow core board, a plurality of core boards, and a prepreg for interlayer bonding. The hollow core board is located at the center of the computing power circuit board along the thickness direction, and the computing power circuit board has a symmetrical structure about the hollow core board.

[0022] In the above scheme, the copper layers on both sides of the hollow core board are removed by etching, and the hollow core board and the prepreg sheets on the upper and lower sides together form the aforementioned dielectric layer.

[0023] Optionally, in one embodiment, the computing power circuit board further includes a top copper layer and a bottom copper layer, the top copper layer and the bottom copper layer being located at the top and bottom of the computing power circuit board along the thickness direction, respectively, and the surface of the top copper layer and the bottom copper layer away from the hollow board layer having an electroplated layer formed by electroplating.

[0024] In the above scheme, the top and bottom copper layers are the surface conductive layers of the circuit board, used to create surface traces, component pads, positioning mounting holes, and external connector pads, forming the basic structure for the multilayer circuit board to have complete application functions. Electroplating layers are attached to the surfaces of the top and bottom copper layers, as well as the hole walls on the computing circuit board, to achieve electrical conductivity between the top, bottom, and inner signal layers, providing conductive paths for the external output of high-speed signals from the inner layers and for component interconnection.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows: The circuit board processing method of this invention replaces the traditional method of stacking multiple prepregs to form a thick dielectric by decomposing the dielectric layer into a three-layer combination structure of a hollow core board and prepregs on the upper and lower sides. Using a prefabricated hollow core board as the main thickness component of the dielectric layer effectively utilizes the high-precision thickness characteristics of the manufactured core board, reducing thickness fluctuations at the structural source. Furthermore, the prepregs on the upper and lower sides only perform interlayer bonding, resulting in thinner layers and controllable resin flow, significantly reducing tolerance accumulation during lamination. Simultaneously, the dynamic compensation mechanism of the prepregs in S4 offsets the thickness fluctuations of conventional incoming materials, keeping the total thickness deviation rate of the final inner dielectric layer extremely low. This solves the core technical problem of large impedance fluctuations caused by excessive deviations after lamination of thick dielectrics in traditional processes, making it unsuitable for high-speed signal transmission. In addition, because the hollow core board has no copper on both sides and a flat surface, the resin flow of the prepregs is not affected by copper surface undulations, resulting in a small in-plane thickness difference in the dielectric layer after lamination, high overall board impedance consistency, and avoiding signal integrity problems caused by local impedance fluctuations.

[0026] The circuit board manufactured by the processing method of the present invention has a uniform and stable dielectric layer thickness, can stably achieve an impedance tolerance within ±5%, has high impedance consistency, effectively reduces reflection loss and return loss of high-speed signals, ensures stable transmission of high-bandwidth interconnect signals such as AI chips, PCIe, and DDR, and improves the operational stability and bandwidth utilization of the circuit board. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a flowchart illustrating Embodiment 1 of the present invention.

[0029] Figure 2 This is a stacked diagram of the computing circuit board according to Embodiment 2 of the present invention. Detailed Implementation

[0030] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein.

[0031] The technical solutions in this application will now be described with reference to the accompanying drawings. Example 1 Please refer to Figure 1This embodiment 1 provides a circuit board processing method, which includes the following steps:

[0032] S1: Design the stack-up structure of a multilayer circuit board, which includes a copper-clad laminate layer, a dielectric layer, and a prepreg layer for interlayer bonding. The dielectric layer includes a hollow core board and prepreg sheets located on the upper and lower sides of the hollow core board. S2: Obtain the copper-clad core board with completed circuit fabrication; S3: Pre-process the copper-clad laminate used to form the dielectric layer to remove the copper layers on both sides of the copper-clad laminate to obtain a hollow core board. S4: Measure the thickness of the hollow core board and adjust the specifications of the prepregs located on the upper and lower sides of the hollow core board according to the measured data so that the total thickness of the hollow core board and the two prepregs is equal to the design thickness of the dielectric layer. S5: Stack the plates according to the stacking structure, and then press the resulting stacked structure.

[0033] Specifically, in step S1, the circuit board stack-up is designed according to actual needs. The stack-up includes at least a copper-clad laminate layer, a dielectric layer, and a prepreg layer. The copper-clad laminate layer is a double-sided copper-clad laminate. The prepreg layer consists of prepreg sheets for bonding. The dielectric layer consists of a hollow core board and prepreg sheets located on the upper and lower sides of the hollow core board. The prepreg sheets on the upper and lower sides are used to bond to the surface copper layer of the adjacent copper-clad laminate layer. In step S2, the copper-clad laminate, i.e., the double-sided copper-clad laminate (Core), is the basic unit for forming a multilayer circuit board. An appropriate number of copper-clad laminates are selected according to the number of layers in the designed circuit board stack-up. Step S3 is used to perform double-sided copper removal processing on the copper-clad laminate constituting the dielectric layer to obtain a hollow core board with a pure dielectric structure. This can eliminate the thickness tolerance of the copper layer itself and avoid the superposition of copper thickness deviations. To ensure the total thickness tolerance of the dielectric layer, on the other hand, the upper and lower surfaces of the hollow core board are flat insulating dielectric surfaces. During lamination, the resin of the prepreg only fills the circuit area on one side (single-sided filling). The resin flow path is short and the filling is uniform, further compressing the thickness deviation of the prepreg after curing. In step S4, by first measuring the actual thickness of the hollow core board and then adjusting the specifications of the prepreg accordingly, the thickness deviation of the incoming material of the hollow core board can be actively offset, so that the total thickness of the hollow core board and the upper and lower prepregs accurately matches the theoretical design thickness of the dielectric layer. This solves the pain point that the traditional fixed stacking process cannot correct the material deviation of the board and the large deviation of the median thickness of the finished product. In step S5, after the stacking is completed according to the designed stacking structure, the lamination process is carried out to allow the prepreg between the layers to flow and fill fully and cure completely, finally forming a complete circuit board.

[0034] The circuit board processing method of this invention replaces the traditional method of stacking multiple prepregs to form a thick dielectric by decomposing the dielectric layer into a three-layer combination structure of a hollow core board and prepregs on the upper and lower sides. Using a prefabricated hollow core board as the main body for dielectric layer thickness, it can effectively utilize the high-precision thickness characteristics of the core board from the factory, reducing thickness fluctuations from the structural source. Moreover, the prepregs on the upper and lower sides only perform the interlayer bonding function, with thin thickness and controllable resin flow, which can significantly reduce the accumulation of tolerances during lamination. At the same time, in conjunction with the dynamic compensation mechanism of the prepreg in S4, it can offset the thickness fluctuations of conventional incoming materials, and control the total thickness deviation rate of the final inner dielectric layer to an extremely low level. This solves the core technical problem of large impedance fluctuations caused by excessive deviations after lamination of thick dielectrics in traditional processes, which cannot adapt to high-speed signal transmission. In addition, since the hollow core board has no copper on both sides and a flat surface, the resin of the prepreg is not affected by the undulations of the copper surface lines during flow. After lamination, the in-plane thickness difference of the dielectric layer is small, the impedance consistency of the whole board is high, and the signal integrity problem caused by local impedance fluctuations is avoided. The circuit board obtained by this processing method has a uniform and stable dielectric layer thickness, can stably achieve an impedance tolerance within ±5%, has high impedance consistency, effectively reduces reflection loss and return loss of high-speed signals of 64Gbps and above, ensures stable transmission of high-bandwidth interconnect signals such as AI chips, PCIe, and DDR, and improves the operational stability and bandwidth utilization of the circuit board.

[0035] Understandably, since the copper layer on the surface of a hollow core board needs to be removed during its fabrication, the copper layer of the copper-clad laminate used to make the hollow core board has no wiring design.

[0036] For example, refer to Figure 2 The diagram illustrates a symmetrically stacked circuit board structure, comprising two copper-clad laminates (CCLs) and one hollow core board. The two CCLs are symmetrically positioned on the upper and lower sides of the hollow core board. The hollow core board serves as the middle layer of the circuit board, namely layers L4-L5, while the CCLs are layers L2-L3 and L6-L7. The hollow core board is connected to the CCLs via prepreg sheets positioned on its upper and lower sides.

[0037] It should be noted that L1, L2, L3...L8 correspond to the copper layers inside the circuit board. The copper layers on both sides of the hollow board in the figure are only for demonstration purposes and have actually been removed in step S4.

[0038] In S4, the thickness of the hollow core board is measured, specifically including: measuring the thickness range and the average thickness of the hollow core board.

[0039] The thickness range is the difference between the maximum and minimum thickness values ​​within the surface of a single hollow core board, while the average thickness is the arithmetic mean obtained by uniformly sampling multiple points on the surface of a single hollow core board. The thickness range reflects the in-plane thickness uniformity of the hollow core board itself, serving as a quantitative indicator for judging incoming material quality and helping to screen out hollow core boards that meet the thickness uniformity requirements. The average thickness avoids the randomness of single-point measurements and the interference of local thickness deviations on the board surface, making the specification adjustment of the prepreg more closely match the true overall thickness of the hollow core board. This allows the median deviation between the total thickness of the dielectric layer and the theoretical design value to be controlled within a smaller range, further enhancing the high-precision dielectric thickness control effect.

[0040] Furthermore, in S4, after measuring the thickness of the hollow core board, the following steps are also included: comparing the thickness range and average thickness of the hollow core board with a preset acceptable range, and selecting hollow core boards whose thickness range and average thickness are within the acceptable range to proceed to the next process.

[0041] After measuring the thickness range and average thickness of the hollow core board, the two data points are compared with preset values ​​to select hollow core boards with suitable thickness uniformity and average thickness, providing a stable basis for subsequent adjustments to the prepreg specifications. The use of these two core parameters, thickness range and average thickness, avoids hidden defects caused by one indicator being acceptable while the other exceeds the limit, ensuring a consistent and stable substrate for subsequent lamination processes.

[0042] For example, the acceptable range for the thickness variation of the hollow core board is ±0.2 mil; if the preset value for the average thickness of the hollow core board is 'a', then the acceptable range for the average thickness of the hollow core board is 'a' ± 1.0 mil. The specific value of 'a' is determined based on the design thickness of the hollow core board. In some embodiments, 'a' = 31.5 mil, in which case the acceptable range for the average thickness of the hollow core board is 30.5-32.5 mil.

[0043] In this embodiment, the copper layers on opposite sides of the hollow core board include process edges and in-board regions, with the process edges distributed around the in-board regions. In S3, the copper-clad laminate used to form the dielectric layer is pre-processed, specifically including: etching the copper-clad laminate to remove the copper layers on both sides of the copper-clad laminate located in the in-board regions, while retaining the copper layers on the process edges.

[0044] Process edges can be fabricated with lamination alignment targets, positioning hole references, optical identification marks, and other process structures to serve as support for processing positioning and interlayer alignment references, ensuring interlayer alignment accuracy during stacking and lamination processes. During etching, only the copper layer in the inner area of ​​the board is removed, leaving the copper layer on the process edges to avoid affecting subsequent stacking and lamination alignment.

[0045] It should be understood that the finished circuit board does not include the process edge portion. After the circuit board is formed, the process edge portion is removed by cutting.

[0046] In S1, the stacked structure also includes a top copper layer and a bottom copper layer, which are located at the top and bottom of the stack, respectively, and are both bonded to the adjacent copper-clad laminate via prepreg. The top and bottom copper layers are the surface conductive layers of the circuit board, used to create surface traces, component pads, positioning mounting holes, and external connector pads, etc., and are the basic structure that enables the multilayer circuit board to have complete application functions.

[0047] Following S5, the process also includes electroplating the rough circuit board obtained after lamination to form electroplated layers on both sides of the rough circuit board. By depositing conductive layers in the holes of the circuit board through electroplating, electrical conduction between the top, bottom, and inner signal layers is achieved, providing conductive paths for the outward lead-out of high-speed signals from the inner layers and the interconnection of components. At the same time, the uniform copper layer formed by electroplating serves as the processing benchmark for subsequent etching of outer layer circuit patterns, and is a necessary process for the multilayer circuit board to have complete electrical functions. Example 2

[0048] Please refer to Figure 2 This embodiment provides a stacked structure of a computing power circuit board, which is manufactured using the circuit board processing method of Embodiment 1. The computing power circuit board includes a hollow core board, a core board, and a prepreg for interlayer bonding. The hollow core board is located at the center of the computing power circuit board along the thickness direction, and the computing power circuit board has a symmetrical structure about the hollow core board.

[0049] like Figure 2 As shown, the computing circuit board mainly consists of a copper layer 1, a substrate 2, and a prepreg 3. The core board is a double-sided copper-clad laminate, which consists of a substrate and copper layers (copper foil) covering both sides of the substrate.

[0050] Specifically, the hollow core board corresponds to layers L4-L5 in the diagram. Two core boards are used, corresponding to layers L2-L3 and L6-L7 respectively, and are symmetrical about the hollow core board. The copper layers on both sides of the hollow core board are removed by etching. Figure 2 The example shown here is only for demonstration purposes; the actual copper layers of L4 and L5 have been removed by etching. The hollow core board and the prepregs on the top and bottom sides together form the dielectric layer of the computing circuit board.

[0051] Preferably, in this embodiment, the hollow core board is designed to have a thickness of 31.5 mil, and the prepregs on the top and bottom sides are both 5.1 mil thick, meaning that the theoretical design thickness of the dielectric layer of this computing power circuit board is 41.7 mil.

[0052] Preferably, the core board has a thickness of 6.4 mil.

[0053] In this embodiment, the computing power circuit board also includes a top copper layer and a bottom copper layer. The top copper layer and the bottom copper layer are located at the top and bottom of the computing power circuit board along the thickness direction, respectively. An electroplated layer 4 is formed on the side of the top copper layer and the bottom copper layer away from the hollow board layer by electroplating.

[0054] Specifically, the top copper layer is L1, and the bottom copper layer is L2. The top and bottom copper layers are the surface conductive layers of the circuit board, used to create surface traces, component pads, mounting holes, and external connector pads, forming the basic structure for the complete application functionality of a multilayer circuit board. Electroplated layer 4 is attached to the surfaces of the top and bottom copper layers, as well as the walls of the holes on the computing circuit board, to achieve electrical conductivity between the top, bottom, and inner signal layers, providing conductive paths for the external output of high-speed signals from the inner layers and for component interconnection.

[0055] In this embodiment, the outer surface of the electroplated layer is coated with solder resist ink 5. Solder resist ink 5 is used to prevent molten solder from accidentally flowing onto adjacent lines or pads that should not be soldered during soldering, thus avoiding short circuits. At the same time, it also provides physical and chemical protection for the computing circuit board.

[0056] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0057] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0058] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referred to each other.

[0059] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for processing a circuit board, characterized in that, The method includes the following steps: S1: Design a multilayer circuit board stack structure, the stack structure including a copper clad laminate layer, a dielectric layer, and a prepreg layer for interlayer bonding, the dielectric layer including a hollow core board and prepreg sheets located on the upper and lower sides of the hollow core board. S2: Obtain the copper-clad core board with completed circuit fabrication; S3: Pre-process the copper-clad laminate used to form the dielectric layer to remove the copper layers on both sides of the copper-clad laminate to obtain the hollow core board; S4: Measure the thickness of the hollow core board, and adjust the specifications of the prepregs located on the upper and lower sides of the hollow core board according to the measured data, so that the total thickness of the hollow core board and the two prepregs is equal to the design thickness of the dielectric layer. S5: Stack the plates according to the aforementioned stacking structure, and then press the resulting stacked body.

2. The circuit board processing method according to claim 1, characterized in that, In S4, the thickness of the hollow core plate is measured, specifically including: measuring the thickness range and the average thickness of the hollow core plate.

3. The circuit board processing method according to claim 2, characterized in that, In step S4, after measuring the thickness of the hollow core plate, the following is also included: The thickness range and average thickness of the hollow core board are compared with a preset acceptable range, and the hollow core boards with thickness range and average thickness within the acceptable range are selected to proceed to the next process.

4. The circuit board processing method according to claim 3, characterized in that, The acceptable range for the thickness variation of the hollow core board is ±0.2 mil; The preset value of the average thickness of the hollow core plate is a, and the acceptable range of the average thickness of the hollow core plate is a ± 1.0 mil.

5. The circuit board processing method according to claim 1, characterized in that, The copper layers on opposite sides of the hollow core board include a process edge and an inner region, with the process edge distributed around the inner region.

6. The circuit board processing method according to claim 5, characterized in that, In S3, the copper-clad laminate used to form the dielectric layer is pre-processed, specifically including: etching the copper-clad laminate to remove the copper layer on both sides of the copper-clad laminate located in the area inside the board, while retaining the copper layer on the process edge.

7. The circuit board processing method according to claim 1, characterized in that, In S1, the stacked structure further includes a top copper layer and a bottom copper layer, which are located at the top and bottom of the stacked structure, respectively.

8. The circuit board processing method according to claim 1, characterized in that, Following S5, the process also includes electroplating the rough circuit board obtained after lamination to form an electroplated layer on both opposite sides of the rough circuit board.

9. A computing power circuit board, characterized in that, The computing power circuit board is manufactured using the processing method described in any one of claims 1 to 7. The computing power circuit board includes a hollow core board, a plurality of core boards, and a prepreg for interlayer bonding. The hollow core plate is located at the center of the computing power circuit board along the thickness direction, and the computing power circuit board has a symmetrical structure about the hollow core plate.

10. The computing power circuit board according to claim 9, characterized in that, The computing power circuit board also includes a top copper layer and a bottom copper layer, which are located at the top and bottom of the computing power circuit board along the thickness direction, respectively. The surface of the top copper layer and the bottom copper layer away from the hollow board layer is electroplated.

Images