A gallium nitride monolithic integrated chip based on high-resistance silicon substrate and a preparation method thereof

Abstract

The application discloses a gallium nitride monolithic integrated chip based on a high-resistance silicon substrate and a preparation method thereof, and belongs to the technical field of semiconductors. The application realizes low-voltage logic control devices, radio frequency amplifier devices, acoustic resonator devices and on-chip passive networks by partitioning on the same p-GaN / AlGaN / GaN epitaxial wafer, avoids extra parasitic parameters and packaging losses caused by multi-chip heterogeneous packaging, and has the advantages of high integration, short interconnection path and small system volume. Higher integration is conducive to further miniaturization and performance upgrading of a radio frequency front-end system. The application adopts a unified heterojunction epitaxial platform as a common material basis of all functional devices, compared with a scheme of multi-process platform chip preparation and system-level packaging, eliminates the risk of thermal mismatch between different chips and packaging interface loss, and can significantly improve the overall operation stability and long-term reliability of the system.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate and its fabrication method. Background Technology

[0002] With the rapid development of 5G / 6G communications, millimeter-wave radar, satellite communications, and high-temperature, high-power electronic systems, the requirements for high frequency, high power, high integration, and high reliability in chip systems are continuously increasing. Gallium nitride (GaN), due to its wide bandgap, high breakdown field strength, high electron mobility, and excellent piezoelectric properties, is more suitable for manufacturing RF power devices and acoustic piezoelectric devices compared to silicon-based materials. High electron mobility transistors (HEMTs) based on AlGaN / GaN heterojunctions have significant advantages in high-frequency, high-power scenarios due to their high-mobility two-dimensional electron gas (2DEG) channels and excellent piezoelectric effect. However, to achieve complete RF front-end functions including logic control, RF amplification, acoustic frequency selection, and passive matching, multi-chip packaging and heterogeneous platform interconnects are required, which significantly reduces cost-effectiveness and system performance. On the other hand, monolithic multi-functional integration is more competitive in improving system integration and performance because all functional devices share the same substrate and interconnect system, eliminating additional package-level interconnect losses and area occupation, and making thermal management and system reliability easier to control. Typically, different functional devices are fabricated on the same wafer by using uniform epitaxial growth and zoned process adjustments. However, the optimal process windows for different devices vary significantly, which can easily lead to performance constraints and process interference when multiple devices are co-integrated. Furthermore, special processes such as back-side release and low-resistivity ohmic contacts for acoustic devices can further limit overall process compatibility and the upper limit of device performance.

[0003] In 2021, Zheng et al. from the Hong Kong University of Science and Technology demonstrated GaN complementary logic integrated circuits based on a commercial p-GaN / AlGaN / GaN-on-Si platform. They implemented enhancement-mode and depletion-mode devices using p-GaN gate and grooved gate structures respectively, demonstrating low quiescent power consumption and fast switching speeds. However, these reported single-function logic devices also exhibited functional limitations, unable to directly support the implementation of a complete RF front-end on a single chip. Subsequent researchers pointed out that existing GaN integration schemes are mostly centered around single device modules, lacking multi-functional system-level end-to-end process design. Although GaN acoustic devices can be realized using the same material platform, the fabrication process conflicts with active devices in several places, making efficient co-integration with logic and RF devices difficult.

[0004] The shortcomings of the existing technical solutions are as follows: Existing technology 1: Zheng, Y. et al., 2021, Gallium nitride-based complementary logic integrated circuits. This discloses... Figure 1 The low-voltage GaN logic device structure shown is illustrated.

[0005] Tsai, C.-L. et al., 2017, Smart GaN Platform: Performance & Challenges. This paper discloses... Figure 2 The E / D-mode integrated circuit shown.

[0006] Based on commercial p-GaN / AlGaN / GaN-on-Si epitaxial platforms, enhancement-mode and depletion-mode GaN HEMTs were fabricated on the same wafer using threshold-controlled processes. Among these, Zheng et al.'s approach implemented a complementary logic architecture based on p-GaN gate structures, validating multi-level logic units such as inverters, NAND gates, transmission gates, latches, and ring oscillators. Tsai et al.'s SmartGaN platform integrated peripheral modules such as low-voltage E / D HEMTs, 2DEG resistors, MIM capacitors, and drive protection circuits, validating the local integration capabilities of single-chip logic and passive devices.

[0007] The shortcomings of the existing technology are: (1) It only realizes the single-chip integration of a single low-voltage logic function, without including radio frequency devices, acoustic resonant devices and on-chip passive networks, and cannot support the single-chip implementation of a complete radio frequency front-end system. (2) The process design only optimizes the performance of logic devices, without considering the process window compatibility and partitioning isolation of multiple types of functional devices, and cannot be directly extended into a multi-functional single-chip integration solution.

[0008] Existing technology 2: Cheng, K. et al., 2023, RF Enhancement-Mode p-GaN Gate HEMT on 200-mm High-Resistivity Si, discloses as follows Figure 3 The radio frequency GaN HEMT shown.

[0009] Then, HW et al., 2023, Enhancement-Mode 300-mm GaN-on-Si(111) WithIntegrated Si CMOS for Future mm-Wave RF Applications. Disclosed as Figure 4The GaN microwave monolithic integrated circuit (GaN MMIC) is shown; (a) is a TEM image of the E-mode GaN MOSHEMT, and (b) is a TEM image of the copper interconnect layer. The 200mm high-resistivity silicon platform adopts a p-GaN gate structure and a carbon-doped buffer layer to reduce substrate RF loss and improve device isolation performance; the 300mm Si(111) platform adopts a grooved gate + high-k gate dielectric MOSHEMT structure, and achieves a gate length of 90nm by relying on DUV lithography and ALE etching processes, verifying the performance of the 42GHz millimeter-wave power amplifier.

[0010] The shortcomings of the existing technology are: (1) The research focuses on a single E / D mode RF device / GaN MMIC, and no large-scale integrated solution integrating passive devices, acoustic devices and logic devices is given. (2) The etching depth of this solution is difficult to control, the threshold voltage varies greatly, the repeatability is low, and the cost is high.

[0011] Existing technology three: Chinese invention patent CN115412057A, a monolithically integrated oscillator and its fabrication method, discloses, as follows: Figure 5 The oscillator shown integrates GaN MEMS, SAW, and FBAR acoustic devices. This oscillator uses a silicon substrate back-side etching release process to form a bulk acoustic resonant cavity. It integrates an FBAR resonator, HEMT device, and basic passive components such as 2DEG resistors and MIM capacitors on the same chip, forming a monolithic oscillator structure. This approach also verifies the feasibility of co-integrating the surface acoustic wave filter unit and the RF amplification unit by fabricating a SAW interdigital transducer and an amplifying HEMT on the front side of the GaN epitaxial layer.

[0012] The shortcomings of the existing technology are as follows: (1) It only achieves partial integration of acoustic devices, active HEMT and basic passive devices, without incorporating low-voltage E / D-mode logic control unit, and cannot support the single-chip full-function operation of the complete RF front-end system. (2) It adopts a globally unified process framework, without customized isolation and partition process design for different functional areas. Special processes such as acoustic back-side release and electrode preparation are prone to interfering with the electrical performance of active devices; it lacks full-process process compatibility constraints and cannot simultaneously meet the multiple requirements of high Q value of acoustics and high frequency and high performance of active devices. Summary of the Invention

[0013] To address the aforementioned problems, this invention provides a gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate and its fabrication method. The provided gallium nitride monolithic integrated structure is a monolithically integrated multifunctional GaN RF front-end structure that utilizes the same high-resistivity silicon GaN epitaxial platform to simultaneously support low-voltage logic control, RF signal amplification, acoustic frequency selection, and on-chip passive matching functions. This invention divides independent functional regions on the same p-GaN / AlGaN / GaN heterojunction epitaxial wafer. Through a compatible process system of local secondary epitaxial low-resistivity contacts for source and drain, device partitioning and isolation, local back-side etching release of acoustic regions, and multi-layer functionalized metal interconnects, it achieves monolithic co-integration of low-voltage E / D-mode logic control devices, RF devices, SAW / FBAR acoustic resonators, and on-chip passive matching networks. This overcomes the shortcomings of existing GaN integration solutions, such as limited functional coverage, large parasitic parameters due to reliance on multi-chip heterogeneous packaging, high packaging losses, significant thermal mismatch, and large system size. Furthermore, it uses a unified high-resistivity silicon GaN epitaxial platform as a common integration basis, enabling the system to have lower interconnect losses, higher integration density, and better operational reliability. At the same time, it has good mass production adaptability due to the maturity of large-size silicon-based processes.

[0014] To achieve the above objectives, the present invention provides the following technical solution: One of the technical solutions of this invention is to provide a gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate. The structure includes: a high-resistivity silicon substrate, a gallium nitride epitaxial structure formed on the high-resistivity silicon substrate, and a low-voltage logic device area, a radio frequency device area, an acoustic device area, and a passive device area required for circuitry formed in partitions on the gallium nitride epitaxial structure. Each functional area shares the same epitaxial base and back-end interconnect system. The isolation of process windows is achieved through active region isolation, local secondary epitaxy, local acoustic release, and metal layer role division. The gallium nitride epitaxial structure includes an AlN nucleation layer, an undoped GaN buffer layer, a C-doped GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, and a p-GaN cap layer sequentially bonded together, wherein the AlN nucleation layer is bonded to the high-resistivity silicon substrate. The low-voltage logic device region includes at least one p-GaN gate enhancement-mode device and at least one depletion-mode gate device.

[0015] In the gallium nitride epitaxial structure provided by the present invention, a high-resistivity silicon substrate is used to reduce radio frequency loss, a C-doped GaN buffer layer is used to improve device isolation and suppress buffer leakage, a two-dimensional electron gas is formed between the GaN channel layer and the AlGaN barrier layer, and a p-GaN cap layer is used to form a p-GaN gate device.

[0016] p-GaN gate enhancement-mode devices and depletion-mode gate devices can be used to construct inverters, buffers, NAND gates, ring oscillators, and bias / control circuits.

[0017] Preferably, the high-resistivity silicon substrate is an 8-inch (111) crystal orientation high-resistivity silicon substrate with a room temperature resistivity greater than 1000 Ω·cm, used to reduce substrate RF loss and improve the isolation performance between devices.

[0018] Preferably, the thickness of the AlGaN barrier layer is 10~20nm; the thickness of the p-GaN cap layer is 60~120nm.

[0019] Preferably, the depletion-type gate device is a planar gate or a T-gate structure, and the gate length is controlled between 100 and 150 nm.

[0020] Preferably, the radio frequency device region includes a multi-gate finger GaN HEMT.

[0021] Local secondary epitaxial low-resistivity contact layers can be provided below the source and drain of this multi-gate finger GaN HEMT to reduce the source-drain contact resistance.

[0022] Preferably, the acoustic device region includes a SAW device and an FBAR device; the SAW device includes an interdigital transducer and a sound propagation path; the FBAR device includes an upper electrode, a gallium nitride piezoelectric layer, a lower electrode, and a local acoustic cavity.

[0023] Preferably, the passive device area includes 2DEG resistors, MIM capacitors, on-chip inductors, and interconnect traces.

[0024] Preferably, the interconnect system includes a gate metal layer GM, a first metal layer M1, a second metal layer M2, and an acoustic electrode AE.

[0025] GM can be used as a partial gate electrode and the bottom electrode of a MIM capacitor; M1 can be used as a logic interconnect, MIM capacitor electrode, on-chip inductor, and local circuit trace; M2 can be used as a cross-area interconnect, local circuit trace, on-chip inductor thickening, pad, and ground connection; AE can be used as a SAW interdigitated electrode, FBAR top electrode, and cross-area interconnect. M1 and M2 are isolated by a dielectric layer and connected to the nodes that need to be interconnected via vias.

[0026] The second technical solution of the present invention provides a method for fabricating the above-mentioned gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate, comprising the following steps: a) Select a high-resistivity silicon substrate and grow an AlN nucleation layer, an undoped GaN buffer layer, a C-doped GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, and a p-GaN cap layer from bottom to top to form a unified heterojunction epitaxial substrate. b) Patterned fabrication of p-GaN gate structure to complete the gate region definition of enhancement-mode device and low-temperature annealing of the channel at 450~600℃; c) Define the source-drain ohmic contact window and grow an n+GaN low-resistivity contact layer using a local secondary epitaxial process; d) Complete the active area isolation process and divide the area into four functional regions: low-voltage logic region, RF device region, acoustic device region and passive device region; e) Depletion-type gate devices, multilayer passivation dielectrics and layered metal interconnect systems are fabricated sequentially to complete the front-side fabrication of active devices, passive devices and acoustic electrodes; f) The resonant structure of the acoustic device is released using the back-side process, ultimately resulting in a gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate.

[0027] Preferably, the local secondary epitaxial process is achieved using molecular beam epitaxy (MBE), where an n+GaN layer is grown only within the source-drain ohmic contact window, without covering the gate region, acoustic propagation region, or back-side aperture region; the n+GaN layer doping concentration is 4 × 10⁻⁶. 19 ~2×10 20 cm -3 It is used to reduce the ohmic contact resistance of the source and drain.

[0028] Preferably, the active region isolation process is achieved using nitrogen ion implantation, with a 3-10 nm thick Al2O3 layer deposited as an implantation protective layer before implantation; the ion implantation employs a 7° tilt angle and multi-energy implantation conditions, resulting in a sheet resistance greater than 10 Ω·cm in the isolation region after implantation. 11 Ω / sq, to ​​achieve electrical isolation between functional areas.

[0029] Preferably, the back-side process includes the following steps: the wafer is temporarily bonded to a glass substrate, the silicon substrate is thinned to 300-350 μm, acoustic back holes and resonant cavities are formed by dry etching, and finally back-side metal is deposited; the non-acoustic areas retain the complete silicon substrate to ensure the mechanical support and thermal conductivity of the active devices.

[0030] The beneficial technical effects of the present invention are as follows: This invention proposes a gallium nitride monolithic integrated structure based on a high-resistivity silicon substrate and its fabrication method. Low-voltage logic control devices, RF amplifier devices, acoustic resonators, and on-chip passive networks are partitioned on the same p-GaN / AlGaN / GaN epitaxial wafer, avoiding the additional parasitic parameters and packaging losses caused by multi-chip heterogeneous packaging. It offers advantages such as high integration density, short interconnect paths, and small system size. Higher integration density facilitates further miniaturization and performance upgrades of RF front-end systems.

[0031] This invention uses a unified heterojunction epitaxial platform as the common material basis for all functional devices. Compared with the scheme of multi-process platform chip fabrication and then system-level packaging, it eliminates the risk of thermal mismatch between different chips and packaging interface loss, which can significantly improve the overall operational stability and long-term reliability of the system.

[0032] This invention uses a high-resistivity silicon substrate as the integration carrier. Compared to self-supporting GaN substrates and SiC substrates, high-resistivity silicon substrates offer advantages such as larger wafer size, mature process supply chain, and lower manufacturing cost. Existing GaN multifunctional integration solutions mostly use small-size SiC or GaN substrates, with commercially available wafer sizes typically only 4-6 inches, resulting in low single-wafer chip yields and high overall system fabrication costs. Therefore, for highly integrated GaN RF front-end monolithic systems, fully utilizing the multiple advantages of GaN material—combining high frequency, high power, and piezoelectric properties—and selecting a high-resistivity silicon substrate and its unified heterojunction epitaxial platform is a choice that offers both performance and cost advantages.

[0033] Existing GaN multifunctional integrated solutions generally suffer from incompatibility of process windows for different functional devices and mutual interference of special processes. This invention achieves non-interference of three special processes—logic threshold control, RF low-impedance contact, and acoustic structure release—through a partitioned customized process design that includes ion implantation isolation in the active region, local secondary epitaxy in the source and drain regions, and local back-side etching release in the acoustic region. This results in a GaN multifunctional monolithic RF front-end system that balances high performance and high integration.

[0034] The source-drain local secondary epitaxy process used in this invention can also effectively alleviate the problem of device leakage current and breakdown performance degradation caused by global heavy doping epitaxy. While reducing ohmic contact resistance, it ensures the breakdown voltage and RF performance of the device, and achieves simultaneous optimization of contact characteristics and device body performance.

[0035] The overall fabrication process of this invention is based on the mature GaN-on-Si mass production process. The core process steps are all compatible with the conventional equipment of existing 8-inch compound semiconductor production lines. It has good process compatibility and low implementation difficulty. The fabricated device has a stable structure and high reliability, which meets the process requirements of large-scale mass production. It has good market application prospects in the fields of 5G / 6G communication, millimeter-wave radar, and satellite communication. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of a low-voltage GaN logic device structure in the prior art.

[0038] Figure 2 This is a schematic diagram of an E / D-mode integrated circuit in the prior art.

[0039] Figure 3 This is a schematic diagram of the structure of a radio frequency GaN HEMT in the prior art.

[0040] Figure 4 The diagram shows the structure of GaN MMIC in the prior art; where (a) is a TEM image of the E-mode GaN MOSHEMT and (b) is a TEM image of the copper interconnect layer.

[0041] Figure 5 This is a schematic diagram of the structure of an oscillator integrating GaN MEMS, SAW, and FBAR acoustic devices in the existing technology 3.

[0042] Figure 6 This is a schematic diagram of the high-resistivity silicon-based p-GaN / AlGaN / GaN heterojunction epitaxial structure used in Example 1.

[0043] Figure 7 This is a schematic cross-sectional view of the device after p-GaN gate patterning and TiN gate metal formation in Example 1.

[0044] Figure 8 This is a schematic diagram of the cross-section of the device after the formation of a local secondary epitaxial n+GaN layer in the source-drain ohmic contact region in Example 1.

[0045] Figure 9 This is a schematic diagram of the cross-section of the device after the formation of the source-drain ohmic metal, active region isolation, and depletion-type device gate metal in Example 1.

[0046] Figure 10 This is a schematic cross-sectional view of the device after the formation of the first passivation dielectric layer, via, and first metal interconnect layer in Example 1.

[0047] Figure 11 This is a schematic cross-sectional view of the device after the formation of the second passivation dielectric layer, via, and second metal interconnect layer in Example 1.

[0048] Figure 12 This is a partial cross-sectional schematic diagram of the acoustic device area after the opening and acoustic electrode formation in Example 1.

[0049] Figure 13 This is a cross-sectional schematic diagram of the wafer temporary bonding, silicon substrate thinning, and back-side patterning etching process in Example 1.

[0050] Figure 14This is a partial cross-sectional schematic diagram of the acoustic device region after back-side release and back-side metal formation in Example 1.

[0051] Figure 15 This is a schematic cross-sectional view of the monolithic integrated chip in Example 1, which integrates an enhancement-mode GaN HEMT, a depletion-mode GaN HEMT, acoustic devices, and on-chip passive devices.

[0052] Figure 16 This is a schematic diagram of the system composition of a monolithic RF-acoustic front-end chip that can be realized using the high-resistivity silicon-based GaN process in Example 1.

[0053] Figure 17 This is a schematic diagram of the silvaco-ATLAS TCAD simulation structure of the RF GaN HEMT in this invention.

[0054] Figure 18 This is an electron concentration distribution diagram of the RF GaN HEMT in this invention.

[0055] Figure 19 This is the transfer characteristic curve of the RF GaN HEMT in this invention when the drain voltage VD=4 V.

[0056] Figure 20 The output characteristic curves of the RF GaN HEMT in this invention are shown at different gate voltages.

[0057] Figure 21 The curves show the short-circuit current gain |h21| of the RF GaN HEMT in this invention as a function of frequency at drain voltage VD=4 V and gate voltages VG=-6.0 V, -5.5 V and -4.5 V.

[0058] Figure 22 The curves show the Rollet stability factor K as a function of frequency for the RF GaN HEMT in this invention at drain voltage VD=4 V and gate voltages VG=-6.0 V, -5.5 V and -4.5 V.

[0059] Figure 23 The curves show the power gain U of the RF GaN HEMT in this invention as a function of frequency at drain voltage VD=4 V and gate voltages VG=-6.0 V, -5.5 V and -4.5 V.

[0060] Figure 24 The results show the linear fitting and contact parameter extraction of the GaN ohmic contact TLM test data of this invention.

[0061] Figure 25 The results are Hall test results after p-GaN etching of the GaN epitaxial wafer of this invention.

[0062] Figure 26 This is a layout of a multifunctional GaN monolithic integrated chip. Detailed Implementation

[0063] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as a limitation of the present invention, but rather as a more detailed description of certain aspects, features, and embodiments of the present invention. It should be understood that the terminology used in this invention is merely for describing particular embodiments and is not intended to limit the present invention.

[0064] It should be noted that any aspects not described in detail in this invention are conventional practices in the field and are not the focus of this invention.

[0065] Furthermore, regarding the numerical ranges in this invention, it should be understood that each intermediate value between the upper and lower limits of the range is also specifically disclosed. Any stated value or intermediate value within a stated range, as well as each smaller range between any other stated value or intermediate value within said range, are also included in this invention. The upper and lower limits of these smaller ranges may be independently included or excluded from the range.

[0066] Unless otherwise stated, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. While only preferred methods and materials have been described herein, any methods and materials similar to or equivalent to those described herein may be used in the implementation or testing of this invention.

[0067] The terms “include,” “including,” “have,” “contain,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0068] Example 1 1) An AlN nucleation layer of 420 nm, an undoped GaN buffer layer of 900 nm, a C-doped GaN buffer layer of 500 nm, a GaN channel layer of 200 nm, an AlGaN barrier layer of 15 nm, and a p-GaN cap layer of 100 nm are grown from bottom to top on an 8-inch notch high-resistivity silicon substrate to form a high-resistivity silicon-based p-GaN / AlGaN / GaN heterojunction epitaxial structure. 2) A TiN gate metal (100 nm thick) and a SiO2 hard mask (300 nm thick) are formed on the surface of the p-GaN cap layer to prepare an enhanced GaN HEMT; and the channel is repaired by low-temperature annealing at 500℃ for 360 s. 3) A local secondary epitaxial growth window is formed in the ohmic contact region between the source and drain electrodes; 4) Perform pre-epitaxy cleaning and surface treatment on the local secondary epitaxial growth window, and use MBE to perform secondary epitaxial growth of an n+GaN layer within the local secondary epitaxial growth window. The n+GaN layer is grown only within the source-drain ohmic contact window, without covering the gate region, acoustic propagation region, and back-side opening region; the n+GaN layer doping concentration is 1.7 × 10⁻⁶. 20 cm -3 This is used to reduce the ohmic contact resistance between the source and drain; 5) Deposit and pattern ohmic metal in the secondary epitaxial region. Before metal deposition, the metal is cleaned with HCl / H2O and dried by SRD. The Ti / Al / TiN metal system is used and no annealing is performed. 6) An Al2O3 protective layer (3 nm thick) was generated using ALD, followed by photolithography using an AA mask, and then N-ion implantation was performed. The N-ion implantation was carried out at an angle of approximately 7°, using multi-energy implantation conditions of 75 keV / 8E12, 150 keV / 2E13, and 375 keV / 3E13. After implantation, the wafer resistivity was greater than 10 Ω. 11 Ω / sq, forming a device isolation region, so that enhancement-mode devices, depletion-mode devices, acoustic devices and passive devices are isolated from each other on the same wafer; 7) Deposit and pattern Ti metal to form a depletion-type gate (gate length of 100nm), which also serves as the underlying metal for the MIM capacitor; 8) Form the first passivation layer (material PECVD TEOS SiO2, thickness 220nm) and wet-process vias to form through-holes (to bring out source / drain ohmic metals, enhancement gate metals and depletion gate metals); 9) Deposit and pattern a first metal layer (Ti / Al / Ti / Ni stack, 1 μm thick) on the first passivation layer to form the first interconnect metal layer, the upper metal layer of the IM capacitor, and the inductor; 10) A second passivation layer (material PECVD TEOS SiO2, thickness 3.0μm, and the thickness can be controlled to about 2.0μm by CMP) and a through-hole are formed on the first metal layer by dry opening (formed using a V1 mask, with a minimum CD of 5μm×10μm and a sidewall angle of 85°±5°). 11) Deposit and pattern a second metal layer (Ti / TiN / Al / TiN stack, 2 μm thick) on the second passivation layer to form a second interconnect metal layer; 12) The acoustic device region is formed by wet and dry etching, and the acoustic electrode (material is Ti / Al, thickness is 100nm, minimum CD is 2μm) is deposited and patterned. Specifically, wet opening is used with a sidewall angle of 25°±5° to facilitate subsequent metal interconnection. The via passes through all passivation layers. The via is used to realize the electrical connection or structural connection between the second metal layer and the upper metal layer and the acoustic electrode. 13) The wafer is first temporarily bonded to a 500μm thick glass substrate, and then the silicon substrate is thinned to 300μm. Subsequently, a BSV mask is used for back-side photolithography and Si-sub dry etching to etch down to the AlN nucleation layer to form acoustic back holes and resonant cavities. Finally, Al metal (100nm thick) is deposited on the back side. The non-acoustic areas retain the complete silicon substrate to ensure the mechanical support and thermal conductivity of the active devices. 14) Final inspection and testing to obtain a monolithic integrated wafer containing enhancement-mode GaN HEMT, depletion-mode GaN HEMT, acoustic devices and on-chip passive devices.

[0069] Figure 6 This is a schematic diagram of the high-resistivity silicon-based p-GaN / AlGaN / GaN heterojunction epitaxial structure used in Example 1. In the schematic diagram, the AlN nucleation layer, the undoped GaN buffer layer, and the C-doped GaN buffer layer are represented as GAN.

[0070] Figure 7 This is a schematic cross-sectional view of the device after p-GaN gate patterning and TiN gate metal formation in Example 1.

[0071] Figure 8 This is a schematic diagram of the cross-section of the device after the formation of a local secondary epitaxial n+GaN layer in the source-drain ohmic contact region in Example 1.

[0072] Figure 9 This is a schematic diagram of the cross-section of the device after the formation of the source-drain ohmic metal, active region isolation, and depletion-type device gate metal in Example 1.

[0073] Figure 10 This is a schematic cross-sectional view of the device after the formation of the first passivation dielectric layer, via, and first metal interconnect layer in Example 1.

[0074] Figure 11 This is a schematic cross-sectional view of the device after the formation of the second passivation dielectric layer, via, and second metal interconnect layer in Example 1.

[0075] Figure 12 This is a partial cross-sectional schematic diagram of the acoustic device area after the opening and acoustic electrode formation in Example 1.

[0076] Figure 13 This is a cross-sectional schematic diagram of the wafer temporary bonding, silicon substrate thinning, and back-side patterning etching process in Example 1.

[0077] Figure 14 This is a partial cross-sectional schematic diagram of the acoustic device region after back-side release and back-side metal formation in Example 1.

[0078] Figure 15 This is a schematic cross-sectional view of the monolithic integrated chip in Example 1, which integrates an enhancement-mode GaN HEMT, a depletion-mode GaN HEMT, acoustic devices, and on-chip passive devices.

[0079] Figure 16 This is a schematic diagram of the system composition of a monolithic RF-acoustic front-end chip that can be realized using the high-resistivity silicon-based GaN process in Example 1.

[0080] The following are some simulation results of the monolithic integrated wafer prepared in Example 1: gm = 0.46~0.48 S / mm; Cgs = 0.22~0.25 pF / mm; Cgd = 0.09~0.13 pF / mm; gds = 0.05~0.09 S / mm; fT = 257~278 GHz; fmax = 286–367 GHz; Id = 496.2 mA / mm; Idss = 1.6490 A / mm; Idq / Idss = 0.3.

[0081] The Silvaco ATLAS device simulation software was used to establish a system such as... Figure 17 The simulated structure of the RF GaN HEMT in Silvaco-ATLAS TCAD is shown. The simulated structure is consistent with the actual process: it includes a high-resistivity substrate equivalent layer, an AlN nucleation layer, an unintentionally doped GaN buffer layer, a C-doped GaN buffer layer, a GaN channel layer, and an Al... 0.24 Ga 0.76 The device consists of an N-type barrier layer, a 3nm thick Al₂O₃ gate dielectric, a SiO₂ passivation layer, and locally epitaxial n+GaN source / drain contact regions. The AlGaN barrier layer is 15nm thick, the gate length of the depletion-mode device is 0.10μm, and the doping concentration of the epitaxial n+GaN for the source / drain is 1.7 × 10⁻⁶. 20 cm -3 The simulation sets up source, drain, gate, and substrate electrodes, and incorporates the measured source-drain ohmic contact resistance and access region resistance into the device model. Figure 17It can be seen that the established simulation structure can reflect the gate dielectric, heterojunction channel, source-drain regeneration contact and buffer layer structure of the actual depletion-type MIS gate GaN HEMT, and can be used for subsequent calculation of DC characteristics and high-frequency small-signal characteristics.

[0082] Through the Figure 17 The device structure shown was obtained by performing an initial equilibrium solution, i.e., solving the Poisson equation, electronic continuity equation, and related carrier transport equations within the device under the condition that no external bias voltage is applied to the source, drain, and gate. The resulting equilibrium structure file was then imported into TonyPlot, and electron concentration was selected as the display variable. The electron concentration distribution plot of the RF GaN HEMT is shown below. Figure 18 An AlGaN / GaN polarization model is introduced into the simulation. (From...) Figure 18 It can be seen that electrons mainly accumulate near the AlGaN / GaN heterojunction interface, forming a high-concentration two-dimensional electron gas channel at the interface, while the electron concentration in the deep buffer layer of the device is low. This indicates that the established epitaxial structure can form the expected heterojunction conductive channel and suppress parasitic conductivity of the buffer layer.

[0083] First to Figure 17 The device underwent thermal equilibrium calculation, and then the drain voltage was gradually increased to 4 V. Using the gate voltage VG = -10 V as the scan starting point, the gate voltage was scanned down to 0 V according to a set voltage step size, and the drain current at each gate voltage was recorded. The simulation results were normalized to a total gate width of 0.44 mm. The transfer characteristic curve of the RF GaN HEMT at a drain voltage VD = 4 V is shown below. Figure 19 .Depend on Figure 19 It can be seen that the device can be turned off under a large negative gate voltage. As the gate voltage increases, the drain current continues to increase and gradually approaches saturation near 0 V. The threshold voltage of the device is negative, indicating that the device belongs to the depletion-type GaN HEMT. The normalized drain current Idss at a gate voltage of 0 V is approximately 1.6490 A / mm, indicating that the device has a high channel current drive capability.

[0084] The gate voltage was set to -10 V, -5 V, and -2 V respectively, and the drain voltage was gradually scanned from 0 V to 4 V under each gate bias, while the drain current was recorded. The output characteristic curves of the RF GaN HEMT under different gate voltages are shown in [Figure number missing]. Figure 20 .Depend on Figure 20It can be seen that the device is basically in the off state when VG = -10 V; when VG = -5 V and VG = -2 V, the drain current increases with the increase of drain voltage and gradually enters the saturation region. After the gate voltage is increased from -5 V to -2 V, the drain current increases significantly, indicating that the gate can effectively modulate the two-dimensional electron gas concentration in the heterojunction channel. The output curve has obvious linear and saturation regions, indicating that the device has the basic conditions for static biasing and small-signal analysis as an RF amplifier.

[0085] The short-circuit current gain |h21| of the RF GaN HEMT as a function of frequency at drain voltage VD=4 V and gate voltages VG=-6.0 V, -5.5 V, and -4.5 V is shown in the figure. Figure 21 First, the DC quiescent operating points under three gate biases are calculated. Then, a small-signal AC perturbation is applied near each quiescent operating point, and a small-signal AC sweep is performed in the frequency range of 20–400 GHz. The short-circuit current gain is calculated based on the simulated two-port small-signal parameters and converted to decibels using H21(dB) = 20log10|h21|. The frequency at which H21 drops to 0 dB, i.e., |h21| = 1, is defined as the current gain cutoff frequency f. T The calculated f values ​​for VG = -6.0 V, -5.5 V, and -4.5 V were obtained. T These are approximately 278.1 GHz, 269.7 GHz, and 256.8 GHz, respectively. (By...) Figure 21 It can be seen that |h21| decreases monotonically with increasing frequency, and the rate of decrease in the 20–200 GHz range is approximately -19 dB / dec, which is close to the -20 dB / dec variation of the current gain of a typical field-effect transistor. Among the three bias points, the highest fg is observed at VG = -6.0 V. T This indicates that the device at this bias point achieves a superior overall balance between transconductance, gate capacitance, and channel carrier transport velocity. use Figure 21 Small-signal AC analysis: First, the S-parameter determinant is calculated based on Δ = S11S22 - S12S21. Then, the Rollet stability factor is calculated based on K = [1 - |S11|^2 - |S22|^2 + |Δ|^2] / [2|S12S21|]. The curves of the Rollet stability factor K versus frequency for RF GaN HEMTs at drain voltage VD = 4 V and gate voltages VG = -6.0 V, -5.5 V, and -4.5 V are shown in the figure. Figure 22 The calculated frequencies corresponding to K rising to 1 when VG = -6.0 V, -5.5 V, and -4.5 V are approximately 220.3 GHz, 198.6 GHz, and 178.8 GHz, respectively. (From...) Figure 22It can be seen that K increases with increasing frequency. This is because the positive gain and feedback loop gain of the device decrease with increasing frequency, reducing the possibility of self-oscillation. When K>1 and |Δ|<1, the device is in an unconditionally stable state; when K<1, the device is in a conditionally stable state, and potential oscillations need to be avoided in actual RF circuits through input-output matching networks and stabilization networks.

[0086] use Figure 21 Small-signal AC analysis: The Mason unidirectional power gain is calculated as U = |Y21 - Y12|^2 / {4[Re(Y11)Re(Y22) - Re(Y12)Re(Y21)]}, and converted to decibels using U(dB) = 10log10(U). The frequency at which U drops to 0 dB is defined as the maximum oscillation frequency f. max The power gain U of the RF GaN HEMT as a function of frequency at drain voltage VD = 4 V and gate voltages VG = -6.0 V, -5.5 V, and -4.5 V are shown in the figure. Figure 23 The calculated f values ​​for VG = -6.0 V, -5.5 V, and -4.5 V were obtained. max These are approximately 366.7 GHz, 327.5 GHz, and 286.4 GHz, respectively. Figure 23 It can be seen that the Mason unidirectional power gain decreases with increasing frequency, and the highest unidirectional power gain and maximum oscillation frequency are observed at VG = -6.0 V, indicating that this bias point is more conducive to obtaining higher high-frequency power gain. Under the conditions of this simulation model and the set parasitic parameters, the device's f... max The GHz range is approximately 286–367 GHz, indicating that this device has the potential for millimeter-wave small-signal amplification applications.

[0087] TLM test structures with the same contact width and different electrode spacings (d) were fabricated on the same GaN epitaxial wafer. The low-field current-voltage characteristics corresponding to each electrode spacing were measured, and the total resistance (Rtotal) was calculated from the slope of the current-voltage curve. A linear fit was performed on the total resistance against the electrode spacing, yielding Rtotal = 5.605d + 9.072. Based on the TLM relationship Rtotal = 2Rc + (Rsh / W)d, and using a contact width W = 100 μm, the sheet resistance (Rsh) was obtained as follows: Rsh = 560.49 Ω / □, individual contact resistance (Rc) = 4.5359 Ω, normalized contact resistance (rc) = 0.4536 Ω·mm, and specific contact resistivity (ρc) = 3.671 × 10⁻⁶. -6 Ω·cm 2 The linear fitting and contact parameter extraction results of GaN ohmic contact TLM test data are shown in [reference needed]. Figure 24 .Depend on Figure 24It can be seen that the total resistance has a good linear relationship with the TLM electrode spacing, indicating that the current transfer in the test structure conforms to the TLM model. The prepared source-drain ohmic contact has a low normalized contact resistance, which can be used to reduce the source-drain series resistance and conduction loss of GaN RF devices.

[0088] Thirty-four test points were set at different locations on the wafer for Hall effect testing. The results showed that the average electron mobility of the 34 test points was 1667.94 cm² / (V·s), with a maximum value of 1837.79 cm² / (V·s) and a minimum value of 1191.07 cm² / (V·s). The standard deviation was 146.03 cm² / (V·s), and the relative standard deviation was 8.75%. The Hall effect test results after p-GaN etching of the GaN epitaxial wafer are shown in [reference needed]. Figure 25 .Depend on Figure 25 It can be seen that the GaN epitaxial wafer has high electron mobility in most areas after p-GaN etching, and the wafer-level mobility distribution is generally continuous, indicating that the epitaxial wafer can provide good two-dimensional electron gas transport performance for GaN HEMT; low-damage p-GaN etching is achieved, which can realize the performance of RF devices while making logic circuits.

[0089] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate, characterized in that, The structure includes: A high-resistivity silicon substrate, a gallium nitride epitaxial structure formed on the high-resistivity silicon substrate, and a low-voltage logic device region, a radio frequency device region, an acoustic device region, and a passive device region required for the circuit formed in partitions on the gallium nitride epitaxial structure; Each functional area shares the same epitaxial base and back-end interconnection system. The isolation of process windows is achieved through active area isolation, local secondary epitaxy, local acoustic release, and metal layer role division. The gallium nitride epitaxial structure includes an AlN nucleation layer, an undoped GaN buffer layer, a C-doped GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, and a p-GaN cap layer, which are sequentially bonded together. The AlN nucleation layer is bonded to the high-resistivity silicon substrate. The low-voltage logic device region includes at least one p-GaN gate enhancement-mode device and at least one depletion-mode gate device.

2. The gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate according to claim 1, characterized in that, The high-resistivity silicon substrate is an 8-inch (111) crystal-oriented high-resistivity silicon substrate with a room temperature resistivity greater than 1000 Ω·cm.

3. The gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate according to claim 1, characterized in that, The thickness of the AlGaN barrier layer is 10~20nm; the thickness of the p-GaN cap layer is 60~120nm.

4. The gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate according to claim 1, characterized in that, The depletion-type gate device is a planar gate or a T-gate structure, with the gate length controlled between 100 and 150 nm.

5. The gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate according to claim 1, characterized in that, The radio frequency device region includes a multi-gate finger GaN HEMT; And / or, the acoustic device region includes SAW devices and FBAR devices; the SAW device includes an interdigital transducer and an acoustic propagation path; the FBAR device includes an upper electrode, a gallium nitride piezoelectric layer, a lower electrode, and a local acoustic cavity; And / or, the passive device region includes 2DEG resistors, MIM capacitors, on-chip inductors, and interconnects; And / or, the interconnect system includes a gate metal layer GM, a first metal layer M1, a second metal layer M2, and an acoustic electrode AE.

6. A method for fabricating a gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate as described in any one of claims 1 to 5, characterized in that, Includes the following steps: a) Select a high-resistivity silicon substrate and grow an AlN nucleation layer, an undoped GaN buffer layer, a C-doped GaN buffer layer, a GaN channel layer, an AlGaN barrier layer, and a p-GaN cap layer from bottom to top to form a unified heterojunction epitaxial substrate. b) Patterned fabrication of p-GaN gate structure to complete the gate region definition of enhancement-mode device and low-temperature annealing of the channel at 450~600℃; c) Define the source-drain ohmic contact window and grow an n+GaN low-resistivity contact layer using a local secondary epitaxial process; d) Complete the active area isolation process and divide the area into four functional regions: low-voltage logic region, RF device region, acoustic device region and passive device region; e) Depletion-type gate devices, multilayer passivation dielectrics and layered metal interconnect systems are fabricated sequentially to complete the front-side fabrication of active devices, passive devices and acoustic electrodes; f) The resonant structure of the acoustic device is released using the back-side process, ultimately resulting in a gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate.

7. The method for fabricating a gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate according to claim 6, characterized in that, The local secondary epitaxial process is achieved using molecular beam epitaxy, where an n+GaN layer is grown only within the source-drain ohmic contact window, without covering the gate region, acoustic propagation region, or back-side aperture region; the n+GaN layer doping concentration is 4×10⁻⁶. 19 ~2×10 20 cm -3 .

8. The method for fabricating a gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate according to claim 6, characterized in that, The active region isolation process is achieved using nitrogen ion implantation. Before implantation, a 3-10 nm thick Al2O3 layer is deposited as an implantation protective layer. Ion implantation is performed at a 7° tilt angle and under multi-energy implantation conditions. After implantation, the sheet resistance of the isolation region is greater than 10 Ω·cm. 11 Ω / sq, to ​​achieve electrical isolation between functional areas.

9. The method for fabricating a gallium nitride monolithic integrated chip based on a high-resistivity silicon substrate according to claim 6, characterized in that, The back-side process includes the following steps: the wafer is first temporarily bonded to a glass substrate, then the silicon substrate is thinned to 300~350μm, then acoustic back holes and resonant cavities are formed by dry etching, and finally back-side metal is deposited.

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