Perovskite-crystalline silicon laminated cell

Abstract

The invention provides a perovskite-crystalline silicon laminated cell, which comprises a heterogeneous crystalline silicon cell, a tunnel junction, a conductive layer, a first carrier transport layer, a perovskite light absorption layer, a second carrier transport layer and a transparent electrode layer which are sequentially laminated, wherein the first carrier transport layer comprises a dendritic structure facing and extending into the perovskite light absorption layer, and the length of the dendritic structure is smaller than the thickness of the perovskite light absorption layer. According to the perovskite-crystalline silicon laminated cell provided by the invention, through the arrangement of the dendritic structure with a relatively good capillary effect in the first carrier transport layer, a high-quality perovskite absorption layer can be formed, so that the energy conversion efficiency of the perovskite-crystalline silicon laminated solar cell is greatly improved.

Description

Technical Field

[0001] The present application relates to the field of battery technology, and in particular to a perovskite-crystalline silicon tandem battery. Background Art

[0002] Monocrystalline silicon solar cells occupy the vast majority of the photovoltaic market due to their high conversion efficiency and low cost. At present, the world's highest conversion efficiency of monocrystalline silicon solar cells is 26.81%, created by LONGi's heterojunction technology, which is very close to the theoretical efficiency of 29.4%. An effective way to break through the theoretical limit is to develop tandem cell technology, that is, stacking absorption layers with different band gaps together to reduce heat loss. Simulations and calculations show that tandem cells at both ends of the surface can achieve a theoretical efficiency of 43%. Perovskite has become an excellent top cell material in tandem cells because of its easy processing, low cost, and easy band gap adjustment. Recently, the Berlin Helmholtz Center (HZB) created a conversion efficiency of 32.5%.

[0003] The structure of the two-terminal perovskite / silicon stacked cell consists of a perovskite top cell and a silicon-based heterogeneous crystalline silicon cell, with a composite layer in the middle connecting the top / heterogeneous crystalline silicon cells. The composite layer plays a connecting role and is required to have high transmittance, good chemical stability, simple process, suitable energy level matching, efficient electron / hole recombination, and low resistance to achieve current matching, which is crucial to the performance of the perovskite / silicon stacked cell device. However, perovskite and crystalline silicon materials have different band gaps, and currently perovskite cells are mainly prepared by solution method, but the surface of crystalline silicon cells has a velvet light trapping structure, and it is difficult to obtain a high-quality perovskite absorption layer on the crystalline silicon velvet surface by solution method. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the purpose of the present application is to propose a perovskite-crystalline silicon tandem cell, which can provide a high-quality perovskite absorption layer by setting a dendrite structure with good capillary effect in the first carrier transport layer, thereby greatly improving the energy conversion efficiency of the perovskite-crystalline silicon tandem solar cell.

[0005] According to an embodiment of the present application, a perovskite-crystalline silicon stacked cell is proposed, comprising a heterogeneous crystalline silicon cell, a tunnel junction, a conductive layer, a first carrier transport layer, a perovskite light absorption layer, a second carrier transport layer and a transparent electrode layer stacked in sequence, wherein the first carrier transport layer comprises a dendrite structure facing and extending into the perovskite light absorption layer, and the length of the dendrite structure is less than the thickness of the perovskite light absorption layer.

[0006] In some embodiments, the dendritic structure is a fiber-like structure, a rod-like structure, or a tubular structure.

[0007] In some embodiments, the coverage rate of the dendrite structure on the surface of the first carrier transport layer is 10-50%.

[0008] In some embodiments, the perovskite light absorbing layer covers the first carrier transporting layer and fills the gaps in the dendrite structure of the first carrier transporting layer.

[0009] In some embodiments, the heterogeneous crystalline silicon cell is n-type or p-type.

[0010] In some embodiments, the structure of the tunnel junction is selected from at least one of a hydrogen-doped n-type microcrystalline silicon stacked with a hydrogen-doped p-type microcrystalline silicon structure, an oxygen-doped n-type amorphous silicon stacked with an oxygen-doped p-type amorphous silicon structure, and a microcrystalline silicon stacked with a silicon oxide structure.

[0011] In some embodiments, the thickness of the tunnel junction is 8-15 nm.

[0012] In some embodiments, the conductive layer has a thickness of 0.5-20 nm and a conductivity greater than 1500 S / m;

[0013] And / or, the material of the conductive layer is metal oxide.

[0014] In some embodiments, the first carrier transport layer has a thickness of 20-120 nm and is selected from TiO 2 SnO 2 , ZnO or selected from PEDOT, PEDOT:PSS, P 3 HT, P 3 OHT, P 3 One of ODDT, PTAA, and NiO.

[0015] In some embodiments, the stacked cell further includes metal electrodes respectively disposed on the heterogeneous crystalline silicon cell and the transparent electrode layer on a side away from the perovskite absorption layer.

[0016] Compared with the related art, this application has the following technical effects:

[0017] The first carrier transport layer of the present application includes a dendrite structure that faces and extends into the perovskite light absorption layer. The first carrier transport layer can enhance the carrier collection and conduction capabilities of the carrier transport material. At the same time, based on the capillary effect, the perovskite precursor solution can form a film with uniform thickness and complete coverage on the velvet pyramid structure of the heterogeneous crystalline silicon battery, so that the perovskite thickness at the top and bottom of the velvet pyramid structure of the heterogeneous crystalline silicon battery is basically the same, avoiding the problem of the absorption layer at the bottom of the pyramid being too thick and the tip of the pyramid being difficult to completely cover, thereby greatly improving the energy conversion efficiency of the perovskite-crystalline silicon stacked battery. In addition, compared with the protruding structure with a single structure, the capillary effect of the dendrite structure is higher, which can enhance the light trapping effect of the perovskite-crystalline silicon stacked battery and further improve the battery conversion efficiency.

[0018] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0020] Figure 1 It is a schematic diagram of the structure of a perovskite-crystalline silicon tandem battery proposed in one embodiment of the present application;

[0021] In the figure, 1. Heterocrystalline silicon cell; 2. Tunnel junction; 3. Conductive layer; 4. First carrier transport layer; 5. Perovskite light absorption layer; 6. Second carrier transport layer; 7. Transparent electrode layer; 8. Dendrite structure; 9. Metal electrode. DETAILED DESCRIPTION

[0022] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be construed as limiting the present application. On the contrary, the embodiments of the present application include all changes, modifications and equivalents that fall within the spirit and connotation of the appended claims.

[0023] Unless otherwise defined, the technical and scientific terms in this specification have the same meaning as those generally understood by those skilled in the art. Although similar or identical methods and materials as described herein may be used in experiments or practical applications, materials and methods are described herein below. In the event of a conflict, the present specification including the definitions therein shall prevail. In addition, materials, methods and examples are provided for illustration only and are not restrictive. The present application is further described below in conjunction with specific embodiments, but is not intended to limit the scope of the present application.

[0024] According to an embodiment of the present application, a perovskite-crystalline silicon stacked cell is proposed, comprising a heterogeneous crystalline silicon cell 1, a tunnel junction 2, a conductive layer 3, a first carrier transport layer 4, a perovskite light absorption layer 5, a second carrier transport layer 6 and a transparent electrode layer 7 stacked in sequence, wherein the first carrier transport layer 4 includes a dendrite structure 8 facing and extending into the perovskite light absorption layer 5, and the length of the dendrite structure 8 is less than the thickness of the perovskite light absorption layer 5.

[0025] The heterogeneous crystalline silicon cell 1 is of n-type or p-type, and can be of single-sided or double-sided structure. It can be prepared by a method known in the prior art, or it can be a commercialized heterogeneous crystalline silicon cell 1, wherein the side of the heterogeneous crystalline silicon cell 1 facing the tunnel junction 2 has a pyramid velvet surface, that is, the heterogeneous crystalline silicon cell 1 has a pyramid velvet surface. Figure 1 In the structure shown, the side facing the tunnel junction 2 has continuously arranged pyramid structures.

[0026] In some embodiments, the structure of the tunnel junction 2 is selected from at least one of a hydrogen-doped n-type microcrystalline silicon stacked with a hydrogen-doped p-type microcrystalline silicon structure, an oxygen-doped n-type amorphous silicon stacked with an oxygen-doped p-type amorphous silicon structure, and a microcrystalline silicon stacked with a silicon oxide structure.

[0027] For example, the structure of the tunnel junction 2 is selected from a structure of hydrogen-doped n-type microcrystalline silicon stacked with hydrogen-doped p-type microcrystalline silicon (nc-Si:H(n + ) / nc-Si:H(p + )), oxygen-doped n-type amorphous silicon stacked with oxygen-doped p-type amorphous silicon structure (a-Si:H(n + ) / a-Si:H(p + )), and microcrystalline silicon stacked silicon oxide structure (nc-Si:H(n + ) / SiO 2 ). During the preparation process, when the tunnel junction 2 is deposited on the n-side of the heterogeneous crystalline silicon cell 1, n-type microcrystalline silicon / amorphous silicon is deposited first, and then p-type microcrystalline silicon / amorphous silicon is deposited thereon; when the tunnel junction 2 is deposited on the p-side of the heterogeneous crystalline silicon cell 1, p-type microcrystalline silicon / amorphous silicon is deposited first, and then n-type microcrystalline silicon / amorphous silicon is deposited thereon.

[0028] The thickness of the tunnel junction 2 is 8-15 nm, for example, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm and any range therebetween.

[0029] In some embodiments, the conductive layer 3 is a metal oxide layer, and may also be a metal material, a mixed material of multiple metals, etc. For example, the material may be selected from indium tin oxide (ITO), indium zinc oxide (IZO), indium tantalum oxide (IWO), indium oxide (InO), 2 O 3 ), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), zinc oxide (ZnO 2 ), antimony tin oxide (ATO), fluorine tin oxide (FTO), tin oxide (SnO 2 ), titanium dioxide (TiO 2 ) or more than one of the above. In addition, the conductive layer 3 may be a complete layer, or may be a structure with holes or grooves filled with conductive materials.

[0030] Meanwhile, the thickness of the conductive layer 3 is 0.5-20 nm, for example, 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, and any ranges between these values. For example, in a specific embodiment, the thickness of the conductive layer 3 is 5-10 nm, and the conductivity of the conductive layer 3 is greater than 1500 S / m, for example, 1500 S / m, 1600 S / m, 1700 S / m, 1800 S / m, 1900 S / m, 2000 S / m, and any ranges between these values.

[0031] For example, the transmittance of the conductive layer 3 in the range of 300-1200nm light wave is greater than 85%, for example, it can be 86%, 87%, 88%, 89%, 90%, 91%, 92%, 93%, 94%, 95%, and any range between these values. Its work function is 4.5-5.4eV, for example, it can be 4.5eV, 4.6eV, 4.7eV, 4.8eV, 4.9eV, 5eV, 5.1eV, 5.2eV, 5.3eV, 5.4eV, and any range between these values. Among them, the conductivity, work function, carrier concentration, conductivity, and carrier concentration of the conductive layer 3 can all be detected by a Hall effect tester, and the work function can be tested by ultraviolet photoelectron spectroscopy.

[0032] When preparing the conductive layer 3, those skilled in the art will appreciate that different processes may be selected according to different heterogeneous crystalline silicon battery types. For example, when the heterogeneous crystalline silicon battery is a heterogeneous crystalline silicon battery 1, the conductive layer 3 may be deposited by PVD, ALD, spin coating, etc., with a deposition temperature of less than 250°C, preferably less than 190°C.

[0033] The tunnel junction 2 and the conductive layer 3 of the present application are located between the heterogeneous crystalline silicon cell 1 and the first carrier transport layer 4, which is conducive to the collection of lateral charges and improves the filling factor of the stacked cell. Among them, the conductive layer 3 can reduce parasitic absorption, increase the current of the stacked cell, improve the contact resistance between the charge transport layer of the top cell and the tunnel junction 2, and improve the filling factor of the stacked cell. The tunnel junction 2 serves as a barrier layer during the preparation of the conductive layer 3, protecting the heterogeneous crystalline silicon cell from process damage and improving the open circuit voltage of the stacked cell.

[0034] In some embodiments, the first carrier transport layer 4 has a thickness of 20-120 nm and is selected from TiO 2 SnO 2 , ZnO or selected from PEDOT, PEDOT:PSS, P 3 HT, P 3 OHT, P 3 One of ODDT, PTAA, and NiO.

[0035] The first carrier transport layer 4 can be an organic polymer material or a metal oxide material. For organic polymers, a one-step conformal preparation method can be used for preparation; for metal oxide materials, a two-step conformal preparation method can be used for preparation. For example, the first carrier transport layer 4 can be made of an electron transport material or a hole transport material. The battery transport material can be TiO 2 SnO 2 , ZnO, BBL:PEI (poly (benzimidazole and benzophenanthroline) - polyethylene imine), etc., wherein the hole transport material can be PEDOT, PEDOT:PSS, P 3 HT, P 3 OHT, P 3 ODDT, PTAA and NiO, etc.

[0036] The material that can be used in the one-step conformal preparation method is an organic polymer material, and the gas phase method known in the art can be used. The gas phase method can form an organic polymer first carrier transport layer 4 with a dendrite structure 8 in one step. For example, a substrate is first prepared: a catalyst layer required for the polymerization reaction of the polymer monomer is deposited on the substrate by a physical vapor deposition method. Then the substrate with the catalyst deposited is placed in the vapor of the polymer monomer, and the monomer vapor encounters the catalyst on the substrate, and a polymerization reaction occurs at the interface between the two phases. The morphology control principle is as follows: a. When the vapor pressure of the monomer in the reaction container is large, the monomer vapor condenses into droplets. When the droplets contact the catalyst layer, the contact area reacts. In the area where there is no droplet contact, there is no monomer, and no polymerization reaction occurs. In this case, a nanostructure is formed; b. When the vapor pressure of the monomer in the reaction container is small, the monomer vapor is evenly distributed in the cavity of the reaction container, and the monomer is evenly in contact with the catalyst, then a uniform polymer film is formed on the substrate. In the above-mentioned polymerization reaction process, the monomer vapor pressure is initially controlled to saturate and form droplets, and then a dendrite structure 8 is formed.

[0037] The materials that can be used in the two-step conformal preparation method are metal oxide materials. First, physical vapor deposition, electroplating, etc. are used. A layer of metal single substance film corresponding to "metal oxide" is deposited or electroplated on the substrate. Then, the metal single substance layer is oxidized to metal oxide by anodic electrochemical oxidation. Specifically, the current, electrolyte solvent type, solute concentration and other parameters are controlled during anodic oxidation. When the oxidation reaction is localized, a dendrite structure is formed.

[0038] In the present application, the thickness of the first carrier transport layer 4 is 20-120nm, for example, it can be 0nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm or 120nm. Among them, the first carrier transport layer 4 mainly plays the role of lateral collection and transmission of carriers, that is, the carriers generated by the absorption layer are collected and transmitted horizontally to the perovskite light absorption layer 5. Therefore, this thickness should not be too thick or too thin. If the thickness of the first carrier transport layer 4 is too thick, the distance of longitudinal transmission to the series structure is too long, resulting in excessive transmission resistance; on the contrary, if the thickness is too thin, the lateral transmission resistance is too large, which is not conducive to the lateral collection and transmission of carriers in the absorption layer.

[0039] Specially, in the present application, the first carrier transport layer 4 includes a dendrite structure 8 that faces and extends into the perovskite light absorption layer 5, and the length of the dendrite structure 8 is less than the thickness of the perovskite light absorption layer 5, that is, one end of the dendrite structure 8 is located in the first carrier transport layer 4, and the other end extends to the perovskite light absorption layer 5. While the first carrier transport layer 4 serves as a carrier transport layer, it can also allow the perovskite precursor solution to form a film with uniform thickness and complete coverage on the velvet pyramid structure of the crystalline silicon cell. The perovskite light absorption layer 5 covers the first carrier transport layer 4 and fills the gaps of the dendrite structure 8 of the first carrier transport layer 4, wherein the perovskite light absorption layer 5 can be fully filled into the gaps of multiple discretely distributed dendrite structures 8, thereby further enhancing the carrier collection and conduction capabilities of the carrier transport material.

[0040] In some embodiments, the dendrite structure 8 is a fiber-like structure, a rod-like structure or a tubular structure.

[0041] Among them, the dendrite structure 8 is a fibrous structure, a rod-like structure or a tubular structure. In addition, the dendrite structure 8 should not be too short or too long. The length of the dendrite structure 8 is less than the thickness of the perovskite light absorption layer 5. When the dendrite structure 8 is too short, the capillary action is too weak; if it is too long, the first carrier transport layer 4 is too thick, which is not conducive to improving the efficiency of the perovskite light absorption layer 5. At the same time, the difficulty of filling the gap of the perovskite precursor solution in the dendrite structure 8 increases, and some gaps will be caused at the root, affecting the efficiency of the perovskite-crystalline silicon stacked battery. For example, the length of the dendrite structure 8 is 50-1000nm. For example, it can be 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm. At the same time, in the field of nanomaterials, it is generally believed that nanostructures above 100nm have better performance in terms of strength and long-term stability, so the diameter of the dendrite structure 8 is not less than 100nm. In addition, the dendrite structure 8 can also produce a light trapping effect. When the surface of the first carrier transport layer 4 facing the perovskite light absorption layer 5 has a suede structure, the light trapping effect can be further enhanced.

[0042] The coverage of the dendrite structure 8 on the surface of the first carrier transport layer is 10-50%, preferably 10-40%, for example, 5%, 10%, 20%, 30%, 40%, 50%. The coverage of the dendrite structure 8 on the surface of the first carrier transport layer refers to the ratio of the area of ​​the dendrite structure 8 on the surface of the first carrier transport layer to the area of ​​the first carrier transport layer.

[0043] In some embodiments, the stacked cell further includes a metal electrode 9 which is respectively arranged on the heterogeneous crystalline silicon cell 1 and the transparent electrode layer 7 on a side away from the perovskite absorption layer.

[0044] The perovskite light absorption layer 5, the second carrier transport layer 6, the transparent electrode layer 7 and the metal electrode 9 can be prepared based on the technology known in the art. For example, the perovskite light absorption layer 5 can be an organic-hybrid halide perovskite, an all-inorganic halide perovskite, or a lead-free perovskite, a double perovskite or other perovskite structure light absorption material; the transparent electrode layer 7 can be a transparent electrode commonly used in the prior art, such as FTO, ITO, AZO, etc.; the second carrier transport layer 6 can be made of an electron transport material or a hole transport material. For example, in a specific embodiment, Figure 1 As shown, the stacked cell includes a heterogeneous crystalline silicon cell 1, a tunnel junction 2, a conductive layer 3, a first carrier transport layer 4, a perovskite absorption layer, a second carrier transport layer 6 and a transparent electrode layer 7 which are stacked in sequence, and a metal electrode 9 arranged on the side of the heterogeneous crystalline silicon cell 1 and the transparent electrode layer 7 away from the perovskite absorption layer.

[0045] Example 1

[0046] Provide an HJT (heterojunction) solar cell with an N-type silicon wafer as the bottom cell, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all of which are deposited using PECVD with a total thickness of 10nm. PVD is used to deposit an ITO layer on the tunnel junction with a thickness of 5nm, and annealed at 190℃ for 30min after deposition.

[0047] A first carrier transport layer is prepared on the surface of the ITO layer, wherein the first carrier transport layer is a hole transport layer having a dendrite structure, which is PEDOT synthesized by a vapor phase method, the thickness of the first carrier transport layer is 100 nm, the dendrite structure is fibrous, the length is 500 nm, the diameter is 150 nm, and the surface coverage of the dendrite structure on the first carrier transport layer is 40%. The morphology, length, and diameter of the dendrite structure can be obtained by electron microscope observation, and the surface coverage can be obtained by a specific surface area analyzer.

[0048] A perovskite light absorption layer is coated on the surface of the first carrier transport layer away from the ITO layer, wherein the perovskite light absorption layer uses MAPbI3 perovskite with a thickness of 1000nm. The perovskite coating method uses a dip coating method to immerse the crystalline silicon cell covered with the first carrier transport layer in a DMF solution of 1.5M MAPbI3 perovskite and pull it at a speed of 20mm / min. After the pulling is completed, it is dried at 100°C for 10 minutes to obtain the MAPbI3 perovskite light absorption layer. The second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation. It is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0049] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the perovskite-crystalline silicon stacked cell of this embodiment is 29.9%.

[0050] Example 2

[0051] Provide a HJT (heterojunction) solar cell with a P-type silicon wafer as the bottom cell, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all of which are deposited using PECVD with a total thickness of 15nm. PVD is used to deposit an ITO layer on the tunnel junction with a thickness of 15nm, and annealed at 190°C for 30min after deposition.

[0052] A first carrier transport layer is prepared on the surface of the ITO layer, wherein the first carrier transport layer is a hole transport layer having a dendrite structure, which is PEDOT synthesized by a vapor phase method, the thickness of the first carrier transport layer is 80nm, the dendrite structure is fibrous, the length is 100nm, the diameter is 100nm, and the surface coverage of the dendrite structure on the first carrier transport layer is 50%. The morphology, length, and diameter of the dendrite structure can be obtained by electron microscope observation, and the surface coverage can be obtained by a specific surface area analyzer.

[0053] A perovskite light absorption layer is coated on the surface of the first carrier transport layer away from the ITO layer, wherein the perovskite light absorption layer uses lead-free perovskite with a thickness of 1000 nm, and the perovskite coating method refers to Example 1. A second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation, which is an electron transport layer, using C60 as the electron transport layer material with a thickness of 50 nm.

[0054] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the perovskite-crystalline silicon stacked cell of this embodiment is 27.8%.

[0055] Example 3

[0056] Provide HJT (heterojunction) solar cells with N-type silicon wafers as the bottom cell, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all of which are deposited by PECVD, with a total thickness of 8nm. PVD is used to deposit an ITO layer on the tunnel junction, with a thickness of 20nm, and annealed at 190℃ for 30min after deposition.

[0057] A first carrier transport layer is prepared on the surface of the ITO layer, wherein the first carrier transport layer is a hole transport layer having a dendrite structure, which is PEDOT synthesized by a vapor phase method, the thickness of the first carrier transport layer is 100 nm, the dendrite structure is fibrous, the length is 200 nm, the diameter is 130 nm, and the surface coverage of the dendrite structure on the first carrier transport layer is 20%. The morphology, length, and diameter of the dendrite structure can be observed by an electron microscope, and the surface coverage can be obtained by a specific surface area analyzer.

[0058] A perovskite light absorption layer is coated on the surface of the first carrier transport layer away from the ITO layer, wherein the perovskite light absorption layer uses lead-free perovskite with a thickness of 1000 nm, and the perovskite coating method refers to Example 1. A second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation, which is an electron transport layer, using C60 as the electron transport layer material with a thickness of 50 nm.

[0059] The magnetron sputtering method is used to form an upper transparent electrode layer on the side of the second carrier transport layer away from the perovskite light absorption layer, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the perovskite-crystalline silicon stacked cell of this embodiment is 28.5%.

[0060] Example 4

[0061] Provide a HJT (heterojunction) solar cell with a P-type silicon wafer as the bottom cell, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all of which are deposited using PECVD with a total thickness of 13nm. PVD is used to deposit an ITO layer on the tunnel junction with a thickness of 3nm, and annealed at 190℃ for 30min after deposition.

[0062] A first carrier transport layer is prepared on the surface of the ITO layer, wherein the first carrier transport layer is a hole transport layer having a dendrite structure, which is PEDOT synthesized by a vapor phase method, the thickness of the first carrier transport layer is 100 nm, the dendrite structure is fibrous, the length is 800 nm, the diameter is 200 nm, and the surface coverage of the dendrite structure on the first carrier transport layer is 30%. The morphology, length, and diameter of the dendrite structure can be obtained by electron microscope observation, and the surface coverage can be obtained by a specific surface area analyzer.

[0063] A perovskite light absorption layer is coated on the surface of the first carrier transport layer away from the ITO layer, wherein the perovskite light absorption layer is made of Cs 4 Mn 1 -xCuxSb2 Cl 12 Perovskite, thickness is 1000nm. The perovskite coating method adopts dip coating method and will not be described in detail. The second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation method. It is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0064] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the perovskite-crystalline silicon stacked cell of this embodiment is 28.8%.

[0065] Example 5

[0066] Provide HJT (heterojunction) solar cells with N-type silicon wafers as the bottom cell, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all of which are deposited by PECVD, with a total thickness of 14nm. PVD is used to deposit an ITO layer on the tunnel junction, with a thickness of 18nm, and annealed at 190℃ for 30min after deposition.

[0067] A first carrier transport layer is prepared on the surface of the ITO layer, wherein the first carrier transport layer is a hole transport layer having a dendrite structure, which is PEDOT synthesized by a vapor phase method, the thickness of the first carrier transport layer is 100 nm, the dendrite structure is fibrous, the length is 600 nm, the diameter is 100 nm, and the surface coverage of the dendrite structure on the first carrier transport layer is 30%. The morphology, length, and diameter of the dendrite structure can be obtained by electron microscope observation, and the surface coverage can be obtained by a specific surface area analyzer.

[0068] A perovskite light absorption layer is coated on the surface of the first carrier transport layer away from the ITO layer, wherein the perovskite light absorption layer uses MAPbI3 perovskite with a thickness of 1000nm. The perovskite coating method adopts the dip coating method and is not described in detail. The second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation, which is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0069] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the perovskite-crystalline silicon stacked cell of this embodiment is 27.9%.

[0070] Comparative Example 1

[0071] An HJT (heterojunction) solar cell with an N-type silicon wafer is provided as a bottom cell. An ITO layer with a thickness of 5 nm is deposited on the n-side of the bottom cell by PVD, and annealed at 190° C. for 30 min after deposition.

[0072] A first carrier transport layer is prepared on the surface of the ITO layer, wherein the first carrier transport layer is a hole transport layer having a dendrite structure, which is PEDOT synthesized by a vapor phase method, the thickness of the first carrier transport layer is 100 nm, the dendrite structure is fibrous, the length is 500 nm, the diameter is 150 nm, and the surface coverage of the dendrite structure on the first carrier transport layer is 40%. The morphology, length, and diameter of the dendrite structure can be obtained by electron microscope observation, and the surface coverage can be obtained by a specific surface area analyzer.

[0073] A perovskite light absorption layer is coated on the surface of the first carrier transport layer away from the ITO layer, wherein the perovskite light absorption layer uses MAPbI3 perovskite with a thickness of 800nm. The perovskite coating method uses a dip coating method to immerse the crystalline silicon cell covered with the first carrier transport layer in a DMF solution of 1.5M MAPbI3 perovskite and pull it at a speed of 20mm / min. After the pulling is completed, it is dried at 100°C for 10 minutes to obtain the MAPbI3 perovskite light absorption layer. The second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation. It is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0074] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the perovskite-crystalline silicon stacked cell in this comparative example is 20.2%.

[0075] Comparative Example 2

[0076] Provide HJT (heterojunction) solar cells with N-type silicon wafers, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all using PECVD deposition, with a total thickness of 10nm.

[0077] A first carrier transport layer is prepared on the surface of the tunnel junction, wherein the first carrier transport layer is a hole transport layer having a dendrite structure, which is PEDOT synthesized by a gas phase method, the thickness of the first carrier transport layer is 100nm, the dendrite structure is fibrous, the length is 500nm, the diameter is 150nm, and the surface coverage of the dendrite structure on the first carrier transport layer is 40%. The morphology, length, and diameter of the dendrite structure can be observed by an electron microscope, and the surface coverage can be obtained by a specific surface area analyzer.

[0078] A perovskite light absorption layer is coated on the surface of the first carrier transport layer away from the tunnel junction, wherein the perovskite light absorption layer uses MAPbI3 perovskite with a thickness of 800nm. The perovskite coating method uses a dip coating method to immerse the crystalline silicon cell covered with the first carrier transport layer in a DMF solution of 1.5M MAPbI3 perovskite and pull it at a speed of 20mm / min. After the pulling is completed, it is dried at 100°C for 10 minutes to obtain the MAPbI3 perovskite light absorption layer. The second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation. It is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0079] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the perovskite-crystalline silicon stacked cell in this comparative example is 18.9%.

[0080] Comparative Example 3

[0081] Provide HJT (heterojunction) solar cells with P-type silicon wafers. Deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure. Both are deposited using PECVD with a total thickness of 15nm. PVD is used to deposit an ITO layer on the tunnel junction with a thickness of 15nm. After deposition, anneal at 190℃ for 30min.

[0082] A first carrier transport layer is prepared on the surface of the ITO layer, wherein the first carrier transport layer is an ordinary hole transport layer, which adopts PEDOT synthesized by a vapor phase method, and the thickness of the first carrier transport layer is 80nm. A perovskite light absorption layer is coated on the surface of the first carrier transport layer away from the ITO layer, wherein the perovskite light absorption layer adopts lead-free perovskite and has a thickness of 800nm. The perovskite coating method refers to comparative example 1. A second carrier transport layer is prepared by evaporation on the side of the perovskite light absorption layer away from the first carrier transport layer, which is an electron transport layer, and C60 is used as the electron transport layer material, with a thickness of 50 nm.

[0083] The magnetron sputtering method is used to form an upper transparent electrode layer on the side of the second carrier transport layer away from the perovskite light absorption layer, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the perovskite-crystalline silicon stacked cell in this comparative example is 21.8%.

[0084] Comparative Example 4

[0085] Provide an HJT (heterojunction) solar cell with an N-type silicon wafer as the bottom cell, deposit hydrogen-doped n-type microcrystalline silicon on the n-side of the bottom cell, and then deposit hydrogen-doped p-type microcrystalline silicon to form a tunnel junction structure, all of which are deposited using PECVD with a total thickness of 10nm. PVD is used to deposit an ITO layer on the tunnel junction with a thickness of 5nm, and annealed at 190℃ for 30min after deposition.

[0086] A first carrier transport layer is prepared on the surface of the ITO layer, wherein the first carrier transport layer is a hole transport layer having a single protruding structure, which is PEDOT synthesized by a vapor phase method, the thickness of the first carrier transport layer is 100 nm, the single protruding structure is fibrous, the length is 500 nm, the diameter is 150 nm, and the surface coverage of the single protruding structure on the first carrier transport layer is 40%. The morphology, length, and diameter of the single protruding structure can be observed by an electron microscope, and the surface coverage can be obtained by a specific surface area analyzer.

[0087] A perovskite light absorption layer is coated on the surface of the first carrier transport layer away from the ITO layer, wherein the perovskite light absorption layer uses MAPbI3 perovskite with a thickness of 800nm. The perovskite coating method uses a dip coating method to immerse the crystalline silicon cell covered with the first carrier transport layer in a DMF solution of 1.5M MAPbI3 perovskite and pull it at a speed of 20mm / min. After the pulling is completed, it is dried at 100°C for 10 minutes to obtain the MAPbI3 perovskite light absorption layer. The second carrier transport layer is prepared on the side of the perovskite light absorption layer away from the first carrier transport layer by evaporation. It is an electron transport layer, and C60 is used as the electron transport layer material with a thickness of 50nm.

[0088] The upper transparent electrode layer is formed on the side of the second carrier transport layer away from the perovskite light absorption layer by magnetron sputtering, wherein ITO is used as the upper transparent electrode with a thickness of 300nm; silver is deposited on the front and back sides as electrodes of the stacked cell, thus forming a complete perovskite / crystalline silicon stacked cell. The efficiency of the perovskite-crystalline silicon stacked cell in this comparative example is 25.9%.

[0089] It should be noted that, in the description of this application, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0090] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0091] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0092] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A perovskite-crystalline silicon tandem battery, characterized in that: The invention comprises a heterogeneous crystalline silicon cell, a tunnel junction, a conductive layer, a first carrier transport layer, a perovskite light absorption layer, a second carrier transport layer and a transparent electrode layer which are stacked in sequence, wherein the first carrier transport layer comprises a dendrite structure which faces and extends into the perovskite light absorption layer, and the length of the dendrite structure is less than the thickness of the perovskite light absorption layer.

2. The perovskite-crystalline silicon tandem cell according to claim 1, characterized in that: The dendrite structure is a fiber-like structure, a rod-like structure or a tubular structure.

3. The perovskite-crystalline silicon tandem cell according to claim 1, characterized in that: The coverage rate of the dendrite structure on the surface of the first carrier transport layer is 10-50%.

4. The perovskite-crystalline silicon tandem cell according to claim 1, characterized in that: The perovskite light absorption layer covers the first carrier transport layer and fills the gaps in the dendrite structure of the first carrier transport layer.

5. The perovskite-crystalline silicon tandem cell according to any one of claims 1 to 4, characterized in that: The heterogeneous crystalline silicon cell is of n-type or p-type.

6. The perovskite-crystalline silicon tandem cell according to claim 5, characterized in that: The structure of the tunnel junction is selected from at least one of a hydrogen-doped n-type microcrystalline silicon stacked with a hydrogen-doped p-type microcrystalline silicon structure, an oxygen-doped n-type amorphous silicon stacked with an oxygen-doped p-type amorphous silicon structure, and a microcrystalline silicon stacked with a silicon oxide structure.

7. The perovskite-crystalline silicon tandem cell according to claim 6, characterized in that: The thickness of the tunnel junction is 8-15 nm.

8. The perovskite-crystalline silicon tandem cell according to claim 5, characterized in that: The conductive layer has a thickness of 0.5-20 nm and a conductivity greater than 1500 S / m; And / or, the material of the conductive layer is metal oxide.

9. The perovskite-crystalline silicon tandem cell according to claim 5, characterized in that: The first carrier transport layer has a thickness of 20-120 nm and is selected from one of TiO2, SnO2, ZnO or one of PEDOT, PEDOT:PSS, P3HT, P3OHT, P3ODDT, PTAA, and NiO.

10. The perovskite-crystalline silicon tandem cell according to claim 5, characterized in that: The stacked cell further comprises metal electrodes respectively arranged on the heterogeneous crystalline silicon cell and the transparent electrode layer on a side away from the perovskite absorption layer.

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