Topcon cell structure and method of manufacturing the same
Patent Information
- Application Number
- CN202611210084.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-11
- Publication Date
- 2026-11-03
AI Technical Summary
The problems of easy oxidation of the gate layer and low photoelectric conversion efficiency in the Topcon cell structure are mainly due to the oxidation of the gate layer and the obstruction of carrier transport caused by the high-temperature preparation of the silicon nitride film.
The first and second antireflection layers are formed using low-temperature silicon nitride material. These layers are deposited on the outside of the gate layer using a low-temperature fabrication process (temperature less than 350°C) to protect the gate layer and avoid hindering carrier transport.
It effectively protects the gate layer from oxidation or corrosion, improves carrier transport efficiency, enhances photoelectric conversion efficiency, and reduces material costs.
Smart Images
Figure CN123035755A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of battery technology, specifically to a Topcon battery structure and its fabrication method. Background Technology
[0002] In Topcon cell structures, the process temperature for fabricating the silicon nitride film is typically above 350°C. If a copper-containing gate layer is formed first, followed by the silicon nitride film, the high temperature above 350°C will cause the copper-containing gate layer to oxidize, thereby damaging the gate layer's structure and conductivity. Therefore, related technologies can only fabricate the silicon nitride film first, followed by the gate layer. Furthermore, when a silicon nitride film exists between the gate layer and the substrate, the copper-containing gate layer has difficulty penetrating the silicon nitride film. This results in significant obstacles to carrier transport between the gate layer and the substrate due to the presence of the silicon nitride film, thus reducing the photoelectric conversion efficiency of the Topcon cell structure.
[0003] Therefore, the Topcon cell structure in related technologies suffers from technical problems such as easy oxidation of the gate layer and low photoelectric conversion efficiency. Summary of the Invention
[0004] The embodiments of this application provide a Topcon battery structure and its fabrication method, which can improve the technical problems of easy oxidation of the gate layer and low photoelectric conversion efficiency in related technologies.
[0005] In a first aspect, embodiments of this application provide a Topcon battery structure, comprising: The first substrate includes a first surface and a second surface located on both sides in the thickness direction; A first doped layer is disposed on the first surface of the first substrate; A first gate layer is disposed on the side of the first doped layer away from the first substrate; A first passivation layer is disposed on the side of the first gate layer away from the first substrate; The first antireflection layer is disposed on the side of the first passivation layer away from the first substrate; A second gate layer is disposed on the second surface of the first substrate; The second antireflection layer is disposed on the side of the second gate layer away from the first substrate; The first and second antireflection layers are made of low-temperature silicon nitride.
[0006] In one embodiment, the material used to fabricate the first gate layer includes copper, and / or the material used to fabricate the second gate layer includes copper.
[0007] In one embodiment, the thickness of the first antireflection layer and / or the second antireflection layer ranges from 50 nm to 120 nm, and the refractive index of the first antireflection layer and / or the second antireflection layer ranges from 1.8 to 2.1.
[0008] In one embodiment, the Topcon battery structure further includes a first through-hole, a second through-hole, and a welding portion. The first through-hole penetrates the first passivation layer and the first antireflection layer to expose the first gate layer, and the second through-hole penetrates the second antireflection layer to expose the second gate layer. The first gate layer and the second gate layer are electrically connected through the welding portion.
[0009] In one embodiment, the first gate layer includes a plurality of spaced-apart first gates, and the first antireflection layer covers at least a portion of the sidewalls of the first gates. The second gate layer includes a plurality of spaced-apart second gates, and the second antireflection layer covers at least a portion of the sidewalls of the second gates.
[0010] In one embodiment, the first surface includes a plurality of protrusions and a recess located between adjacent protrusions, the protrusions facing one side of the first antireflective layer.
[0011] In one embodiment, the material used to prepare the first passivation layer is aluminum oxide.
[0012] Secondly, embodiments of this application provide a Topcon battery structure, comprising: The second substrate includes a third surface and a fourth surface located on both sides in the thickness direction; A second doped layer is disposed on the third surface of the second substrate, and the second doped layer includes P-type emitters and N-type emitters arranged at intervals. A third gate layer is disposed on the side of the second doped layer away from the second substrate. The third gate layer includes a plurality of third gates, and one of the third gates is disposed opposite to and electrically connected to a P-type emitter or an N-type emitter. The third antireflection layer is disposed on the side of the third gate layer away from the second substrate; The material used to prepare the third antireflection layer is low-temperature silicon nitride.
[0013] Thirdly, embodiments of this application provide a method for fabricating a Topcon battery structure, used to fabricate a Topcon battery structure as described in any of the above embodiments, comprising: A first substrate is provided, and the first doped layer is prepared on the first surface of the first substrate; The first gate layer is formed on the side of the first doped layer away from the first substrate, and the second gate layer is formed on the second surface of the first substrate; The first passivation layer is prepared on the side of the first gate layer away from the first substrate; The first antireflection layer is prepared on the side of the first passivation layer away from the first substrate, and the second antireflection layer is prepared on the side of the second gate layer away from the first substrate. The materials for preparing the first antireflection layer and the second antireflection layer are low-temperature silicon nitride. The first gate layer and the second gate layer are electrically connected by laser drilling and low-temperature welding.
[0014] In one embodiment, the steps of fabricating the first antireflection layer and the second antireflection layer further include: Under reaction conditions ranging from 80°C to 350°C, a mixture of silane and ammonia is used for the reaction, wherein the gas flow rate ratio of silane to ammonia ranges from 1:3 to 1:1.5, the deposition rate of the first antireflection layer is from 2 nm / min to 15 nm / min, and the deposition rate of the second antireflection layer is from 2 nm / min to 15 nm / min.
[0015] The beneficial effects of the embodiments of this application are as follows: The first and second antireflective layers are formed using low-temperature silicon nitride. Because the low-temperature silicon nitride fabrication temperature does not easily cause oxidation of the first and second gate layers, the first antireflective layer can be disposed on the side of the first gate layer away from the first substrate, and the second antireflective layer can be disposed on the side of the second gate layer away from the first substrate. On one hand, the first and second antireflective layers protect the first and second gate layers, preventing corrosion or oxidation. On the other hand, because the first and second antireflective layers are located on the outside of the first and second gate layers, they do not obstruct the transport of charge carriers between the first substrate and the first and second gate layers, thereby improving the carrier transport efficiency. This alleviates the technical problems of easy oxidation of the gate layer and low photoelectric conversion efficiency in Topcon cell structures in related technologies. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a first cross-sectional schematic diagram of the Topcon battery structure provided in the embodiments of this application; Figure 2 This is a second cross-sectional schematic diagram of the Topcon battery structure provided in the embodiments of this application.
[0018] Explanation of reference numerals in the attached figures: 1. First substrate; 2. First doped layer; 3. First gate layer; 4. First passivation layer; 5. First antireflection layer; 6. Second gate layer; 7. Second antireflection layer; 8. Second substrate; 9. Second doped layer; 91. P-type emitter; 92. N-type emitter; 10. Third gate layer; 11. Third antireflection layer. Detailed Implementation
[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.
[0020] Furthermore, the terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms "multiple" and similar words indicate two or more unless otherwise expressly specified.
[0021] Firstly, please refer to Figure 1 The Topcon battery structure provided in the embodiments of this application includes a first substrate 1, a first doped layer 2, a first gate layer 3, a first passivation layer 4, a first antireflection layer 5, a second gate layer 6, and a second antireflection layer 7. The first substrate 1 includes a first surface and a second surface. The first doped layer 2 is disposed on the first surface of the first substrate 1, the first gate layer 3 is disposed on the side of the first doped layer 2 away from the first substrate 1, the first passivation layer 4 is disposed on the side of the first gate layer 3 away from the first substrate 1, the first antireflection layer 5 is disposed on the side of the first passivation layer 4 away from the first substrate 1, the second gate layer 6 is disposed on the second surface of the first substrate 1, and the second antireflection layer 7 is disposed on the side of the second gate layer 6 away from the first substrate 1. The first antireflection layer 5 and the second antireflection layer 7 are made of low-temperature silicon nitride.
[0022] The first doped layer 2 is formed by surface doping of the substrate 1, and the first doped layer 2 and the substrate 1 form a PN junction.
[0023] The first surface and the second surface are two surfaces of the first substrate 1 along the thickness direction.
[0024] It is understandable that the antireflection layer in related technologies can also be made of silicon nitride material, but it is not the low-temperature silicon nitride of this application. Since the temperature during the preparation of the antireflection layer is relatively high (greater than 350°C), if the gate layer is formed before the preparation of the antireflection layer, the high temperature during the preparation of the antireflection layer will easily cause the gate layer to be oxidized. Therefore, in related technologies, the antireflection layer is usually formed before the gate to avoid the gate being affected by high temperature.
[0025] It should be noted that since the first antireflection layer 5 and the second antireflection layer 7 are disposed outside the first gate layer 3 and the second gate layer 6, the first antireflection layer 5 and the second antireflection layer 7 will not hinder the transport of charge carriers between the first substrate 1 and the first gate layer 3 and the second gate layer 6, thereby improving the transport efficiency of charge carriers.
[0026] Based on the above principles, this application proposes a technical solution to form the first antireflection layer 5 and the second antireflection layer 7 using low-temperature silicon nitride as a material. By using low-temperature silicon nitride (preparation temperature less than 350°C), the first gate layer 3 and the second gate layer 6 can be formed first. After the fabrication processes of the first gate layer 3 and the second gate layer 6 are completed, the first antireflection layer 5 and the second antireflection layer 7 are then fabricated. The advantages of this technical solution are as follows: (1) The fabrication process of the first antireflection layer 5 and the second antireflection layer 7 is a low-temperature process, which will not affect the stability of the first gate layer 3 and the second gate layer 6; (i.e., avoid oxidation of the first gate layer 3 and the second gate layer 6 due to high temperature) (2) The first antireflection layer 5 is formed on the side of the first gate layer 3 away from the first substrate 1. The first antireflection layer 5 can cover the first gate layer 3 except for the welding hole position, thus protecting the first gate layer 3 and preventing the first gate layer 3 from being directly contacted with the outside world and corroded and oxidized. (3) Using existing process technology (only the order of the anti-reflection layer process and the gate layer process is adjusted), there is no need to prepare a protective film layer on the side of the first gate layer 3 and the second gate layer 6 away from the first substrate 1, without adding extra process, and the cost is lower.
[0027] In this embodiment, by forming the first antireflection layer 5 and the second antireflection layer 7 after the corresponding first gate layer 3 and second gate layer 6 processes, the first antireflection layer 5 and the second antireflection layer 7 protect the first gate layer 3 and the second gate layer 6, preventing the first gate layer 3 and the second gate layer 6 from being corroded or oxidized.
[0028] In one embodiment, the first gate layer 3 is made of copper, and / or the second gate layer 6 is made of copper.
[0029] The first gate layer 3 may include copper and silver, and the second gate layer 6 may also include copper and silver.
[0030] The mass percentage of copper in the first gate layer 3 can be from 5% to 95%, and the mass percentage of copper in the second gate layer 6 can be from 5% to 95%.
[0031] The mass percentage of copper in the first gate layer 3 can be any one of 5%, 50%, or 95%, and the mass percentage of copper in the second gate layer 6 can be any one of 5%, 50%, or 95%.
[0032] Understandably, copper, as a low-cost material, is more susceptible to oxidation and corrosion than silver. Since this application uses low-temperature silicon nitride to form the first antireflection layer 5 and the second antireflection layer 7, the first antireflection layer 5 and the second antireflection layer 7 can cover the first gate layer 3 and the second gate layer 6, thereby preventing the first gate layer 3 and the second gate layer 6 from being oxidized and corroded. This allows the first gate layer 3 and the second gate layer 6 to use copper, which is easily oxidized and corroded, as the preparation material, thereby reducing the material cost of the first gate layer 3 and the second gate layer 6.
[0033] In this embodiment, the mass percentage of copper in the materials used to prepare the first gate layer 3 and the second gate layer 6 is selected according to requirements. When cost reduction is a priority, copper with a higher mass percentage can be used as the main material to prepare the first gate layer 3 and the second gate layer 6.
[0034] In one embodiment, the thickness of the first antireflection layer 5 and / or the second antireflection layer 7 ranges from 50 nm to 120 nm, and the refractive index of the first antireflection layer 5 and / or the second antireflection layer 7 ranges from 1.8 to 2.1.
[0035] The thickness of the first antireflection layer 5 can be any one of 50nm, 80nm, or 120nm, and the thickness of the second antireflection layer 7 can be any one of 50nm, 80nm, or 120nm.
[0036] The refractive index of the first antireflective layer 5 can be any one of 1.8, 1.9, 2.0, or 2.1. The refractive index of the second antireflective layer 7 can be any one of 1.8, 1.9, 2.0, or 2.1.
[0037] It is understandable that the refractive index of the first antireflection layer 5 and the second antireflection layer 7 affects the surface reflection of light. When the refractive index is less than 1.8 or greater than 2.1, it will enhance surface reflection and thus reduce light absorption. For the Topcon battery structure, less light absorption will affect energy efficiency and result in low battery energy conversion efficiency.
[0038] It is understandable that when the thickness of the first antireflection layer 5 and the second antireflection layer 7 is less than 50nm, it will be too thin to properly cover and protect the underlying first gate layer 3 and the second gate layer 6. At the same time, a thickness of less than 50nm will also reduce the passivation effect of the interface, resulting in a decrease in the transport efficiency of charge carriers (holes and electrons). When the thickness of the first antireflection layer 5 and the second antireflection layer 7 is greater than 120nm, the excessive thickness of the first antireflection layer 5 and the second antireflection layer 7 will result in an excessively large overall film thickness of the Topcon battery structure, which is not conducive to achieving a thinner and lighter design.
[0039] In this embodiment, by limiting the refractive index and thickness of the first antireflection layer 5 and the second antireflection layer 7, the carrier transport efficiency is further increased while achieving a thinner and lighter design, thereby enhancing the energy conversion efficiency of the Topcon battery structure.
[0040] In one embodiment, the Topcon battery structure further includes a first through-hole, a second through-hole, and a welding portion. The first through-hole penetrates the first passivation layer 4 and the first antireflection layer 5 to expose the first gate layer 3, and the second through-hole penetrates the second antireflection layer 7 to expose the second gate layer 6. The first gate layer 3 and the second gate layer 6 are electrically connected through the welding portion.
[0041] The Topcon battery structure also has a tunneling oxide layer and a doped polysilicon layer on the second surface. The doped polysilicon layer includes a high-concentration doped region and a low-concentration doped region. The high-concentration doped region is corresponding to the second gate in the second gate layer 6. The tunneling oxide layer can be made of silicon dioxide and has a thickness ranging from 1 nm to 3 nm. The main function of the tunneling oxide layer is to allow electrons to tunnel through while blocking a few holes to achieve selective contact. The doped polysilicon layer is used to collect the tunneled electrons and transfer them to the second gate layer 6.
[0042] It is understandable that, since the first passivation layer 4 and the first antireflection layer 5 are formed on the side of the first gate layer 3 away from the first substrate 1, and the second antireflection layer 7 is formed on the side of the second gate layer 6 away from the first substrate 1, if it is necessary to electrically connect the first gate layer 3 and the second gate layer 6, a first via is required to expose the portion of the first gate layer 3 used for electrical connection, and a second via is required to expose the portion of the second gate layer 6 used for electrical connection; thereby enabling the Topcon battery structure to form a complete current path.
[0043] It is understandable that the first and second through holes can be formed by laser. The welding part can be a welding strip, one end of which is electrically connected to the first gate layer 3 and the other end is electrically connected to the second gate layer 6. The Topcon battery structure includes multiple battery parts, and the voltage generated by each battery part is relatively small. Multiple battery parts need to be connected in series through the welding part to form a larger voltage for use.
[0044] It should be noted that this embodiment does not add a drilling process. Related technologies require drilling even if the antireflection layer is placed on the side of the gate layer facing the substrate, so that the gate layer can be connected to the tunnel oxide layer and the doped polysilicon layer. In this application, the manufacturing process of the first antireflection layer 5 and the second antireflection layer 7 is placed after the manufacturing process of the first gate layer 3 and the second gate layer 6. Therefore, the corresponding drilling process is also placed after the manufacturing process of the first gate layer 3 and the second gate layer 6, and no additional drilling process is required.
[0045] In this embodiment, since the first antireflection layer 5 and the second antireflection layer 7 cover the first gate layer 3 and the second gate layer 6, the first gate layer 3 and the second gate layer 6 need to be drilled before they can be electrically connected through the solder joint. The area except for the first through hole and the second through hole is covered by the first antireflection layer 5 and the second antireflection layer 7, thereby effectively protecting the first gate layer 3 and the second gate layer 6.
[0046] In one embodiment, the first gate layer 3 includes a plurality of spaced-apart first gates, the first antireflection layer 5 is disposed to at least cover a portion of the sidewalls of the first gates, the second gate layer 6 includes a plurality of spaced-apart second gates, and the second antireflection layer 7 is disposed to at least cover a portion of the sidewalls of the second gates.
[0047] The first antireflective layer 5 can completely cover the sidewall of the first gate, and / or the second antireflective layer 7 can completely cover the sidewall of the second gate; this arrangement can better protect the first gate and the second gate, exposing only the parts of the first gate and the second gate used for soldering.
[0048] It is understood that the first gate may include a first sub-gate and a second sub-gate, which intersect in space and are selectively connected at the intersection. Similarly, the second gate may include a third sub-gate and a fourth sub-gate, which intersect in space and are selectively connected at the intersection.
[0049] In one embodiment, the first surface includes a plurality of protrusions and a recess located between adjacent protrusions, with the protrusions facing one side of the first antireflective layer 5.
[0050] The first surface can be configured with a serrated structure.
[0051] Among them, the first doped layer 2, the first gate layer 3, the first passivation layer 4 and the first antireflection layer 5 are designed to mimic the shape of the first surface. That is, the first doped layer 2, the first gate layer 3, the first passivation layer 4 and the first antireflection layer 5 also form similar protrusions at the protrusions of the corresponding first surface and similar depressions at the concave parts of the corresponding first surface.
[0052] Understandably, the design of the convex and concave portions causes light rays incident on the first surface to undergo multiple reflections and refractions between the convex and concave portions, thereby greatly increasing the path length of light transmission within the Topcon cell structure. This allows more light to be absorbed by the Topcon cell structure instead of being directly reflected back into the air; in other words, the design of the convex and concave portions is to reduce surface reflection. Because the first doped layer 2, the first gate layer 3, the first passivation layer 4, and the first antireflection layer 5 are contoured to the first surface, light undergoes multiple reflections and refractions between any of these layers, further enhancing light absorption.
[0053] It should be noted that since the second surface of the first substrate 1 needs to have a passivation effect (i.e., the surface needs to be smoother, as an uneven surface can easily trap electrons and reduce the transmission efficiency), the second surface can be polished to make it smooth and flat. Similarly, the surface of the tunneling oxide layer and the doped polysilicon layer can also be planarized to improve the electron transmission efficiency.
[0054] In this embodiment, a protrusion and a recess are formed on the first surface of the first substrate 1. The protrusion and the recess are used to make each film layer subsequently prepared on the first surface corresponding to the protrusion and the recess, so that the light is reflected and refracted multiple times between the protrusion and the recess, thereby increasing the path length of the light transmission inside the Topcon battery structure and thus enhancing the absorption of light.
[0055] In one embodiment, the first passivation layer 4 is made of aluminum oxide.
[0056] The thickness of the first passivation layer 4 ranges from 2 nm to 6 nm.
[0057] The thickness of the first passivation layer 4 can be any one of 2nm, 4nm, or 6nm.
[0058] It is understandable that when the thickness of the first passivation layer 4 is less than 2nm, it may cause the first passivation layer 4 to be discontinuous, thus failing to effectively cover the first doped layer 2 below. At the same time, it may also lead to an insufficient number of negative electrons in the first passivation layer 4, resulting in an inability to effectively repel electrons from the first doped layer 2 to move toward the first passivation layer 4. When the thickness of the first passivation layer 4 is greater than 6nm, not only will the excessive thickness increase the process time and cost, but it will also increase the absorption of light by the first passivation layer 4, thus causing some light to fail to reach the first substrate 1 and affecting the light absorption efficiency of the Topcon battery structure.
[0059] It is understandable that the first passivation layer 4 is used to passivate the first doped layer 2. Since there are a large number of negative charges on the inner wall of the alumina material, it repels the electrons of the lower first doped layer 2 to move toward the first passivation layer 4, thus preventing electrons from running to the side of the first doped layer 2 away from the first substrate 1 to recombine, thereby reducing the surface recombination rate of the first doped layer 2.
[0060] It should be noted that the first passivation layer 4 and the first antireflection layer 5 can be prepared using the same process. Therefore, they can both be prepared after the formation of the first gate layer 3. This eliminates the need to prepare the first passivation layer 4 and the first antireflection layer 5 separately in two steps, which can reduce the number of processes.
[0061] Secondly, please refer to Figure 2 Another Topcon battery structure provided in the embodiments of this application includes a second substrate 8, a second doped layer 9, a third gate layer 10, and the second substrate 8 includes a third surface and a fourth surface located on both sides in the thickness direction. The second doped layer 9 is disposed on the third surface of the second substrate 8 and includes P-type emitters 91 and N-type emitters 92 arranged at intervals. The third gate layer 10 is disposed on the side of the second doped layer 9 away from the second substrate 8 and includes a plurality of third gates. A third gate is disposed opposite to and electrically connected to a P-type emitter 91 or an N-type emitter 92. A third antireflection layer 11 is disposed on the side of the third gate layer 10 away from the second substrate 8. The material of the third antireflection layer 11 is low-temperature silicon nitride.
[0062] In this embodiment, since both the P-type emitter 91 and the N-type emitter 92 are disposed on the same side of the second substrate 8 (i.e., one side of the third surface), no other passivation film layer and gate layer are disposed on the fourth surface side, which reduces the shading rate on the fourth surface side and improves the light absorption efficiency; at the same time, the fourth surface is smooth and flat, making the Topcon battery structure more aesthetically pleasing.
[0063] In one embodiment, the third antireflection layer 11 is doped with conductive particles.
[0064] In particular, by doping with conductive particles, the third antireflection layer 11 can enhance conductivity and lateral carrier collection capabilities.
[0065] It is understandable that the doping concentration of the third antireflection layer 11 in the thickness direction can be set in a gradient. That is, the doping concentration is lower on the side closer to the second substrate 8 to passivate the substrate, while the doping concentration is relatively higher on the side farther from the second substrate 8 to achieve the function of lateral carrier collection.
[0066] Thirdly, embodiments of this application provide a method for fabricating a Topcon battery structure, used to fabricate a Topcon battery structure as described in any of the above embodiments, the method comprising: S1: A first substrate 1 is provided, and a first doped layer 2 is prepared on the first surface of the first substrate 1; S2: A first gate layer 3 is formed on the side of the first doped layer 2 away from the first substrate 1, and a second gate layer 6 is formed on the second surface of the first substrate 1; S3: A first passivation layer 4 is prepared on the side of the first gate layer 3 away from the first substrate 1; S4: A first antireflection layer 5 is prepared on the side of the first passivation layer 4 away from the first substrate 1, and a second antireflection layer 7 is prepared on the side of the second gate layer 6 away from the first substrate 1. The materials for preparing the first antireflection layer 5 and the second antireflection layer 7 are low-temperature silicon nitride. S5: The first gate layer 3 and the second gate layer 6 are electrically connected by laser drilling and low-temperature welding.
[0067] In step S1, any one of the following first substrates 1 can be selected: crystalline silicon wafer, heterojunction silicon wafer, or flexible photovoltaic substrate. The first substrate 1 also needs to undergo multi-stage cleaning and drying to ensure that the film layer prepared subsequently has good adhesion to the first substrate 1, which facilitates the preparation of the subsequent film layer.
[0068] In step S2, low-temperature copper paste or silver-coated copper paste can be used for screen printing to form the first gate layer 3 and the second gate layer 6. Specifically, a high-precision screen printing process is used to uniformly print the low-temperature copper paste or silver-coated copper paste on the surface of the pretreated first substrate 1 according to a preset pattern to form the first gate layer 3 and the second gate layer 6. The paste is then cured and dried.
[0069] In step S4, an inductively coupled plasma chemical vapor deposition (ICP-CVD) device can be used to deposit low-temperature silicon nitride layers on the first and second surfaces, respectively, to form the first antireflection layer 5 and the second antireflection layer 7.
[0070] In step S5, a high-precision laser device can be used to locally ablate and open the first antireflection layer 5 and the second antireflection layer 7 covering the first gate layer 3 and the second gate layer 6 according to the preset welding points, so as to form the first through hole and the second through hole.
[0071] In step S5, the welding part coated with low-temperature solder is aligned with the formed first through hole and second through hole, and low-temperature welding is performed to make the first gate layer 3 and the second gate layer 6 electrically connected.
[0072] In one embodiment, the steps of preparing the first antireflection layer 5 and the second antireflection layer 7 further include: Under reaction conditions with a temperature range of 80℃ to 350℃, silane and ammonia are mixed for the reaction, wherein the gas flow ratio of silane to ammonia ranges from 1:3 to 1:1.5, the deposition rate of the first antireflection layer 5 is from 2nm / min to 15nm / min, and the deposition rate of the second antireflection layer 7 is from 2nm / min to 15nm / min.
[0073] The temperature can be selected from any of the following: 80℃, 150℃, 250℃, and 350℃.
[0074] The ratio of silane to ammonia gas flow rate can be any one of 1:3, 1:2, or 1:1.5.
[0075] The deposition rate of the first antireflection layer 5 is any one of 2nm / min, 6nm / min, 10nm / min, and 15nm / min.
[0076] The deposition rate of the second antireflection layer 7 is any one of 2 nm / min, 6 nm / min, 10 nm / min, and 15 nm / min.
[0077] It is understandable that when the temperature is below 80°C, the gas decomposes incompletely and the deposition rate is extremely low; when the temperature is above 350°C, the copper in the first gate layer 3 and the second gate layer 6 is easily oxidized.
[0078] In this embodiment, the temperature range is 80°C to 350°C, which ensures that the first gate layer 3 and the second gate layer 6 are not oxidized or damaged; the gas flow ratio of silane to ammonia is 1:3 to 1:1.5, which allows the refractive index of the first antireflection layer 5 and the second antireflection layer 7 to be maintained in the optimal antireflection range of 1.8 to 2.1; and the deposition rate of the first antireflection layer 5 and the second antireflection layer 7 is in the range of 2 nm / min to 15 nm / min, which is to balance improving the film quality of the first antireflection layer 5 and the second antireflection layer 7 with mass production efficiency.
[0079] This application provides a Topcon battery structure that uses low-temperature silicon nitride to form the first antireflection layer 5 and the second antireflection layer 7, ensuring that the temperature during the fabrication of the first antireflection layer 5 and the second antireflection layer 7 does not exceed 350°C, thereby reducing the oxidation and damage to the first gate layer 3 and the second gate layer 6. This inventive concept allows for more possibilities in the stacking order of the film layers in the Topcon battery structure. By fabricating the first gate layer 3 and the second gate layer 6 first, and then fabricating the first antireflection layer 5 and the second antireflection layer 7, the first antireflection layer 5 and the second antireflection layer 7 can also act as protective layers covering the outside of the first gate layer 3 and the second gate layer 6, thus protecting the first gate layer 3 and the second gate layer 6.
[0080] Based on the above design, the first gate layer 3 and the second gate layer 6 can be made of pure copper material, or the first gate layer 3 and the second gate layer 6 can be made of silver-clad copper material, thereby reducing material costs.
[0081] Meanwhile, this application also discloses a Topcon battery structure, in which the P-type emitter 91, the N-type emitter 92 and the corresponding third gate layer 10 are all disposed on the third surface of the second substrate 8, so that the fourth surface on the other side of the second substrate 8 does not need to be provided with other film layers, thereby enhancing the absorption of light by the fourth surface.
[0082] In addition, this application also discloses a method for preparing a Topcon battery structure, specifically disclosing that a mixture of silane and ammonia is used to react at a reaction temperature of 80°C to 350°C to prepare a low-temperature silicon nitride film layer; thereby making the first antireflection layer 5 and the second antireflection layer 7 made of low-temperature silicon nitride.
[0083] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A Topcon battery structure, characterized in that, include: The first substrate (1) includes a first surface and a second surface located on both sides in the thickness direction; A first doped layer (2) is disposed on the first surface of the first substrate (1); The first gate layer (3) is disposed on the side of the first doped layer (2) away from the first substrate (1); The first passivation layer (4) is disposed on the side of the first gate layer (3) away from the first substrate (1); The first antireflection layer (5) is disposed on the side of the first passivation layer (4) away from the first substrate (1); A second gate layer (6) is disposed on the second surface of the first substrate (1); The second antireflection layer (7) is disposed on the side of the second gate layer (6) away from the first substrate (1); The first antireflection layer (5) and the second antireflection layer (7) are made of low-temperature silicon nitride.
2. The Topcon battery structure according to claim 1, characterized in that, The first gate layer (3) is made of copper and silver, and / or the second gate layer (6) is made of copper and silver.
3. The Topcon battery structure according to claim 1, characterized in that, The thickness of the first antireflection layer (5) and / or the second antireflection layer (7) ranges from 50 nm to 120 nm, and the refractive index of the first antireflection layer (5) and / or the second antireflection layer (7) ranges from 1.8 to 2.
1.
4. The Topcon battery structure according to claim 1, characterized in that, The Topcon battery structure further includes a first through hole, a second through hole, and a welding part. The first through hole penetrates the first passivation layer (4) and the first antireflection layer (5) to expose the first gate layer (3). The second through hole penetrates the second antireflection layer (7) to expose the second gate layer (6). The first gate layer (3) and the second gate layer (6) are electrically connected through the welding part.
5. The Topcon battery structure according to claim 4, characterized in that, The first gate layer (3) includes a plurality of spaced first gates, the first antireflection layer (5) covers at least a portion of the sidewalls of the first gates, the second gate layer (6) includes a plurality of spaced second gates, and the second antireflection layer (7) covers at least a portion of the sidewalls of the second gates.
6. The Topcon battery structure according to claim 1, characterized in that, The first surface includes a plurality of protrusions and a recess located between adjacent protrusions, the protrusions being on one side facing the first antireflective layer (5).
7. The Topcon battery structure according to claim 1, characterized in that, The first passivation layer (4) is made of aluminum oxide.
8. A Topcon battery structure, characterized in that, include: The second substrate (8) includes a third surface and a fourth surface located on both sides in the thickness direction; The second doped layer (9) is disposed on the third surface of the second substrate (8), and the second doped layer (9) includes P-type emitters (91) and N-type emitters (92) arranged at intervals. The third gate layer (10) is disposed on the side of the second doped layer (9) away from the second substrate (8). The third gate layer (10) includes a plurality of third gates, and one of the third gates is disposed opposite to and electrically connected to a P-type emitter (91) or an N-type emitter (92). The third antireflection layer (11) is disposed on the side of the third gate layer (10) away from the second substrate (8); The material used to prepare the third antireflection layer (11) is low-temperature silicon nitride.
9. A method for fabricating a Topcon battery structure, used to fabricate the Topcon battery structure as described in any one of claims 1 to 7, characterized in that, include: A first substrate (1) is provided, and the first doped layer (2) is prepared on the first surface of the first substrate (1). The first gate layer (3) is formed on the side of the first doped layer (2) away from the first substrate (1), and the second gate layer (6) is formed on the second surface of the first substrate (1); the first passivation layer (4) is formed on the side of the first gate layer (3) away from the first substrate (1). The first antireflection layer (5) is prepared on the side of the first passivation layer (4) away from the first substrate (1), and the second antireflection layer (7) is prepared on the side of the second gate layer (6) away from the first substrate (1). The materials for preparing the first antireflection layer (5) and the second antireflection layer (7) are low-temperature silicon nitride. The first gate layer (3) and the second gate layer (6) are electrically connected by laser drilling and low-temperature welding.
10. The method for fabricating a Topcon battery structure according to claim 9, characterized in that, The steps of preparing the first antireflection layer (5) and the second antireflection layer (7) further include: Under reaction conditions with a temperature range of 80°C to 350°C, silane and ammonia are mixed for the reaction, wherein the ratio of the gas flow rates of silane to ammonia is in the range of 1:3 to 1:1.5, the deposition rate of the first antireflection layer (5) is 2 nm / min to 15 nm / min, and the deposition rate of the second antireflection layer (7) is 2 nm / min to 15 nm / min.