Back contact photovoltaic cell and method of manufacture, photovoltaic module and photovoltaic system

Abstract

The application relates to the technical field of photovoltaic cells, and discloses a back contact photovoltaic cell and a preparation method thereof, a photovoltaic module and a photovoltaic system. The cell comprises a crystalline silicon substrate, at least one amorphous layer, the amorphous layer being located inside the crystalline silicon substrate and close to the front surface of the crystalline silicon substrate, the back surface of the crystalline silicon substrate comprising alternately distributed first areas and second areas, and the first areas and the second areas being separated by an isolation area, a first electrode being located in the first areas, and a second electrode being located in the second areas. When hot carriers excited by high-energy photons pass through the amorphous layer, efficient collision ionization is triggered, a plurality of secondary electron-hole pairs are generated, the residual energy of the high-energy photons is converted into additional photocurrent, the photovoltaic conversion efficiency of the cell is improved, and the thermal relaxation loss of the high-energy photons is reduced. In addition, the substrate of the back contact cell is a crystalline silicon substrate, so the back contact cell is compatible with the conventional crystalline silicon cell process.

Description

Technical Field

[0001] This application relates to the field of photovoltaic cell technology, and more specifically, to a back-contact photovoltaic cell and its preparation method, a photovoltaic module and a photovoltaic system. Background Technology

[0002] Crystalline silicon photovoltaic cells are semiconductor devices that utilize the photovoltaic effect of crystalline silicon to directly convert light energy into electrical energy, and are currently the mainstream product in the photovoltaic market. At present, the photoelectric conversion efficiency of single-junction silicon cells is approaching the theoretical limit of single-junction cells—the Shockley-Quyther limit (approximately 29.4%).

[0003] One of the key bottlenecks limiting further efficiency improvements is the thermal relaxation loss from high-energy photons. In the solar spectrum, photons with energies higher than the silicon band gap (approximately 1.12 eV) are absorbed, and the excess energy is rapidly converted into lattice thermal vibrations through processes such as phonon scattering, failing to contribute to electrical output. It is estimated that thermal relaxation loss accounts for more than 25% of the total solar incident energy, the highest proportion among all energy loss channels, far exceeding the losses caused by Auger recombination, surface recombination, and series resistance.

[0004] To improve the utilization of high-energy photons, current technologies include tandem solar cells, which use multiple sub-cells with different bandgapes for hierarchical absorption. However, this method has poor compatibility with existing production lines.

[0005] Therefore, how to further improve battery efficiency by utilizing high-energy photons while maintaining compatibility with existing crystalline silicon technology should be a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] This application provides a back-contact photovoltaic cell and its preparation method, a photovoltaic module and a photovoltaic system, which can improve the efficiency of the cell while being compatible with existing crystalline silicon technology.

[0007] In a first aspect, a back-contact photovoltaic cell is provided, comprising: Crystalline silicon substrate; At least one amorphous layer is located inside the crystalline silicon substrate and close to the front side of the crystalline silicon substrate; The back side of the crystalline silicon substrate includes alternating first and second regions, with an isolation region distributed between the first and second regions, and the first and second regions having opposite polarities. The first electrode is located in the first region; The second electrode is located in the second region.

[0008] The back-contact photovoltaic cell provided in this embodiment has at least one amorphous layer disposed inside a crystalline silicon substrate, near the front side of the substrate. When hot carriers excited by high-energy photons pass through the amorphous layer, they trigger efficient collisional ionization, generating multiple secondary electron-hole pairs, thereby converting the remaining energy of the high-energy photons into additional photocurrent. In other words, this application converts energy that would otherwise be dissipated as heat into additional photocurrent, improving the cell's photoelectric conversion efficiency while reducing thermal relaxation losses from high-energy photons. Furthermore, the photovoltaic cell in this embodiment is a back-contact cell with a crystalline silicon substrate, therefore, the photovoltaic cell in this embodiment is compatible with conventional crystalline silicon cell processes.

[0009] In some embodiments, the amorphous layer is 0.2 μm to 2 μm away from the front surface of the crystalline silicon substrate.

[0010] If the distance between the amorphous layer and the front side of the crystalline silicon substrate is less than 0.2 μm, the distance is too small and can easily lead to high recombination of surface defects. If the distance between the amorphous layer and the front side of the crystalline silicon substrate is greater than 2 μm, the distance is too large and does not match the absorption depth of high-energy photons. The remaining energy of the high-energy photons cannot be converted into additional photocurrent, or the converted photocurrent is very small, which cannot effectively reduce the thermal relaxation loss of high-energy photons.

[0011] In some embodiments, the amorphous layer ranges from 2 nm to 20 nm.

[0012] Since the amorphous layer is amorphous and the crystalline silicon substrate is crystalline, if the thickness of the amorphous layer is too large (greater than 20nm), it will introduce defects into the crystalline silicon substrate, affecting the photoelectric conversion efficiency of the battery.

[0013] In some embodiments, the forming ions of the amorphous layer include any one or any combination of the following ions: Silicon ions, germanium ions, carbon ions, argon ions, xenon ions.

[0014] The implanted ions are any one or any combination of silicon ions, germanium ions, carbon ions, argon ions, and xenon ions. The above ions are implanted into the interior of crystalline silicon to form an amorphous layer of ultrathin amorphous silicon buried layer, which promotes the multiplication of low-energy electrons. When the hot carriers (electrons) excited by high-energy photons pass through this region, they trigger efficient collisional ionization, generating multiple secondary electron-hole pairs, thereby converting the remaining energy of the high-energy photons into additional photocurrent.

[0015] In some embodiments, the amorphous layer is one layer.

[0016] When the number of amorphous layers is one, the fabrication process of back-contact photovoltaic cells can be simplified.

[0017] In some embodiments, the number of amorphous layers is at least two, and the crystalline silicon substrate is located between adjacent amorphous layers.

[0018] Since crystalline silicon is crystalline and the amorphous layer is amorphous, a periodic amorphous / crystalline superlattice structure can be formed in this embodiment to enhance the electron multiplication probability, thereby further improving the photoelectric conversion efficiency of the battery.

[0019] Secondly, a method for preparing a back-contact photovoltaic cell is provided, comprising: Prepare a crystalline silicon substrate; Ions are implanted into the interior of the crystalline silicon substrate from the front side, and annealed in an inert atmosphere to form at least one amorphous layer; wherein the implanted ions include one or any combination of silicon ions, germanium ions, carbon ions, argon ions, and xenon ions. A first electrode is formed in a first region on the back side of the crystalline silicon substrate, and a second electrode is formed in a second region on the back side of the crystalline silicon substrate. The back side of the crystalline silicon substrate includes alternating first and second regions, and an isolation region is distributed between the first and second regions. The first and second regions have opposite polarities.

[0020] In this embodiment, the back-contact photovoltaic cell is fabricated inside a crystalline silicon substrate, with at least one amorphous layer near the front surface of the substrate. When hot carriers excited by high-energy photons pass through the amorphous layer, they trigger efficient collisional ionization, generating multiple secondary electron-hole pairs. This converts the remaining energy of the high-energy photons into additional photocurrent. In other words, this application converts energy that would otherwise be dissipated as heat into additional photocurrent, improving the cell's photoelectric conversion efficiency while reducing thermal relaxation losses from high-energy photons. Furthermore, the photovoltaic cell fabricated in this embodiment is a back-contact cell with a crystalline silicon substrate, making it compatible with conventional crystalline silicon cell processes.

[0021] In some embodiments, when ions are implanted from the front side of the crystalline silicon substrate into the interior of the crystalline silicon substrate, the implantation dose is 1×10⁻⁶. 14 ~5×10 15 / cm 2 The implantation depth is 0.2 μm to 2 μm from the front surface of the crystalline silicon substrate; In this process, when ions are implanted into the interior of the crystalline silicon substrate from the front side and annealed in an inert atmosphere to form at least one amorphous layer, the annealing temperature is lower than the crystallization temperature of the amorphous layer.

[0022] By controlling the injection dose and injection depth, amorphous layers with a thickness of 2nm to 20nm can be obtained.

[0023] Thirdly, a photovoltaic module is provided, comprising: a back-contact photovoltaic cell as described in any of the above.

[0024] Fourthly, a photovoltaic system is provided, including the photovoltaic modules described above. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the back-contact photovoltaic cell provided in this application. Figure 1 ; Figure 2 This is a schematic diagram of the structure of the back-contact photovoltaic cell provided in this application. Figure 2 ; Figure 3 This is a flowchart of the back-contact photovoltaic cell fabrication method provided in this application; Figure 4 This is a schematic diagram of the photovoltaic module provided in this application; Figure 5 This is an exploded view of the photovoltaic module provided in this application; Figure 6 This is a schematic diagram of the photovoltaic system provided in this application; The accompanying drawings are not drawn to scale.

[0026] Reference numerals: 1. Crystalline silicon substrate; 2. Amorphous layer; 3. First electrode; 4. Second electrode; 5. Type I structure; 51. First dielectric layer; 52. Type I polycrystalline silicon layer; 53. Mask layer; 6. Type II structure; 61. Second dielectric layer; 62. Type II polycrystalline silicon layer; 63. Type II hydrogenated amorphous silicon layer; 7. Intrinsic hydrogenated amorphous silicon layer; 8. Transparent conductive layer; 9. First passivation layer; 10. Front cover plate; 11. First antireflection layer; 12. Second antireflection layer; 13. Second passivation layer; 1000. Photovoltaic system; 100. Photovoltaic module; 20. First encapsulating film; 30. Cell string layer; 40. Second encapsulating film; 50. Back cover plate; 60. Frame; 70. Junction box. Detailed Implementation

[0027] The descriptions of specific structures or functions implemented according to the concept of this application disclosed in this specification are merely illustrative examples for explaining embodiments based on the concept of this application. Those skilled in the art will understand that embodiments based on the concept of this application can have various variations and forms, and are not limited to the embodiments described in this specification, but also include various modifications, equivalents, or substitutions made within the scope of the purpose, concept, and technology of this application.

[0028] In the description of this application, it should be understood that the use of terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" indicates the relative orientation or positional relationship between different components, and is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0029] Although the terms "first" or "second" may be used to describe various components or components, the components or components should not be limited by the terms. The terms above are used only for the purpose of distinguishing one component or component from another. For example, without departing from the scope of the claims according to the concept of this application, a first battery cell may be referred to as a second battery cell, and similarly, a second battery cell may be referred to as a first battery cell.

[0030] In this application, unless otherwise expressly specified and limited, the terms "connected," "fixed," "set," etc., should be interpreted broadly. For example, when one component is said to "connect" another component, it should be understood that it can be directly or indirectly connected to the other component, meaning that other components may also be present in between. Similarly, the terms "fixed" and "set" should be interpreted broadly in a similar way. Furthermore, the term "connected" can refer to a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. In this application, unless otherwise expressly specified and limited, the description of "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. The first feature being "below", "under", or "below" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0031] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0032] The researchers involved in this application have discovered that, in order to improve the utilization of high-energy photons, the current technology employed is a tandem cell method: absorbing photons in stages through multiple sub-cells with different band gaps. However, this method has poor compatibility with existing production lines.

[0033] Based on this, this application provides a back-contact photovoltaic cell, please refer to... Figure 1 and Figure 2 The battery may include: Crystalline silicon substrate 1; At least one amorphous layer 2 is located inside the crystalline silicon substrate 1 and close to the front side of the crystalline silicon substrate 1; The back side of the crystalline silicon substrate 1 includes an alternately distributed first region S1 and a second region S2, and an isolation region S3 is distributed between the first region S1 and the second region S2. The first region S1 and the second region S2 have opposite polarities. The first electrode 3 is located in the first region S1; The second electrode 4 is located in the second region S2.

[0034] The crystalline silicon substrate 1 can be an N-type crystalline silicon substrate 1 with a resistivity of 0.5~5Ω·cm and a thickness of 100μm~200μm.

[0035] In this application, the front side of the back contact photovoltaic cell has no doped layer (no emitter), and the carriers are collected entirely by the first electrode 3 and the second electrode 4 on the back side, thereby eliminating the influence of front doping on the amorphous layer 2.

[0036] The atoms in amorphous layer 2 are arranged in a disordered state, which is the amorphous state.

[0037] The role of amorphous layer 2 is to achieve low-energy electron multiplication. When hot carriers (electrons) excited by high-energy photons pass through amorphous layer 2, they will trigger efficient collisional ionization, generating multiple secondary electron-hole pairs, thereby converting the remaining energy of high-energy photons into additional photocurrent.

[0038] The amorphous layer 2 is formed by implanting ions into the crystalline silicon substrate 1, causing the silicon to arrange in a disordered manner and then annealing at a low temperature. Furthermore, the implanted ions cannot be high recombination centers of silicon, nor can they be deep-level defect ions.

[0039] In one embodiment of this application, the ions forming the amorphous layer 2 include any one or any combination of the following ions: Silicon ions, germanium ions, carbon ions, argon ions, xenon ions.

[0040] The implanted ions are any one or any combination of silicon ions, germanium ions, carbon ions, argon ions, and xenon ions. The above ions are implanted into the interior of crystalline silicon to form an amorphous layer of ultrathin amorphous silicon buried layer, which promotes the multiplication of low-energy electrons. When the hot carriers (electrons) excited by high-energy photons pass through this region, they trigger efficient collisional ionization, generating multiple secondary electron-hole pairs, thereby converting the remaining energy of the high-energy photons into additional photocurrent.

[0041] The density, defect state density, and recrystallization temperature of the amorphous layer 2 can be adjusted by injecting ions into the crystalline silicon substrate 1.

[0042] It should be noted that this application does not limit the distance between the amorphous layer 2 and the front side of the crystalline silicon substrate 1 (i.e., the depth of the amorphous layer 2), but depends on the specific circumstances.

[0043] As one possible implementation, the distance between the amorphous layer 2 and the front surface of the crystalline silicon substrate 1 can be 0.2 μm to 2 μm. If the distance between the amorphous layer 2 and the front surface of the crystalline silicon substrate 1 is less than 0.2 μm, the distance is too small, which can easily lead to high recombination of surface defects. If the distance between the amorphous layer 2 and the front surface of the crystalline silicon substrate 1 is greater than 2 μm, the distance is too large and does not match the absorption depth of high-energy photons. The remaining energy of the high-energy photons cannot be converted into additional photocurrent, or the converted photocurrent is very small, which cannot effectively reduce the thermal relaxation loss of high-energy photons.

[0044] The specific value of the distance between the amorphous layer 2 and the positive surface of the crystalline silicon substrate 1 can be adjusted according to the incident spectrum. For example, when the depth of the amorphous layer 2 is less than 0.5 μm, the blue light response can be enhanced, and when the depth of the amorphous layer 2 is greater than 1 μm, the green or red light response can be enhanced.

[0045] It should be noted that the number of amorphous layer 2 is not limited in this application and can be set by the user.

[0046] As one possible implementation, the amorphous layer 2 is a single layer, which can simplify the fabrication process of the back contact photovoltaic cell.

[0047] As another possible implementation, the number of amorphous layers 2 is at least two, and the space between adjacent amorphous layers 2 is a crystalline silicon substrate 1.

[0048] Since crystalline silicon is crystalline and amorphous layer 2 is amorphous, this embodiment can form periodic amorphous and crystalline superlattice structures, enhancing the electron multiplication probability and thus further improving the photoelectric conversion efficiency of the battery.

[0049] It should be noted that the thickness range of the amorphous layer 2 is not limited in this application and depends on the specific circumstances.

[0050] The thickness of the amorphous layer 2 can range from 2nm to 20nm. For example, the thickness of the amorphous layer 2 can be 2nm, 4nm, 8nm, 10nm, 14nm, 16nm, 20nm, etc.

[0051] Since the amorphous layer 2 is amorphous and the crystalline silicon substrate 1 is crystalline, if the thickness of the amorphous layer 2 is too large (greater than 20nm), it will introduce defects into the crystalline silicon substrate 1, affecting the photoelectric conversion efficiency of the battery.

[0052] In one embodiment of this application, the back-contact photovoltaic cell may further include a first passivation layer 9 and a first antireflection layer 11, located on the front side of the crystalline silicon substrate 1.

[0053] The first passivation layer 9 can be an aluminum oxide layer, and the first antireflection layer 11 can be a silicon nitride layer, etc.

[0054] By setting the first passivation layer 9, surface recombination can be reduced, thereby increasing the open-circuit voltage and short-circuit current of the battery; reducing the reflectivity of light on the front side allows more light to enter the battery, which can excite more photogenerated carriers, thus increasing the short-circuit current density. The first anti-reflection layer 11 can reduce light reflection, allowing more light energy to enter the battery and improving the battery conversion efficiency.

[0055] In one embodiment of this application, the front side of the crystalline silicon substrate 1 has a textured structure. The textured structure can increase the number of reflections and refractions of light on the front side of the crystalline silicon substrate 1, thereby increasing the amount of light entering the battery and increasing light absorption, which in turn effectively improves the short-circuit current density of the battery.

[0056] The first region S1 and the second region S2 are designated as P-region and N-region, respectively. The specific structure of the first region S1 and the second region S2 depends on the type of back-contact photovoltaic cell.

[0057] Please refer to Figure 4 In one embodiment of this application, when the back contact photovoltaic cell is a cell in which both the first region S1 and the second region S2 are passivated contact structures, the first region S1 includes a first type structure 5, which includes a first dielectric layer 51 and a first type polycrystalline silicon layer 52 stacked on the back side of the crystalline silicon substrate 1; the second region S2 includes a second type structure 6, which includes a second dielectric layer 61 and a second type polycrystalline silicon layer 62 stacked on the back side of the crystalline silicon substrate 1, wherein the doping types of the first type polycrystalline silicon layer 52 and the second type polycrystalline silicon layer 62 are opposite.

[0058] The first dielectric layer 51 and the second dielectric layer 61 can be silicon dioxide layers.

[0059] Of the first type polycrystalline silicon layer 52 and the second type polycrystalline silicon layer 62, one is a P-type polycrystalline silicon layer and the other is an N-type polycrystalline silicon layer.

[0060] The first type structure 5 and the second type structure 6 serve as tunneling passivation contact structures, enabling efficient passivation and selective carrier transport, thereby improving battery conversion efficiency.

[0061] The first electrode 3 is electrically connected to the first type of polysilicon layer 52, and the second electrode 4 is electrically connected to the second type of polysilicon layer 62.

[0062] As one possible implementation, the back-contact photovoltaic cell may further include: The second passivation layer 13 and the second antireflection layer 12 are stacked on the back side. The second passivation layer 13 can suppress minority carrier recombination near the first electrode 3 and the second electrode 4, thereby avoiding the deterioration of the fill factor and open circuit voltage. The second antireflection layer 12 can reduce light reflection, allowing more light energy to enter the battery and improve the battery conversion efficiency.

[0063] The second passivation layer 13 can be an aluminum oxide layer, and the second antireflection layer 12 can be a silicon nitride layer, etc.

[0064] The second passivation layer is located on the surface of the first type polysilicon layer 52 and the second type polysilicon layer 62.

[0065] Please refer to Figure 5 In one embodiment of this application, when the back-contact photovoltaic cell is a dual-structure cell with a back heterojunction and a passivated contact, the first region S1 includes a first type structure 5. The first type structure 5 includes a first dielectric layer 51, a first type polycrystalline silicon layer 52, a mask layer 53, an intrinsic hydrogenated amorphous silicon layer 7, a second type hydrogenated amorphous silicon layer 63, and a transparent conductive layer 8 stacked on the back side of the crystalline silicon substrate 1. The intrinsic hydrogenated amorphous silicon layer 7 and the second type hydrogenated amorphous silicon layer 63 have openings, and the transparent conductive layer 8 is distributed on the surface of the first type polycrystalline silicon layer 52 corresponding to the openings. The second region S2 includes a second type structure 6. The second type structure 6 includes an intrinsic hydrogenated amorphous silicon layer 7, a second type hydrogenated amorphous silicon layer 63, and a transparent conductive layer 8 stacked on the back side of the crystalline silicon substrate 1. Figure 5 The example shown uses the first region S1 as region N and the second region S2 as region P.

[0066] The first electrode 3 is electrically connected to the first type polycrystalline silicon layer 52 through the transparent conductive layer 8 at the opening; the second electrode 4 is electrically connected to the second type hydrogenated amorphous silicon layer 63 through the transparent conductive layer 8 and the intrinsic hydrogenated amorphous silicon layer 7.

[0067] The first type polycrystalline silicon layer 52 and the second type hydrogenated amorphous silicon layer 63 have opposite doping types; one is P-type doped and the other is N-type doped. For example, the first type polycrystalline silicon layer 52 is an N-type polycrystalline silicon layer, and the second type hydrogenated amorphous silicon layer 63 is a P-type hydrogenated amorphous silicon layer.

[0068] The mask layer 53 can be silicon nitride, which serves to passivate the first region S1.

[0069] The transparent conductive layer 8 can be an indium tin oxide layer.

[0070] The transparent conductive layer 8 has the function of conducting electricity, and also has a similar function to the passivation layer, which can play a protective and anti-reflective role.

[0071] In this embodiment, the back-contact photovoltaic cell is located inside a crystalline silicon substrate 1, with at least one amorphous layer 2 disposed near the front side of the crystalline silicon substrate 1. When hot carriers excited by high-energy photons pass through the amorphous layer 2, they trigger efficient collisional ionization, generating multiple secondary electron-hole pairs, thereby converting the remaining energy of the high-energy photons into additional photocurrent. In other words, this application converts energy that would otherwise be dissipated as heat into additional photocurrent, improving the cell's photoelectric conversion efficiency while reducing the thermal relaxation loss of high-energy photons. Furthermore, since the photovoltaic cell in this embodiment is a back-contact cell and the substrate is a crystalline silicon substrate 1, the photovoltaic cell in this embodiment is compatible with conventional crystalline silicon cell processes.

[0072] This application also provides a method for preparing a back-contact photovoltaic cell; please refer to [reference needed]. Figure 3 The method may include: Step S101: Prepare a crystalline silicon substrate.

[0073] The crystalline silicon substrate can be an N-row crystalline silicon substrate that has been cleaned and polished.

[0074] Step S102: A first-type structure is fabricated in a first region on the back side of the crystalline silicon substrate, a second-type structure is fabricated in a second region on the back side of the crystalline silicon substrate, and an isolation region is formed between the first region and the second region, with the first region and the second region having opposite polarities.

[0075] The fabrication of the first and second type structures differs depending on the type of back-contact photovoltaic cell. The following explanation is based on the type of back-contact photovoltaic cell.

[0076] As one possible implementation, when the back contact photovoltaic cell is a cell where both the first and second regions are passivated contact structures, a first type structure is fabricated in the first region on the back side of the crystalline silicon substrate, a second type structure is fabricated in the second region on the back side of the crystalline silicon substrate, and an isolation region is formed between the first and second regions, including: Step S1021a: A first dielectric layer and a first intrinsic polysilicon layer are stacked on the back side of a crystalline silicon substrate; the back side of the crystalline silicon substrate includes alternating first and second regions.

[0077] The first dielectric layer can be a silicon dioxide layer, which can be formed by oxidation.

[0078] The first intrinsic polycrystalline silicon layer can be formed using LPCVD (Low Pressure Chemical Vapor Deposition).

[0079] Step S1022a: Doping the first intrinsic polysilicon layer to form a first type polysilicon layer.

[0080] The doping method can be diffusion doping. When the first polysilicon layer is a P-type polysilicon layer, the doping is P-type doping, and the doping element can be boron, etc.

[0081] Step S1023a: Remove the first dielectric layer and the first type polysilicon layer located in the second region.

[0082] This step can use etching to remove the first dielectric layer and the first type polysilicon layer in the second region.

[0083] Step S1024a: Form a stacked second dielectric layer and a second intrinsic polysilicon layer in the second region.

[0084] The second dielectric layer can be a silicon dioxide layer, which can be formed by oxidation.

[0085] The second intrinsic polysilicon layer can be formed using LPCVD.

[0086] Step S1025a: Doping the second intrinsic polysilicon layer to form a second type polysilicon layer.

[0087] The doping method can be diffusion doping. When the second polysilicon layer is an N-type polysilicon layer, the doping is N-type doping, and the doping element can be phosphorus, etc.

[0088] Step S1026a: Etch the area between the first and second regions to form an isolation zone.

[0089] As another possible implementation, when the back-contact photovoltaic cell is a dual-structure cell with a back-side heterojunction and a passivated contact, a first-type structure is fabricated in a first region on the back side of the crystalline silicon substrate, a second-type structure is fabricated in a second region on the back side of the crystalline silicon substrate, and an isolation region is formed between the first and second regions, including: Step S1021b: A first dielectric layer and a first intrinsic polysilicon layer are stacked on the back side of a crystalline silicon substrate; the back side of the crystalline silicon substrate includes alternating first and second regions.

[0090] The first dielectric layer can be a silicon dioxide layer, which can be formed by oxidation.

[0091] The first intrinsic polycrystalline silicon layer can be formed using LPCVD.

[0092] Step S1022b: Doping the first intrinsic polysilicon layer to form a first type polysilicon layer.

[0093] The doping method can be diffusion doping. When the first polysilicon layer is an N-type polysilicon layer, the doping is N-type doping, and the doping element can be phosphorus, etc.

[0094] Step S1023b: Remove the first dielectric layer and the first type polysilicon layer located in the second region.

[0095] This step can use etching to remove the first dielectric layer and the first type polysilicon layer in the second region.

[0096] Step S1024b: Fabricate intrinsic hydrogenated amorphous silicon layers on the front and back sides of the crystalline silicon substrate, respectively.

[0097] It should be noted that in the actual production process, steps S1024b to S1027b are performed after the amorphous layer is formed. For ease of explanation, the formation of the first type structure and the second type structure are described together in this application.

[0098] The intrinsic hydrogenated amorphous silicon layer can be produced using methods such as PECVD (Plasma Enhanced Chemical Vapor Deposition), and its thickness can be 5 nm.

[0099] The intrinsic hydrogenated amorphous silicon layer is deposited on both the front and back sides.

[0100] Step S1025b: Fabricate a second type of hydrogenated amorphous silicon layer on the surface of the intrinsic hydrogenated amorphous silicon layer located on the back side of the crystalline silicon substrate.

[0101] An intrinsic hydrogenated amorphous silicon layer is deposited on the entire back side of the substrate, and then doped to form a second type of hydrogenated amorphous silicon layer.

[0102] Doping can be p-type doping, and the doping element can be boron, etc.

[0103] Step S1026b: Etch the second type hydrogenated amorphous silicon layer and the intrinsic hydrogenated amorphous silicon layer located in the first region to form an opening.

[0104] The purpose of forming the opening is to fabricate a first electrode within the opening, which is electrically connected to a type-1 polysilicon layer through a transparent conductive layer.

[0105] Step S1027b: Deposit a transparent conductive layer on the back side of the crystalline silicon substrate. The transparent conductive layer can be fabricated by sputtering, and its thickness can be 65nm~85nm.

[0106] Step S1028b: Form an isolation zone between the first zone and the second zone.

[0107] In one embodiment of this application, after a first type structure is formed in a first region on the back side of the crystalline silicon substrate and a second type structure is formed in a second region on the back side of the crystalline silicon substrate, the process may further include forming a first passivation layer on the front side of the crystalline silicon substrate.

[0108] The first passivation layer can be an aluminum oxide layer and / or a silicon nitride layer, etc.

[0109] The first passivation layer can be fabricated using methods such as PECVD (Plasma Enhanced Chemical Vapor Deposition) or ALD (Atomic Layer Deposition).

[0110] By creating a first passivation layer, surface recombination can be reduced, thereby increasing the open-circuit voltage and short-circuit current of the battery. Reducing the reflectivity of light on the front side allows more light to enter the battery, which can excite more photogenerated carriers, thus increasing the short-circuit current density.

[0111] Step S103: Ions are implanted into the interior of the crystalline silicon substrate from the front side, and annealed in an inert atmosphere to form at least one amorphous layer; wherein the implanted ions include one or any combination of silicon ions, germanium ions, carbon ions, argon ions, and xenon ions.

[0112] The inert atmosphere can be nitrogen. The annealing temperature is lower than the crystallization temperature of the amorphous layer.

[0113] As one possible implementation, when implanting ions from the front side of a crystalline silicon substrate into the interior of the substrate, the implantation dose is 1×10⁻⁶. 14 ~5×10 15 / cm 2 The implantation depth is 0.2 μm to 2 μm from the front side of the crystalline silicon substrate; In the process of implanting ions into the interior of the crystalline silicon substrate from the front side and annealing it in an inert atmosphere to form at least one amorphous layer, the annealing temperature is lower than the crystallization temperature of the amorphous layer.

[0114] By controlling the injection dose and injection depth, amorphous layers with a thickness of 2nm to 20nm can be obtained.

[0115] The purpose of annealing is to repair the implanted damaged parts, but at the same time, the amorphous silicon layer needs to be preserved. Therefore, the annealing temperature must be controlled to be lower than the crystallization temperature of the amorphous layer.

[0116] The crystallization temperature of the amorphous layer is higher than the recrystallization temperature threshold of the crystalline silicon substrate, and the amorphous state of the amorphous layer can be selectively retained by controlling the thermal budget.

[0117] The annealing temperature can be 400℃~600℃, and the annealing time can be 1 second~60 seconds.

[0118] It should be noted that this application does not limit the method of annealing and can be chosen at one's own discretion.

[0119] As one possible implementation method, annealing includes performing annealing using any one of rapid thermal annealing, laser annealing, and microwave annealing.

[0120] In one embodiment of this application, before implanting ions into the interior of the crystalline silicon substrate from the front side, the process may further include texturing the front side of the crystalline silicon substrate.

[0121] By texturing, the front side of the crystalline silicon substrate is made into a textured structure. The textured structure can increase the number of reflections and refractions of light on the front side of the crystalline silicon substrate, thereby increasing the amount of light entering the battery and increasing light absorption, which in turn effectively improves the short-circuit current density of the battery.

[0122] In one embodiment of this application, when the back contact photovoltaic cell is a passivated contact cell, after ions are implanted into the interior of the crystalline silicon substrate from the front side and annealed in an inert atmosphere to form at least one amorphous layer, the process may further include forming a second passivation layer on the back side.

[0123] By fabricating a second passivation layer, minority carrier recombination near the first and second electrodes can be suppressed, thereby avoiding deterioration of the fill factor and open-circuit voltage.

[0124] Step S104: Fabricate a first electrode in the first region and a second electrode in the second region.

[0125] The fabrication of the first and second electrodes can refer to existing technologies, and will not be described in detail here.

[0126] In this embodiment, the back-contact photovoltaic cell is fabricated inside a crystalline silicon substrate, with at least one amorphous layer near the front surface of the substrate. When hot carriers excited by high-energy photons pass through the amorphous layer, they trigger efficient collisional ionization, generating multiple secondary electron-hole pairs. This converts the remaining energy of the high-energy photons into additional photocurrent. In other words, this application converts energy that would otherwise be dissipated as heat into additional photocurrent, improving the cell's photoelectric conversion efficiency while reducing thermal relaxation losses from high-energy photons. Furthermore, the photovoltaic cell fabricated in this embodiment is a back-contact cell with a crystalline silicon substrate, making it compatible with conventional crystalline silicon cell processes.

[0127] The fabrication method of this application will be described below using different back-contact photovoltaic cells as examples.

[0128] Example 1: The back contact photovoltaic cell is a cell in which both the first and second regions have passivated contact structures, and the number of amorphous layers is one.

[0129] Step 1: Select an N-type single crystal silicon wafer (resistivity 3~20Ω·cm, thickness 100μm~200μm), polish and clean it to obtain a crystalline silicon substrate.

[0130] Step 2: Pre-oxidize the back side of the crystalline silicon substrate to form a silicon dioxide layer, denoted as the first dielectric layer.

[0131] Step 3: Deposit a first intrinsic polysilicon layer with a thickness of 100nm~300nm on the surface of the first dielectric layer.

[0132] Step 4: Boron-doped first intrinsic polysilicon layer to obtain P-type polysilicon layer, denoted as first polysilicon layer, with sheet resistance of 100Ω / sq~200Ω / sq.

[0133] Step 5: Perform the first graphic processing and modify or open the BSG locally (outside the P area).

[0134] Step 6: Wet etching and cleaning to remove the P-type polysilicon layer and silicon dioxide layer outside the P-region, and polishing the laser-modified area from Step 5.

[0135] Step 7: Oxidize the area outside the P-region on the back side to form a silicon dioxide layer, denoted as the second dielectric layer.

[0136] Step 8: Deposit a second intrinsic polysilicon layer with a thickness of 50nm~200nm on the surface of the second dielectric layer.

[0137] Step 9: Phosphorus diffusion doping is performed on the second intrinsic polysilicon layer to obtain an N-type polysilicon layer, denoted as the second polysilicon layer, with a sheet resistance of 30Ω / sq~100Ω / sq.

[0138] Step 10: Perform a second patterning process to modify or open the PSG in the isolation zone between the P and N regions.

[0139] Step 11: Perform etching and texturing to achieve texturing of the front side and etching of the isolation area.

[0140] Step 12: Perform Si formation from the front side of the crystalline silicon substrate. + Ion implantation, implantation energy 80 keV, dose 5×10 14 / cm 2 The peak injection depth is about 0.5 μm, forming an amorphous damage layer with a thickness of about 10 nm, which serves as the amorphous layer.

[0141] Step 13: Rapidly heat anneal at 550°C for 30 seconds in a N2 atmosphere to repair the crystalline portion while retaining the amorphous layer.

[0142] Step 14: Deposit an aluminum oxide layer and a silicon nitride layer stack on the front and back sides as the first passivation layer and the second passivation layer (alumina layer thickness 3nm~5nm, silicon nitride layer thickness 70nm~90nm).

[0143] Step 15: Screen print paste in the P and N regions and sinter it to form back interdigitated electrodes, which are referred to as the first electrode and the second electrode, respectively.

[0144] Step 16, Hydrogen passivation photothermal treatment (100mW / cm) 2 (200℃) to obtain a back-contact photovoltaic cell.

[0145] Example 2: The back-contact photovoltaic cell is a dual-structure cell with a back heterojunction and a passivated contact, and the number of amorphous layers is two.

[0146] Step 1: Select an N-type single crystal silicon wafer (resistivity 0.5~20Ω·cm, thickness 100μm~200μm), polish and clean it to obtain a crystalline silicon substrate.

[0147] Step 2: Pre-oxidize the back side of the crystalline silicon substrate to form a silicon dioxide layer, denoted as the first dielectric layer.

[0148] Step 3: Deposit a first intrinsic polysilicon layer with a thickness of 50nm~200nm on the surface of the first dielectric layer.

[0149] Step 4: Phosphorus diffusion doping is performed on the first intrinsic polycrystalline silicon layer to obtain an N-type polycrystalline silicon layer, denoted as the first polycrystalline silicon layer, with a sheet resistance of 30Ω / sq~100Ω / sq.

[0150] Step 5: Deposit a mask layer on the back and front sides, and perform the first patterning process on the area outside the N area to achieve patterned opening of the surface mask.

[0151] Step 6: Perform etching and texturing to achieve texturing of the front side and P area.

[0152] Step 7, Two-stage ion implantation: First implantation of Si + Injected energy 50 keV, injection dose 3×10 14 / cm 2 Second injection of Ar + Injected energy 120keV, injection dose 1×10 15 / cm 2 Two amorphous layers are formed, located at distances of 0.3 μm and 0.9 μm from the front surface, respectively, with thicknesses of approximately 8 nm and 15 nm.

[0153] Step 8: Perform rapid thermal annealing at 550°C for 30 seconds in a N2 atmosphere to repair the crystalline portion while retaining the two amorphous layers.

[0154] Step 9: PECVD is used to deposit an intrinsic hydrogenated amorphous silicon layer (ia-Si:H) on the front and back sides of the crystalline silicon substrate, with a thickness of 5 nm.

[0155] Step 10: Fabricate a p-type hydrogenated amorphous silicon layer (p-type) on the surface of the intrinsic hydrogenated amorphous silicon layer located on the back side. + a-Si:H), with a thickness of 5nm~30nm.

[0156] Step 11: Perform laser delamination in the N-region metal gate contact area to form an opening, with the bottom of the opening being an N-type polycrystalline silicon layer.

[0157] Step 12: Sputter a transparent conductive layer onto the entire back side.

[0158] Step 13: Use a laser to isolate the P-region and N-region to form an isolation zone.

[0159] Step 14: Screen print silver electrodes and cure them at low temperature to form the first electrode and the second electrode. The curing temperature is ≤200℃.

[0160] Example 3: The back contact photovoltaic cell is a cell in which both the first and second regions have passivated contact structures, and the number of amorphous layers is one.

[0161] Step 1: Select an N-type single crystal silicon wafer (resistivity 3~20Ω·cm, thickness 100μm~200μm), polish and clean it to obtain a crystalline silicon substrate.

[0162] Step 2: Pre-oxidize the back side of the crystalline silicon substrate to form a silicon dioxide layer, denoted as the first dielectric layer.

[0163] Step 3: Deposit a first intrinsic polysilicon layer with a thickness of 100nm~300nm on the surface of the first dielectric layer.

[0164] Step 4: Boron-doped first intrinsic polysilicon layer to obtain P-type polysilicon layer, denoted as first polysilicon layer, with sheet resistance of 100Ω / sq~200Ω / sq.

[0165] Step 5: Perform the first graphic processing and modify or open the BSG locally (outside the P area).

[0166] Step 6: Wet etching and cleaning to remove the P-type polysilicon layer and silicon dioxide layer outside the P-region, and polishing the laser-modified area from Step 5.

[0167] Step 7: Oxidize the area outside the P-region on the back side to form a silicon dioxide layer, denoted as the second dielectric layer.

[0168] Step 8: Deposit a second intrinsic polysilicon layer with a thickness of 50nm~200nm on the surface of the second dielectric layer.

[0169] Step 9: Phosphorus diffusion doping is performed on the second intrinsic polysilicon layer to obtain an N-type polysilicon layer, denoted as the second polysilicon layer, with a sheet resistance of 30Ω / sq~100Ω / sq.

[0170] Step 10: Perform a second patterning process to modify or open the PSG in the isolation zone between the P and N regions.

[0171] Step 11: Perform etching and texturing to achieve texturing of the front side and etching of the isolation area.

[0172] Step 12: Perform germanium ion implantation from the front side of the crystalline silicon substrate at an implantation energy of 80 keV and a dose of 5 × 10⁻⁶. 14 / cm 2 The peak injection depth is about 1.2 μm, forming an amorphous damage layer with a thickness of about 12 nm, which serves as the amorphous layer.

[0173] Step 13: Rapidly heat anneal at 550°C for 30 seconds in a N2 atmosphere to repair the crystalline portion while retaining the amorphous layer.

[0174] Step 14: Deposit an aluminum oxide layer and a silicon nitride layer stack on the front and back sides as the first passivation layer and the second passivation layer (alumina layer thickness 3nm~5nm, silicon nitride layer thickness 70nm~90nm).

[0175] Step 15: Screen print paste in the P and N regions and sinter it to form back interdigitated electrodes, which are referred to as the first electrode and the second electrode, respectively.

[0176] Step 16, Hydrogen passivation photothermal treatment (100mW / cm) 2 (200℃) to obtain a back-contact photovoltaic cell.

[0177] Example 4: The back contact photovoltaic cell is a cell in which both the first and second regions have passivated contact structures, and the number of amorphous layers is one.

[0178] Step 1: Select an N-type single crystal silicon wafer (resistivity 3~20Ω·cm, thickness 100μm~200μm), polish and clean it to obtain a crystalline silicon substrate.

[0179] Step 2: Pre-oxidize the back side of the crystalline silicon substrate to form a silicon dioxide layer, denoted as the first dielectric layer.

[0180] Step 3: Deposit a first intrinsic polysilicon layer with a thickness of 100nm~300nm on the surface of the first dielectric layer.

[0181] Step 4: Boron-doped first intrinsic polysilicon layer to obtain P-type polysilicon layer, denoted as first polysilicon layer, with sheet resistance of 100Ω / sq~200Ω / sq.

[0182] Step 5: Perform the first graphic processing and modify or open the BSG locally (outside the P area).

[0183] Step 6: Wet etching and cleaning to remove the P-type polysilicon layer and silicon dioxide layer outside the P-region, and polishing the laser-modified area from Step 5.

[0184] Step 7: Oxidize the area outside the P-region on the back side to form a silicon dioxide layer, denoted as the second dielectric layer.

[0185] Step 8: Deposit a second intrinsic polysilicon layer with a thickness of 50nm~200nm on the surface of the second dielectric layer.

[0186] Step 9: Phosphorus diffusion doping is performed on the second intrinsic polysilicon layer to obtain an N-type polysilicon layer, denoted as the second polysilicon layer, with a sheet resistance of 30Ω / sq~100Ω / sq.

[0187] Step 10: Perform a second patterning process to modify or open the PSG in the isolation zone between the P and N regions.

[0188] Step 11: Perform etching and texturing to achieve texturing of the front side and etching of the isolation area.

[0189] Step 12: Xenon ion implantation is performed from the front side of the crystalline silicon substrate at an implantation energy of 80 keV and a dose of 5 × 10⁻⁶ kilometres per second. 14 / cm 2 The peak implantation depth is about 1.7 μm, forming an amorphous damage layer with a thickness of about 18 nm, which serves as the amorphous layer.

[0190] Step 13: Rapidly heat anneal at 550°C for 30 seconds in a N2 atmosphere to repair the crystalline portion while retaining the amorphous layer.

[0191] Step 14: Deposit an aluminum oxide layer and a silicon nitride layer stack on the front and back sides as the first passivation layer and the second passivation layer (alumina layer thickness 3nm~5nm, silicon nitride layer thickness 70nm~90nm).

[0192] Step 15: Screen print paste in the P and N regions and sinter it to form back interdigitated electrodes, which are referred to as the first electrode and the second electrode, respectively.

[0193] Step 16, Hydrogen passivation photothermal treatment (100mW / cm) 2 (200℃) to obtain a back-contact photovoltaic cell.

[0194] Comparative Example 1: The back-contact photovoltaic cell is a cell with passivated contact structure in both the first and second regions, and the number of amorphous layers is one.

[0195] Step 1: Select an N-type single crystal silicon wafer (resistivity 3~20Ω·cm, thickness 100μm~200μm), polish and clean it to obtain a crystalline silicon substrate.

[0196] Step 2: Pre-oxidize the back side of the crystalline silicon substrate to form a silicon dioxide layer, denoted as the first dielectric layer.

[0197] Step 3: Deposit a first intrinsic polysilicon layer with a thickness of 100nm~300nm on the surface of the first dielectric layer.

[0198] Step 4: Boron-doped first intrinsic polysilicon layer to obtain P-type polysilicon layer, denoted as first polysilicon layer, with sheet resistance of 100Ω / sq~200Ω / sq.

[0199] Step 5: Perform the first graphic processing and modify or open the BSG locally (outside the P area).

[0200] Step 6: Wet etching and cleaning to remove the P-type polysilicon layer and silicon dioxide layer outside the P-region, and polishing the laser-modified area from Step 5.

[0201] Step 7: Oxidize the area outside the P-region on the back side to form a silicon dioxide layer, denoted as the second dielectric layer.

[0202] Step 8: Deposit a second intrinsic polysilicon layer with a thickness of 50nm~200nm on the surface of the second dielectric layer.

[0203] Step 9: Phosphorus diffusion doping is performed on the second intrinsic polysilicon layer to obtain an N-type polysilicon layer, denoted as the second polysilicon layer, with a sheet resistance of 30Ω / sq~100Ω / sq.

[0204] Step 10: Perform a second patterning process to modify or open the PSG in the isolation zone between the P and N regions.

[0205] Step 11: Perform etching and texturing to achieve texturing of the front side and etching of the isolation area.

[0206] Step 12: Perform Si formation from the front side of the crystalline silicon substrate. + Ion implantation, implantation energy 80 keV, dose 5×10 14 / cm 2 The peak implantation depth is about 15 μm, forming an amorphous damage layer with a thickness of about 0.5 nm, which serves as the amorphous layer.

[0207] Step 13: Rapidly heat anneal at 550°C for 30 seconds in a N2 atmosphere to repair the crystalline portion while retaining the amorphous layer.

[0208] Step 14: Deposit an aluminum oxide layer and a silicon nitride layer stack on the front and back sides as the first passivation layer and the second passivation layer (alumina layer thickness 3nm~5nm, silicon nitride layer thickness 70nm~90nm).

[0209] Step 15: Screen print paste in the P and N regions and sinter it to form back interdigitated electrodes, which are referred to as the first electrode and the second electrode, respectively.

[0210] Step 16, Hydrogen passivation photothermal treatment (100mW / cm) 2 (200℃) to obtain a back-contact photovoltaic cell.

[0211] The electrical performance parameters of the battery cells prepared in the above embodiments and comparative examples are shown in Table 1.

[0212] Table 1

[0213] As shown in Table 1, compared with Comparative Example 1, the conversion efficiency Eta, open-circuit voltage Voc, short-circuit current Isc, and filling shadow FF of the cells in Examples 1 to 4 of this application are all improved, indicating that the setting of the amorphous layer converts the remaining energy of high-energy photons into additional photocurrent, thereby improving the performance of the cells.

[0214] The performance of the solar cells was tested in the following ways: I. Preparatory work before testing 1. Battery cell cleaning, including: Wipe the surface of the battery cells with ultrapure water, ethanol or isopropanol to remove fingerprints, dust and organic residues; After drying the solar cells with nitrogen, let them stand for 10 minutes to avoid surface contamination affecting their optical properties.

[0215] 2. Electrode contact inspection, including: Use a four-wire probe (such as the Keithley 2400 series) to perform electrical measurements on the solar cells, ensuring that the contact resistance between the metal electrodes of the solar cells and the probe is <0.1Ω; Use silver paste or spring probes to secure the battery cells and avoid pressure damage.

[0216] 3. Stabilization treatment, including: The solar cells were aged under standard light (1000W / m²) for 1 hour to eliminate light-induced degradation (LID). The temperature of the solar cells was maintained at 25℃±0.5℃ using a constant temperature stage to avoid the impact of thermal effects on carrier mobility.

[0217] 4. Equipment calibration, including: The light source spectrum was calibrated using a standard reference cell to conform to the AM1.5G standard spectral conditions, with a calibration wavelength range of 300 nm to 1200 nm. The irradiance uniformity deviation in the test area does not exceed ±2%, and the measurement error of the temperature sensor used is less than ±0.1℃.

[0218] II. Testing Equipment and Conditions

[0219] 1. Core equipment

[0220] IV tester: Keysight B2900A series, with a voltage resolution of 0.1mV and a current resolution of 0.1μA; Solar simulator: Class AAA compliant, with selectable pulsed or steady-state light source (e.g., Wacom WXS-200S-20). Temperature control console: Temperature regulation is achieved based on a thermoelectric cooling (TEC) module, with a control accuracy of ±0.2℃; Spectral response instrument: equipped with a quantum efficiency (QE) testing system (such as Bentham PVE300).

[0221] 2. Standard Test Conditions (STC)

[0222] Irradiance: 1000W / m² (AM1.5G standard spectrum); Temperature: 25℃±1℃ (real-time monitoring via TEC module); Light spot uniformity: The uniformity of the light spot covering the effective area of ​​the battery is >95%.

[0223] III. Key Parameter Testing Procedures

[0224] 1. Conversion efficiency (Eta) and IV characteristics (Voc, Isc, FF) testing

[0225] Test equipment: solar simulator, IV tester and four-wire probe.

[0226] step: (1) Sample placement: Place the battery cell in the center of the light spot of the simulator, and use a light shield to block the edge of the battery cell by 5mm to avoid light leakage at the edge; (2) IV scan: Apply a scan voltage from -0.5V to Voc+0.5V through an IV tester, set the scan step size to 10mV, and record the IV characteristic curve of the battery simultaneously; (3) Parameter extraction: Extract the open-circuit voltage Voc (voltage when current = 0) and short-circuit current Isc (current when voltage = 0) from the IV curve; (4) Calculation of power and fill factor: Calculate the maximum power point (Pmax=Vmpp×Impp) and fill factor FF=Pmax / (Voc×Isc) on the IV curve; (5) Efficiency calculation: The conversion efficiency Eta = (Pmax / Pin) × 100% is calculated, where the incident light power Pin is calibrated by a calibrated standard cell.

[0227] like Figure 4 and Figure 5 As shown, this application provides a photovoltaic module 100, which is a device that directly converts light energy into electrical energy through the photoelectric effect or photochemical effect. The photovoltaic module 100 is generally a stacked encapsulation structure, which includes at least the following from the light-facing side to the backlight side: a front cover plate 10, a first encapsulating film 20, a cell string layer 30, a second encapsulating film 40, and a back cover plate 50, as well as a frame 60 arranged around the periphery of the stacked structure and a junction box 70 disposed on one side of the back cover plate 50.

[0228] The front cover 10 may be made of a material with excellent light transmittance, impact resistance, corrosion resistance, and weather resistance, and may optionally include at least one of the following materials: tempered glass, plexiglass, transparent ceramics, organic fibers, or polymers. In some embodiments, the front cover 10 may include at least one of an insulating barrier layer, a fluorinated weather-resistant layer, and a transition adhesive layer.

[0229] The back cover 50 typically needs to possess insulation, water resistance, aging resistance, weather resistance, and corrosion resistance, and may optionally include at least one of the following composite back covers with tempered glass, plexiglass, metal back cover, or PET film as the substrate. The PET-based composite back cover may, depending on the needs of different scenarios, include various types such as composite (e.g., TPT / KPK, TPE / KPE), coated (e.g., TPC, KPC, CPC), and co-extruded (e.g., PO).

[0230] It is understandable that the material selection of the front cover plate 10 and the back cover plate 50 does not affect each other, and the same or different materials can be selected according to different application scenarios of the components (such as residential photovoltaics and building-integrated photovoltaics).

[0231] The first encapsulating film 20 and the second encapsulating film 40 can be selected from at least one of ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, EVA-POE-EVA co-extruded film (EPE), PVB (polyvinyl butyral), polyethylene terephthalate (PET) film, or liquid silicone. In some embodiments, the first encapsulating film 20 and the second encapsulating film 40 may further include one or more functional additives selected from the group consisting of crosslinking agents, coupling agents, antioxidants, ultraviolet absorbers, etc., to improve the degree of crosslinking, weather resistance, adhesive strength, and anti-aging properties of the film. It is understood that the first encapsulating film 20 and the second encapsulating film 40 can be made of the same or different materials.

[0232] The battery string layer 30 includes multiple battery strings, which can be combined in series, parallel, or series-parallel configurations to achieve current collection and output. Further, each battery string is formed by sequentially connecting multiple battery cells via connectors. In some embodiments, at least a portion of the connector is electrically connected to the back electrode of one battery cell, and at least another portion of the connector is electrically connected to the front or back electrode of another battery cell to form a battery string. The connector may optionally include conductive elements such as solder strips, busbars, or metal clips. In some embodiments, to improve welding performance, oxidation resistance, and weather resistance, the connector material may preferably be a highly conductive metal material, such as at least one of silver, copper, tin, and nickel, or an alloy thereof. In some embodiments, to balance conductivity and cost control, the connector material may also be at least one of metal-clad composite materials such as silver-coated copper, copper-coated silver, copper-coated aluminum, aluminum-coated copper, tin-plated copper, or nickel-plated copper. The electrical connection may be selected from one of the following methods: laser welding, spot welding, bonding, ultrasonic welding, resistance welding, or brazing.

[0233] The solar cell can be the back-contact photovoltaic cell provided in this application.

[0234] The solar cell can employ a grid line design with no main grid (OBB), multiple main grid (MBB), or super-multiple main grid (SMBB). In some embodiments, the grid line material can be selected as at least one of silver-based conductive paste or silver-coated copper composite paste. The paste uses highly conductive metal powder as the conductive substrate, and the substrate can be selected as at least one of silver powder, copper powder, or silver-coated copper composite powder. To improve the ohmic contact performance, conductivity, and long-term weather resistance of the electrodes, a composite amorphous layer 2 can be formed on the surface of the substrate or in the grid line structure. The amorphous layer 2 material includes at least one of glass powder, organic carrier, nickel-based barrier layer, tin-based alloy layer, or anti-oxidation and corrosion-resistant coating.

[0235] A frame 60 surrounds the periphery of the stacked structure and is typically made of aluminum alloy or steel alloy. In some embodiments, the frame 60 may also be a fiberglass frame 60 or a plastic frame 60. The inner side of the frame 60 usually has grooves for filling with sealant to achieve a sealed bond with the stacked components formed by the front cover plate 10, the first encapsulating film 20, the battery string layer 30, the second encapsulating film 40, and the back cover plate 50, thereby blocking moisture and buffering external impacts. In some embodiments, the frame 60 can be assembled using corner brackets.

[0236] A junction box 70 is located on one side of the back cover 50 and is electrically connected to the terminals of the bus electrodes in the battery string layer 30 via a lead-out busbar for energy extraction. The junction box 70 typically includes a housing and cover made of weather-resistant insulating material, conductive connecting tabs disposed within the housing, and one or more bypass diodes. The bypass diodes are connected in parallel with sub-units of the battery string. The electrical leads of the junction box 70 include photovoltaic-specific connectors and cables. The cables preferably use cross-linked polyethylene insulation sheaths and tinned copper core wires. In some embodiments, the interior of the junction box 70 may also be filled and encapsulated with potting compound to achieve insulation, thermal conductivity, moisture protection, and fixation.

[0237] like Figure 6 As shown, this application provides a photovoltaic system 1000, which can be applied in photovoltaic power plants, such as ground power plants, rooftop power plants, and water surface power plants, and can also be applied to equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc.

[0238] It is understandable that the application scenarios of the photovoltaic system 1000 are not limited to this; that is to say, the photovoltaic system 1000 can be applied in all fields that require solar power generation. Taking a photovoltaic power generation system as an example, the photovoltaic system 1000 may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic modules 100. For example, multiple photovoltaic modules 100 can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, which can collect the current generated by the photovoltaic array. The collected current flows through the inverter and is converted into AC power required by the mains power grid before being connected to the mains power grid to realize solar power supply.

Claims

1. A back-contact photovoltaic cell, characterized in that, include: Crystalline silicon substrate; At least one amorphous layer is located inside the crystalline silicon substrate and close to the front side of the crystalline silicon substrate; The back side of the crystalline silicon substrate includes alternating first and second regions, with an isolation region distributed between the first and second regions, and the first and second regions having opposite polarities. The first electrode is located in the first region; The second electrode is located in the second region.

2. The back-contact photovoltaic cell as described in claim 1, characterized in that, The amorphous layer is 0.2 μm to 2 μm away from the front surface of the crystalline silicon substrate.

3. The back-contact photovoltaic cell as described in claim 1, characterized in that, The thickness of the amorphous layer ranges from 2 nm to 20 nm.

4. The back-contact photovoltaic cell as described in claim 1, characterized in that, The amorphous layer is formed by any one or any combination of the following ions: Silicon ions, germanium ions, carbon ions, argon ions, xenon ions.

5. The back-contact photovoltaic cell according to any one of claims 1 to 4, characterized in that, The amorphous layer consists of one layer.

6. The back-contact photovoltaic cell according to any one of claims 1 to 4, characterized in that, The amorphous layer has at least two layers, and the crystalline silicon substrate is located between adjacent amorphous layers.

7. A method for preparing a back-contact photovoltaic cell, characterized in that, include: Prepare a crystalline silicon substrate; Ions are implanted into the interior of the crystalline silicon substrate from the front side, and annealed in an inert atmosphere to form at least one amorphous layer; wherein the implanted ions include one or any combination of silicon ions, germanium ions, carbon ions, argon ions, and xenon ions. A first electrode is formed in a first region on the back side of the crystalline silicon substrate, and a second electrode is formed in a second region on the back side of the crystalline silicon substrate. The back side of the crystalline silicon substrate includes alternating first and second regions, and an isolation region is distributed between the first and second regions. The first and second regions have opposite polarities.

8. The method for preparing a back-contact photovoltaic cell as described in claim 7, characterized in that, When ions are implanted from the front side of the crystalline silicon substrate into the interior of the crystalline silicon substrate, the implantation dose is 1×10⁻⁶. 14 ~5×10 15 / cm 2 The implantation depth is 0.2 μm to 2 μm from the front surface of the crystalline silicon substrate; In this process, when ions are implanted into the interior of the crystalline silicon substrate from the front side and annealed in an inert atmosphere to form at least one amorphous layer, the annealing temperature is lower than the crystallization temperature of the amorphous layer.

9. A photovoltaic module, characterized in that, include: Including the back-contact photovoltaic cell as described in any one of claims 1 to 6.

10. A photovoltaic system, characterized in that, Including the photovoltaic module as described in claim 9.

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