N-type back contact cell and its preparation method and application

Abstract

The application relates to the technical field of solar cell preparation, in particular to an N-type back contact cell and a preparation method and application thereof. The surface of a P-type doped contact region and an N-type doped contact region of the N-type back contact cell is covered with a composite passivation contact layer; the composite passivation contact layer comprises an Al2O3 passivation layer, a TiN transition layer and a polysilicon contact layer; a modified electrode is arranged on the composite passivation contact layer; the modified electrode comprises a nickel-vanadium alloy layer arranged on the surface of the composite passivation contact layer, electrode grid lines arranged on the surface of the nickel-vanadium alloy layer and a bus bar electrically connected with the electrode grid lines. The N-type back contact cell has low contact loss, good long-term anti-degradation and production compatibility.

Description

Technical Field

[0001] This invention relates to the field of solar cell fabrication technology, and more specifically, to an N-type back contact cell, its fabrication method, and its application. Background Technology

[0002] N-type BC batteries face three prominent problems during industrial-scale mass production: First, there is the challenge of synergistic control of contact loss and passivation performance. Existing N-type BC batteries mostly use a single passivation layer or a simple stacked passivation design for the P-type and N-type doped contact regions on the back side, which has a significant "seesaw" effect. Increasing the thickness of the passivation layer can improve the passivation effect and reduce carrier recombination, but it will lead to an increase in contact resistance and exacerbate carrier transport loss. Thinning the passivation layer can reduce the contact resistance, but it will cause passivation failure, leading to a surge in the surface carrier recombination rate, which directly restricts the improvement of battery conversion efficiency. Secondly, the battery's long-term anti-degradation performance is insufficient. Under outdoor high temperature and high humidity conditions, the interface between the battery's back electrode and the doped contact area is prone to oxidation and peeling. At the same time, the edge cutting damage area is prone to forming leakage channels, which leads to continuous degradation of the battery's electrical performance and shortens its service life. Third, it suffers from poor mass production compatibility. The preparation of existing high-efficiency N-type BC cells largely relies on special technologies such as high-precision laser etching and dedicated doping sources. These technologies have low compatibility with core equipment in existing photovoltaic production lines, such as PECVD and screen printing. The investment in production line modification is huge, and the preparation process is cumbersome, making it difficult to achieve large-scale mass production. This results in high battery production costs and limits its industrialization and popularization.

[0003] Current technologies fail to achieve a balance between conversion efficiency, long-term stability, and mass production cost: some patents reduce contact resistance by optimizing doping process parameters, but sacrifice passivation performance, leading to faster long-term battery degradation; some patents use composite passivation layer structures to improve surface passivation, but the process steps are cumbersome, requiring additional specialized equipment and cannot be adapted to existing mass production lines; still other patents use precious metal electrode materials to reduce contact loss, but significantly increase electrode fabrication costs. Furthermore, while some existing technologies can achieve high efficiency in the laboratory, they cannot meet the process precision and cost control requirements of large-scale industrial production.

[0004] Therefore, there is an urgent need to develop an N-type BC battery and its manufacturing process that can simultaneously address the three core pain points of contact loss, long-term anti-attenuation, and mass production compatibility, and is compatible with existing mass production processes.

[0005] In view of this, the present invention is hereby proposed. Summary of the Invention

[0006] The purpose of this invention is to overcome the defects of the prior art.

[0007] In order to achieve the above-mentioned objectives of the present invention, the following technical solution is adopted: An N-type back-contact solar cell includes: an N-type silicon substrate; a textured layer, a SiO2 transition layer, and a SiN2 layer are sequentially disposed on the front side of the N-type silicon substrate. x An anti-reflection passivation layer is provided; the back side of the N-type silicon substrate has alternating P-type doped contact regions and N-type doped contact regions, and the surfaces of the P-type doped contact regions and the N-type doped contact regions are covered with a composite passivation contact layer; the composite passivation contact layer includes: an Al2O3 passivation layer, a TiN transition layer, and a polycrystalline silicon contact layer; the Al2O3 passivation layer is in contact with the P-type doped contact regions and the N-type doped contact regions; A modified electrode is disposed on the composite passivation contact layer; the modified electrode includes: a nickel-vanadium alloy layer disposed on the surface of the composite passivation contact layer; an electrode grid line disposed on the surface of the nickel-vanadium alloy layer; and a busbar electrically connected to the electrode grid line.

[0008] A method for preparing the aforementioned N-type back contact battery includes the following steps: (a) Fabrication of a textured structure layer, deposition of a SiO2 transition layer, and deposition of SiN on the front side of an N-type silicon substrate. x Anti-reflection passivation layer; (b) A P-type doped contact region and an N-type doped contact region are prepared on the back side of an N-type silicon substrate; a composite passivation contact layer is prepared on the surface of the P-type doped contact region and the N-type doped contact region; (c) Deposit a nickel-vanadium alloy layer on the composite passivated contact layer; fabricate an electrode grid line on the nickel-vanadium alloy layer; fabricate a busbar.

[0009] A photovoltaic module includes the aforementioned N-type back contact cell or an N-type back contact cell prepared by the method described above.

[0010] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) In the composite passivation contact layer, the Al2O3 layer is highly efficient passivation, the polycrystalline silicon layer is low resistance contact, and the TiN layer is interface connection. The three layers work together to reduce the contact resistance of the battery, reduce the surface carrier recombination rate by more than 30%, increase the open circuit voltage to more than 720mV, achieve a conversion efficiency of more than 26.5%, and have stable performance.

[0011] (2) The silicon substrate has passivation structures on the front, back and edge to effectively suppress edge leakage and carrier recombination; the modified electrode has significantly improved the bonding force between the electrode and the film through the Ni-V alloy layer and copper-silver composite grid line, avoiding electrode oxidation and peeling. After high temperature and high humidity aging test, the battery conversion efficiency decay rate is ≤2%, and the service life is extended to more than 30 years, which is suitable for the needs of complex outdoor working conditions.

[0012] (3) The structural parameters and process parameters of each layer of the present invention are in line with the semiconductor physical theory and mass production practice. The battery has high consistency in electrical performance, is easy to obtain and has low cost. It does not need to rely on scarce materials or special preparation technology, has high mass production feasibility and product cost performance, and is suitable for large-scale promotion and application.

[0013] (4) The preparation process of the present invention adopts the core equipment such as ALD, PECVD, laser doping, and screen printing of existing photovoltaic production lines, without the need for additional special equipment; the design of copper-silver composite grid lines and low silver content busbars reduces the amount of silver used and lowers the cost of electrodes; at the same time, the process steps are simple and do not require additional processing steps such as edge passivation, which improves mass production efficiency and realizes large-scale mass production. Attached Figure Description

[0014] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of the N-type back contact battery provided by the present invention. Detailed Implementation

[0016] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and specific embodiments. However, those skilled in the art will understand that the embodiments described below are some embodiments of the present invention, but not all embodiments, and are only used to illustrate the present invention, and should not be regarded as limiting the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall be followed. Where the manufacturers of reagents or instruments are not specified, they are all conventional products that can be purchased commercially.

[0017] One aspect of the present invention relates to an N-type back contact battery, such as Figure 1 As shown, it includes: an N-type silicon substrate; The front side of the N-type silicon substrate is sequentially formed with a textured structure layer, a SiO2 transition layer, and a SiN layer. x Anti-reflection passivation layer; The back side of the N-type silicon substrate has alternating P-type doped contact regions and N-type doped contact regions, and the surfaces of the P-type doped contact regions and the N-type doped contact regions are covered with a composite passivation contact layer; the composite passivation contact layer includes: an Al2O3 passivation layer, a TiN transition layer and a polycrystalline silicon contact layer; the Al2O3 passivation layer is in contact with the P-type doped contact regions and the N-type doped contact regions; A modified electrode is disposed on the composite passivation contact layer; the modified electrode includes: a nickel-vanadium alloy layer disposed on the surface of the composite passivation contact layer; an electrode grid line disposed on the surface of the nickel-vanadium alloy layer; and a busbar electrically connected to the electrode grid line.

[0018] The aforementioned N-type back contact battery features a composite passivation contact layer with an efficient Al2O3 layer for passivation, a low-resistance polycrystalline silicon layer for contact, and an interface-connected TiN layer. The three layers work synergistically to reduce the battery's contact resistance, decrease the surface carrier recombination rate by more than 30%, increase the open-circuit voltage to over 720mV, achieve a conversion efficiency of over 26.5%, and maintain stable performance.

[0019] The silicon substrate has passivation structures on the front, back and edges to effectively suppress edge leakage and carrier recombination; the modified electrode significantly improves the adhesion between the electrode and the film through the Ni-V alloy layer and copper-silver composite grid line, avoiding electrode oxidation and peeling. After high temperature and high humidity aging test, the battery conversion efficiency decay rate is ≤2% and the service life is extended to more than 30 years, which is suitable for the needs of complex outdoor working conditions.

[0020] The structural parameters and process parameters of each layer of this invention are consistent with semiconductor physics theory and mass production practice. The battery has high consistency in electrical performance, is easy to obtain, has low cost, does not rely on scarce materials or special preparation technology, has high mass production feasibility and product cost performance, and is suitable for large-scale promotion and application.

[0021] Furthermore, the thickness of the composite passivation contact layer is 80~110nm, including but not limited to a point value of any one of 80nm, 90nm, 100nm or 110nm or a range between any two.

[0022] Furthermore, the Al2O3 passivation layer has a thickness of 25~35nm, including but not limited to a point value of 25nm, 28nm, 30nm, 33nm or 35nm or a range between any two, and is prepared using ALD process, with a passivation charge density ≥5×10¹²cm. - ², can effectively passivate dangling bonds on the surface of the doped contact region through the electric field effect, suppress carrier surface recombination, and improve the open-circuit voltage of the battery.

[0023] Furthermore, the thickness of the TiN transition layer is 8~15nm, including but not limited to any one of 8nm, 10nm, 13nm or 15nm or any range between two of them. It is prepared by magnetron sputtering and has excellent conductivity and interfacial bonding ability. It can effectively improve the interfacial bonding force between the Al2O3 passivation layer and the polycrystalline silicon contact layer, while preventing impurities in the polycrystalline silicon layer from diffusing into the Al2O3 layer, avoiding passivation layer failure, and solving the problems of interfacial separation and performance degradation of existing composite passivation layers.

[0024] Furthermore, the polycrystalline silicon contact layer has a thickness of 45~60nm, including but not limited to a point value of 45nm, 50nm, 55nm, or 60nm, or a range between any two. It is prepared using PECVD combined with low-temperature crystallization (crystallization temperature 450~500℃), achieving a crystallinity ≥85%. It possesses excellent conductivity and can significantly reduce the contact resistance with subsequent electrodes (contact resistance ≤5mΩ·cm). 2 ).

[0025] The composite passivation contact layer breaks the existing "seesaw" effect between passivation performance and contact resistance. Through layered functional positioning, the Al2O3 layer is responsible for efficient passivation, the polycrystalline silicon layer is responsible for low-resistance contact, and the TiN layer achieves effective connection between the two, thereby achieving a synergistic improvement in passivation performance and contact efficiency.

[0026] Furthermore, in the nickel-vanadium alloy layer, the mass ratio of nickel to vanadium is 85~95:5~15, including but not limited to 85:15, 90:10 or 95:5. The nickel-vanadium alloy layer can optimize the interface characteristics between the electrode and the polycrystalline silicon contact layer, reduce the contact resistance, and significantly improve the adhesion between the electrode and the film layer, avoiding problems such as electrode peeling and detachment during long-term use.

[0027] Furthermore, the thickness of the nickel-vanadium alloy layer is 6~12nm, including but not limited to a point value of any one of 6nm, 8nm, 10nm or 12nm or a range between any two, and is prepared by magnetron sputtering.

[0028] Furthermore, the electrode grid line includes: a copper grid line laid on the surface of the nickel-vanadium alloy layer and a silver plating layer disposed on the copper grid line.

[0029] Further, the thickness of the copper gate lines is 12~18μm, including but not limited to a value of any one of 12μm, 14μm, 16μm, or 18μm, or a range between any two; the thickness of the silver plating layer is 1.5~2.5μm, including but not limited to a value of any one of 1.5μm, 1.8μm, 2.0μm, 2.3μm, or 2.5μm, or a range between any two. It is prepared using an electroplating process. The bottom copper gate lines bear the core function of efficient carrier transport, while the top silver plating layer provides protection against oxidation and improves interfacial contact performance. The two layers are tightly bonded with no obvious interfacial gaps, and the overall thickness is controlled between 13.5~20.5μm.

[0030] Replacing traditional pure silver grid wires with copper grid wires can reduce silver usage by more than 70%, significantly reducing electrode manufacturing costs. The top silver plating layer can effectively improve the oxidation resistance and conductivity of copper grid wires, preventing them from oxidizing and failing under outdoor conditions.

[0031] In some specific embodiments, the method for fabricating the electrode grid lines includes: 1. Pretreatment: The nickel-vanadium alloy layer is subjected to plasma cleaning with a power of 300~400W (for example, it can be any one of 30W, 330W, 350W, 380W or 400W or any range between two), and a time of 1~2min (for example, it can be any one of 1min, 1.5min or 2min or any range between two) to remove residual moisture, impurities and oxide layer on the surface; 2. Copper grid line deposition: Copper grid lines are prepared by electroplating on a nickel-vanadium alloy layer. The electroplating solution is a copper sulfate system, with a copper sulfate concentration of 180~220 g / L (e.g., any value or range between 180 g / L, 190 g / L, 200 g / L, 210 g / L, or 220 g / L), a sulfuric acid concentration of 50~70 g / L (e.g., any value or range between 50 g / L, 55 g / L, 60 g / L, 65 g / L, or 70 g / L), an electroplating temperature of 50~60℃ (e.g., any value or range between 50℃, 53℃, 58℃, or 60℃), and a current density of 2~3 A / dm³. 2 (For example, it can be, but is not limited to, 2A / dm) 2 2.5A / dm 2 or 3A / dm 2The point value of any one of the values ​​or the range between any two can be used), and the electroplating time is 15~25min (for example, it can be any one of 15min, 18min, 20min, 23min or 25min or the range between any two), to ensure that the copper grid line is deposited uniformly and densely, without defects such as pinholes and cracks, and forms a good ohmic contact with the nickel-vanadium alloy layer, thereby reducing the contact resistance; 3. Copper layer surface activation: The copper grid lines are acid-washed, washed with water, and dried using a sulfuric acid solution of 5wt%~10wt% (for example, it can be any point value or any range between 5wt%, 8wt%, or 10wt%). The acid washing time is 30~60s to remove trace amounts of cuprous oxide generated on the copper layer surface, activate the copper layer surface, and prevent the oxide layer from affecting the interface bonding between copper and silver. The drying temperature is 80~100℃ and the time is 5~8min to ensure that the copper layer surface is dry and clean. 4. Silver Plating Top Layer Coating: A silver plating layer is deposited on the surface of the copper grid lines. The plating solution is a silver cyanide system, with a silver cyanide concentration of 30-40 g / L (e.g., any point value or range between 30 g / L, 35 g / L, or 40 g / L), a potassium cyanide concentration of 80-100 g / L (e.g., any point value or range between 80 g / L, 90 g / L, or 100 g / L), and the plating temperature controlled at 50-60℃ (e.g., any point value or range between 50℃, 55℃, or 60℃), and a current density of 1-2 A / dm³. 2 (For example, it can be, but is not limited to, 1A / dm) 2 1.5A / dm 2 or 2A / dm 2 The silver plating layer can be uniformly covered by a point value of any one of the following or a range of values ​​between any two: 3 min, 4 min, or 5 min. The silver plating layer is tightly bonded to the bottom layer of the copper grid line through a metal bond, forming a seamless composite structure that does not affect the conductivity of the copper grid line and can fully wrap the copper layer, isolate air and moisture, and prevent the copper layer from oxidizing. 5. Post-treatment: After the silver plating is deposited, it is washed with water and dried. The drying temperature is 120~150℃ and the time is 10~15min.

[0032] Furthermore, the busbar is primarily made of silver paste, with a silver content of 75wt%~85wt% (for example, it can be any one of, but not limited to, 75wt%, 78wt%, 80wt%, 83wt%, or 85wt%, or any range between two values). It is prepared using a screen printing process, with a thickness of 22~32μm (for example, it can be any one of, but not limited to, 22μm, 25μm, 28μm, 30μm, or 32μm, or any range between two values). It is perpendicularly connected to the electrode grid lines to achieve efficient collection and transport of charge carriers. The low-silver-content silver paste is fully compatible with existing screen printing processes, requiring no equipment modification. Furthermore, through composition optimization, the conductivity and reliability of the busbar are ensured while reducing the amount of silver used.

[0033] Furthermore, the N-type back contact cell also includes an edge passivation layer. The edge passivation layer is attached to the four sidewalls of the N-type silicon substrate, with its inner side (the side closest to the edge surface of the silicon substrate) directly bonded to the edge damage layer of the N-type silicon substrate, and its outer side bonded to the SiN... x The edges of the anti-reflection passivation layer and the composite passivation contact layer are seamlessly connected, i.e., SiN x The edge of the anti-reflection passivation layer extends to the side of the silicon substrate and is completely attached to the upper edge of the edge passivation layer; the edge of the composite passivation contact layer extends to the side of the silicon substrate and is completely attached to the lower edge of the edge passivation layer. The three form a gapless, fully enclosed integrated passivation structure that fully covers the front, back and edge areas of the N-type silicon substrate.

[0034] Furthermore, the edge passivation layer comprises, from the inside out, an Al2O3 layer and a SiN layer. x The layers have a thickness of 90~110nm; wherein the Al2O3 layer has a thickness of 35~45nm (for example, it can be any point value of 35nm, 40nm or 45nm or any range between two values), and the SiN layer has a thickness of 90~110nm; x The layer thickness is 55~65nm (for example, it can be any point value or a range between 55nm, 60nm, or 65nm, but not limited to 55nm, 60nm, or 65nm), and it is fabricated simultaneously with the front and back passivation layers using PECVD technology to form a fully encapsulated passivation protection structure. The edge passivation layers are respectively coated with SiN x The anti-reflection passivation layer and the composite passivation contact layer are seamlessly connected to form a fully enclosed passivation protection structure, which comprehensively suppresses edge leakage and carrier recombination.

[0035] The edges of N-type silicon substrates generate numerous damage layers and dangling bonds due to cutting and processing, making them prone to becoming carrier recombination centers and leakage channels. Existing edge passivation technologies mostly involve additional processing, which is cumbersome and results in poor passivation stability. The edge passivation layer of this invention can fully cover the edge damage area, effectively suppressing edge leakage and carrier recombination, improving the battery fill factor and long-term stability. The simultaneous fabrication process can reduce additional processing steps, improve mass production efficiency, and reduce process costs. Moreover, the passivation effect of the stacked structure is better than that of a single passivation layer, achieving long-term stable passivation protection.

[0036] Furthermore, the N-type silicon substrate uses N-type CZ silicon wafers commonly used in industrial mass production, with a thickness of 110~130μm, resistivity of 2~6Ω·cm, carrier lifetime ≥1200μs, and no damage layer on the substrate surface (damage layer thickness <5nm). This thickness ensures the structural strength of the substrate, meets the requirements of mass production handling and processing, reduces the amount of silicon material used, lowers the cost of silicon wafers, shortens the longitudinal transport distance of carriers, and reduces the transport loss within the carrier. This resistivity can achieve a balance between carrier concentration and transport efficiency, avoiding the increase in series resistance and decrease in fill factor caused by excessively high resistivity, or the aggravation of carrier recombination caused by excessively low resistivity. This carrier lifetime can effectively reduce the probability of carrier recombination within the carrier, and improve the open-circuit voltage and short-circuit current of the battery.

[0037] Furthermore, the textured surface layer is prepared using an alkaline texturing process, resulting in a random pyramid textured surface with a pyramid height of 0.6~1.2μm, a base side length of 1.2~2.2μm, and a textured surface reflectivity ≤12% (wavelength range 400-1100nm). The random pyramid textured surface structure effectively consumes incident light energy through multiple reflections and refractions, significantly reducing frontal light reflectivity and improving light absorption efficiency. The pyramid height ensures low reflectivity, avoiding mass production challenges such as textured surface cracking and poor adhesion of subsequent film layers caused by excessively high pyramids.

[0038] Furthermore, the SiO2 transition layer has a thickness of 12~22nm (for example, it can be any one of 12nm, 15nm, 18nm, 20nm or 22nm or any range between two), is prepared by atomic layer deposition (ALD) process, and the deposition temperature is 280~320℃ (for example, it can be any one of 280℃, 290℃, 300℃, 310℃ or 320℃ or any range between two), with a density ≥98%.

[0039] Furthermore, the SiN xThe antireflection passivation layer has a thickness of 75~95nm (for example, it can be a point value of any one of 75nm, 85nm or 95nm or a range of any two), is prepared by plasma-enhanced chemical vapor deposition (PECVD), has a refractive index of 2.1~2.3, and a hydrogen content ≥10 at.

[0040] The SiO2 transition layer possesses excellent compactness and can effectively block SiN. x Hydrogen atoms in the antireflection passivation layer diffuse into the N-type silicon substrate, preventing the reduction in substrate carrier lifetime caused by hydrogen atoms, and simultaneously mitigating the interaction between the silicon substrate and SiN. x The stress difference between the layers prevents problems such as film peeling and cracking in subsequent processes; the above-mentioned SiN x The refractive index and thickness of the layer enable low reflection in the visible light band, maximizing light absorption efficiency. At the same time, the hydrogen atoms it contains can effectively passivate the dangling bonds on the front side of the silicon substrate, reducing surface carrier recombination. Both ALD and PECVD processes are core processes in existing photovoltaic production lines and can be directly adapted to mass production needs without the need for additional equipment.

[0041] Furthermore, the P-type doped contact region is boron doped with a doping concentration of 1.2 × 10⁻⁶. 19 ~1.2×10 20 cm -3 The doping depth is 0.35~0.55μm; the N-type doped contact region is phosphorus doped with a doping concentration of 6×10⁻⁶. 18 ~6×10 19 cm -3 The doping depth is 0.25~0.45μm (for example, it can be a point value of any one of 0.25μm, 0.35μm or 0.45μm or a range of any two).

[0042] Furthermore, the width ratio of the P-type doped contact region to the N-type doped contact region is 1.3 to 1.6:1 (for example, it can be, but is not limited to, 1.3:1, 1.5:1 or 1.6:1), and the spacing between two adjacent doped contact regions is 55 to 85 μm (for example, it can be, but is not limited to, any one of 55 μm, 65 μm, 75 μm or 85 μm or any range between two).

[0043] The P-type doped contact region uses a higher doping concentration, which reduces the contact resistance with subsequent electrodes and improves carrier collection efficiency. At the same time, the doping depth is strictly controlled to avoid excessive carrier recombination caused by excessive doping. The N-type doped contact region has a slightly lower doping concentration than the P-type doped contact region, which can form a good ohmic contact with the N-type silicon substrate, reduce the interface barrier, and reduce carrier transport loss. The optimized design of the width ratio and spacing can achieve a balance between carrier lateral transport efficiency and leakage current suppression, avoid leakage between adjacent doped contact regions, and ensure the cell fill factor. All doping parameters can be achieved through existing laser doping processes without relying on special doping sources or high-precision doping equipment, and are suitable for mass production process requirements.

[0044] Another aspect of the present invention relates to a method for preparing the aforementioned N-type back contact battery, comprising the following steps: (a) Fabrication of a textured structure layer, deposition of a SiO2 transition layer, and deposition of SiN on the front side of an N-type silicon substrate. x Anti-reflection passivation layer; (b) A P-type doped contact region and an N-type doped contact region are prepared on the back side of an N-type silicon substrate; a composite passivation contact layer is prepared on the surface of the P-type doped contact region and the N-type doped contact region; (c) Deposit a nickel-vanadium alloy layer on the composite passivated contact layer; fabricate an electrode grid line on the nickel-vanadium alloy layer; fabricate a busbar.

[0045] The method for preparing the N-type back contact battery described above is compatible with existing photovoltaic mass production lines, requires no additional core equipment, has simple steps, strong controllability, and the process parameters have been verified through mass production, enabling large-scale production.

[0046] Furthermore, the method for preparing the composite passivated contact layer includes the following steps: An Al2O3 passivation layer, a TiN transition layer, and an amorphous silicon layer are deposited on the surfaces of the P-type doped contact region and the N-type doped contact region; the amorphous silicon is then crystallized to form a polycrystalline silicon contact layer.

[0047] Furthermore, the method for fabricating the N-type back contact battery further includes: fabricating an edge passivation layer on the four sidewalls of the N-type silicon substrate.

[0048] Furthermore, the temperature for depositing the Al2O3 passivation layer is 300~310℃ (for example, it can be any one of 300℃, 305℃ or 310℃ or any range between two), and the time is 12~18min (for example, it can be any one of 12min, 14min, 16min or 18min or any range between two).

[0049] Furthermore, the sputtering power for depositing the TiN transition layer is 800~1000W (for example, it can be any one of the values ​​or any range between the two), and the time is 5~8min (for example, it can be any one of the values ​​or any range between the two).

[0050] Furthermore, the crystallization temperature is 450~500℃ (for example, it can be any one of 450℃, 460℃, 470℃, 480℃, 490℃ or 500℃ or a range between any two), and the time is 25~35min (for example, it can be any one of 25min, 27min, 29min, 31min, 33min or 35min or a range between any two).

[0051] Furthermore, the sputtering power for depositing the nickel-vanadium alloy layer is 700~900W (for example, it can be any one of 700W, 750W, 800W, 850W or 900W or any range between two), and the time is 4~6min (for example, it can be any one of 4min, 5min or 6min or any range between two).

[0052] Furthermore, a screen printing process is used to print silver paste to prepare busbars. After printing, the busbars are sintered at a temperature of 750~800℃ (for example, it can be any value or a range between any two of 750℃, 760℃, 770℃, 780℃, 790℃ or 800℃) for a time of 10~15min (for example, it can be any value or a range between any two of 10min, 13min or 15min) to achieve good ohmic contact between the electrode and the composite passivation contact layer, thereby improving the adhesion and stability of the electrode.

[0053] Furthermore, an edge passivation layer is deposited around the perimeter of the N-type silicon substrate, with deposition parameters similar to those of the backside SiN. x The layers remain consistent, ensuring a seamless connection between the edge passivation layer and the front and back passivation layers, forming a fully enclosed passivation structure without the need for additional process steps.

[0054] Furthermore, before use, the N-type silicon substrate is subjected to alkaline washing, acid washing, texturing, RCA cleaning, and drying.

[0055] Furthermore, the alkaline washing temperature is 60~70℃, and the time is 5~8 minutes.

[0056] Furthermore, the pickling process uses a dilute hydrofluoric acid solution and the pickling time is 2-3 minutes.

[0057] Furthermore, the flocking process employs an alkaline flocking process, with a temperature of 80~85℃ (for example, it can be any one of the values ​​or any range between the two, but not limited to), and a time of 15~20min (for example, it can be any one of the values ​​or any range between the two, but not limited to the two), to prepare a random pyramidal flocked surface structure.

[0058] Furthermore, the drying temperature is 120~150℃, and the time is 10~15min.

[0059] Furthermore, the temperature for depositing the SiO2 transition layer is 300~310℃ (e.g., any value or a range between 300℃, 305℃, or 310℃), and the time is 10~15 min (e.g., any value or a range between 10 min, 13 min, or 15 min), ensuring a dense and uniform film. SiN deposition. x The antireflection passivation layer is deposited at a temperature of 380–400°C (e.g., any value or range between 380°C, 390°C, or 400°C), with an RF power of 1200–1500 W (e.g., any value or range between 1200 W, 1300 W, 1400 W, or 1500 W), and a deposition time of 8–12 min (e.g., any value or range between 8 min, 9 min, 10 min, 11 min, or 12 min). After deposition, it is dried at a low temperature of 120–150°C for 20–30 min. By optimizing the deposition parameters, a SiO2 layer and a SiN layer are achieved. x Layered interface matching enhances the front passivation and anti-reflection effects.

[0060] Furthermore, the preparation of the P-type doped contact region and the N-type doped contact region includes the following steps: The oxide layer on the back side of the N-type silicon substrate is etched away, and laser doping and annealing are performed on the back side of the N-type silicon substrate to form P-type doped contact regions and N-type doped contact regions.

[0061] Furthermore, the etching time is 3-5 minutes and the power is 500-600W.

[0062] Furthermore, the P-type doped contact region uses a boron doping source, with a laser power of 80~100W and a scanning speed of 500~600mm / s.

[0063] Furthermore, the N-type doped contact region uses a phosphorus doping source, with a laser power of 60~80W and a scanning speed of 400~500mm / s.

[0064] Furthermore, the annealing temperature is 450~500℃ (for example, it can be any value of 450℃, 480℃, or 500℃, or a range between any two), and the time is 30~40min (for example, it can be any value of 30min, 35min, or 40min, or a range between any two). Annealing activates the doped atoms, improves the conductivity of the doped region, and simultaneously repairs surface damage caused by laser doping, reducing carrier recombination.

[0065] Another aspect of the present invention relates to a photovoltaic module comprising the aforementioned N-type back contact cell or an N-type back contact cell prepared by the method thereof.

[0066] The embodiments of the present invention will be described in detail below with reference to examples. However, those skilled in the art will understand that the following examples are for illustrative purposes only and should not be considered as limiting the scope of the invention. Unless otherwise specified in the examples, conventional conditions or conditions recommended by the manufacturer are followed. Reagents or instruments whose manufacturers are not specified are all commercially available conventional products.

[0067] Example 1 The N-type back contact battery provided in this embodiment includes: an N-type silicon substrate; The front side of the N-type silicon substrate is sequentially formed with a textured layer, a SiO2 transition layer, and a SiN layer. x Anti-reflection passivation layer; SiO2 transition layer thickness is 17nm; SiN x The antireflective passivation layer has a thickness of 85 nm, a refractive index of 2.2, and a hydrogen content of ≥10 at.%; The back side of the N-type silicon substrate has alternating P-type and N-type doped contact regions. The surfaces of the P-type and N-type doped contact regions are covered with a composite passivation contact layer, which includes an Al₂O₃ passivation layer, a TiN transition layer, and a polycrystalline silicon contact layer. The Al₂O₃ passivation layer is in contact with the P-type and N-type doped contact regions. The thickness of the Al₂O₃ passivation layer is 30 nm; the thickness of the TiN transition layer is 12 nm; the thickness of the polycrystalline silicon contact layer is 50 nm; and the crystallinity is ≥85%. A modified electrode is disposed on the composite passivation contact layer; the modified electrode includes: a nickel-vanadium alloy layer disposed on the surface of the composite passivation contact layer; an electrode grid line disposed on the surface of the nickel-vanadium alloy layer; and a bus bar electrically connected to the electrode grid line; In the nickel-vanadium alloy layer, the mass ratio of nickel to vanadium is 90:10; the thickness of the nickel-vanadium alloy layer is 9 nm. The electrode grid line includes: a copper grid line laid on the surface of the nickel-vanadium alloy layer and a silver plating layer disposed on the copper grid line; the thickness of the copper grid line is 14 μm; the thickness of the silver plating layer is 2 μm. The busbar is made of low silver content silver paste (silver content 80wt%), prepared by screen printing process, with a thickness of 27μm, and is perpendicularly connected to the grid lines; An edge passivation layer is disposed at the edge of the N-type silicon substrate, and the edge passivation layer is respectively connected to the SiN... x The anti-reflection passivation layer and the composite passivation contact layer are seamlessly connected to form a fully enclosed passivation protection structure; the edge passivation layer, from the inside out, includes: an Al2O3 layer and a SiN layer. x The Al2O3 layer is 40 nm thick, and the SiN layer is... x The layer thickness is 60nm; The suede structure layer is a random pyramid suede with a pyramid height of 0.6~1.2μm, a base side length of 1.2~2.2μm, and a suede reflectivity of ≤12%. The P-type doped contact region is boron doped with a doping concentration of 1.2 × 10⁻⁶. 19 cm -3 The doping depth is 0.45 μm; the N-type doped contact region uses phosphorus doping with a doping concentration of 6 × 10⁻⁶. 18 cm -3 The doping depth is 0.35 μm; the width ratio of the P-type doped contact region to the N-type doped contact region is 1.5:1, and the spacing between two adjacent doped contact regions is 75 μm.

[0068] The above-mentioned method for preparing an N-type BC battery includes the following steps: 1. N-type silicon substrate pretreatment: Select N-type CZ silicon wafers that meet the parameter requirements, and sequentially perform alkaline washing (to remove surface oil and impurities, alkaline washing temperature 65℃, time 7min), acid washing (to remove the surface oxide layer, using dilute hydrofluoric acid solution, acid washing time 3min), and texturing (using alkaline texturing process, temperature 83℃, time 18min) to prepare a random pyramid textured surface structure; then use RCA cleaning process to remove the damaged layer and residual impurities on the textured surface, and dry (drying temperature 140℃, time 13min) for later use.

[0069] 2. Front passivation and antireflection layer fabrication: The pretreated silicon substrate is placed in an ALD (Alternating Discharge) device, and a SiO2 transition layer is deposited on the front side; then the silicon substrate is transferred to a PECVD (Pure Carbon Dioxide) device, and SiN is deposited on the surface of the SiO2 transition layer. x Anti-reflection passivation layer; after deposition, low-temperature drying (temperature 130℃, time 25min).

[0070] 3. Backside doped contact region fabrication: The silicon substrate with the film layer fabricated on the front side is flipped over, and the natural oxide layer on the back side is removed by plasma etching (etching time 4 min, etching power 550 W); then, P-type doped contact regions and N-type doped contact regions are fabricated on the back side by laser doping. The P-type doping uses a boron doping source, laser power 90 W, scanning speed 550 mm / s; the N-type doping uses a phosphorus doping source, laser power 70 W, scanning speed 450 mm / s; after doping, an annealing process is performed (temperature 480℃, time 35 min).

[0071] 4. Preparation of composite passivation contact layer: The silicon substrate with the back side doped is placed in an ALD device, and an Al2O3 passivation layer is deposited on the surface of all doped contact areas on the back side; then it is transferred to a magnetron sputtering device to deposit a TiN transition layer; then it is transferred to a PECVD device to deposit an amorphous silicon layer, and then low-temperature crystallization (temperature 480℃, time 30min) is performed to form a polycrystalline silicon contact layer.

[0072] 5. Edge passivation layer preparation: After the composite passivation contact layer is prepared, Al2O3-SiN is simultaneously deposited on the edge of the silicon substrate using PECVD process. x The stacked closed-loop edge passivation layer has deposition parameters similar to those of the backside SiN. x The layers are kept consistent to ensure a seamless connection between the edge passivation layer and the front and back passivation layers, forming a fully enclosed passivation structure.

[0073] 6. Modified Electrode Fabrication: First, a Ni-V alloy layer was deposited on the surface of the composite passivated contact layer using magnetron sputtering at a power of 800 W for 5 min. Then, copper-silver composite gate lines were fabricated on the Ni-V alloy layer surface using electroplating at a temperature of 55℃ and a current density of 2.5 A / dm². 2 Finally, a screen printing process was used to print low-silver-content silver paste manifolds, which were then sintered (temperature 780℃, time 13min).

[0074] Example 2 The N-type back contact battery provided in this embodiment includes: an N-type silicon substrate; The front side of the N-type silicon substrate is sequentially formed with a textured layer, a SiO2 transition layer, and a SiN layer. x Anti-reflection passivation layer; SiO2 transition layer thickness is 12nm; SiN x The antireflective passivation layer has a thickness of 75 nm, a refractive index of 2.1, and a hydrogen content of ≥10 at.%; The back side of the N-type silicon substrate has alternating P-type and N-type doped contact regions. The surfaces of the P-type and N-type doped contact regions are covered with a composite passivation contact layer, which includes an Al₂O₃ passivation layer, a TiN transition layer, and a polycrystalline silicon contact layer. The Al₂O₃ passivation layer is in contact with the P-type and N-type doped contact regions. The thickness of the Al₂O₃ passivation layer is 25 nm; the thickness of the TiN transition layer is 8 nm; and the thickness of the polycrystalline silicon contact layer is 45 nm, with a crystallinity ≥85%. A modified electrode is disposed on the composite passivation contact layer; the modified electrode includes: a nickel-vanadium alloy layer disposed on the surface of the composite passivation contact layer; an electrode grid line disposed on the surface of the nickel-vanadium alloy layer; and a bus bar electrically connected to the electrode grid line; In the nickel-vanadium alloy layer, the mass ratio of nickel to vanadium is 85:15; the thickness of the nickel-vanadium alloy layer is 6 nm. The electrode grid line includes: copper grid lines laid on the surface of the nickel-vanadium alloy layer and a silver plating layer disposed on the copper grid lines; the thickness of the copper grid lines is 12 μm; the thickness of the silver plating layer is 1.5 μm; The busbar is made of low silver content silver paste (silver content 75wt.%), prepared by screen printing process, with a thickness of 22μm, and is perpendicularly connected to the grid lines; An edge passivation layer is disposed at the edge of the N-type silicon substrate, and the edge passivation layer is respectively connected to the SiN... x The anti-reflection passivation layer and the composite passivation contact layer are seamlessly connected to form a fully enclosed passivation protection structure; the edge passivation layer, from the inside out, includes: an Al2O3 layer and a SiN layer. x The Al2O3 layer is 35 nm thick, and the SiN layer is... x The layer thickness is 55nm; The velvet structure layer is the same as in Example 1; The P-type doped contact region is boron doped with a doping concentration of 1.2 × 10⁻⁶. 20 cm -3 The doping depth is 0.35 μm; the N-type doped contact region uses phosphorus doping with a doping concentration of 6 × 10⁻⁶. 18 cm -3 The doping depth is 0.25 μm; the width ratio of the P-type doped contact region to the N-type doped contact region is 1.3:1, and the spacing between two adjacent doped contact regions is 55 μm.

[0075] The above-mentioned method for preparing an N-type BC battery includes the following steps: 1. Same as Example 1.

[0076] 2. Same as Example 1.

[0077] 3. Backside doped contact region fabrication: The silicon substrate with the film layer fabricated on the front side is flipped over, and the natural oxide layer on the back side is removed by plasma etching (etching time 5 min, etching power 600 W); then, P-type doped contact regions and N-type doped contact regions are fabricated on the back side by laser doping. The P-type doping uses a boron doping source, laser power 100 W, scanning speed 600 mm / s; the N-type doping uses a phosphorus doping source, laser power 80 W, scanning speed 500 mm / s; after doping, an annealing process is performed (temperature 500℃, time 40 min).

[0078] 4. Preparation of composite passivation contact layer: The silicon substrate with the back side doped is placed in an ALD device, and an Al2O3 passivation layer is deposited on the surface of all doped contact areas on the back side; then it is transferred to a magnetron sputtering device to deposit a TiN transition layer; then it is transferred to a PECVD device to deposit an amorphous silicon layer, and then low-temperature crystallization (temperature 500℃, time 35min) is performed to form a polycrystalline silicon contact layer.

[0079] 5. Same as Example 1.

[0080] 6. Modified Electrode Fabrication: First, a Ni-V alloy layer was deposited on the surface of the composite passivated contact layer using magnetron sputtering at a power of 900 W for 6 min. Then, copper-silver composite gate lines were fabricated on the surface of the Ni-V alloy layer using electroplating at a temperature of 60℃ and a current density of 3 A / dm². 2 Finally, a screen printing process was used to print low-silver-content silver paste manifolds, which were then sintered (at 800℃ for 15 minutes).

[0081] Example 3 The N-type back contact battery provided in this embodiment includes: an N-type silicon substrate; The front side of the N-type silicon substrate is sequentially formed with a textured layer, a SiO2 transition layer, and a SiN layer. x Anti-reflection passivation layer; SiO2 transition layer thickness is 22nm; SiN x The antireflective passivation layer has a thickness of 95 nm, a refractive index of 2.3, and a hydrogen content of ≥10 at.%; The back side of the N-type silicon substrate has alternating P-type and N-type doped contact regions. The surfaces of the P-type and N-type doped contact regions are covered with a composite passivation contact layer, which includes an Al₂O₃ passivation layer, a TiN transition layer, and a polycrystalline silicon contact layer. The Al₂O₃ passivation layer is in contact with the P-type and N-type doped contact regions. The thickness of the Al₂O₃ passivation layer is 35 nm; the thickness of the TiN transition layer is 15 nm; the thickness of the polycrystalline silicon contact layer is 60 nm; and the crystallinity is ≥85%. A modified electrode is disposed on the composite passivation contact layer; the modified electrode includes: a nickel-vanadium alloy layer disposed on the surface of the composite passivation contact layer; an electrode grid line disposed on the surface of the nickel-vanadium alloy layer; and a bus bar electrically connected to the electrode grid line; In the nickel-vanadium alloy layer, the mass ratio of nickel to vanadium is 95:5; the thickness of the nickel-vanadium alloy layer is 12 nm. The electrode grid line includes: a copper grid line laid on the surface of the nickel-vanadium alloy layer and a silver plating layer disposed on the copper grid line; the thickness of the copper grid line is 18 μm; the thickness of the silver plating layer is 2.5 μm; The busbar is made of low silver content silver paste (silver content 85wt.%), prepared by screen printing process, with a thickness of 32μm, and is perpendicularly connected to the grid lines; An edge passivation layer is disposed at the edge of the N-type silicon substrate, and the edge passivation layer is respectively connected to the SiN... x The anti-reflection passivation layer and the composite passivation contact layer are seamlessly connected to form a fully enclosed passivation protection structure; the edge passivation layer, from the inside out, includes: an Al2O3 layer and a SiN layer. x The Al2O3 layer has a thickness of 45 nm, and the SiN layer... x The layer thickness is 65nm; The velvet structure layer is the same as in Example 1; The P-type doped contact region is boron doped with a doping concentration of 1.2 × 10⁻⁶. 19 cm -3 The doping depth is 0.55 μm; the N-type doped contact region uses phosphorus doping with a doping concentration of 6 × 10⁻⁶. 19 cm -3 The doping depth is 0.45 μm; the width ratio of the P-type doped contact region to the N-type doped contact region is 1.6:1, and the spacing between two adjacent doped contact regions is 85 μm.

[0082] The above-mentioned method for preparing an N-type BC battery includes the following steps: 1. Same as Example 1.

[0083] 2. Same as Example 1.

[0084] 3. Fabrication of back-side doped contact regions: The silicon substrate with the film layer prepared on the front side is flipped over, and the natural oxide layer on the back side is removed by plasma etching (etching time 3 min, etching power 500 W); then, P-type doped contact regions and N-type doped contact regions are prepared on the back side by laser doping. The P-type doping uses a boron doping source, laser power 80 W, scanning speed 500 mm / s; the N-type doping uses a phosphorus doping source, laser power 60 W, scanning speed 400 mm / s; after doping, an annealing process is performed (temperature 450℃, time 30 min).

[0085] 4. Preparation of composite passivation contact layer: The silicon substrate with the back side doped is placed in an ALD device, and an Al2O3 passivation layer is deposited on the surface of all doped contact areas on the back side; then it is transferred to a magnetron sputtering device to deposit a TiN transition layer; then it is transferred to a PECVD device to deposit an amorphous silicon layer, and then low-temperature crystallization (temperature 450℃, time 25min) is performed to form a polycrystalline silicon contact layer.

[0086] 5. Same as Example 1.

[0087] 6. Modified Electrode Fabrication: First, a Ni-V alloy layer was deposited on the surface of the composite passivated contact layer using magnetron sputtering at a power of 700 W for 4 min. Then, copper-silver composite gate lines were fabricated on the surface of the Ni-V alloy layer using electroplating at a temperature of 50℃ and a current density of 2 A / dm². 2 Finally, a screen printing process was used to print low-silver-content silver paste manifolds, which were then sintered (at 750℃ for 10 minutes).

[0088] Although the present invention has been illustrated and described with specific embodiments, it should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; those skilled in the art should understand that modifications can be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein, without departing from the spirit and scope of the present invention; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An N-type back contact battery, characterized in that, include: N-type silicon substrate; The front side of the N-type silicon substrate is sequentially formed with a textured layer, a SiO2 transition layer, and a SiN layer. x Anti-reflection passivation layer; The back side of the N-type silicon substrate has alternating P-type doped contact regions and N-type doped contact regions, and the surfaces of the P-type doped contact regions and the N-type doped contact regions are covered with a composite passivation contact layer; the composite passivation contact layer includes: an Al2O3 passivation layer, a TiN transition layer and a polycrystalline silicon contact layer; the Al2O3 passivation layer is in contact with the P-type doped contact regions and the N-type doped contact regions; A modified electrode is disposed on the composite passivation contact layer; the modified electrode includes: a nickel-vanadium alloy layer disposed on the surface of the composite passivation contact layer; an electrode grid line disposed on the surface of the nickel-vanadium alloy layer; and a busbar electrically connected to the electrode grid line.

2. The N-type back contact battery according to claim 1, characterized in that, Includes at least one of the following technical features: (1) The thickness of the Al2O3 passivation layer is 25~35nm; (2) The thickness of the TiN transition layer is 8~15nm; (3) The thickness of the polycrystalline silicon contact layer is 45~60nm.

3. The N-type back contact battery according to claim 1, characterized in that, In the nickel-vanadium alloy layer, the mass ratio of nickel to vanadium is 85~95:5~15; And / or, the thickness of the nickel-vanadium alloy layer is 6~12nm.

4. The N-type back contact battery according to claim 1, characterized in that, The electrode grid lines include: copper grid lines laid on the surface of the nickel-vanadium alloy layer and silver plating layers disposed on the copper grid lines.

5. The N-type back contact battery according to claim 4, characterized in that, The thickness of the copper grid line is 12~18μm; And / or, the thickness of the silver plating layer is 1.5~2.5μm.

6. The N-type back contact battery according to claim 1, characterized in that, The busbar is mainly made of silver paste, and the silver content in the silver paste is 75wt%~85wt%. And / or, the N-type back contact cell further includes: an edge passivation layer; the edge passivation layer is attached to the surrounding sidewalls of the N-type silicon substrate.

7. The N-type back contact battery according to claim 6, characterized in that, The edge passivation layer comprises, from the inside out, an Al2O3 layer and a SiN layer. x layer; And / or, the thickness of the Al2O3 layer is 35~45nm, and the SiN layer is... x The thickness of the layer is 55~65nm.

8. The method for preparing an N-type back contact battery according to any one of claims 1 to 7, characterized in that, Includes the following steps: (a) Fabrication of a textured structure layer, deposition of a SiO2 transition layer, and deposition of SiN on the front side of an N-type silicon substrate. x Anti-reflection passivation layer; (b) A P-type doped contact region and an N-type doped contact region are prepared on the back side of an N-type silicon substrate; a composite passivation contact layer is prepared on the surface of the P-type doped contact region and the N-type doped contact region; (c) Deposit a nickel-vanadium alloy layer on the composite passivated contact layer; fabricate an electrode grid line on the nickel-vanadium alloy layer; fabricate a busbar.

9. The method for preparing an N-type back contact battery according to claim 8, characterized in that, Includes at least one of the following technical features: (1) The method for preparing the composite passivation contact layer includes the following steps: depositing an Al2O3 passivation layer, a TiN transition layer, and an amorphous silicon layer on the surface of the P-type doped contact region and the N-type doped contact region; crystallizing the amorphous silicon to form a polycrystalline silicon contact layer; (2) The method for preparing the N-type back contact battery further includes: preparing an edge passivation layer on the four sidewalls of the N-type silicon substrate.

10. A photovoltaic module, characterized in that, The N-type back contact battery includes the N-type back contact battery as described in any one of claims 1 to 7 or the N-type back contact battery prepared by the preparation method of the N-type back contact battery as described in claim 8 or 9.

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