Silicon heterojunction cell, photovoltaic module and method for manufacturing silicon heterojunction cell

Abstract

The application provides a silicon heterojunction cell, a photovoltaic module and a preparation method of the silicon heterojunction cell, and relates to the technical field of photovoltaics.The silicon heterojunction cell provided by the application comprises an N-type crystalline silicon substrate, the N-type crystalline silicon substrate comprises a center thinning area, a transition area and an edge strengthening area, and the thickness of the transition area continuously decreases from the edge strengthening area to the center thinning area; a first intrinsic amorphous silicon layer is arranged on the front surface of the N-type crystalline silicon substrate; a P-type amorphous silicon layer is arranged outside the first intrinsic amorphous silicon layer; a second intrinsic amorphous silicon layer is arranged on the back surface of the N-type crystalline silicon substrate; an N-type amorphous silicon layer is arranged outside the second intrinsic amorphous silicon layer; and a transparent conductive oxide film is arranged outside the P-type amorphous silicon layer and the N-type amorphous silicon layer.The silicon heterojunction cell, the photovoltaic module and the preparation method of the silicon heterojunction cell provided by the application can ensure the mechanical properties and production yield of the silicon heterojunction cell under the condition of reducing the amount of silicon material.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a silicon heterojunction cell, a photovoltaic module, and a method for preparing a silicon heterojunction cell. Background Technology

[0002] Silicon heterojunction solar cells are a new type of high-efficiency photovoltaic cell combining a crystalline silicon substrate and an amorphous silicon thin film, belonging to the next generation of crystalline silicon cell technology. This technology is based on a crystalline silicon light-absorbing substrate, combined with a high-quality amorphous silicon thin film to form a heterojunction structure. It enables passivation and junction layer preparation at low temperatures, effectively avoiding the material loss and performance defects caused by the high-temperature preparation of traditional crystalline silicon cells. With its unique structural and process advantages, it has become a core technology direction for key research and industrialization in the photovoltaic field. In the manufacturing of silicon heterojunction solar cells, the silicon wafer is the core substrate, and its material cost accounts for a very high proportion of the overall manufacturing cost. The total amount of silicon material consumed directly determines the production cost level of silicon heterojunction solar cells. Therefore, optimizing the process to achieve ultra-thin silicon wafers and reduce the amount of silicon material used per watt is currently the most direct and core technical path for the silicon heterojunction solar cell industry to reduce costs, increase efficiency, and enhance product market competitiveness.

[0003] However, due to the inherent mechanical brittleness of crystalline silicon, this characteristic leads to a significant decrease in overall mechanical properties and fracture resistance as the wafer thickness decreases. With the continuous reduction in wafer thickness, the yield rate during wafer slicing becomes difficult to guarantee. Furthermore, during production line transport and multi-process manufacturing, warping and deformation are highly likely to occur, significantly increasing the risk of uncontrollable impacts and breakage during production. Ultimately, this results in a substantial increase in the breakage rate of battery production, severely impacting the yield of silicon heterojunction solar cells.

[0004] Therefore, how to ensure the mechanical properties and production yield of silicon heterojunction solar cells while reducing the amount of silicon material used is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] This application provides a silicon heterojunction cell, a photovoltaic module, and a method for preparing a silicon heterojunction cell, which can ensure the mechanical properties and production yield of the silicon heterojunction cell while reducing the amount of silicon material used.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] In a first aspect, this application provides a silicon heterojunction solar cell, comprising:

[0008] An N-type crystalline silicon substrate includes a central thinning region, a transition region, and an edge reinforcement region. The transition region surrounds the central thinning region, and the edge reinforcement region surrounds the transition region. The thickness of the edge reinforcement region is greater than the thickness of the central thinning region. The outer side of the transition region is connected to the edge reinforcement region, and the inner side of the transition region is connected to the central thinning region. The thickness of the transition region continuously decreases from the edge reinforcement region to the central thinning region.

[0009] The first intrinsic amorphous silicon layer is disposed on the front side of the N-type crystalline silicon substrate;

[0010] A P-type amorphous silicon layer is disposed outside the first intrinsic amorphous silicon layer;

[0011] The second intrinsic amorphous silicon layer is disposed on the back side of the N-type crystalline silicon substrate;

[0012] An N-type amorphous silicon layer is disposed outside the second intrinsic amorphous silicon layer;

[0013] A transparent conductive oxide thin film is disposed outside a P-type amorphous silicon layer and an N-type amorphous silicon layer.

[0014] As an optional implementation, the thickness of the edge reinforcement region is 130μm-180μm, and the thickness of the central thinning region is 80μm-120μm.

[0015] As an optional implementation, the area of ​​the central thinning region accounts for 85%-95% of the total area of ​​the N-type crystalline silicon substrate.

[0016] As an optional implementation, the thickness of the first intrinsic amorphous silicon layer is 5nm-10nm, and the thickness of the P-type amorphous silicon layer is 20nm-30nm.

[0017] As an optional implementation, the thickness of the second intrinsic amorphous silicon layer is 4nm-8nm, and the thickness of the N-type amorphous silicon layer is 8nm-15nm.

[0018] As an optional implementation, the transparent conductive oxide film is indium tin oxide, aluminum-doped zinc oxide, or indium tungsten oxide.

[0019] As an alternative implementation, the N-type crystalline silicon substrates are symmetrical to each other along their thickness direction.

[0020] Secondly, this application also provides a photovoltaic module, including the silicon heterojunction cell described in the first aspect.

[0021] Thirdly, this application also provides a method for preparing a silicon heterojunction solar cell, used to prepare the silicon heterojunction solar cell of the first aspect, comprising the following steps:

[0022] N-type single-crystal silicon rods are cut into silicon wafers with a thickness of 130μm-180μm using diamond wire.

[0023] An edge reinforcement region covered by a mask protective layer is formed at the edge of both sides of the silicon wafer. An etching process is used to etch the areas on the silicon wafer not covered by the mask protective layer to form a central thinning region with a thickness of 80μm-120μm and a transition region connecting the central thinning region and the edge reinforcement region. The thickness of the transition region increases continuously from the central thinning region to the edge reinforcement region, thereby fabricating an N-type crystalline silicon substrate with central thinning and edge reinforcement. The mask protective layer is a photoresist, silicon oxide or silicon nitride thin film.

[0024] A plasma-enhanced chemical vapor deposition process is used to sequentially deposit a first intrinsic amorphous silicon layer with a thickness of 5nm-10nm and a P-type amorphous silicon layer with a thickness of 20nm-30nm on the front side of an N-type crystalline silicon substrate. On the back side of the N-type crystalline silicon substrate, a second intrinsic amorphous silicon layer with a thickness of 4nm-8nm and an N-type amorphous silicon layer with a thickness of 8nm-15nm are sequentially deposited. Transparent conductive oxide films made of indium tin oxide, aluminum-doped zinc oxide, or indium tungsten oxide are deposited on the outside of the P-type and N-type amorphous silicon layers, respectively.

[0025] As an optional implementation, prior to processing with plasma-enhanced chemical vapor deposition, the following steps are also included:

[0026] An N-type crystalline silicon substrate is immersed in a 5%-15% potassium hydroxide or sodium hydroxide solution and treated at 70℃-85℃ for 3 to 10 minutes. The central thinning area and the transition area are then etched using an alkaline solution containing texturing additives to form a textured surface on the central thinning area and the transition area.

[0027] The silicon heterojunction solar cell provided in this application sets a central thinning region, a transition region, and an edge reinforcement region on an N-type crystalline silicon substrate. The transition region surrounds the central thinning region, and the edge reinforcement region surrounds the transition region. The thickness of the edge reinforcement region is greater than that of the central thinning region. The outer side of the transition region is connected to the edge reinforcement region, and the inner side of the transition region is connected to the central thinning region. The thickness of the transition region continuously decreases from the edge reinforcement region to the central thinning region. The central thinning region can achieve thinning of the main area of ​​the silicon wafer, reducing the amount of silicon material used and achieving cost reduction and efficiency improvement of the cell. The edge reinforcement region retains a larger thickness, improving the structural strength and fracture resistance at the edge of the silicon wafer. The transition region achieves a continuous and smooth thickness transition, avoiding stress concentration caused by abrupt thickness changes, alleviating silicon wafer warping and deformation, and reducing the risk of impact and breakage during wafer preparation, production line transfer, and multi-process processing. Thus, while reducing silicon material consumption, it ensures the overall mechanical performance and production yield of the cell. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A schematic diagram of a silicon heterojunction solar cell provided in an embodiment of this application;

[0030] Figure 2 A cross-sectional view of a silicon heterojunction solar cell provided in an embodiment of this application;

[0031] Figure 3 This is a schematic diagram of an N-type crystalline silicon substrate in a silicon heterojunction solar cell provided in an embodiment of this application.

[0032] Explanation of reference numerals in the attached figures:

[0033] 100. Silicon heterojunction solar cell; 110. N-type crystalline silicon substrate; 111. Central thinning region; 112. Transition region; 113. Edge reinforcement region; 120. First intrinsic amorphous silicon layer; 130. P-type amorphous silicon layer; 140. Second intrinsic amorphous silicon layer; 150. N-type amorphous silicon layer; 160. Transparent conductive oxide thin film. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] In this application, the terms “upper,” “lower,” “left,” “right,” “front,” “back,” “top,” “bottom,” “inner,” “outer,” “vertical,” “horizontal,” “lateral,” and “longitudinal” indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to be constructed and operated in a specific orientation.

[0036] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0037] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0038] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, elements, or components (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, elements, or components. Unless otherwise stated, "a plurality of" means two or more.

[0039] Silicon heterojunction solar cells are a new type of high-efficiency photovoltaic cell that combines a crystalline silicon substrate with an amorphous silicon thin film, belonging to the next generation of crystalline silicon cell technology. In the manufacturing of silicon heterojunction solar cells, the silicon wafer is the core substrate, and its material cost accounts for a very high proportion of the overall manufacturing cost. The total amount of silicon material consumed directly determines the production cost level of silicon heterojunction solar cells. Therefore, optimizing the process to achieve ultra-thin silicon wafers and reduce the amount of silicon material used per watt is currently the most direct and core technical path for the silicon heterojunction solar cell industry to reduce costs, increase efficiency, and enhance product market competitiveness. However, due to the inherent mechanical brittleness of crystalline silicon, this material characteristic leads to a significant decrease in overall mechanical properties and fracture resistance after the silicon wafer thickness is reduced, resulting in a sharp increase in the breakage rate during cell production and seriously affecting the production yield of silicon heterojunction solar cells.

[0040] In view of this, this application provides a silicon heterojunction solar cell, which sets a central thinning region, a transition region, and an edge reinforcement region on an N-type crystalline silicon substrate. The transition region surrounds the central thinning region, and the edge reinforcement region surrounds the transition region. The thickness of the edge reinforcement region is greater than that of the central thinning region. The outer side of the transition region is connected to the edge reinforcement region, and the inner side of the transition region is connected to the central thinning region. The thickness of the transition region continuously decreases from the edge reinforcement region to the central thinning region. The central thinning region can achieve thinning of the main area of ​​the silicon wafer, reduce the amount of silicon material used, and achieve cost reduction and efficiency improvement of the cell. The edge reinforcement region retains a larger thickness, which improves the structural strength and fracture resistance of the edge position of the silicon wafer. The transition region achieves a continuous and smooth thickness transition, avoids stress concentration caused by abrupt thickness changes, alleviates silicon wafer warping deformation, and reduces the risk of impact and breakage during wafer preparation, production line transfer, and multi-process processing. Thus, while reducing silicon material consumption, it ensures the overall mechanical performance and production yield of the cell.

[0041] Figure 1 A schematic diagram of a silicon heterojunction solar cell provided in an embodiment of this application; Figure 2A cross-sectional view of a silicon heterojunction solar cell provided in an embodiment of this application; Figure 3 This is a schematic diagram of an N-type crystalline silicon substrate in a silicon heterojunction solar cell provided in an embodiment of this application.

[0042] You can refer to this. Figures 1 to 3 This application provides a silicon heterojunction solar cell 100, comprising:

[0043] An N-type crystalline silicon substrate 110 includes a central thinning region 111, a transition region 112, and an edge reinforcement region 113. The transition region 112 surrounds the central thinning region 111, and the edge reinforcement region 113 surrounds the transition region 112. The thickness of the edge reinforcement region 113 is greater than the thickness of the central thinning region 111. The outer side of the transition region 112 is connected to the edge reinforcement region 113, and the inner side of the transition region 112 is connected to the central thinning region 111. The thickness of the transition region 112 continuously decreases from the edge reinforcement region 113 to the central thinning region 111.

[0044] The first intrinsic amorphous silicon layer 120 is disposed on the front side of the N-type crystalline silicon substrate 110;

[0045] A p-type amorphous silicon layer 130 is disposed outside the first intrinsic amorphous silicon layer 120;

[0046] A second intrinsic amorphous silicon layer 140 is disposed on the back side of the N-type crystalline silicon substrate 110;

[0047] An N-type amorphous silicon layer 150 is disposed outside the second intrinsic amorphous silicon layer 140;

[0048] A transparent conductive oxide thin film 160 is disposed outside the P-type amorphous silicon layer 130 and the N-type amorphous silicon layer 150.

[0049] The silicon heterojunction solar cell 100 provided in this application embodiment comprises a central thinning region 111, a transition region 112, and an edge reinforcement region 113 formed on an N-type crystalline silicon substrate 110. The transition region 112 surrounds the central thinning region 111, and the edge reinforcement region 113 surrounds the transition region 112. The thickness of the edge reinforcement region 113 is greater than the thickness of the central thinning region 111. The outer side of the transition region 112 is connected to the edge reinforcement region 113, and the inner side of the transition region 112 is connected to the central thinning region 111. The thickness of the transition region 112 increases from the edge reinforcement region 113 towards the center. The thinning zone 111 continuously decreases in size. The central thinning zone 111 can achieve thinning of the main area of ​​the silicon wafer, reduce the amount of silicon material used, and achieve cost reduction and efficiency improvement of the battery. The edge reinforcement zone 113 retains a larger thickness, improves the structural strength and fracture resistance of the edge of the silicon wafer, and the transition zone 112 achieves a continuous and smooth thickness transition, avoids stress concentration caused by abrupt thickness changes, alleviates silicon wafer warping and deformation, and reduces the risk of impact and breakage during wafer preparation, production line transfer and multi-process processing. Thus, while reducing silicon material consumption, it ensures the overall mechanical performance and production yield of the battery.

[0050] In this battery, the N-type crystalline silicon substrate 110 serves as the core substrate, playing a crucial role in light absorption and carrier transport. A first intrinsic amorphous silicon layer 120 is disposed on the front side of the N-type crystalline silicon substrate 110, effectively passivating surface defects on the front side of the silicon substrate, reducing interfacial carrier recombination losses, and improving the battery's photoelectric conversion efficiency. A P-type amorphous silicon layer 130 is deposited outside the first intrinsic amorphous silicon layer 120, forming a front heterojunction structure with the N-type crystalline silicon substrate 110. This structure constructs a forward electric field for the separation and transport of photogenerated carriers, enabling effective collection of photogenerated holes. A second intrinsic amorphous silicon layer 140 is disposed on the N-type crystalline silicon substrate 110. The back side of the bulk silicon substrate 110 can passivate surface and interface defects on the back side of the silicon substrate, further suppress carrier recombination, and optimize the minority carrier lifetime of the battery. The N-type amorphous silicon layer 150 is disposed outside the second intrinsic amorphous silicon layer 140 to form a back field structure, which effectively reflects minority carriers, reduces the probability of back carrier recombination, and improves carrier collection efficiency. The transparent conductive oxide film 160 covers the outside of the P-type amorphous silicon layer 130 and the N-type amorphous silicon layer 150, and has excellent light transmittance and conductivity. It can ensure that sunlight can effectively enter the battery and can also realize the rapid export of photogenerated carriers to complete the battery current collection and output.

[0051] In the above embodiments, the thickness of the edge reinforcement region 113 can be 130μm-180μm, and the thickness of the central thinning region 111 is 80μm-120μm. The edge reinforcement region 113's thickness of 130μm-180μm ensures sufficient structural rigidity at the edge of the silicon wafer, improving its impact and bending resistance, and suppressing edge chipping and breakage during transmission and processing. The central thinning region 111, selected at 80μm-120μm, significantly reduces silicon material consumption in the main body of the wafer, achieving cost reduction while maintaining sufficient silicon substrate thickness to ensure light absorption capacity, avoiding insufficient light absorption due to an excessively thin substrate. The thickness continuously changes from the edge reinforcement region 113 to the central thinning region 111 via the transition region 112, mitigating interface stress caused by the thickness difference and reducing the risk of warping deformation. If the edge reinforcement region 113 is too thin... If the thickness is less than 130μm, the structural strength of the edge is insufficient and cannot play a reinforcing role. The edge of the silicon wafer is still prone to chipping and breakage, and the fragmentation rate increases. If the thickness of the edge reinforcement zone 113 is greater than 180μm, it will increase the overall silicon material consumption of the silicon wafer, weaken the cost reduction effect of ultrathin wafers, and increase the overall weight of the silicon wafer, which will exacerbate the deformation risk during transmission. If the thickness of the central thinning zone 111 is less than 80μm, the mechanical strength of the silicon wafer substrate is insufficient, and the whole wafer is prone to breakage. At the same time, the light absorption capacity of the silicon substrate decreases, the short-circuit current of the battery decreases, and the photoelectric performance deteriorates. If the thickness of the central thinning zone 111 is greater than 120μm, the reduction of silicon material is limited, and it is difficult to give full play to the technical advantages of cost reduction and efficiency improvement of ultrathin silicon wafers.

[0052] In the above embodiments, the area of ​​the central thinning region 111 can account for 85%-95% of the total area of ​​the N-type crystalline silicon substrate 110. This area ratio allows for thinning of most areas of the silicon wafer, maximizing the cost reduction effect of ultra-thinning. At the same time, a reasonable area is reserved for the transition area 112 and the edge reinforcement area 113. The edge reinforcement area 113 maintains the overall edge mechanical strength of the silicon wafer, ensuring the wafer's resistance to breakage during slicing, transport, and various processing steps. If the area ratio of the central thinning area 111 is less than 85%, the central thinning area 111 is too small, and the edge reinforcement area 113 and the transition area 112 occupy too much substrate area. The overall silicon material reduction of the silicon wafer is limited, the reduction in silicon consumption is insufficient, and the cost reduction benefits of ultra-thinning are weakened. If the area ratio of the central thinning area 111 is greater than 95%, the annular width of the edge reinforcement area 113 and the transition area 112 will be too narrow, the effective support area of ​​the edge reinforcement structure will be insufficient, the edge reinforcement effect will be difficult to fully exert, the edge resistance to bending and impact of the silicon wafer will decrease, and edge chipping and cracking will easily occur, increasing the production breakage rate and thus affecting the yield of battery production.

[0053] In the above embodiments, the thickness of the first intrinsic amorphous silicon layer 120 can be 5nm-10nm, and the thickness of the p-type amorphous silicon layer 130 can be 20nm-30nm. The 5nm-10nm thickness of the first intrinsic amorphous silicon layer 120 can fully cover the surface dangling bonds on the front side of the N-type crystalline silicon substrate 110, achieving a good interface passivation effect and effectively reducing interface carrier recombination loss. Simultaneously, the moderate film thickness can reduce light absorption loss, ensuring that incident light enters the silicon substrate. The 20nm-30nm thickness of the p-type amorphous silicon layer 130 can form a stable p-type doped heterojunction, constructing an effective built-in electric field to achieve efficient transport and collection of photogenerated holes. If the thickness of the first intrinsic amorphous silicon layer 120 is less than 5 nm, the film cannot completely cover the surface of the silicon substrate, resulting in insufficient passivation, increased interfacial recombination rate, and decreased open-circuit voltage. If the thickness of the first intrinsic amorphous silicon layer 120 is greater than 10 nm, the light absorption loss of the amorphous silicon layer increases, reducing the number of photons reaching the silicon substrate, causing a decrease in short-circuit current and a decline in battery output performance. If the thickness of the P-type amorphous silicon layer 130 is less than 20 nm, the doped film is too thin, resulting in insufficient effective doped carriers, a weak built-in electric field in the heterojunction, poor hole collection ability, increased series resistance, and a decrease in battery fill factor. If the thickness of the P-type amorphous silicon layer 130 is greater than 30 nm, it will increase the parasitic absorption of sunlight by the film, causing aggravated light loss. At the same time, the number of defects in the film increases, the probability of carrier recombination increases, and thus the photoelectric conversion performance of the battery deteriorates.

[0054] In the above embodiments, the thickness of the second intrinsic amorphous silicon layer 140 can be 4nm-8nm, and the thickness of the N-type amorphous silicon layer 150 is 8nm-15nm. The 4nm-8nm thickness of the second intrinsic amorphous silicon layer 140 can effectively passivate the surface dangling bonds on the back side of the N-type crystalline silicon substrate 110, suppress carrier recombination at the back interface, improve minority carrier lifetime, and simultaneously control parasitic light absorption losses caused by the amorphous silicon thin film. The 8nm-15nm thickness of the N-type amorphous silicon layer 150 can form a stable and effective back surface field structure, creating a reflective barrier for photogenerated minority carriers, reducing back surface carrier recombination, and improving electron collection efficiency.

[0055] If the thickness of the second intrinsic amorphous silicon layer 140 is less than 4 nm, it will lead to insufficient film coverage integrity, inadequate passivation of interface defects on the back side of the silicon substrate, increased interface recombination, and damage to the open-circuit voltage of the battery. If the thickness of the second intrinsic amorphous silicon layer 140 is greater than 8 nm, the parasitic absorption of amorphous silicon will increase, resulting in a worse long-wavelength response and a decrease in short-circuit current. If the thickness of the N-type amorphous silicon layer 150 is less than 8 nm, it will lead to insufficient effective doping concentration of the doped layer, weakened reflection blocking effect of the back surface field, increased back surface carrier recombination, increased series resistance, and decreased fill factor. If the thickness of the N-type amorphous silicon layer 150 is greater than 15 nm, it will further aggravate parasitic light absorption of the film, while increasing the internal defect density of the film and introducing additional carrier recombination centers, thereby degrading the overall photoelectric output performance of the battery.

[0056] In the above embodiments, the transparent conductive oxide thin film 160 can be indium tin oxide, aluminum-doped zinc oxide, or indium tungsten oxide. Indium tin oxide, aluminum-doped zinc oxide, or indium tungsten oxide all have excellent visible light transmittance and conductivity, which can ensure that sunlight can pass through the film without loss to the maximum extent and enter the battery to complete photoelectric conversion, while efficiently collecting and exporting photogenerated carriers, effectively reducing the battery series resistance, improving the battery fill factor and overall photoelectric conversion efficiency. Among them, indium tin oxide (ITO) thin films have excellent crystal quality, superior conductivity, and high carrier mobility, enabling the formation of a uniform and dense thin film structure. They exhibit good interfacial adhesion with the upper and lower amorphous silicon film layers, extremely low contact resistance, and a mature fabrication process. The films also demonstrate strong uniformity and controllability, making them suitable for precision coating processes in heterojunction solar cells, ensuring stable and efficient carrier transport. Aluminum-doped zinc oxide (AD) materials are inexpensive to prepare and possess excellent bombardment and processing stability. Their dense and robust film structure can withstand disturbances in subsequent battery manufacturing processes, minimizing the risk of film damage and performance degradation. They offer outstanding cost-effectiveness and process adaptability. Indium tungsten oxide (ITO) materials combine high transmittance and low resistivity, exhibiting strong thermal stability and environmental adaptability. Under high-temperature battery manufacturing processes and long-term outdoor operating conditions, the transmittance and conductivity of the film do not easily degrade, maintaining stable photoelectric output performance over a long period. This effectively improves the lifespan and operational stability of silicon heterojunction solar cells.

[0057] In the above embodiments, the N-type crystalline silicon substrate 110 can be made symmetrical along its thickness direction. The symmetrical structure can keep the morphology and thickness distribution of the front and back sides of the N-type crystalline silicon substrate 110 consistent, so that the stress on both sides of the substrate can cancel each other out during the heating, coating and other processes. This avoids unidirectional warping of the silicon wafer caused by stress differences on one side, reduces the risk of wafer cracking and edge chipping during the process, and facilitates the simultaneous deposition of amorphous silicon thin films on both sides of the substrate. This reduces the problem of stress mismatch between the two sides of the film layers, ensures that the growth conditions of the passivation film layer and the doped film layer on both sides are consistent, and the film layer thickness and quality are uniform and controllable, which is beneficial to improving the overall photoelectric performance consistency of the battery.

[0058] Furthermore, this application embodiment also provides a photovoltaic module, including the silicon heterojunction cell 100 in the above embodiment. The silicon heterojunction cell 100 comprises a central thinning region 111, a transition region 112, and an edge reinforcement region 113 formed on an N-type crystalline silicon substrate 110. The transition region 112 surrounds the central thinning region 111, and the edge reinforcement region 113 surrounds the transition region 112. The thickness of the edge reinforcement region 113 is greater than the thickness of the central thinning region 111. The outer side of the transition region 112 is connected to the edge reinforcement region 113, and the inner side of the transition region 112 is connected to the central thinning region 111. The thickness of the transition region 112 is determined by the thickness of the edge reinforcement region 113. The thickness of the thinning zone 111 decreases continuously towards the center, which reduces the thickness of the main body of the silicon wafer, thereby reducing the amount of silicon material used and achieving cost reduction and efficiency improvement in the battery. The edge reinforcement zone 113 retains a larger thickness, improving the structural strength and fracture resistance of the edge of the silicon wafer. The transition zone 112 achieves a continuous and smooth thickness transition, avoiding stress concentration caused by abrupt thickness changes, alleviating silicon wafer warping and deformation, and reducing the risk of impact and breakage during wafer preparation, production line transfer, and multi-process processing. While reducing silicon material consumption, it ensures the overall mechanical performance and production yield of the battery, thereby reducing the cost of photovoltaic modules and improving their reliability.

[0059] Furthermore, this application embodiment also provides a method for fabricating a silicon heterojunction solar cell 100, used to fabricate the silicon heterojunction solar cell 100 in the above embodiment, comprising the following steps:

[0060] N-type single-crystal silicon rods are cut into silicon wafers with a thickness of 130μm-180μm using diamond wire.

[0061] Edge reinforcement regions 113 covered by a mask protective layer are formed in the edge regions of both sides of the silicon wafer. An etching process is used to etch the areas of the silicon wafer not covered by the mask protective layer to form a central thinning region 111 with a thickness of 80μm-120μm and a transition region 112 connecting the central thinning region 111 and the edge reinforcement region 113. The thickness of the transition region 112 increases continuously from the central thinning region 111 to the edge reinforcement region 113, thereby fabricating an N-type crystalline silicon substrate 110 with central thinning and edge reinforcement. The mask protective layer is a photoresist, silicon oxide or silicon nitride thin film.

[0062] A first intrinsic amorphous silicon layer 120 with a thickness of 5nm-10nm and a P-type amorphous silicon layer 130 with a thickness of 20nm-30nm are sequentially deposited on the front side of an N-type crystalline silicon substrate 110 using a plasma-enhanced chemical vapor deposition process. A second intrinsic amorphous silicon layer 140 with a thickness of 4nm-8nm and an N-type amorphous silicon layer 150 with a thickness of 8nm-15nm are sequentially deposited on the back side of the N-type crystalline silicon substrate 110. A transparent conductive oxide thin film 160 made of indium tin oxide, aluminum-doped zinc oxide, or indium tungsten oxide is deposited on the outside of the P-type amorphous silicon layer 130 and the N-type amorphous silicon layer 150, respectively.

[0063] It is understandable that using diamond wire to cut N-type single-crystal silicon rods into silicon wafers with a thickness of 130μm-180μm, and leveraging the advantages of diamond wire cutting technology—high cutting precision and minimal surface damage—can yield initial silicon wafers with excellent surface quality and uniform thickness, laying a solid foundation for subsequent substrate forming and thin film deposition processes. Subsequently, a mask protective layer composed of photoresist, silicon oxide, or silicon nitride thin films is formed on the edge regions of both sides of the silicon wafer, covering and forming edge reinforcement regions 113. Etching processes are then used to etch the areas of the silicon wafer not covered by the mask protective layer, precisely forming a central thinning region 111 with a thickness of 80μm-120μm. The transition region 112, which connects the central thinning region 111 and the edge reinforcement region 113, allows the thickness of the transition region 112 to continuously increase from the central thinning region 111 to the edge reinforcement region 113, thus stably fabricating a symmetrical N-type crystalline silicon substrate 110 with central thinning and edge reinforcement. This fabrication method can precisely control the thickness structure of different regions of the silicon wafer, significantly reducing the amount of silicon material used in the central region of the substrate and achieving cost reduction and efficiency improvement in the battery, while retaining the structural thickness and mechanical strength of the edge region. Furthermore, the stress concentration problem caused by the abrupt change in thickness is eliminated through the continuously and gradually changing transition region 112, effectively improving the problem of silicon wafer warping and deformation, and enhancing the overall structural stability and production yield of the silicon wafer.

[0064] Finally, plasma-enhanced chemical vapor deposition (PECVD) is used to sequentially deposit a first intrinsic amorphous silicon layer 120 and a P-type amorphous silicon layer 130 of a predetermined thickness on the front side of the N-type crystalline silicon substrate 110, and a second intrinsic amorphous silicon layer 140 and an N-type amorphous silicon layer 150 of a predetermined thickness on the back side. A transparent conductive oxide thin film 160 made of indium tin oxide, aluminum-doped zinc oxide, or indium tungsten oxide is deposited on the outer side. This low-temperature deposition process can avoid the silicon wafer damage, performance degradation, and material loss problems caused by traditional high-temperature processes. It can uniformly deposit various functional films on the surface of silicon substrates with different thicknesses, ensuring the complete formation of the front passivation junction and the back field structure. The thickness of each functional film layer is uniform and the interface is tightly bonded, which can give full play to the functions of interface passivation, carrier separation and collection, and photoelectric conduction, thereby stably preparing a silicon heterojunction cell 100 with excellent mechanical properties, production yield, and photoelectric conversion performance.

[0065] In the above embodiments, prior to the plasma-enhanced chemical vapor deposition process, the following steps may also be included:

[0066] The N-type crystalline silicon substrate 110 is immersed in a 5%-15% potassium hydroxide or sodium hydroxide solution and treated at 70℃-85℃ for 3 to 10 minutes. The central thinning region 111 and the transition region 112 are etched using an alkaline solution containing texturing additives to form a textured surface structure on the surface of the central thinning region 111 and the transition region 112.

[0067] Before using plasma-enhanced chemical vapor deposition (PECVD), the N-type crystalline silicon substrate 110 is immersed in a 5%-15% potassium hydroxide or sodium hydroxide solution and treated at 70℃-85℃ for 3 to 10 minutes. Under these process parameters, the surface damage layer, particulate impurities, and surface microcracks left on the N-type crystalline silicon substrate 110 after cutting and etching (except for the edge reinforcement region 113, which is covered by a mask protective layer) can be efficiently removed, resulting in a clean silicon substrate surface. This provides a high-quality interface foundation for subsequent thin film deposition. Then, an alkaline solution containing texturing additives is used to etch the central thinning region 111 and the transition region 112 to form a textured surface structure on their surfaces. The textured surface structure can increase the light-receiving area of ​​the silicon wafer, extend the light absorption path through multiple diffuse reflections, reduce surface reflection loss, and increase the generation of photogenerated carriers. At the same time, it is beneficial for the uniform adhesion and growth of subsequent amorphous silicon thin films and improves the interface bonding state.

[0068] If the concentration of potassium hydroxide or sodium hydroxide solution is less than 5%, the processing temperature is below 70℃, and the processing time is less than 3 minutes, the corrosion removal capacity will be insufficient, and the damaged layer and impurities on the silicon wafer surface cannot be fully removed. The residual defects will increase the interfacial recombination rate and affect the subsequent film deposition quality. If the concentration of potassium hydroxide or sodium hydroxide solution is greater than 15%, the processing temperature is higher than 85℃, and the processing time is longer than 10 minutes, it will cause excessive corrosion of the silicon substrate, resulting in uncontrollable thinning of the central thinning area 111, destroying the already formed thickness distribution structure of the substrate, aggravating the overall stress of the silicon wafer, increasing the risk of warping and cracking, and causing uncontrolled surface roughness, which is not conducive to the uniform film formation of subsequent amorphous silicon films.

[0069] To facilitate understanding of the solution in this application, several specific implementation examples are listed below:

[0070] Example 1

[0071] N-type single-crystal silicon rods are cut into silicon wafers with a thickness of 130 μm using diamond wire. Then, photoresist mask protective layers are formed on the edge regions of both sides of the silicon wafer, covering and forming edge reinforcement regions 113. Etching processes are used to etch the areas of the silicon wafer not covered by the mask protective layers, forming a central thinning region 111 with a thickness of 80 μm and a transition region 112 whose thickness continuously increases from the central thinning region 111 to the edge reinforcement region 113. The central thinning region 111 accounts for 85% of the total area of ​​the N-type crystalline silicon substrate 110. After substrate forming is completed, the prepared N-type crystalline silicon substrate 110 is immersed in a 5% potassium hydroxide solution and kept at a constant temperature of 70°C. After processing for 3 minutes, an alkaline solution containing texturing additives is used to etch the central thinning region 111 and the transition region 112 to form a uniform texturing structure on the substrate surface. After the pretreatment, a plasma-enhanced chemical vapor deposition process is used to sequentially deposit a first intrinsic amorphous silicon layer 120 with a thickness of 5 nm and a P-type amorphous silicon layer 130 with a thickness of 20 nm on the front side of the N-type crystalline silicon substrate 110. On the back side of the substrate, a second intrinsic amorphous silicon layer 140 with a thickness of 4 nm and an N-type amorphous silicon layer 150 with a thickness of 8 nm are sequentially deposited. Finally, transparent conductive oxide films 160 of indium tin oxide are deposited on the outer sides of the P-type amorphous silicon layer 130 and the N-type amorphous silicon layer 150, respectively.

[0072] Example 2

[0073] N-type single-crystal silicon rods are cut into silicon wafers with a thickness of 155 μm using diamond wire. Subsequently, a silicon oxide mask protective layer is formed on the edge regions of both sides of the silicon wafer to cover and form edge reinforcement regions 113. An etching process is used to etch the areas of the silicon wafer not covered by the mask protective layer to form a central thinning region 111 with a thickness of 100 μm and a transition region 112 whose thickness continuously increases from the central thinning region 111 to the edge reinforcement region 113. The area of ​​the central thinning region 111 accounts for 90% of the total area of ​​the N-type crystalline silicon substrate 110. After the substrate is formed, the prepared N-type crystalline silicon substrate 110 is immersed in a 10% sodium hydroxide solution and is kept at a constant temperature of 78°C. After 5 minutes, an alkaline solution containing texturing additives is used to etch the central thinning region 111 and the transition region 112 to form a uniform texturing structure on the substrate surface. After the pretreatment, plasma-enhanced chemical vapor deposition is used to sequentially deposit a first intrinsic amorphous silicon layer 120 with a thickness of 7.5 nm and a P-type amorphous silicon layer 130 with a thickness of 25 nm on the front side of the N-type crystalline silicon substrate 110. On the back side of the substrate, a second intrinsic amorphous silicon layer 140 with a thickness of 6 nm and an N-type amorphous silicon layer 150 with a thickness of 11.5 nm are sequentially deposited. Finally, transparent conductive oxide films 160 made of aluminum-doped zinc oxide are deposited on the outer sides of the P-type amorphous silicon layer 130 and the N-type amorphous silicon layer 150, respectively.

[0074] Example 3

[0075] N-type single-crystal silicon rods are cut into silicon wafers with a thickness of 180 μm using diamond wire. Then, a silicon nitride thin film mask layer is formed on the edge regions of both sides of the silicon wafer, covering and forming edge reinforcement regions 113. An etching process is used to etch the areas of the silicon wafer not covered by the mask layer, forming a 120 μm thick central thinning region 111 and a transition region 112 whose thickness continuously increases from the central thinning region 111 to the edge reinforcement region 113. The central thinning region 111 accounts for 95% of the total area of ​​the N-type crystalline silicon substrate 110. After substrate forming is completed, the prepared N-type crystalline silicon substrate 110 is immersed in a 15% sodium hydroxide solution and kept at a constant temperature of 85°C. After processing for 10 minutes, an alkaline solution containing texturing additives is used to etch the central thinning region 111 and the transition region 112 to form a uniform texturing structure on the substrate surface. After the pretreatment, a plasma-enhanced chemical vapor deposition process is used to sequentially deposit a first intrinsic amorphous silicon layer 120 with a thickness of 10 nm and a P-type amorphous silicon layer 130 with a thickness of 30 nm on the front side of the N-type crystalline silicon substrate 110. On the back side of the substrate, a second intrinsic amorphous silicon layer 140 with a thickness of 8 nm and an N-type amorphous silicon layer 150 with a thickness of 15 nm are sequentially deposited. Finally, transparent conductive oxide films 160 of indium tungsten oxide are deposited on the outer sides of the P-type amorphous silicon layer 130 and the N-type amorphous silicon layer 150, respectively.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A silicon heterojunction cell, characterized by, include: An N-type crystalline silicon substrate includes a central thinning region, a transition region, and an edge reinforcement region. The transition region surrounds the central thinning region, and the edge reinforcement region surrounds the transition region. The thickness of the edge reinforcement region is greater than the thickness of the central thinning region. The outer side of the transition region is connected to the edge reinforcement region, and the inner side of the transition region is connected to the central thinning region. The thickness of the transition region continuously decreases from the edge reinforcement region to the central thinning region. A first intrinsic amorphous silicon layer is disposed on the front side of the N-type crystalline silicon substrate; A P-type amorphous silicon layer is disposed outside the first intrinsic amorphous silicon layer; A second intrinsic amorphous silicon layer is disposed on the back side of the N-type crystalline silicon substrate; An N-type amorphous silicon layer is disposed outside the second intrinsic amorphous silicon layer; A transparent conductive oxide thin film is disposed outside the P-type amorphous silicon layer and the N-type amorphous silicon layer.

2. The silicon heterojunction cell of claim 1, wherein, The thickness of the edge reinforcement zone is 130μm-180μm, and the thickness of the central thinning zone is 80μm-120μm.

3. The silicon heterojunction cell of claim 1, wherein, The area of ​​the central thinning region accounts for 85%-95% of the total area of ​​the N-type crystalline silicon substrate.

4. The silicon heterojunction cell of claim 1, wherein, The thickness of the first intrinsic amorphous silicon layer is 5nm-10nm, and the thickness of the P-type amorphous silicon layer is 20nm-30nm.

5. The silicon heterojunction cell of claim 1, wherein, The thickness of the second intrinsic amorphous silicon layer is 4nm-8nm, and the thickness of the N-type amorphous silicon layer is 8nm-15nm.

6. The silicon heterojunction cell of claim 1, wherein, The transparent conductive oxide film is indium tin oxide, aluminum-doped zinc oxide, or indium tungsten oxide.

7. The silicon heterojunction cell of claim 1, wherein, The N-type crystalline silicon substrates are symmetrical to each other along their own thickness direction.

8. A photovoltaic module, characterized by, Including the silicon heterojunction solar cell according to any one of claims 1-7.

9. A method of fabricating a silicon heterojunction cell, characterized by, The method for preparing the silicon heterojunction solar cell according to any one of claims 1 to 7 includes the following steps: N-type single-crystal silicon rods are cut into silicon wafers with a thickness of 130μm-180μm using diamond wire. An edge reinforcement region covered by a mask protective layer is formed at the edge regions on both sides of the silicon wafer. An etching process is used to etch the areas on the silicon wafer not covered by the mask protective layer to form a central thinning region with a thickness of 80μm-120μm and a transition region connecting the central thinning region and the edge reinforcement region. The thickness of the transition region continuously increases from the central thinning region to the edge reinforcement region, thereby fabricating an N-type crystalline silicon substrate with central thinning and edge reinforcement. The mask protective layer is a photoresist, silicon oxide, or silicon nitride thin film. A first intrinsic amorphous silicon layer with a thickness of 5nm-10nm and a P-type amorphous silicon layer with a thickness of 20nm-30nm are sequentially deposited on the front side of an N-type crystalline silicon substrate using plasma-enhanced chemical vapor deposition (PECVD). A second intrinsic amorphous silicon layer with a thickness of 4nm-8nm and an N-type amorphous silicon layer with a thickness of 8nm-15nm are sequentially deposited on the back side of the N-type crystalline silicon substrate. Transparent conductive oxide films made of indium tin oxide, aluminum-doped zinc oxide, or indium tungsten oxide are deposited on the outside of the P-type amorphous silicon layer and the N-type amorphous silicon layer, respectively.

10. The method of claim 9, wherein the silicon heterojunction cell is prepared by a process comprising: Prior to the plasma-enhanced chemical vapor deposition process, the procedure further includes: ​ The N-type crystalline silicon substrate is immersed in a potassium hydroxide or sodium hydroxide solution with a concentration of 5%-15%, and is treated at 70-85°C for 3-10 minutes, and the central thinning area and the transition area are subjected to etching treatment using an alkaline solution containing a texturing additive, so that the surface of the central thinning area and the transition area forms a textured structure.

Images