A flat panel detector and a method of manufacturing a flat panel detector

Abstract

The present disclosure provides a kind of detection substrate and flat panel detector, two diodes made by the same manufacturing process of photodiode of detection area are used to build the ESD discharge circuit of periphery, compared with the ESD discharge circuit of traditional transistor built by source-gate shorting, diode forward conduction is more superior than source-gate shorting TFT, it can be opened instantly in positive bias state, the cross-sectional area of current flow is much larger than the cross-sectional area of TFT thin layer channel, the path length of carrier transport is much shorter than the length of TFT channel;Diode reverse cut-off characteristic is more superior than source-gate shorting TFT, leakage current is lower;Since diode does not have the thin gate oxide layer structure of TFT, there is no ESD gate oxide breakdown problem, and the ability to resist large current ablation is much better than TFT.The present disclosure uses diode to build ESD discharge circuit to achieve better static discharge effect, and has stronger ESD breakdown and ablation resistance, which greatly reduces the probability of subsequent laser cutting repair.

Description

Technical Field

[0001] This disclosure relates to the field of backplane technology, and in particular to a detection substrate and a flat panel detector. Background Technology

[0002] Flat X-ray Panel Detectors (FPXDs) based on thin-film transistor (TFT) technology are crucial components in digital imaging technology. Due to their advantages such as fast imaging speed, good spatial and density resolution, high signal-to-noise ratio, and direct digital output, they are widely used in medical imaging (such as chest X-rays), industrial inspection (such as metal flaw detection), security inspection, and air transport.

[0003] X-ray flat panel detectors mainly consist of thin-film transistors (TFTs) and photodiodes (PINs). Under X-ray irradiation, the scintillator or phosphor layer of the indirect conversion type X-ray flat panel detector converts X-ray photons into visible light. Then, under the action of the PIN, the visible light is converted into an electrical signal. Finally, the thin-film transistor reads the electrical signal and outputs it to obtain the displayed image. Summary of the Invention

[0004] This disclosure provides a detection substrate and a flat panel detector, the specific solutions of which are as follows: This disclosure provides a detection substrate, including a detection area and a peripheral area surrounding the detection area. The detection area includes a plurality of detection pixel units arranged in an array. The detection substrate includes: Substrate; Multiple photodiodes are located on one side of the substrate and are respectively located within the detection pixel unit; each photodiode includes a bottom electrode, a photoelectric conversion layer and a top electrode stacked sequentially along a direction away from the substrate. Multiple signal lines are located between the substrate and the photodiode, and are located in the detection area and extend to the peripheral area; An electrostatic discharge lead is located on the side of the photodiode away from the substrate and in the peripheral region; A first diode is connected between the signal line and the electrostatic discharge lead and is located in the peripheral region; the first diode includes: a first positive electrode disposed in the same layer and material as the bottom electrode, a first semiconductor layer disposed in the same layer and material as the photoelectric conversion layer, and a first negative electrode disposed in the same layer and material as the top electrode; The second diode is connected between the signal line and the electrostatic discharge lead and is located in the peripheral region; the second diode includes: a second positive electrode disposed in the same layer and material as the bottom electrode, a second semiconductor layer disposed in the same layer and material as the photoelectric conversion layer, and a second negative electrode disposed in the same layer and material as the top electrode; The first connecting part and the second connecting part are both disposed in the same layer and of the same material as the electrostatic discharge lead; wherein, the first positive electrode is electrically connected to the signal line, the first negative electrode and the second positive electrode are electrically connected at least through the first connecting part, the first positive electrode and the second negative electrode are electrically connected at least through the second connecting part, and the first connecting part is electrically connected to the electrostatic discharge lead.

[0005] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the signal line extends along a first direction, the electrostatic discharge lead extends along a second direction, and the first direction and the second direction intersect. The orthographic projection of the first diode on the substrate and the orthographic projection of the second diode on the substrate are located on the same side of the orthographic projection of the signal line on the substrate, and are located between the orthographic projection of the electrostatic discharge lead on the substrate and the detection area; The orthogonal projection of the first diode on the substrate is located between the orthogonal projection of the signal line on the substrate and the orthogonal projection of the second diode on the substrate.

[0006] In one possible implementation, the detection substrate provided in the embodiments of this disclosure further includes a first adapter portion integrally connected to the signal line, wherein the first adapter portion and the orthographic projection of the first diode on the plane where the signal line is located are located on the same side of the signal line; The first positive electrode includes: a first main body extending along the first direction, and a second adapter electrically connected to one end of the first main body facing the detection area; The orthographic projection of the second adapter on the substrate at least partially overlaps with the orthographic projection of the first adapter on the substrate, and the second adapter and the first adapter are connected by a via.

[0007] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the second positive electrode includes: a second main body portion extending along the first direction, and a third adapter portion electrically connected to the side of the second main body portion facing the first main body portion; the third adapter portion is close to the detection area; The first connection portion includes: a third main body portion extending along the first direction, and a fourth adapter portion electrically connected to the side of the third main body portion facing the second diode; the fourth adapter portion is close to the detection area, and the orthographic projection of the third main body portion on the substrate completely covers the orthographic projection of the first semiconductor layer on the substrate; The third main body is integrally formed with the electrostatic discharge lead at one end. The third main body is connected to the first negative electrode through a via. The orthographic projection of the fourth adapter on the substrate overlaps at least partially with the orthographic projection of the third adapter on the substrate. The fourth adapter is connected to the third adapter through a via.

[0008] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the first positive electrode further includes: a fifth adapter portion electrically connected to the side of the first main body portion facing the second diode; the fifth adapter portion is close to the electrostatic discharge lead; The second connection portion includes: a fourth main body portion extending along the first direction, and a sixth adapter portion electrically connected to the side of the fourth main body portion facing the signal line; the sixth adapter portion is close to the electrostatic discharge lead, and the orthographic projection of the fourth main body portion on the substrate completely covers the orthographic projection of the second semiconductor layer on the substrate; The fourth main body is connected to the second negative electrode through a via, and the orthographic projection of the sixth adapter on the substrate at least partially overlaps with the orthographic projection of the fifth adapter on the substrate. The sixth adapter and the fifth adapter are connected through a via.

[0009] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the signal line extends along a first direction, the electrostatic discharge lead extends along a second direction, and the first direction and the second direction intersect. The orthographic projections of the first diode and the second diode on the substrate are located on the same side of the orthographic projection of the signal line on the substrate. The orthographic projection of the first diode on the substrate is located between the orthographic projection of the electrostatic discharge lead on the substrate and the detection area. The orthographic projection of the second diode on the substrate is located on the side of the orthographic projection of the electrostatic discharge lead on the substrate away from the detection area.

[0010] In one possible implementation, the detection substrate provided in the embodiments of this disclosure further includes a seventh adapter and an eighth adapter integrally connected to the signal line. The orthographic projection of the seventh adapter on the substrate is located on the side of the orthographic projection of the first diode on the substrate that is close to the detection area. The orthographic projection of the eighth adapter on the substrate is located on the side of the orthographic projection of the second diode on the substrate that is far away from the electrostatic discharge lead. The orthographic projection of the first positive electrode on the substrate at least partially overlaps with the orthographic projection of the seventh adapter on the substrate, and the first positive electrode and the seventh adapter are connected through a via. The orthogonal projection of the second connection portion on the substrate completely covers the orthogonal projection of the second semiconductor layer on the substrate, and the second connection portion is connected to the second negative electrode through a via. The orthographic projection of the second connecting portion on the substrate at least partially overlaps with the orthographic projection of the eighth adapter portion on the substrate, and the second connecting portion and the eighth adapter portion are connected by a via.

[0011] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the first connection portion includes: a first sub-connection portion connected to the side of the electrostatic discharge lead near the detection area, and a second sub-connection portion connected to the side of the electrostatic discharge lead away from the detection area; The orthogonal projection of the first sub-connection portion on the substrate completely covers the orthogonal projection of the first semiconductor layer on the substrate, and the first sub-connection portion is connected to the first negative electrode through a via. The orthographic projection of the second sub-connection portion on the substrate at least partially overlaps with the orthographic projection of the second positive electrode on the substrate, and the second sub-connection portion and the second positive electrode are connected through a via.

[0012] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the signal line extends along a first direction, the electrostatic discharge lead extends along a second direction, and the first direction and the second direction intersect. The orthographic projections of the first diode and the second diode on the substrate are located on both sides of the orthographic projection of the signal line on the substrate, and are located between the orthographic projection of the electrostatic discharge lead on the substrate and the detection area.

[0013] In one possible implementation, the detection substrate provided in the embodiments of this disclosure further includes a ninth adapter and a tenth adapter integrally connected to the signal line. The orthographic projection of the ninth adapter on the substrate is located on the side of the orthographic projection of the first diode on the substrate that is close to the detection area. The orthographic projection of the tenth adapter on the substrate is located on the side of the orthographic projection of the second diode on the substrate that is close to the detection area. The orthographic projection of the first positive electrode on the substrate at least partially overlaps with the orthographic projection of the ninth adapter on the substrate, and the first positive electrode and the ninth adapter are connected through a via. The orthogonal projection of the second connection portion on the substrate completely covers the orthogonal projection of the second semiconductor layer on the substrate, and the second connection portion is connected to the second negative electrode through a via. The orthographic projection of the second connecting portion on the substrate at least partially overlaps with the orthographic projection of the tenth adapter portion on the substrate, and the second connecting portion and the tenth adapter portion are connected by a via.

[0014] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the first connection portion includes a third sub-connection portion and a fourth sub-connection portion connected to the side of the electrostatic discharge lead near the detection area; The orthogonal projection of the third sub-connection on the substrate completely covers the orthogonal projection of the first semiconductor layer on the substrate, and the third sub-connection is connected to the first negative electrode through a via. The orthographic projection of the fourth sub-connection on the substrate at least partially overlaps with the orthographic projection of the second positive electrode on the substrate, and the fourth sub-connection is connected to the second positive electrode through a via.

[0015] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the signal line extends along a first direction, the electrostatic discharge lead extends along a second direction, and the first direction and the second direction intersect. The orthogonal projections of the signal line and the electrostatic discharge lead on the substrate have an overlapping region, and the orthogonal projection of the first diode on the substrate overlaps with the overlapping region. The first positive electrode and the signal line are connected in the overlapping area through a via, and the first negative electrode and the electrostatic discharge lead are connected in the overlapping area through a via.

[0016] In one possible implementation, in the probe substrate provided in the embodiments of this disclosure, the overlapping region completely covers the orthographic projection of the first semiconductor layer on the substrate.

[0017] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the orthogonal projection of the second diode on the substrate does not overlap with the orthogonal projection of the signal line on the substrate, and the orthogonal projection of the second diode on the substrate is located between the orthogonal projection of the electrostatic discharge lead on the substrate and the detection area.

[0018] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the first connection portion is connected to the side of the electrostatic discharge lead near the detection area, the orthographic projection of the first connection portion on the substrate does not overlap with the orthographic projection of the signal line on the substrate, and the orthographic projection of the first connection portion on the substrate at least partially overlaps with the orthographic projection of the second positive electrode on the substrate, and the first connection portion and the second positive electrode are connected through a via.

[0019] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the orthogonal projection of the second connection portion on the substrate completely covers the orthogonal projection of the second semiconductor layer on the substrate, and the second connection portion is connected to the second negative electrode through a via. The orthographic projection of the second connection portion on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate, and the second connection portion and the signal line are connected through a via.

[0020] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the second diode is located between the first diode and the detection area, and the orthogonal projection of the second diode on the substrate overlaps with the orthogonal projection of the signal line on the substrate.

[0021] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the first connection portion is connected to the side of the electrostatic discharge lead near the second diode, the orthographic projection of the first connection portion on the substrate overlaps with the orthographic projection of the signal line on the substrate, and the orthographic projection of the first connection portion on the substrate at least partially overlaps with the orthographic projection of the second positive electrode on the substrate, and the first connection portion and the second positive electrode are connected through a via.

[0022] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the second connection portion is located between the first connection portion and the detection area, the orthogonal projection of the second connection portion on the substrate completely covers the orthogonal projection of the second semiconductor layer on the substrate, one end of the second connection portion near the first connection portion is connected to the second negative electrode through a via, and one end of the second connection portion near the detection area is connected to the signal line through a via.

[0023] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the peripheral region further includes a driving circuit located on the side of the electrostatic discharge lead away from the detection region, the driving circuit having a low-voltage power supply terminal, and the electrostatic discharge lead being electrically connected to the low-voltage power supply terminal.

[0024] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, at least one end of the signal line is connected to the first diode, the second diode, and the electrostatic discharge lead.

[0025] In one possible implementation, in the detection substrate provided in the embodiments of this disclosure, the signal line is a scan line, and the detection area further includes a plurality of read lines that are insulated from and intersected with the signal line, the scan line and the read line defining the plurality of detection pixel units; The detection pixel unit further includes a thin-film transistor electrically connected to the photodiode. The thin-film transistor is located between the substrate and the photodiode. The gate of the thin-film transistor is electrically connected to the signal line. The first electrode of the thin-film transistor is electrically connected to the bottom electrode. The second electrode of the thin-film transistor is electrically connected to the readout line.

[0026] Accordingly, this disclosure also provides a flat panel detector, including the detection substrate described in any of the above embodiments of this disclosure. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a planar structure of a detector substrate provided in an embodiment of the present disclosure; Figure 2 for Figure 1 A magnified schematic diagram of the structure within the dashed box EE; Figure 3 for Figure 2 Layout of the membrane structure within the dashed box FF; Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure along the CC' direction; Figure 5 for Figure 1A cross-sectional view of a single pixel unit; Figure 6 for Figure 3 Schematic diagram of the structure of the signal line; Figure 7 for Figure 3 Schematic diagrams of the structure of the first and second positive electrodes; Figure 8 for Figure 3 Schematic diagram of the structure of the first connecting part and the second connecting part; Figure 9 For preparation Figure 3 A schematic diagram of a cross-sectional structure of the probe substrate shown; Figure 10 For preparation Figure 3 A schematic diagram of another cross-sectional structure of the probe substrate shown; Figure 11 For preparation Figure 3 A schematic diagram of another cross-sectional structure of the probe substrate shown; Figure 12 For preparation Figure 3 A schematic diagram of another cross-sectional structure of the probe substrate shown; Figure 13 A schematic diagram of another planar structure of the probe substrate provided in an embodiment of this disclosure; Figure 14 for Figure 13 A magnified schematic diagram of the structure within the dashed box MM; Figure 15 for Figure 14 The corresponding membrane structure layout; Figure 16 A schematic diagram of another planar structure of the probe substrate provided in an embodiment of this disclosure; Figure 17 for Figure 16 A schematic diagram of the enlarged structure within the dashed box NN; Figure 18 for Figure 17 The corresponding membrane structure layout; Figure 19 This is yet another film structure layout corresponding to the first diode, second diode, signal line, and electrostatic discharge lead in the peripheral region of the probe substrate provided in this embodiment of the disclosure; Figure 20 This is yet another film structure layout corresponding to the first diode, second diode, signal line, and electrostatic discharge lead in the peripheral region of the probe substrate provided in this embodiment of the disclosure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "comprising" or "including," and similar terms as used in this disclosure, mean that an element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0030] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0031] The backplane technology of large-area TFT-based photodetectors originates from the traditional LCD display field. In the peripheral ESD discharge circuit (usually on the gate side), TFTs with source-gate shorted are used to form equivalent diodes and are shorted back to back to form a bidirectional discharge channel structure (one diode will be turned on in both positive and negative voltage electrostatic discharge), and led out to the electrostatic discharge lead (Shorting Ring) for global discharge to protect the driving TFT of the detection area.

[0032] In practical applications, the source-gate short-circuit equivalent diode structure has limited ability to withstand ESD voltage and current. Firstly, TFT devices with gate oxide structures are inherently sensitive to high-voltage electrostatic breakdown; once the gate oxide breaks down, it becomes a resistive structure with a certain resistance, forming a continuous leakage path. Secondly, due to limited design space, the aspect ratio of the TFT used for ESD discharge cannot be very high, resulting in a limited open-channel cross-sectional area and a lower ability to withstand large currents. Therefore, it is prone to overcurrent short circuits during current (or power) type ESD discharge, also becoming a continuous low-resistance leakage path. The inventors of this case discovered that in FPXD products based on X-ray detection, ESD gradient lines frequently appear on the gate side. Microscopic observation confirmed that the TFT in the ESD discharge circuit exhibited gate oxide breakdown or overcurrent ablation. If the breakdown or ablation was not severe, the image returned to normal by laser cutting and isolating the partially failed ESD discharge circuit. Mechanistically, this is explained by the reduction in the gate's remote load-carrying capacity caused by the ESD leakage path. However, in actual mass production, this localized, finely cut and isolated repair method cannot meet the needs of mass production in terms of either cost or efficiency.

[0033] To achieve superior electrostatic discharge performance, possess stronger resistance to ESD breakdown and ablation, and significantly reduce the probability of subsequent laser cutting and repair, this disclosure provides a detection substrate, such as... Figures 1-4 As shown, Figure 1 This is a schematic diagram of a planar structure for a probe substrate. Figure 2 for Figure 1 A magnified schematic diagram of the structure within the dashed box EE. Figure 3 for Figure 2 Layout of the membrane structure within the dashed box FF. Figure 4 for Figure 3 A cross-sectional view along the CC' direction is shown. The detector substrate includes a detector region AA and a peripheral region BB surrounding the detector region AA. The detector region AA includes multiple detector pixel units P arranged in an array. The detector substrate includes: Substrate 1; Multiple photodiodes 100 are located on one side of the substrate 1 and are respectively located within the detection pixel unit P; such as Figure 5 As shown, Figure 5 for Figure 1 A cross-sectional view of a pixel unit P is shown in the figure. The photodiode 100 includes a bottom electrode 101, a photoelectric conversion layer 102 and a top electrode 103, which are sequentially stacked along the direction away from the substrate 1. Signal line 2 is located between substrate 1 and photodiode 100, and is located in the detection area AA and extends to the peripheral area BB; The electrostatic discharge lead 3 is located on the side of the photodiode 100 away from the substrate 1, and is located in the peripheral region BB; The first diode 4 is connected between the signal line 2 and the electrostatic discharge lead 3 and is located in the peripheral area BB. The first diode 4 includes: a first positive electrode 41 disposed in the same layer and material as the bottom electrode 101, a first semiconductor layer 42 disposed in the same layer and material as the photoelectric conversion layer 102, and a first negative electrode 43 disposed in the same layer and material as the top electrode 103. The second diode 5 is connected between the signal line 2 and the electrostatic discharge lead 3 and is located in the peripheral area BB. The second diode 5 includes: a second positive electrode 51 disposed in the same layer and material as the bottom electrode 101, a second semiconductor layer 52 disposed in the same layer and material as the photoelectric conversion layer 102, and a second negative electrode 53 disposed in the same layer and material as the top electrode 103. The first connecting part 6 and the second connecting part 7 are both disposed in the same layer and with the same material as the electrostatic discharge lead 3; wherein, the first positive electrode 41 is electrically connected to the signal line 2, the first negative electrode 43 and the second positive electrode 51 are electrically connected at least through the first connecting part 6, the first positive electrode 41 and the second negative electrode 53 are electrically connected at least through the second connecting part 7, and the first connecting part 6 is electrically connected to the electrostatic discharge lead 3.

[0034] The detection substrate provided in this embodiment uses two diodes fabricated using the same process as the photodiode in the detection area to construct the ESD discharge circuit around the detection substrate. This eliminates the need for a separate fabrication process for the peripheral ESD discharge circuit, reducing costs. Furthermore, the electrostatic discharge lead can be connected to a low-voltage power supply terminal, and the signal line is also connected to a low-voltage power supply terminal most of the time. When the static charge on the signal line is positive, the positive charge pulls the potential on the signal line higher, thus turning on the second diode and turning off the first diode, releasing the static charge to the electrostatic discharge lead via the second diode. When the static charge on the signal line is negative, the negative charge pulls the potential on the signal line lower, thus turning on the first diode. The second diode is turned off, and static electricity is released to the static discharge lead via the first diode. This disclosure uses two diodes instead of the traditional ESD discharge circuit constructed using a source-gate short-circuited transistor. First, the forward conductivity of a diode is superior to that of a source-gate short-circuited TFT; it can be turned on instantaneously in a forward-biased state, and the cross-sectional area for current flow is much larger than that of the thin-layer channel of a TFT, while the carrier transport path length is much shorter. Second, the reverse cutoff characteristics of a diode are superior to those of a source-gate short-circuited TFT, and the leakage current is lower. Finally, since diodes do not have the thin gate oxide layer structure of TFTs, there is no ESD gate oxide breakdown problem, and their resistance to high-current ablation is far superior to that of TFT structures. Therefore, the ESD discharge circuit constructed using diodes in this disclosure achieves a superior static discharge effect and possesses stronger resistance to ESD breakdown and ablation, significantly reducing the probability of subsequent laser cutting repairs. The detection substrate provided in this embodiment can be applied to high-performance, large-area photoelectric detection fields, such as X-ray medical imaging.

[0035] It should be noted that the above descriptions of the same layer and same material setting, taking the first positive electrode 41 which is set in the same layer and same material as the bottom electrode 101 as an example, means that the bottom electrode 101 and the first positive electrode 41 are made in one process, such as depositing a metal layer, etching the metal layer to form the bottom electrode 101 located in the detection area AA and the first positive electrode 41 located in the surrounding area BB. That is, the above descriptions of the same layer and same material setting refer to the same layer in a physical sense or to the preparation using the same mask process.

[0036] In some embodiments, such as Figure 5 As shown, the photoelectric conversion layer 102 is used to convert optical signals into electrical signals. The photoelectric conversion layer 102 can be a PN structure or a PIN structure; this disclosure uses a PIN structure as an example. Specifically, the PIN structure includes a P-type doped P-type semiconductor layer, an undoped intrinsic semiconductor layer I, and an N-type doped N-type semiconductor layer. The thickness of the intrinsic semiconductor layer I can be greater than the thickness of the P-type semiconductor layer and the N-type semiconductor layer.

[0037] For example, the first diode 4 and the second diode 5 can be turned on instantaneously in the forward bias state, and the cross-sectional area of ​​the current flowing through them is much larger than that of the TFT thin-layer channel. Moreover, the carrier transport path length does not exceed 1.5μm (the maximum overall thickness of the PIN device), which is much shorter than the TFT channel length L (generally not less than 3μm). Secondly, the reverse cutoff characteristics of the first diode 4 and the second diode 5 are also better than those of the source-gate short-circuited TFT. Taking a PIN photodiode with a pixel size of 140μm as an example (the PIN fill rate is generally around 60%), its leakage current is about 5~8fA when the reverse bias voltage difference is 7V. After the area is reduced accordingly, the leakage current will be further reduced. On the other hand, the leakage current of the source-gate short-circuited TFT is difficult to achieve within 10fA when the source-drain voltage Vds=7V.

[0038] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 1 As shown, signal line 2 can be a scan line, and the detection area AA also includes multiple read lines DL that are insulated from and intersected with signal line 2. Signal line 2 and read lines DL define multiple detection pixel units P. The detection pixel unit P includes a thin-film transistor T electrically connected to a photodiode 100. The thin-film transistor T is located between the substrate 1 and the photodiode 100. The gate G of the thin-film transistor T is electrically connected to a signal line 2, which is used to control the opening and closing of the thin-film transistor T. The first electrode (e.g., the source S) of the thin-film transistor T is electrically connected to the bottom electrode 101, and the second electrode (e.g., the drain D) of the thin-film transistor T is electrically connected to a readout line DL, which is used to read the photogenerated carriers generated in the detection pixel unit P.

[0039] It should be noted that, Figure 1 The diagram only shows a portion of the photodiode 100 and thin-film transistor T within the detection pixel unit P.

[0040] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 1 and Figure 5As shown, it also includes a bias voltage line BL and a light-shielding layer LS disposed on the same layer and material as the electrostatic discharge lead 3. The orthogonal projection of the light-shielding layer LS on the substrate 1 covers the orthogonal projection of the thin-film transistor T on the substrate 1. The bias voltage line BL is electrically connected to the top electrode 103 of the photodiode 100 and provides a negative bias voltage, so that the photodiode 100 operates in a reverse bias state in which photoelectric conversion can occur. The thin-film transistor T plays the role of controlling the switching of the entire pixel. Specifically, the bias voltage line BL is used to apply a bias voltage to the top electrode 103. The photoelectric conversion layer 102 converts the light signal into an electrical signal. The bottom electrode 101 is used to conduct the electrical signal formed by the photoelectric conversion layer 102 after illumination. There is a facing area between the bottom electrode 101 and the top electrode 103, and a storage capacitor is formed between them. When the thin-film transistor T is turned on, the charge carriers generated by the photoelectric effect accumulated in the photodiode 100 in the detection pixel unit P are detected and read through the readout IC (ROIC) connected to the readout line DL; when the thin-film transistor T is turned off, the photodiode 100 is illuminated and continues to undergo photoelectric conversion, and accumulates photogenerated charge carriers through the storage capacitor, waiting to be released through the readout line DL when the thin-film transistor T is turned on.

[0041] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 1 As shown, the peripheral area BB also includes a drive circuit (e.g., Gate IC, not shown) located on the side of the electrostatic discharge lead 3 away from the detection area AA. The drive circuit has a low-voltage power supply terminal (VGL), and the electrostatic discharge lead 3 is electrically connected to the low-voltage power supply terminal (VGL) to realize the electrostatic discharge on the signal line 2.

[0042] In some embodiments, the thin-film transistor T can be either an N-type transistor or a P-type transistor; the N-type transistor turns on at a high potential and turns off at a low potential; the P-type transistor turns on at a low potential and turns off at a high potential.

[0043] In some embodiments, the driving circuit can drive multiple scan lines to scan line by line. Taking an N-type thin-film transistor as an example, within one frame, the potential on each scan line is high for only a small portion of the time, while it is low for the vast majority of the time. That is, the scan line is connected to a low-voltage power supply terminal for most of the time. When static electricity is not considered, the potential on the electrostatic discharge lead is in equilibrium with the potential on the scan line. When the static electricity on the scan line is positive, the positive charge pulls the potential on the scan line high, so the second diode conducts and the first diode is turned off, and the static electricity is released to the electrostatic discharge lead through the second diode. When the static electricity on the signal line is negative, the negative charge pulls the potential on the signal line even lower, so the first diode conducts and the second diode is turned off, and the static electricity is released to the electrostatic discharge lead through the first diode.

[0044] For example, the substrate can be a flexible substrate, such as a plastic substrate with excellent heat resistance and durability made of polyvinyl ether phthalate, polyethylene naphthalate, polycarbonate, polyaryl compounds, polyetherimide, polyethersulfone or polyimide; or it can be a rigid substrate, such as a glass substrate, without limitation.

[0045] In some embodiments, the materials of the signal line 2, the first positive electrode 41, the second positive electrode 51 and the electrostatic discharge lead 4 may include molybdenum, aluminum, silver, copper, titanium, platinum, tungsten, tantalum, tantalum nitride, their alloys and combinations thereof or other suitable metallic materials, and the materials of the first negative electrode 43 and the second negative electrode 53 may be indium tin oxide (ITO) or indium zinc oxide (IZO) or other suitable transparent materials.

[0046] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 1 As shown, signal line 2 extends along the first direction X, and electrostatic discharge lead 3 extends along the second direction Y, with the first direction X and the second direction Y intersecting. like Figure 2 and Figure 3 As shown, the orthographic projection of the first diode 4 on the substrate 1 and the orthographic projection of the second diode 5 on the substrate 1 are located on the same side of the orthographic projection of the signal line 2 on the substrate 1, and are located between the orthographic projection of the electrostatic discharge lead 3 on the substrate 1 and the detection area AA; the orthographic projection of the first diode 4 on the substrate 1 is located between the orthographic projection of the signal line 2 on the substrate 1 and the orthographic projection of the second diode 5 on the substrate 1. In this embodiment, the first diode 4 and the second diode 5 are arranged longitudinally in the second direction Y, and the conduction and turn-off characteristics of the diodes can be controlled by adjusting the area of ​​the semiconductor layer.

[0047] In some embodiments, Figure 3 The first diode 4 and the second diode 5 can also be arranged laterally in the first direction X.

[0048] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 4 and Figure 5As shown, it also includes: a gate insulating layer 8 located between signal line 2 and the first positive electrode 41; a first passivation layer 9 located between gate insulating layer 8 and the first positive electrode 41; a buffer layer BF located between the first diode 4, the second diode 5, and the electrostatic discharge lead 3; a planarization layer 10 located between buffer layer BF and the electrostatic discharge lead 3; and a second passivation layer 11 located between planarization layer 10 and the electrostatic discharge lead 3. The gate G of the thin-film transistor T is electrically connected to the scan line on the same layer, the source S and drain D are located between gate insulating layer 8 and the first passivation layer 9, and the active layer Act is located between gate insulating layer 8 and the source S and drain D. The bias voltage line BL is electrically connected to the top electrode 103 of photodiode 100 through a via penetrating planarization layer 10 and second passivation layer 11.

[0049] For example, the materials of the gate insulating layer 8, the first passivation layer 9, the buffer layer and the second passivation layer 11 can be one or any combination of silicon oxide, silicon nitride, and silicon oxynitride, without limitation.

[0050] For example, the material of the planarization layer 10 can be an organic insulating material such as polyacrylic resin, polyepoxyacrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, phenolic epoxy acrylic resin, etc., and is not limited herein.

[0051] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 3 , Figure 4 and Figure 6 As shown, Figure 6 for Figure 3 The schematic diagram of the structure of the signal line 2 also includes a first adapter 21 integrally connected to the signal line 2. The first adapter 21 and the first diode 4 are located on the same side of the plane where the signal line 2 is located. like Figure 3 and Figure 7 As shown, Figure 7 for Figure 3 The schematic diagram of the structure of the first positive electrode 41 and the second positive electrode 51 is shown. The first positive electrode 41 includes: a first main body portion 411 extending along the first direction X, and a second adapter portion 412 electrically connected to one end of the first main body portion 411 facing the detection area AA. like Figure 3 , Figure 4 , Figure 6 and Figure 7 As shown, the orthographic projection of the second adapter 412 on the substrate 1 at least partially overlaps with the orthographic projection of the first adapter 21 on the substrate 1. The second adapter 412 and the first adapter 21 are connected through a via. Specifically, the second adapter 412 and the first adapter 21 are connected through a first via V1 that penetrates the gate insulating layer 8 and the first passivation layer 9.

[0052] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 3 and Figure 7 As shown, the second positive electrode 51 includes: a second main body portion 511 extending along the first direction X, and a third adapter portion 512 electrically connected to the side of the second main body portion 511 facing the first main body portion 411; the third adapter portion 512 is close to the detection area AA; like Figure 3 and Figure 8 As shown, Figure 8 for Figure 3 The diagram shows the structure of the first connecting part 6 and the second connecting part 7. The first connecting part 6 includes a third main body 61 extending along the first direction X, and a fourth adapter 62 electrically connected to the side of the third main body 61 facing the second diode 5. The fourth adapter 62 is close to the detection area AA. The orthogonal projection of the third main body 61 on the substrate 1 completely covers the orthogonal projection of the first semiconductor layer 42 on the substrate 1. This ensures that the first semiconductor layer 42 is not affected by light, so that the first diode 4 has unidirectional conduction characteristics. The orthogonal projection of the first semiconductor layer 42 on the substrate 1 roughly overlaps with the orthogonal projection of the first negative electrode 43 on the substrate 1. like Figure 3 , Figure 4 , Figure 7 and Figure 8 As shown, the third main body 61 is integrally formed with the electrostatic discharge lead 3 at one end. The third main body 61 is connected to the first negative electrode 43 through a via. Specifically, the third main body 61 and the first negative electrode 43 are connected through a second via V2 penetrating the second passivation layer 11 and a third via V3 penetrating the planarization layer 10. The orthogonal projections of the second via V2 and the third via V3 on the substrate 1 overlap with each other. The orthogonal projection of the fourth transition part 62 on the substrate 1 at least partially overlaps with the orthogonal projection of the third transition part 512 on the substrate 1. The fourth transition part 62 and the third transition part 512 are connected through a via. Specifically, the fourth transition part 62 and the third transition part 512 are connected through a fourth via V4 penetrating the second passivation layer 11 and a fifth via V5 penetrating the planarization layer 10. The orthogonal projections of the fourth via V4 and the fifth via V5 on the substrate 1 overlap with each other.

[0053] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 3 and Figure 7 As shown, the first positive electrode 41 further includes a fifth adapter 413 electrically connected to the side of the first main body 411 facing the second diode 5; the fifth adapter 413 is close to the electrostatic discharge lead 3; like Figure 3 and Figure 8As shown, the second connection portion 7 includes: a fourth main body portion 71 extending along the first direction X, and a sixth adapter portion 72 electrically connected to the side of the fourth main body portion 71 facing the signal line 2; the sixth adapter portion 72 is close to the electrostatic discharge lead 3, and the orthographic projection of the fourth main body portion 71 on the substrate 1 completely covers the orthographic projection of the second semiconductor layer 52 on the substrate 1; this ensures that the second semiconductor layer 52 is not affected by light, so that the second diode 5 has unidirectional conduction characteristics; the orthographic projection of the second semiconductor layer 52 on the substrate 1 and the orthographic projection of the second negative electrode 53 on the substrate 1 substantially overlap; like Figure 3 , Figure 4 , Figure 7 and Figure 8 As shown, the fourth main body 71 is connected to the second negative electrode 53 through vias. Specifically, the fourth main body 71 and the second negative electrode 53 are connected through a sixth via V6 penetrating the second passivation layer 11 and a seventh via V7 penetrating the planarization layer 10. The orthogonal projections of the sixth via V6 and the seventh via V7 on the substrate 1 overlap with each other. The orthogonal projection of the sixth transition part 72 on the substrate 1 and the orthogonal projection of the fifth transition part 413 on the substrate 1 at least partially overlap. The sixth transition part 72 and the fifth transition part 413 are connected through vias. Specifically, the sixth transition part 72 and the fifth transition part 413 are connected through an eighth via V8 penetrating the second passivation layer 11 and a ninth via V9 penetrating the planarization layer 10. The orthogonal projections of the eighth via V8 and the ninth via V9 on the substrate 1 overlap with each other.

[0054] It should be noted that, Figure 4 The buffer layer is not shown in the figure. The buffer layer has vias corresponding to the second via V2, the fourth via V4, the sixth via V6 and the eighth via V8, respectively.

[0055] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 1 As shown, the left end of signal line 2 is connected to the first diode 4, the second diode 5 and the electrostatic discharge lead 3. Alternatively, the right end of signal line 2 can be connected to the first diode 4, the second diode 5 and the electrostatic discharge lead 3. Or, both the left and right ends of signal line 2 can be connected to the first diode 4, the second diode 5 and the electrostatic discharge lead 3. In this way, the electrostatic discharge leads 3 on both sides can be a ring structure with an integrated structure.

[0056] The following is about Figure 3 The fabrication process of the probe substrate shown is described below: (1) such as Figure 9 As shown, a gate metal layer is deposited and patterned on the substrate 1. A signal line 2 and a first transition portion 21 with an integral structure are formed in the detection region AA. The signal line 2 extends to the peripheral region BB. Figure 9 Only a portion of the outer perimeter region BB is shown. Then, a gate insulating layer 8 and a first passivation layer 9 are deposited sequentially on the side of the signal line 2 away from the substrate 1. The gate insulating layer 8 and the first passivation layer 9 are etched to form a first via V1. The orthographic projection of the first via V1 on the substrate 1 overlaps with the orthographic projection of the first adapter 21 on the substrate 1.

[0057] (2) such as Figure 10 As shown, a source / drain metal layer is deposited and patterned on the side of the first passivation layer 9 away from the substrate 1. The required pattern is formed in the detection area AA, and a first positive electrode 41 and a second positive electrode 51 are formed in the peripheral area BB. The first positive electrode 41 is electrically connected to the first adapter 21 through the first via V1.

[0058] (3) such as Figure 11 As shown, a semiconductor layer and a transparent conductive layer are sequentially deposited on the side of the source / drain metal layer away from the substrate 1. The transparent conductive layer is etched to form the required pattern in the detection region AA, and a first negative electrode 43 and a second negative electrode 53 are formed in the peripheral region BB. Then, using the first negative electrode 43 and the second negative electrode 53 as a mask, the semiconductor layer is etched to form the required pattern in the detection region AA, and a first semiconductor layer 42 and a second semiconductor layer 52 are formed in the peripheral region BB. That is, a first diode 4 and a second diode 5 are formed in the peripheral region BB.

[0059] (4) such as Figure 12 As shown, a buffer layer (not shown) covering the first diode 4 and the second diode 5, and a planarization layer 10 are deposited sequentially. The planarization layer 10 is etched to form the desired pattern in the detection region AA, and a third via V3, a fifth via V5, a seventh via V7, and a ninth via V9 penetrating the planarization layer 10 are formed in the peripheral region BB. Then, a second passivation layer 11 is deposited, and the second passivation layer 11 and the buffer layer are etched simultaneously to form the desired pattern in the detection region AA, and a second via V2 and a fourth via V9 penetrating the second passivation layer 11 are formed in the peripheral region BB. 4. The sixth via V6 and the eighth via V8, and vias (not shown) that form a through buffer layer in the peripheral region BB and correspond to the second via V2, the fourth via V4, the sixth via V6 and the eighth via V8 respectively. The orthographic projections of the second via V2 and the third via V3 on the substrate 1 overlap with each other, the orthographic projections of the fourth via V4 and the fifth via V5 on the substrate 1 overlap with each other, the orthographic projections of the sixth via V6 and the seventh via V7 on the substrate 1 overlap with each other, and the orthographic projections of the eighth via V8 and the ninth via V9 on the substrate 1 overlap with each other.

[0060] (5) such as Figure 3As shown, a top metal layer is deposited on the side of the second passivation layer 11 away from the substrate 1. The top metal layer is etched to form an integral electrostatic discharge lead 3, a first connection portion 6, and a second connection portion 7. The first connection portion 6 is electrically connected to the first negative electrode 43 through the second via V2 and the third via V3. The first connection portion 6 is electrically connected to the second positive electrode 51 through the fourth via V4 and the fifth via V5. The second connection portion 7 is electrically connected to the second negative electrode 53 through the sixth via V6 and the seventh via V7. The second connection portion 7 is electrically connected to the first positive electrode 41 through the eighth via V8 and the ninth via V9, thereby achieving a short circuit between the first diode 4 and the second diode 5.

[0061] In some embodiments, in the detection substrate provided in the present disclosure, such as Figures 13-15 As shown, Figure 13 This is a schematic diagram of yet another planar structure of the detector substrate provided in an embodiment of this disclosure. Figure 14 for Figure 13 Enlarged structural diagram within the dashed box MM. Figure 15 for Figure 14 The corresponding membrane structure layout, Figures 13-15 and Figures 1-3 The principle of static electricity release is the same, the difference lies in the positions of the first diode 4 and the second diode 5. Figures 13-15 The orthographic projections of the first diode 4 and the second diode 5 on the substrate 1 are located on the same side of the orthographic projection of the signal line 2 on the substrate 1. The orthographic projection of the first diode 4 on the substrate 1 is located between the orthographic projection of the electrostatic discharge lead 3 on the substrate 1 and the detection area AA. The orthographic projection of the second diode 5 on the substrate 1 is located on the side of the orthographic projection of the electrostatic discharge lead 3 on the substrate 1 that is farther away from the detection area AA. In this embodiment, the first diode 4 and the second diode 5 are arranged on the left and right sides of the electrostatic discharge lead 3, which is more efficient than... Figures 1-3 This arrangement can reduce the space occupied on one side of the electrostatic discharge lead 3 (especially the side close to the detection area AA), and is more suitable for situations where the electrostatic discharge lead 3 needs to be designed to be relatively close to the detection area AA.

[0062] It should be noted that, Figure 15 Cross-sectional views of the first diode 4, the second diode 5, the signal line 2, and the electrostatic discharge lead 3 can be found in [reference needed]. Figure 4 .

[0063] In some embodiments, in the detection substrate provided in the present disclosure, due to Figures 13-15 The positions of the first diode 4 and the second diode 5 are... Figures 1-3 The differences mean that the corresponding membrane structure will also change, such as... Figure 15As shown, it also includes a seventh adapter 27 and an eighth adapter 28 integrally connected to the signal line 2. The orthographic projection of the seventh adapter 27 on the substrate 1 is located on the side of the orthographic projection of the first diode 4 on the substrate 1 that is close to the detection area AA. The orthographic projection of the eighth adapter 28 on the substrate 1 is located on the side of the orthographic projection of the second diode 5 on the substrate 1 that is far away from the electrostatic discharge lead 3. The orthographic projection of the first positive electrode 41 on the substrate 1 and the orthographic projection of the seventh transition portion 27 on the substrate 1 at least partially overlap. The first positive electrode 41 and the seventh transition portion 27 are connected through a via. Specifically, the first positive electrode 41 and the seventh transition portion 27 are connected through a tenth via V10 that penetrates the gate insulating layer 8 and the first passivation layer 9. The orthogonal projection of the second connecting portion 7 on the substrate 1 completely covers the orthogonal projection of the second semiconductor layer 52 on the substrate 1. The second connecting portion 7 and the second negative electrode 53 are connected through vias. Specifically, the second connecting portion 7 and the second negative electrode 53 are connected through the eleventh via V11 penetrating the second passivation layer 11 and the twelfth via V12 penetrating the planarization layer 10. The orthogonal projections of the eleventh via V11 and the twelfth via V12 on the substrate 1 overlap each other. The orthographic projection of the second connecting portion 7 on the substrate 1 at least partially overlaps with the orthographic projection of the eighth transition portion 28 on the substrate 1. The second connecting portion 7 and the eighth transition portion 28 are connected by vias. Specifically, the second connecting portion 7 and the eighth transition portion 28 are connected by a thirteenth via V13 that penetrates the second passivation layer 11, the first passivation layer 9 and the gate insulating layer 8 and a fourteenth via V14 that penetrates the planarization layer 10. The orthographic projections of the thirteenth via V13 and the fourteenth via V14 on the substrate 1 overlap with each other.

[0064] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 15 As shown, the first connection part 6 includes: a first sub-connection part 63 connected to the side of the electrostatic discharge lead 3 near the detection area AA, and a second sub-connection part 64 connected to the side of the electrostatic discharge lead 3 away from the detection area AA. The orthographic projection of the first sub-connection portion 63 on the substrate 1 completely covers the orthographic projection of the first semiconductor layer 42 on the substrate 1. The first sub-connection portion 63 is connected to the first negative electrode 41 through a via. Specifically, the first sub-connection portion 63 and the first negative electrode 41 are connected through the fifteenth via V15 penetrating the second passivation layer 11 and the sixteenth via V16 penetrating the planarization layer 10. The orthographic projections of the fifteenth via V15 and the sixteenth via V16 on the substrate 1 overlap with each other. The orthographic projection of the second sub-connection portion 64 on the substrate 1 at least partially overlaps with the orthographic projection of the second positive electrode 51 on the substrate 1. The second sub-connection portion 64 and the second positive electrode 51 are connected through vias. Specifically, the second sub-connection portion 64 and the second positive electrode 51 are connected through the seventeenth via V17 penetrating the second passivation layer 11 and the eighteenth via V18 penetrating the planarization layer 10. The orthographic projections of the seventeenth via V17 and the eighteenth via V18 on the substrate 1 overlap with each other.

[0065] It should be noted that, Figure 15 The buffer layer is not shown in the figure. The buffer layer has vias corresponding to the eleventh via V11, the thirteenth via V13, the fifteenth via V15 and the seventeenth via V17, respectively.

[0066] In some embodiments, in the detection substrate provided in the present disclosure, such as Figures 16-18 As shown, Figure 16 This is a schematic diagram of yet another planar structure of the detector substrate provided in an embodiment of this disclosure. Figure 17 for Figure 16 A magnified schematic diagram of the structure within the dashed box NN. Figure 18 for Figure 17 The corresponding membrane structure layout, Figures 16-18 and Figures 1-3 The principle of static electricity release is the same, the difference lies in the positions of the first diode 4 and the second diode 5. Figures 16-18 The orthographic projections of the first diode 4 and the second diode 5 on the substrate 1 are located on either side of the orthographic projection of the signal line 2 on the substrate 1, and between the orthographic projection of the electrostatic discharge lead 3 on the substrate 1 and the detection area AA. In this embodiment, the first diode 4 and the second diode 5 are arranged on the upper and lower sides of the signal line 2, compared to... Figures 13-15 This arrangement further reduces the space occupied by the electrostatic discharge lead 3 on the side away from the detection area AA (the side closer to the cut edge), which is more suitable for products with extremely narrow bezel designs such as breast detection.

[0067] It should be noted that, Figure 18 Cross-sectional views of the first diode 4, the second diode 5, the signal line 2, and the electrostatic discharge lead 3 can be found in [reference needed]. Figure 4 .

[0068] In some embodiments, in the detection substrate provided in the present disclosure, due to Figures 16-18 The positions of the first diode 4 and the second diode 5 are... Figures 1-3 The differences mean that the corresponding membrane structure will also change, such as... Figure 18As shown, it also includes a ninth adapter 29 and a tenth adapter 210 integrally connected to the signal line 2. The orthographic projection of the ninth adapter 29 on the substrate 1 is located on the side of the orthographic projection of the first diode 4 on the substrate 1 that is close to the detection area AA. The orthographic projection of the tenth adapter 210 on the substrate 1 is located on the side of the orthographic projection of the second diode 5 on the substrate 1 that is close to the detection area AA. The orthographic projection of the first positive electrode 41 on the substrate 1 and the orthographic projection of the ninth transition portion 29 on the substrate 1 at least partially overlap. The first positive electrode 41 and the ninth transition portion 29 are connected through a via. Specifically, the first positive electrode 41 and the ninth transition portion 29 are connected through the nineteenth via V19 that penetrates the gate insulating layer 8 and the first passivation layer 9. The orthogonal projection of the second connecting portion 7 on the substrate 1 completely covers the orthogonal projection of the second semiconductor layer 52 on the substrate 1. The second connecting portion 7 and the second negative electrode 53 are connected through vias. Specifically, the second connecting portion 7 and the second negative electrode 53 are connected through the twentieth via V20 penetrating the second passivation layer 11 and the twentieth via V21 penetrating the planarization layer 10. The orthogonal projections of the twentieth via V20 and the twentieth via V21 on the substrate 1 overlap each other. The orthographic projection of the second connecting portion 7 on the substrate 1 at least partially overlaps with the orthographic projection of the tenth transition portion 210 on the substrate 1. The second connecting portion 7 and the tenth transition portion 210 are connected by vias. Specifically, the second connecting portion 7 and the tenth transition portion 210 are connected by a twenty-second via V22 that penetrates the second passivation layer 11, the first passivation layer 9 and the gate insulating layer 8 and a twenty-third via V23 that penetrates the planarization layer 10. The orthographic projections of the twenty-second via V22 and the twenty-third via V23 on the substrate 1 overlap with each other.

[0069] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 18 As shown, the first connection part 6 includes a third sub-connection part 65 and a fourth sub-connection part 66 that are connected to the side of the electrostatic discharge lead 3 near the detection area AA; The orthogonal projection of the third sub-connection portion 65 on the substrate 1 completely covers the orthogonal projection of the first semiconductor layer 42 on the substrate 1. The third sub-connection portion 65 is connected to the first negative electrode 41 through a via. Specifically, the third sub-connection portion 65 is connected to the first negative electrode 41 through a twenty-fourth via V24 penetrating the second passivation layer 11 and a twenty-fifth via V24 penetrating the planarization layer 10. The orthogonal projections of the twenty-fourth via V24 and the twenty-fifth via V24 on the substrate 1 overlap with each other. The orthographic projection of the fourth sub-connection portion 66 on the substrate 1 at least partially overlaps with the orthographic projection of the second positive electrode 51 on the substrate 1. The fourth sub-connection portion 66 and the second positive electrode 51 are connected through vias. Specifically, the fourth sub-connection portion 66 and the second positive electrode 51 are connected through a twenty-sixth via V26 penetrating the second passivation layer 11 and a twenty-seventh via V27 penetrating the planarization layer 10. The orthographic projections of the twenty-sixth via V26 and the twenty-seventh via V27 on the substrate 1 overlap with each other.

[0070] It should be noted that, Figure 18 The buffer layer is not shown in the figure. The buffer layer has vias corresponding to the 20th via V20, the 22nd via V22, the 24th via V24, and the 26th via V26, respectively.

[0071] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 19 As shown, Figure 19 This is yet another film structure layout corresponding to the first diode 4, the second diode 5, the signal line 2, and the electrostatic discharge lead 3 in the peripheral region of the detector substrate provided in this embodiment of the disclosure. Figure 19 and Figures 1-3 The principle of static electricity release is the same, the difference lies in the position of the first diode 4 and the second diode 5. Figure 19 As shown, the orthogonal projections of signal line 2 and electrostatic discharge lead 3 on substrate 1 have an overlapping region DD. The orthogonal projection of the first diode 4 on substrate 1 overlaps with the overlapping region DD. The first positive electrode 41 is connected to signal line 2 in the overlapping region DD via a via. Specifically, the first positive electrode 41 is connected to signal line 2 in the overlapping region DD via a twenty-eighth via V28 penetrating the gate insulating layer 8 and the first passivation layer 9. The first negative electrode 43 is connected to electrostatic discharge lead 3 in the overlapping region DD via a via. Specifically, the first negative electrode 43 is connected to electrostatic discharge lead 3 in the overlapping region DD via a twenty-ninth via V29 penetrating the second passivation layer 11 and a thirtieth via V30 penetrating the planarization layer 10. The orthogonal projections of the twenty-ninth via V29 and the thirtieth via V30 on substrate 1 overlap. In this embodiment, the first diode 4 is arranged at the intersection of signal line 2 and electrostatic discharge lead 3.

[0072] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 19 As shown, the overlapping region DD completely covers the orthographic projection of the first semiconductor layer 42 on the substrate 1, that is, the orthographic projection of the electrostatic discharge lead 3 on the substrate 1 completely covers the orthographic projection of the first semiconductor layer 42 on the substrate 1, ensuring that the first semiconductor layer 42 is not affected by light, so that the first diode 4 has unidirectional conduction characteristics.

[0073] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 19 As shown, the orthographic projection of the second diode 5 on the substrate 1 does not overlap with the orthographic projection of the signal line 2 on the substrate 1, and the orthographic projection of the second diode 5 on the substrate 1 is located between the orthographic projection of the electrostatic discharge lead 3 on the substrate 1 and the detection area AA. In this embodiment, the second diode 5 is arranged on the right side of the electrostatic discharge lead 3. Compared with the previous three schemes, this scheme makes full use of the overlapping area between the electrostatic discharge lead 3 and the signal line 2 to arrange the first diode 4, which is equivalent to saving the area of ​​one of the two diodes, achieving further optimization of space occupancy, and also allowing the area and size of the diode to be more flexibly adjusted according to specific electrical requirements.

[0074] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 19 As shown, the first connection part 6 is connected to the side of the electrostatic discharge lead 3 near the detection area AA. The orthographic projection of the first connection part 6 on the substrate A does not overlap with the orthographic projection of the signal line 2 on the substrate A, and the orthographic projection of the first connection part 6 on the substrate A overlaps at least partially with the orthographic projection of the second positive electrode 51 on the substrate A. The first connection part 6 and the second positive electrode 51 are connected through vias. Specifically, the first connection part 6 and the second positive electrode 51 are connected through the thirty-first via V31 penetrating the second passivation layer 11 and the thirty-second via V32 penetrating the planarization layer 10. The orthographic projections of the thirty-first via V31 and the thirty-second via V32 on the substrate 1 overlap with each other.

[0075] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 19 As shown, the orthogonal projection of the second connection portion 7 on the substrate 1 completely covers the orthogonal projection of the second semiconductor layer 52 on the substrate 1. The second connection portion 7 is connected to the second negative electrode 53 through vias. Specifically, the second connection portion 7 and the second negative electrode 53 are connected through the thirty-third via V33 penetrating the second passivation layer 11 and the thirty-fourth via V34 penetrating the planarization layer 10. The orthogonal projections of the thirty-third via V33 and the thirty-fourth via V34 on the substrate 1 overlap each other. The orthographic projection of the second connection portion 7 on the substrate 1 at least partially overlaps with the orthographic projection of the signal line 2 on the substrate 1. The second connection portion 7 and the signal line 2 are connected through vias. Specifically, the second connection portion 7 and the signal line 2 are connected through the thirty-fifth via V35 that penetrates the second passivation layer 11, the first passivation layer 9 and the gate insulating layer 8 and the thirty-sixth via V36 that penetrates the planarization layer 10. The orthographic projections of the thirty-third via V35 and the thirty-sixth via V36 on the substrate 1 overlap with each other.

[0076] Specifically, Figure 19 The corresponding equivalent circuit diagram can be compared with Figure 17 same.

[0077] It should be noted that, Figure 19 The buffer layer is not shown in the figure. The buffer layer has vias corresponding to the twenty-ninth via V29, the thirty-first via V31, the thirty-third via V33, and the thirty-fifth via V35, respectively.

[0078] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 20 As shown, Figure 20 This is yet another film structure layout corresponding to the first diode 4, the second diode 5, the signal line 2, and the electrostatic discharge lead 3 in the peripheral region of the detector substrate provided in this embodiment of the disclosure. Figure 20 and Figure 19 The principle of static electricity release is the same, the difference lies in the position of the second diode 5. Figure 20 As shown, the second diode 5 is located between the first diode 4 and the detection area AA. The orthographic projection of the second diode 5 on the substrate 1 overlaps with the orthographic projection of the signal line 2 on the substrate 1. In this embodiment, the second diode 5 is arranged on the signal line 2. Compared with the previous four schemes, this scheme occupies the least amount of extra space beyond conventional wiring. This scheme is a design that maximizes the space utilization of the ESD discharge circuit, making full use of the wiring areas of the electrostatic discharge lead 3 and the signal line 2 to arrange the two diodes, thus possessing all the advantages of the above four implementation schemes.

[0079] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 20 As shown, the first connection part 6 is connected to the side of the electrostatic discharge lead 3 near the second diode 5. The orthographic projection of the first connection part 6 on the substrate 1 overlaps with the orthographic projection of the signal line 2 on the substrate 1. The orthographic projection of the first connection part 6 on the substrate 1 overlaps at least partially with the orthographic projection of the second positive electrode 51 on the substrate 1. The first connection part 6 and the second positive electrode 51 are connected through vias. Specifically, the first connection part 6 and the second positive electrode 51 are connected through the thirty-seventh via V37 penetrating the second passivation layer 11 and the thirty-eighth via V38 penetrating the planarization layer 10. The orthographic projections of the thirty-seventh via V37 and the thirty-eighth via V38 on the substrate 1 overlap with each other.

[0080] In some embodiments, in the detection substrate provided in the present disclosure, such as Figure 20As shown, the second connection portion 7 is located between the first connection portion 6 and the detection area AA. The orthogonal projection of the second connection portion 7 on the substrate 1 completely covers the orthogonal projection of the second semiconductor layer 52 on the substrate 1. The end of the second connection portion 7 near the first connection portion 6 is connected to the second negative electrode 53 through a via. Specifically, the end of the second connection portion 7 near the first connection portion 6 is connected to the second negative electrode 53 through the thirty-ninth via V39 penetrating the second passivation layer 11 and the fortieth via V40 penetrating the planarization layer 10. The orthogonal projections of the thirty-ninth via V39 and the fortieth via V40 on the substrate 1 overlap with each other. The end of the second connection portion 7 near the detection area AA is connected to the signal line 2 through a via. Specifically, the end of the second connection portion 7 near the detection area AA is connected to the signal line 2 through the forty-first via V41 penetrating the second passivation layer 11 and the forty-second via V42 penetrating the planarization layer 10. The orthogonal projections of the forty-first via V41 and the forty-second via V42 on the substrate 1 overlap with each other.

[0081] Specifically, Figure 20 The corresponding equivalent circuit diagram can be compared with Figure 17 same.

[0082] It should be noted that, Figure 20 The buffer layer is not shown in the figure. The buffer layer has vias corresponding to the 29th via V29, the 37th via V37, the 39th via V39, and the 41st via V41, respectively.

[0083] Based on the same inventive concept, this disclosure also provides a flat panel detector, including the detection substrate described above. Since the principle by which this flat panel detector solves the problem is similar to that of the aforementioned detection substrate, the implementation of this flat panel detector can refer to the implementation of the aforementioned detection substrate, and repeated details will not be elaborated further.

[0084] In some embodiments, the above-mentioned flat panel detector may be an X-ray flat panel detector.

[0085] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0086] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A detection substrate, wherein, It includes a detection area and a peripheral area surrounding the detection area, wherein the detection area includes multiple detection pixel units arranged in an array; The detection substrate includes: Substrate; Multiple photodiodes are located on one side of the substrate and are respectively located within the detection pixel unit; each photodiode includes a bottom electrode, a photoelectric conversion layer, and a top electrode stacked sequentially along a direction away from the substrate. Multiple signal lines are located between the substrate and the photodiode, and are located in the detection area and extend to the peripheral area; An electrostatic discharge lead is located on the side of the photodiode away from the substrate and in the peripheral region; A first diode is connected between the signal line and the electrostatic discharge lead and is located in the peripheral region; the first diode includes: a first positive electrode disposed in the same layer and material as the bottom electrode, a first semiconductor layer disposed in the same layer and material as the photoelectric conversion layer, and a first negative electrode disposed in the same layer and material as the top electrode; The second diode is connected between the signal line and the electrostatic discharge lead and is located in the peripheral region; the second diode includes: a second positive electrode disposed in the same layer and material as the bottom electrode, a second semiconductor layer disposed in the same layer and material as the photoelectric conversion layer, and a second negative electrode disposed in the same layer and material as the top electrode; The first connecting part and the second connecting part are both disposed in the same layer and of the same material as the electrostatic discharge lead; wherein, the first positive electrode is electrically connected to the signal line, the first negative electrode and the second positive electrode are electrically connected at least through the first connecting part, the first positive electrode and the second negative electrode are electrically connected at least through the second connecting part, and the first connecting part is electrically connected to the electrostatic discharge lead.

2. The detection substrate as described in claim 1, wherein, The signal line extends along a first direction, and the electrostatic discharge lead extends along a second direction, with the first and second directions intersecting. The orthographic projection of the first diode on the substrate and the orthographic projection of the second diode on the substrate are located on the same side of the orthographic projection of the signal line on the substrate, and are located between the orthographic projection of the electrostatic discharge lead on the substrate and the detection area; The orthogonal projection of the first diode on the substrate lies between the orthogonal projection of the signal line on the substrate and the orthogonal projection of the second diode on the substrate.

3. The detection substrate as described in claim 2, wherein, It also includes a first adapter portion integrally connected to the signal line, wherein the first adapter portion and the orthographic projection of the first diode on the plane where the signal line is located are located on the same side of the signal line; The first positive electrode includes: a first main body extending along the first direction, and a second adapter electrically connected to one end of the first main body facing the detection area; The orthographic projection of the second adapter on the substrate at least partially overlaps with the orthographic projection of the first adapter on the substrate, and the second adapter and the first adapter are connected by a via.

4. The detector substrate as described in claim 3, wherein, The second positive electrode includes: a second main body extending along the first direction, and a third adapter electrically connected to the side of the second main body facing the first main body; the third adapter is located near the detection area; The first connection portion includes: a third main body portion extending along the first direction, and a fourth adapter portion electrically connected to the side of the third main body portion facing the second diode; the fourth adapter portion is close to the detection area, and the orthographic projection of the third main body portion on the substrate completely covers the orthographic projection of the first semiconductor layer on the substrate; The third main body is integrally formed with the electrostatic discharge lead at one end. The third main body is connected to the first negative electrode through a via. The orthographic projection of the fourth adapter on the substrate overlaps at least partially with the orthographic projection of the third adapter on the substrate. The fourth adapter is connected to the third adapter through a via.

5. The detector substrate as described in claim 4, wherein, The first positive electrode further includes a fifth adapter portion electrically connected to the side of the first main body portion facing the second diode; the fifth adapter portion is located near the electrostatic discharge lead; The second connection portion includes: a fourth main body portion extending along the first direction, and a sixth adapter portion electrically connected to the side of the fourth main body portion facing the signal line; the sixth adapter portion is close to the electrostatic discharge lead, and the orthographic projection of the fourth main body portion on the substrate completely covers the orthographic projection of the second semiconductor layer on the substrate; The fourth main body is connected to the second negative electrode through a via, and the orthographic projection of the sixth adapter on the substrate at least partially overlaps with the orthographic projection of the fifth adapter on the substrate. The sixth adapter and the fifth adapter are connected through a via.

6. The detection substrate as claimed in claim 1, wherein, The signal line extends along a first direction, and the electrostatic discharge lead extends along a second direction, with the first and second directions intersecting. The orthographic projections of the first diode and the second diode on the substrate are located on the same side of the orthographic projection of the signal line on the substrate. The orthographic projection of the first diode on the substrate is located between the orthographic projection of the electrostatic discharge lead on the substrate and the detection area. The orthographic projection of the second diode on the substrate is located on the side of the orthographic projection of the electrostatic discharge lead on the substrate away from the detection area.

7. The detector substrate as claimed in claim 6, wherein, It also includes a seventh adapter and an eighth adapter integrally connected to the signal line. The orthographic projection of the seventh adapter on the substrate is located on the side of the orthographic projection of the first diode on the substrate that is closer to the detection area. The orthographic projection of the eighth adapter on the substrate is located on the side of the orthographic projection of the second diode on the substrate that is farther away from the electrostatic discharge lead. The orthographic projection of the first positive electrode on the substrate at least partially overlaps with the orthographic projection of the seventh adapter on the substrate, and the first positive electrode and the seventh adapter are connected through a via. The orthogonal projection of the second connection portion on the substrate completely covers the orthogonal projection of the second semiconductor layer on the substrate, and the second connection portion is connected to the second negative electrode through a via. The orthographic projection of the second connecting portion on the substrate at least partially overlaps with the orthographic projection of the eighth adapter portion on the substrate, and the second connecting portion and the eighth adapter portion are connected by a via.

8. The detector substrate as claimed in claim 7, wherein, The first connection portion includes: a first sub-connection portion connected to the side of the electrostatic discharge lead near the detection area, and a second sub-connection portion connected to the side of the electrostatic discharge lead away from the detection area; The orthogonal projection of the first sub-connection portion on the substrate completely covers the orthogonal projection of the first semiconductor layer on the substrate, and the first sub-connection portion is connected to the first negative electrode through a via. The orthographic projection of the second sub-connection portion on the substrate at least partially overlaps with the orthographic projection of the second positive electrode on the substrate, and the second sub-connection portion and the second positive electrode are connected through a via.

9. The detector substrate as claimed in claim 1, wherein, The signal line extends along a first direction, and the electrostatic discharge lead extends along a second direction, with the first and second directions intersecting. The orthographic projections of the first diode and the second diode on the substrate are located on both sides of the orthographic projection of the signal line on the substrate, and are located between the orthographic projection of the electrostatic discharge lead on the substrate and the detection area.

10. The detector substrate as claimed in claim 9, wherein, It also includes a ninth adapter and a tenth adapter integrally connected to the signal line. The orthographic projection of the ninth adapter on the substrate is located on the side of the orthographic projection of the first diode on the substrate that is closer to the detection area. The orthographic projection of the tenth adapter on the substrate is located on the side of the orthographic projection of the second diode on the substrate that is closer to the detection area. The orthographic projection of the first positive electrode on the substrate at least partially overlaps with the orthographic projection of the ninth adapter on the substrate, and the first positive electrode and the ninth adapter are connected through a via. The orthogonal projection of the second connection portion on the substrate completely covers the orthogonal projection of the second semiconductor layer on the substrate, and the second connection portion is connected to the second negative electrode through a via. The orthographic projection of the second connecting portion on the substrate at least partially overlaps with the orthographic projection of the tenth adapter portion on the substrate, and the second connecting portion and the tenth adapter portion are connected by a via.

11. The detector substrate as claimed in claim 10, wherein, The first connection portion includes a third sub-connection portion and a fourth sub-connection portion connected to the side of the electrostatic discharge lead near the detection area; The orthogonal projection of the third sub-connection on the substrate completely covers the orthogonal projection of the first semiconductor layer on the substrate, and the third sub-connection is connected to the first negative electrode through a via. The orthographic projection of the fourth sub-connection on the substrate at least partially overlaps with the orthographic projection of the second positive electrode on the substrate, and the fourth sub-connection is connected to the second positive electrode through a via.

12. The detection substrate as claimed in claim 1, wherein, The signal line extends along a first direction, and the electrostatic discharge lead extends along a second direction, with the first and second directions intersecting. The orthogonal projections of the signal line and the electrostatic discharge lead on the substrate have an overlapping region, and the orthogonal projection of the first diode on the substrate overlaps with the overlapping region. The first positive electrode and the signal line are connected in the overlapping area through a via, and the first negative electrode and the electrostatic discharge lead are connected in the overlapping area through a via.

13. The detector substrate as claimed in claim 12, wherein, The overlapping area completely covers the orthogonal projection of the first semiconductor layer onto the substrate.

14. The detector substrate as claimed in claim 13, wherein, The orthographic projection of the second diode on the substrate does not overlap with the orthographic projection of the signal line on the substrate, and the orthographic projection of the second diode on the substrate is located between the orthographic projection of the electrostatic discharge lead on the substrate and the detection area.

15. The detector substrate as claimed in claim 14, wherein, The first connection portion is connected to the side of the electrostatic discharge lead near the detection area. The orthographic projection of the first connection portion on the substrate does not overlap with the orthographic projection of the signal line on the substrate. The orthographic projection of the first connection portion on the substrate at least partially overlaps with the orthographic projection of the second positive electrode on the substrate. The first connection portion and the second positive electrode are connected through a via.

16. The detector substrate as claimed in claim 15, wherein, The orthogonal projection of the second connection portion on the substrate completely covers the orthogonal projection of the second semiconductor layer on the substrate, and the second connection portion is connected to the second negative electrode through a via. The orthographic projection of the second connection portion on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate, and the second connection portion and the signal line are connected through a via.

17. The detector substrate as claimed in claim 13, wherein, The second diode is located between the first diode and the detection area, and the orthogonal projection of the second diode on the substrate overlaps with the orthogonal projection of the signal line on the substrate.

18. The detector substrate as claimed in claim 17, wherein, The first connection portion is connected to the side of the electrostatic discharge lead near the second diode. The orthographic projection of the first connection portion on the substrate overlaps with the orthographic projection of the signal line on the substrate. The orthographic projection of the first connection portion on the substrate at least partially overlaps with the orthographic projection of the second positive electrode on the substrate. The first connection portion and the second positive electrode are connected through a via.

19. The detector substrate as claimed in claim 18, wherein, The second connection portion is located between the first connection portion and the detection area. The orthogonal projection of the second connection portion on the substrate completely covers the orthogonal projection of the second semiconductor layer on the substrate. One end of the second connection portion near the first connection portion is connected to the second negative electrode through a via, and the other end of the second connection portion near the detection area is connected to the signal line through a via.

20. The detector substrate according to any one of claims 1-19, wherein, The peripheral area also includes a driving circuit located on the side of the electrostatic discharge lead away from the detection area. The driving circuit has a low-voltage power supply terminal, and the electrostatic discharge lead is electrically connected to the low-voltage power supply terminal.

21. The detector substrate according to any one of claims 1-19, wherein, At least one end of the signal line is connected to the first diode, the second diode, and the electrostatic discharge lead.

22. The detector substrate according to any one of claims 1-19, wherein, The signal line is a scan line, and the detection area also includes multiple read lines that are insulated from and intersect with the signal line. The scan line and the read lines define the multiple detection pixel units. The detection pixel unit further includes a thin-film transistor electrically connected to the photodiode. The thin-film transistor is located between the substrate and the photodiode. The gate of the thin-film transistor is electrically connected to the signal line. The first electrode of the thin-film transistor is electrically connected to the bottom electrode. The second electrode of the thin-film transistor is electrically connected to the readout line.

23. A flat panel detector, wherein, Includes the probe substrate as described in any one of claims 1-22.

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