A method for improving the dark slide by adjusting the lp tunneling thickness matching phosphor expansion

Abstract

The application discloses a method for improving dark film by adjusting LP tunneling thickness and matching phosphorus diffusion, and relates to the technical field of solar cell manufacturing. The method comprises the following steps: S1, preparing a tunneling oxide layer on the back surface of a silicon wafer: a tunneling oxide layer is prepared on the surface of a single crystal silicon wafer by a LP device through a thermal oxidation method, so that the thickness of the tunneling layer is accurately controlled to be 0.8-1.0 nm; S2, phosphorus diffusion: phosphorus diffusion is performed on the tunneling oxide layer, and phosphorus oxychloride is used as a diffusion source during diffusion, the flow rate of a carrier gas during diffusion is 20-25 slm, the diffusion temperature is 850-870 DEG C, and the diffusion time is 30-40 min; the formed emitter sheet resistance after diffusion is 50-60; S3, annealing: after the phosphorus diffusion is completed, annealing is performed in a nitrogen environment to repair the interface defects of the tunneling oxide layer and the emitter. The method can achieve the following effects: the performance of the battery can be improved while the proportion of dark film is reduced; the improvement effect of the dark film is very excellent, the dark-state minority carrier lifetime of the battery is improved, the conversion efficiency of the battery is improved, and the process stability is enhanced.

Description

Technical Field

[0001] This invention relates to the field of crystalline silicon solar cell manufacturing technology, and in particular to a method for adjusting the LP tunneling thickness to match phosphorus diffusion and improve dark spots. Background Technology

[0002] In the manufacturing process of high-efficiency crystalline silicon solar cells such as TopCon, phosphorus diffusion is used to form the emitter, while the tunneling oxide layer (referring to the tunneling oxide layer - SiO2 grown using LPCVD equipment) serves as a passivation layer, which can effectively reduce the recombination rate on the silicon wafer surface and improve the open-circuit voltage and short-circuit current of the cell.

[0003] However, in traditional processes, the thickness of the tunneling oxide layer is typically set to 1.1-1.3 nm, and the phosphorus diffusion sheet resistance is controlled at 40-60 nm. The diffusion temperature is 870-890℃, and the time is 20-25 min. When these parameters are matched and set, the following problems are likely to occur when depositing a tunnel oxide layer using traditional processes: 1. Severe dark film defects; 2. High interface recombination rate; 3. Poor process stability.

[0004] Therefore, this solution studies the causes of the above problems (severe dark film defects, high interface recombination rate, and poor process stability) and improves the entire process so that the final battery can not only improve the dark film problem, but also avoid the degradation of other performance. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an improved method for preparing PL bright and dark patches induced by LPCVD winding plating of N-type TOPCon cells. It aims to overcome the defects in the prior art, such as severe dark patches, high interface recombination rate and poor process stability caused by the mismatch between LP tunneling layer and phosphorus diffusion process, and to provide a dark patch improvement method with precise parameter matching and significant effect.

[0006] Therefore, based on the above findings, this solution addresses the aforementioned issues through the following methods.

[0007] This invention provides a method for adjusting LP tunneling thickness to match phosphor diffusion and improve film quality, comprising: A method for adjusting LP tunneling thickness to match phosphor diffusion and improve film quality includes the following steps: S1. Preparation of a tunneling oxide layer on the back side of a silicon wafer: A tunneling oxide layer is prepared on the surface of a single-crystal silicon wafer using a thermal oxidation method with an LP device, so that the thickness of the tunneling layer is precisely controlled within 0.8-1.0 nm. S2. Phosphorus Diffusion: Phosphorus diffusion is performed on the tunneling oxide layer using phosphorus oxychloride as the diffusion source. The carrier gas flow rate is 20-25 slm, the diffusion temperature is 850-870℃, and the diffusion time is 30-40 min. The emitter sheet resistance formed after diffusion is 50-60. ; S3. Annealing: After phosphorus diffusion is complete, annealing is performed in a nitrogen atmosphere to repair defects at the tunnel oxide layer and emitter interface.

[0008] Furthermore, in S1, during the preparation of the tunneling oxide layer: the oxygen flow rate is 10-15 slm, the temperature is controlled at 550-700℃, and the oxidation time is 5-8 min.

[0009] Furthermore, in S3, during annealing: the annealing temperature is 750-780℃, and the annealing time is 10-15min.

[0010] Furthermore, in S1, the thickness of the tunneling oxide layer is 0.8 nm; in S2, when phosphorus oxychloride is used as the diffusion source, the diffusion temperature is 850 °C and the diffusion time is 40 min; the emitter sheet resistance formed after diffusion is 60 Ω. In step S3, the annealing temperature is 750℃ and the annealing time is 15min.

[0011] Further, in S1, the thickness of the tunneling oxide layer is 0.9 nm; in S2, when phosphorus oxychloride is used as the diffusion source, the diffusion temperature is 860℃ and the diffusion time is 35 min; the emitter sheet resistance formed after diffusion is 55. In step S3, the annealing temperature is 760℃ and the annealing time is 12min.

[0012] Furthermore, in S1, the thickness of the tunneling oxide layer is 1.0 nm; in S2, when phosphorus oxychloride is used as the diffusion source, the diffusion temperature is 870℃ and the diffusion time is 30 min; the emitter sheet resistance formed after diffusion is 50 Ω. In step S3, the annealing temperature is 780℃ and the annealing time is 10min.

[0013] The above-described technical solution of the present invention has the following beneficial effects: (1) This solution not only significantly improves the dark plate, but also improves the dark state minority carrier lifetime and the battery conversion efficiency. Traditional methods of improving the dark area still result in a dark area ratio of 15.2% (which is not a sufficient improvement; this solution achieves 2% or less). Furthermore, traditional methods of improving the dark area also reduce the battery's dark-state minority carrier lifetime and corresponding battery conversion efficiency. In this scheme, the LP tunneling layer thickness is 0.8-1.0 nm, and the emitter sheet resistance after phosphorus diffusion is 50-60 nm. Compared to traditional methods, this solution offers the following advantages: a. Significant improvement in dark film defects: Through precise matching of LP thickness and phosphorus diffusion process, the interfacial carrier recombination rate is reduced by 60%-70%, the dark film area ratio is reduced from about 15% in traditional process to less than 2%, and the appearance yield is improved to more than 98%. b. Significantly improved battery performance: b1. Dark state minority carrier lifetime increased from the traditional 120-150μs to 160-180μs; ​​b2. Battery open-circuit voltage increased by 15-20mV, short-circuit current increased by 0.1-0.2A, and conversion efficiency increased by 0.35-0.48 percentage points. (2) Enhanced process stability; This scheme achieves a tunnel oxide layer thickness of 0.8-1.0 nm and an emitter sheet resistance of 50-60 nm after phosphorus diffusion. At the same time, the parameters for the deposition of the tunneling oxide layer, the parameters for phosphorus diffusion, and the parameters for annealing were also designed. Through these parameter designs, the thickness fluctuation of the LP tunneling layer during fabrication is kept to ±0.1 nm, and the phosphorus expansion resistance fluctuation is kept to ±5 nm. At the same time, the change in the proportion of dark film does not exceed 0.5%, the production line yield fluctuation is controlled within 1%, and the process stability is significantly improved. Detailed Implementation

[0014] The specific embodiments of the present invention will be described in detail below to facilitate a further understanding of the invention.

[0015] It should be noted that there are currently two main ways to improve the dark film in the industry: the first is to adjust the sheet resistance of phosphorus diffusion alone; the second is to adjust the thickness of the tunneling layer alone. However, there are still some problems: (1) the improvement of the dark film by these two methods is limited; (2) these two methods only adjust one parameter and do not change other parameters in the entire preparation process. Although they improve the dark film problem to a certain extent, the effect is limited and it is easy to cause other performance degradation problems.

[0016] It should be noted that the inventor discovered the following phenomenon: (1) The situation of severe dark spot defects is: when the LP tunneling layer is too thick (≥1.2nm), the carrier tunneling resistance increases. During the phosphorus diffusion process, a large number of carriers are easily accumulated at the interface between the emitter and the tunneling layer, which leads to a sharp increase in non-radiative recombination in the dark state. Large-area dark spots (dark spots) appear on the silicon wafer surface, accounting for up to 12%-18%, which seriously affects the appearance and yield of the battery. (2) The situation with high interface recombination rate is: if the LP tunneling layer is too thin (≤0.7nm), phosphorus impurities can easily penetrate the tunneling layer during phosphorus diffusion, contaminating the intrinsic interface of the silicon wafer, resulting in an increase in interface state density, a decrease in minority carrier lifetime, and a reduction in battery conversion efficiency of 0.4-0.6 percentage points. (3) The situation with poor process stability is: under traditional parameter matching, the fluctuation of the tunneling layer thickness and phosphor diffusion sheet resistance has a high sensitivity to the influence of the film, and the production line yield can fluctuate by 5%-7%, increasing the manufacturing cost.

[0017] Therefore, based on the observed phenomena, the inventors improved the traditional process (the process parameters for phosphorus diffusion to form a tunneling oxide layer in high-efficiency crystalline silicon solar cells such as TopCon using LPCVD equipment). This improved the dark spot problem during tunneling oxide layer formation without causing other performance degradation.

[0018] The following specific embodiments illustrate this scheme (unless otherwise specified, all experimental methods used in the following embodiments are conventional methods; all materials and reagents used in the following embodiments can be obtained commercially unless otherwise specified).

[0019] Example 1 A method for adjusting LP tunneling thickness to match phosphor diffusion and improve film quality includes the following steps: S1. Preparation of tunneling oxide layer: A tunneling oxide layer is prepared on the back side of an n-type single crystal silicon wafer using a thermal oxidation method with LP equipment, so that the thickness of the tunneling layer is precisely controlled at 0.8nm; It should be noted that during preparation, as long as the final tunneling layer thickness is precisely controlled at 0.8 nm, the oxidation temperature, oxygen flow rate, and oxidation time can be within a suitable range. Specifically, the oxidation temperature is controlled at 550-700℃ (550℃ is selected in this example), the oxygen flow rate is 10-15 slm (10 slm is selected in this example), and the oxidation time is 5-8 min (5 min is selected in this example). S2. Phosphorus Diffusion: Phosphorus diffusion was performed on the tunneling oxide layer using phosphorus oxychloride as the diffusion source. The carrier gas flow rate was 20-25 slm, the diffusion temperature was 850℃, and the diffusion time was 40 min. The emitter sheet resistance formed after diffusion was 60. ; It should be noted that the important parameters in S2 are diffusion temperature, diffusion time, and emitter sheet resistance; while the carrier gas flow rate during diffusion only needs to be in the range of 20-25 slm (for example, 25 slm is selected in this embodiment). S3. Annealing: After phosphorus diffusion is complete, annealing is performed in a nitrogen atmosphere at a temperature of 750℃ for 15 minutes to repair defects at the tunnel oxide layer and emitter interface. It should be noted that both annealing time and annealing temperature are very important.

[0020] Example 2 A method for adjusting LP tunneling thickness to match phosphor diffusion and improve film quality includes the following steps: S1. Preparation of tunneling oxide layer: A tunneling oxide layer is prepared on the back side of an n-type single crystal silicon wafer using a thermal oxidation method with LP equipment, so that the thickness of the tunneling layer is precisely controlled at 0.9nm; It should be noted that during preparation, as long as the final tunneling layer thickness is precisely controlled at 0.9 nm, the corresponding oxidation temperature, oxygen flow rate, and oxidation time can be within a suitable range. Specifically, the oxidation temperature is controlled at 550-700℃ (600℃ in this example), the oxygen flow rate is 10-15 slm (13 slm in this example), and the oxidation time is 5-8 min (6 min in this example). S2. Phosphorus Diffusion: Phosphorus diffusion was performed on the tunneling oxide layer using phosphorus oxychloride as the diffusion source. The carrier gas flow rate was 20-25 slm, the diffusion temperature was 860℃, and the diffusion time was 35 min. The emitter sheet resistance formed after diffusion was 55. ; It should be noted that the important parameters in S2 are diffusion temperature, diffusion time, and emitter sheet resistance; while the carrier gas flow rate during diffusion only needs to be in the range of 20-25 slm (for example, 23 slm is selected in this embodiment). S3. Annealing: After phosphorus diffusion is complete, annealing is performed in a nitrogen atmosphere at a temperature of 760℃ for 12 minutes to repair defects at the interface between the tunneling oxide layer and the emitter. It should be noted that both annealing time and annealing temperature are very important.

[0021] Example 3 A method for adjusting LP tunneling thickness to match phosphor diffusion and improve film quality includes the following steps: S1. Preparation of tunneling oxide layer: A tunneling oxide layer is prepared on the back side of an n-type single crystal silicon wafer using a thermal oxidation method with LP equipment, so that the thickness of the tunneling layer is precisely controlled at 1.0 nm. It should be noted that during preparation, as long as the final tunneling layer thickness is precisely controlled to 1.0 nm, the corresponding oxidation temperature, oxygen flow rate, and oxidation time can be within a suitable range. Specifically, the oxidation temperature is controlled at 550-700℃ (700℃ is selected in this example), the oxygen flow rate is 10-15 slm (15 slm is selected in this example), and the oxidation time is 5-8 min (8 min is selected in this example). S2. Phosphorus Diffusion: Phosphorus diffusion was performed on the tunneling oxide layer using phosphorus oxychloride as the diffusion source. The carrier gas flow rate was 20-25 slm, the diffusion temperature was 870℃, and the diffusion time was 30 min. The emitter sheet resistance formed after diffusion was 50. ; It should be noted that the important parameters in S2 are diffusion temperature, diffusion time, and emitter sheet resistance; while the carrier gas flow rate during diffusion only needs to be in the range of 20-25 slm (for example, 20 slm is selected in this embodiment). S3. Annealing: After phosphorus diffusion is complete, annealing is performed in a nitrogen atmosphere at a temperature of 780℃ for 10 minutes to repair defects at the tunnel oxide layer and emitter interface. It should be noted that both annealing time and annealing temperature are very important.

[0022] control group A method for adjusting the LP tunneling thickness to match phosphor diffusion and improve the dark film was prepared using the method described in Example 3; Unlike Example 3, the thickness of the tunneling oxide layer deposited in S1 was 1.2 nm by changing the corresponding preparation parameters; the diffusion temperature in S2 was controlled at 880 °C and the diffusion time at 25 min; and finally, the emitter sheet resistance was set to 40 Ω. In S3, the annealing temperature is 760℃ and the annealing time is 12 minutes.

[0023] It should be noted that in this control group, the thickness of the tunneling oxide layer is the thickness of the prior art, the diffusion temperature and diffusion time in S2 are also conventional data of the prior art, and the desizing time and annealing temperature in S3 are also conventional data of the prior art.

[0024] Experimental comparison The samples were prepared using the methods described in Examples 1-3 above, and also using methods found in the prior art (the control group). The parameters of each example and the control group are shown in Table 1. Table 1 Comparison of Experimental Groups and Parameter Settings After preparing the batteries using the methods described in Examples 1, 2, 3, and the control group, the preparation parameters for the front and back sides of the other batteries remained unchanged. The prepared batteries were subjected to performance testing, and the results are shown in Table 2.

[0025] Table 2 Performance Test Results As can be seen from Table 2: (1) The dark film produced by this scheme has been improved: The proportion of negative film in the control group was 15.2%, while that in Examples 1, 2, and 3 of this solution was 1.8%, 1.5%, and 2.0%, respectively; indicating that the negative film of this solution is sufficiently improved. This indicates that if the thickness of the tunneling oxide layer is controlled within 0.8-1.0 nm, the phosphorus diffusion sheet resistance can be set to 40-60 nm. The combination of the two can effectively suppress interfacial carrier recombination and reduce the generation of dark spots; (2) The dark state minority carrier lifetime of this scheme has been improved, and the conversion efficiency has also been improved; The dark state minority carrier lifetime of the control group was 132 μs, while the dark state minority carrier lifetimes of Examples 1, 2, and 3 of this scheme were 178 μs, 182 μs, and 175 μs, respectively. It can be seen that the dark state minority carrier lifetime of this scheme is improved by 33%-38% compared with the control group.

[0026] The battery conversion efficiency of the control group was 26.55%, while the battery conversion efficiencies of Examples 1, 2, and 3 of this solution were 27.1%, 27.15%, and 26.99%, respectively. It can be seen that the battery conversion efficiency of this solution improved by 0.3 percentage points (which is already a good result); especially in Example 2 (LP thickness 0.9nm, phosphorus sheet resistance 55...). The battery conversion efficiency is higher, and under this parameter combination, the passivation effect of the tunneling layer and the carrier collection ability of the phosphorus diffuse emitter are optimally balanced.

[0027] In summary, it can be seen that this scheme reduces the thickness of the tunneling oxide layer to 0.8-1.0 nm while maintaining a sheet resistance of 50-60 nm after phosphorus diffusion. This not only improves the dark spot, but also extends the lifetime of dark minority carriers, thereby improving the conversion efficiency of the battery.

[0028] Furthermore, the scheme achieves a LP tunneling layer thickness of 0.8-1.0 nm and an emitter sheet resistance of 50-60 nm after phosphorus diffusion. Furthermore, parameters for depositing the LP tunneling layer, phosphorus diffusion, and annealing were designed. Through these parameter designs, the thickness fluctuation of the LP tunneling layer was minimized to ±0.1 nm, and the phosphorus diffusion resistance fluctuation was minimized to ±5 nm. At the same time, the change in the proportion of dark film does not exceed 0.5%, the production line yield fluctuation is controlled within 1%, and the process stability is significantly improved.

[0029] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various different choices and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is defined by the claims and their equivalents.

Claims

1. A method for adjusting the LP tunneling thickness to match phosphor diffusion and improve the image, characterized in that, Includes the following steps: S1. Preparation of a tunneling oxide layer on the back side of a silicon wafer: A tunneling oxide layer is prepared on the surface of a single-crystal silicon wafer using a thermal oxidation method with an LP device, such that the thickness of the tunneling oxide layer is controlled at 0.8-1.0 nm. S2. Phosphorus Diffusion: Phosphorus diffusion is performed on the tunneling oxide layer, using phosphorus oxychloride as the diffusion source; the emitter sheet resistance formed after diffusion is 50-60. ; S3. Annealing: After phosphorus diffusion is complete, annealing is performed in a nitrogen atmosphere.

2. The method for adjusting LP tunneling thickness to match phosphor diffusion and improve the image according to claim 1, characterized in that, In S1, during the preparation of the tunneling oxide layer: the oxygen flow rate is 10-15 slm, the temperature is controlled at 550-700℃, and the oxidation time is 5-8 min.

3. The method for adjusting LP tunneling thickness to match phosphor diffusion and improve the image according to claim 2, characterized in that, In S2, when phosphorus oxychloride is used as the diffusion source for phosphorus diffusion: the carrier gas flow rate is 20-25 slm, the diffusion temperature is 850-870℃, and the diffusion time is 30-40 min.

4. The method for adjusting LP tunneling thickness to match phosphor diffusion and improve the image according to claim 3, characterized in that, In S3, during annealing: the annealing temperature is 750-780℃, and the annealing time is 10-15min.

5. The method for adjusting LP tunneling thickness to match phosphor diffusion and improve the image according to claim 4, characterized in that, In S1, the thickness of the tunneling oxide layer is 0.8 nm; In S2, when phosphorus oxychloride is used as the diffusion source, the diffusion temperature is 850℃ and the diffusion time is 40 min; the emitter sheet resistance formed after diffusion is 60. ; In step S3, the annealing temperature is 750℃ and the annealing time is 15min.

6. The method for adjusting LP tunneling thickness to match phosphor diffusion and improve the image according to claim 4, characterized in that, In S1, the thickness of the tunneling oxide layer is 0.9 nm; In S2, when phosphorus oxychloride is used as the diffusion source, the diffusion temperature is 860℃ and the diffusion time is 35 min; the emitter sheet resistance formed after diffusion is 55. ; In step S3, the annealing temperature is 760℃ and the annealing time is 12min.

7. The method for adjusting LP tunneling thickness to match phosphor diffusion and improve the image according to claim 4, characterized in that, In S1, the thickness of the tunneling oxide layer is 1.0 nm; In S2, when phosphorus oxychloride is used as the diffusion source, the diffusion temperature is 870℃ and the diffusion time is 30 min; the emitter sheet resistance formed after diffusion is 50. ; In step S3, the annealing temperature is 780℃ and the annealing time is 10min.

Images