Back contact solar cell, method of manufacturing the same, and photovoltaic module

Abstract

The present disclosure provides a back contact solar cell, a preparation method thereof and a photovoltaic module. The back contact solar cell comprises a silicon substrate (1) having at least two cell unit regions and a cutting region (14) on the back surface, each cell unit region comprising a spacing region (13) and first and second conductive regions (11, 12) with opposite polarities, adjacent first and second conductive regions (11, 12) being separated by the spacing region (13), and the cutting region (14) being located between adjacent cell unit regions; and a protective layer provided on the back surface of the silicon substrate (1) and located in the cutting region (14). The back contact solar cell is provided with the cutting region and the protective layer in the cutting region, which is conducive to reducing the damage to the p-n junction.

Description

Technical Field

[0001] This disclosure relates to the field of photovoltaic technology, and in particular to a back-contact solar cell, a method for its fabrication, and a photovoltaic module. Background Technology

[0002] For solar cells fabricated from large-size silicon wafers, the current of a single cell is too high, making it difficult to meet the requirements of photovoltaic modules for applications with different voltages and power outputs. Therefore, large-size solar cells can be cut into smaller cell slices, and these smaller cell slices can be combined in series and parallel to create photovoltaic modules of different specifications, thereby meeting the needs of various application scenarios from low-voltage residential use to high-voltage power plants.

[0003] Currently, Thermal Laser Separation (TLS) is a commonly used cutting process in the fabrication of battery slices, offering advantages such as less contamination, smaller heat-affected zone, less damage to pn junctions, and lower efficiency loss. However, battery slices cut and passivated using the TLS process still exhibit poor electrical performance in practical applications. Summary of the Invention

[0004] The purpose of this disclosure is to provide a back-contact solar cell, a method for its fabrication, and a photovoltaic module, with the aim of improving the electrical performance of the back-contact solar cell.

[0005] The first aspect of this disclosure provides a back-contact solar cell, comprising: A silicon substrate has at least two cell cell regions and a dicing region on its back side. Each cell cell region includes a spacer region and a first conductive region and a second conductive region with opposite polarities. Adjacent first conductive regions and second conductive regions are separated by the spacer region, and the dicing region is located between adjacent cell cell regions. A protective layer is located on the back of the silicon substrate and in the dicing area.

[0006] In some embodiments, the protective layer includes a first byproduct layer and / or a second byproduct layer; In some embodiments, the first byproduct layer comprises a borosilicate glass layer; and / or The second byproduct layer includes a phosphosilicate glass layer.

[0007] In some embodiments, the thickness of the protective layer ranges from 690µm to 710µm; and / or

[0008] The width of the cutting area ranges from 0.55mm to 0.7mm.

[0009] In some embodiments, the back-contact solar cell further includes: a first carrier collection layer having a first conductivity type, disposed at least on the back side of the silicon substrate and located in a first conductivity region; and

[0010] The second carrier collection layer, having a second conductivity type opposite to the first conductivity type, is disposed at least on the back side of the silicon substrate and located in the second conductivity region.

[0011] In some embodiments, the first carrier collection layer includes a first tunneling layer and a first doped polysilicon layer, the first doped polysilicon layer being disposed on the side of the first tunneling layer away from the silicon substrate, and the protective layer including at least one of the first tunneling layer and the first doped polysilicon layer; and / or

[0012] The second carrier collection layer includes a second tunneling layer and a second doped polysilicon layer, the second doped polysilicon layer being disposed on the side of the second tunneling layer away from the silicon substrate, and the protective layer including at least one of the second tunneling layer and the second doped polysilicon layer.

[0013] In some embodiments, the cut area is separated from the adjacent first conductive area or second conductive area by a gap.

[0014] In some embodiments, the back surface of the silicon substrate is textured in the spacer region; and / or

[0015] The back surface of the silicon substrate is a polished surface in the first conductive region and / or the second conductive region; and / or

[0016] The protective layer also includes a passivation layer and / or an antireflection layer.

[0017] A second aspect of this disclosure provides a photovoltaic module comprising multiple back-contact solar cells of the above embodiments cut into cell slices in a dicing region, preferably wherein at least a portion of the edges of the cell slices include a protective layer.

[0018] A third aspect of this disclosure provides a method for fabricating a back-contact solar cell, comprising: S10. A silicon substrate is provided, the back side of which has at least two cell cell regions and a dicing region. Each cell cell region includes a spacer region and a first conductive region and a second conductive region with opposite polarities. Adjacent first conductive regions and second conductive regions are separated by the spacer region, and the dicing region is located between adjacent cell cell regions. S20. A layer structure is formed on a silicon substrate, and a protective layer is formed on the back side of the silicon substrate at the dicing area to form a back-contact solar cell.

[0019] In some embodiments, S20 includes: S1. A first carrier collection layer is formed on the surface of a silicon substrate; S2. A first byproduct layer is formed on the outer surface of the first carrier collection layer; S3. Remove the first carrier collection layer and the first byproduct layer from the front side, the second conductive region and the spacer region of the silicon substrate; S4. Retain at least a portion of the first carrier collection layer and the first by-product layer on the back side of the silicon substrate in the dicing region to form at least a partial protective layer; or remove the first carrier collection layer and the first by-product layer on the back side of the silicon substrate in the dicing region. In some embodiments, S20 further includes: S5. A second carrier collection layer is formed on the surface of the silicon substrate, the second carrier collection layer having the opposite conductivity type to the first carrier collection layer; S6. A second byproduct layer is formed on the outer surface of the second carrier collection layer; S7. Remove the second carrier collection layer and the second byproduct layer from the front side, the first conductive region and the spacer region of the silicon substrate; S8. Retain at least a portion of the second carrier collection layer and the second by-product layer on the back side of the silicon substrate in the dicing region to form at least a partial protective layer; or remove the second carrier collection layer and the second by-product layer on the back side of the silicon substrate in the dicing region.

[0020] In some embodiments, S3 includes: S31. Using a first laser, at least a portion of the thickness of the first by-product layer of the silicon substrate in the second conductive region and the spacer region is removed to form a first pattern; S32, Remove the first byproduct layer on the front side of the silicon substrate; S33. The first carrier collection layer and the first byproduct layer of the second conductive region and the spacer region on the front and back sides of the silicon substrate are removed by wet etching. And / or S7 includes: S71. A second laser is used to remove at least a portion of the thickness of the second by-product layer of the silicon substrate in the first conductive region and the spacer region to form a second pattern; S72, Remove the second byproduct layer on the front side of the silicon substrate; S73. The second carrier collection layer and the second byproduct layer of the first conductive region and the spacer region on the front and back sides of the silicon substrate are removed by wet etching.

[0021] In some embodiments, along the width direction of the cutting area, the distance between the irradiated areas on both sides of the cutting area by the first laser is a first distance e, and the distance between the irradiated areas on both sides of the cutting area by the second laser is a second distance d, where the second distance d ≥ the first distance e; preferably, the range of the first distance e and / or the second distance d is 0.5 mm to 0.8 mm; and / or

[0022] The parameters of the first laser include: a laser wavelength range of 355nm~1064nm, a power range of 35W~60W, a frequency range of 400kHz~600kHz, a velocity range of 15000mm / s~40000mm / s, and a spot diameter range of 100µm~200µm; and / or

[0023] The parameters of the second laser include: laser wavelength range of 355nm~1064nm, power range of 5w~60w, frequency range of 200khz~500khz, speed range of 15000mm / s~40000mm / s, and spot diameter range of 100um~200um.

[0024] In some embodiments, S20 includes: A passivation layer and / or an antireflection layer are formed on the surface of the silicon substrate to form at least a partial protective layer in the diced area.

[0025] In some embodiments, the preparation method further includes: Within the cutting zone, a thermal cracking laser is used to cut the back-contact solar cell along the length of the cutting zone to form at least two cell slices. In some embodiments, the thermal cracking laser uses a dashed line scanning cutting path, which includes alternating real-running segments and empty-running segments. Preferably, the first length b of the actual walking segment is in the range of b ≥ 20 mm; the second length c of the idle walking segment is in the range of 2 mm ≤ c ≤ 5 mm; Preferably, the parameters of the thermal cracking laser are as follows: the laser wavelength is 1064nm, the pulse width is in the nanosecond range, and the spot is a circular spot with a diameter in the range of 0.2mm-0.4mm, or an elliptical spot with the major axis and minor axis dimensions in the range of 0.2mm-0.4mm.

[0026] In some embodiments, the preparation method further includes: A grooving laser is used to form a grooving at at least one end of the dashed scanning cutting path; Preferably, the range of the third length 'a' of the slot is 3mm ≤ a ≤ 7mm; Preferably, the parameters of the slotting laser include: a laser wavelength of 1064nm, a pulse width of 100-400ns, and a circular spot size of 30-50um.

[0027] The back-contact solar cell of this disclosure has at least two cell cell regions and a dicing region on the back side of a silicon substrate. The dicing region is located between adjacent cell cell regions, and a protective layer is disposed within the dicing region. The dicing region, used to cut the back-contact solar cell, prevents heat generated during cutting from diffusing to the cell cell regions, reducing uneven instantaneous heat distribution within the back-contact solar cell and thus helping to reduce pn junction damage. Furthermore, the protective layer blocks optical penetration damage caused by lasers, reduces longitudinal heat accumulation during cutting, and homogenizes heat accumulation and diffusion at different thickness locations of the back-contact solar cell, preventing wavy lines from forming on the cut cross-section of the back-contact solar cell, thereby further reducing pn junction damage.

[0028] The photovoltaic module of this disclosure includes multiple cell slices cut from the back-contact solar cells of the above embodiments in the cutting area. Since the edges of the cell slices are less affected by heat damage and have good electrical performance, the output power of the photovoltaic module can also be guaranteed.

[0029] The method for preparing a back-contact solar cell based on the embodiments of this disclosure can prepare the solar cell described in the above embodiments, that is, a protective layer can be formed in the cutting area of ​​the solar cell, thereby reducing thermal damage to the cutting edge of the solar cell.

[0030] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0031] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this application, illustrate exemplary embodiments of this disclosure and are used to explain this disclosure, but do not constitute an undue limitation of this disclosure. In the drawings: Figure 1 This is a schematic diagram of the structure of a back-contact solar cell according to some embodiments of the present disclosure. It shows two cell cell regions adjacent to the cutting area. The white area is the first conductive area, the black area is the second conductive area, the gray area is the spacing area, and the dashed line shows the dashed scanning cutting path.

[0032] Figure 2 This is a schematic diagram of the dashed line scanning cutting path for some embodiments of this disclosure.

[0033] Figure 3 This is a partial structural schematic diagram of a first or second pattern according to some embodiments of this disclosure.

[0034] Figure 4 This is a schematic diagram of a structure in which a first carrier collection layer and a first byproduct layer are formed on the surface of a silicon substrate, according to some embodiments of this disclosure.

[0035] Figure 5 This is a schematic diagram of a structure in which a first pattern is formed on a first byproduct layer on the back side of a silicon substrate, as provided in some embodiments of this disclosure. The arrows in the diagram represent the first laser.

[0036] Figure 6 This is a schematic diagram of the structure for removing the first byproduct layer on the front side of a silicon substrate, provided in some embodiments of this disclosure.

[0037] Figure 7 This is a schematic diagram of the structure of removing the first carrier collection layer, the second conductive region, and the first carrier collection layer and the first by-product layer in the spacer region on the front side of the silicon substrate, as provided in some embodiments of this disclosure.

[0038] Figure 8 This is a schematic diagram of a structure in which a second carrier collection layer and a second byproduct layer are formed on the surface of a silicon substrate, according to some embodiments of this disclosure.

[0039] Figure 9 This is a schematic diagram of a structure in which a second pattern is formed on a second byproduct layer on the back side of a silicon substrate, as provided in some embodiments of this disclosure. The arrows in the diagram represent the second laser.

[0040] Figure 10 This is a schematic diagram of the structure for removing the second byproduct layer on the front side of the silicon substrate, provided in some embodiments of this disclosure.

[0041] Figure 11 This is a schematic diagram of a structure provided in some embodiments of the present disclosure, showing the removal of a second carrier collection layer on the front side of a silicon substrate, a second carrier collection layer and a second byproduct layer on the back side, a first byproduct layer on the first conductive region on the back side of the silicon substrate, and texturing of the front side of the silicon substrate.

[0042] Explanation of reference numerals in the attached figures: 1. Silicon substrate; 11. First conductive region; 12. Second conductive region; 13. Spacer region; 14. Cutting region; 21. First tunneling layer; 22. Second tunneling layer; 3. First doped polysilicon layer; 4. First by-product layer; 5. Second doped polysilicon layer; 6. Second by-product layer; 30. Diffusion layer; 210. First carrier collection layer; 220. Second carrier collection layer; 10. First laser; 20. Second laser; a. Third length; b. First length; c. Second length; d. Second distance; e. First distance; f. Branch road width; g. Third distance; h. Fourth distance; k. Main road width. Detailed Implementation

[0043] The embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and examples. The following detailed description of the embodiments and the accompanying drawings are used to illustrate the principles of this disclosure by way of example, but should not be used to limit the scope of this disclosure, that is, this disclosure is not limited to the described embodiments.

[0044] In the description of this disclosure, it should be understood that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this disclosure.

[0045] In the fabrication of back-contact solar cells, the TLS (Thickening and Cutting) process is generally used to automatically cut the cells from large silicon wafers into smaller cell slices. The TLS process consists of three steps: First, a grooving laser is used to pre-etch grooves at both ends of the cell along the cutting path; second, the cell is locally heated using a thermal cracking laser; and third, the heated area is rapidly cooled using a coolant to induce the cell to naturally split along the predetermined path.

[0046] After the solar cell is thermally cracked by laser scanning and cooled, a longitudinal temperature field is formed along the thickness of the cell. This temperature field generates a temperature gradient along the longitudinal direction of the cell, inducing thermal stress. The laser spot scanning location is under compressive stress, while the area around the laser spot is under tensile stress. Since the compressive strength of the material used to manufacture the solar cell is greater than its tensile strength, when the tensile stress reaches the material's fracture strength, the material will fracture, enabling the cell to be cut into sections.

[0047] Although the TLS process offers advantages such as less pollution, a smaller heat-affected zone, reduced pn junction damage, and lower cutting efficiency losses, the resulting solar cell slices still exhibit poor electrical performance in practical applications. This is primarily due to two factors: firstly, the laser can cause optical penetration damage along the longitudinal direction of the silicon wafer; secondly, uneven instantaneous heat distribution can create wavy patterns on the cut surface. Both of these issues contribute to a decline in the electrical performance of the solar cell slices, thereby limiting the output power of photovoltaic modules.

[0048] Specifically, the wavy lines are caused by the thermal cracking laser scanning the solar cell. A hot spot forms at the point of contact between the laser and the cell surface. After the laser passes, it cools rapidly, generating compressive stress at the hot spot and tensile stress in the cooled area. Furthermore, the crack tip propagates along the region of maximum tensile stress. Therefore, when the power or speed of the thermal cracking laser is unstable, it leads to uneven crack propagation, ultimately resulting in wavy lines on the cut surface.

[0049] Therefore, to reduce the optical damage and wavy lines caused by laser penetration, it is necessary to reduce the thermal impact of the thermal cracking laser on the solar cells and reduce the damage to the pn junctions generated during the cutting process, thereby ensuring the electrical performance of the solar cell slices obtained after cutting and thus improving the output power of the photovoltaic module.

[0050] Based on the above ideas, this disclosure provides a back-contact solar cell. For example... Figures 1 to 11 As shown, in some embodiments, the back-contact solar cell includes: A silicon substrate 1 has at least two cell cell regions and a dicing region 14 on its back side. Each cell cell region includes a spacer region 13 and a first conductive region 11 and a second conductive region 12 with opposite polarities. Adjacent first conductive regions 11 and second conductive regions 12 are separated by the spacer region 13. The dicing region 14 is located between adjacent cell cell regions. A protective layer is disposed on the back side of the silicon substrate 1 and located in the dicing area 14.

[0051] For example, the silicon substrate 1 can be an N-type silicon wafer, such as a phosphorus-doped single-crystal silicon wafer with a resistivity of 0.1-100Ω. cm, for example, can be 0.1Ω cm, 10Ω cm, 20Ω cm, 30Ω cm, 40Ω cm, 50Ω cm, 60Ω cm, 70Ω cm, 80Ω cm, 90Ω cm or 100Ω The thickness is 100um-500um, such as 100um, 200um, 300um, 400um, or 500um. Optionally, the front side of the silicon substrate 1 has a textured surface to reduce light reflection and increase light absorption, thereby improving the efficiency of the back-contact solar cell. The back side of the silicon substrate 1 has a polished surface to reduce surface defects and improve passivation.

[0052] The first conductive region 11, the second conductive region 12, the spacer region 13, and the cutting region 14 are not solid components, but regions divided within the extended plane of the silicon substrate 1. The spacer region 13 is a gap. At least one first conductive region 11 and at least one second conductive region 12 can be provided. If multiple first conductive regions 11 and multiple second conductive regions 12 are provided, they can be alternately arranged, for example, alternately arranged along a preset direction, which can be the length or width direction of the silicon substrate 1.

[0053] The first conductive region 11 and the second conductive region 12 can be in the form of an interdigitated structure, or they can be in other regular or irregular structures.

[0054] A protective layer is disposed on the back side of the silicon substrate 1 and located in the cutting area 14, which is rectangular in shape. For example, the protective layer can completely cover the cutting area 14; or the protective layer can completely cover the cutting area 14 along its extension direction and partially cover it in the width direction of the cutting area 14, with the laser cutting position located within the protective layer when the battery is subsequently sliced ​​into slices.

[0055] The back-contact solar cell of this embodiment has at least two cell regions and a cutting region 14 on the back side of a silicon substrate 1. The cutting region 14 is located between adjacent cell regions, and a protective layer is provided within the cutting region 14. The protective layer helps to reduce the heat from the laser reaching the silicon substrate 1 during laser dicing to form cell slices, reducing optical penetration damage caused by the laser and minimizing longitudinal heat accumulation during dicing. It also prevents wavy lines from forming on the cut cross-section of the back-contact solar cell, thereby reducing pn junction damage. Furthermore, by providing the cutting region 14, it is beneficial to cut the back-contact solar cell within a predetermined area. The cutting region 14 is independent of the cell regions, preventing heat generated during dicing from diffusing to the cell regions, thus reducing uneven instantaneous heat distribution within the back-contact solar cell. Therefore, the back-contact solar cell with the protective layer can reduce laser damage during dicing to form cell slices, thereby improving photoelectric conversion efficiency.

[0056] In addition, the battery cell area includes a spacer area 13 and a first conductive area 11 and a second conductive area 12 with opposite polarities. The adjacent first conductive area 11 and second conductive area 12 are separated by the spacer area 13, which can avoid leakage problems.

[0057] In some embodiments, the protective layer includes a first byproduct layer 4 and / or a second byproduct layer 6.

[0058] Specifically, such as Figure 11 As shown, the protective layer may include a first byproduct layer 4 and a second byproduct layer 6. Along the thickness direction of the back contact solar cell, the second byproduct layer 6 is located outside the first byproduct layer 4, or the second byproduct layer 6 may also be located inside the first byproduct layer 4 (not shown).

[0059] Specifically (not shown), the protective layer may have only the first byproduct layer 4; or the protective layer may have only the second byproduct layer 6.

[0060] In addition to longitudinal heat accumulation, thermal cracking lasers also accumulate heat laterally in back-contact solar cells. Monocrystalline silicon exhibits anisotropic thermal conductivity; therefore, to ensure complete release of longitudinal heat accumulation, back-contact solar cells in related technologies require a wider cutting area 14 to release lateral heat accumulation.

[0061] The protective layer of this embodiment includes a first byproduct layer 4 and / or a second byproduct layer 6. The first byproduct layer 4 and the second byproduct layer 6 have an unoriented lattice arrangement and are isotropic in thermal conductivity, thus blocking the instantaneous heat generated by the laser from being conducted to the silicon substrate 1. Furthermore, within the first byproduct layer 4 and the second byproduct layer 6, the space and time required for longitudinal heat accumulation and lateral heat accumulation release are consistent, allowing the instantaneous heat generated by the laser to be uniformly distributed longitudinally and laterally through the protective layer of amorphous silicon. This facilitates the creation of a smoother cutting cross-section, reduces edge defects, and thus reduces edge recombination. Moreover, the cutting area 14 does not need to be set with a large width to release lateral heat accumulation, which helps to reduce the width of the cutting area 14. With a fixed size of the cell cell area, the use of silicon substrate 1 can be saved. With a fixed size of silicon substrate 1, the area of ​​the photoelectric conversion region can be increased, improving the photoelectric conversion efficiency of the back contact solar cell. When cutting into sliced ​​cells, it also helps to increase the yield.

[0062] In some embodiments, such as Figures 4 to 11 As shown, the first byproduct layer 4 includes a borosilicate glass (BSG) layer; and / or the second byproduct layer 6 includes a phosphosilicate glass (PSG) layer.

[0063] Both BSG and PSG can improve the heat resistance of the cutting area 14, suppress thermal damage and lattice distortion caused during hot cracking laser scanning, and block heat from diffusing into the silicon substrate 1, thereby maintaining the electrical performance stability of the cutting edge.

[0064] In addition, BSG has a higher density than PSG, which is more conducive to reducing thermal damage to the cutting edge caused by laser cutting.

[0065] In some embodiments, the thickness of the BSG ranges from 25nm to 50nm, such as 25nm, 30nm, 35nm, 40nm, 45nm, or 50nm.

[0066] In some embodiments, the thickness of the PSG ranges from 30nm to 50nm, such as 30nm, 35nm, 40nm, 45nm, or 50nm.

[0067] In some embodiments, the thickness of the protective layer ranges from 690um to 710um, such as 690um, 695um, 700um, 705um, and 710um.

[0068] Within this thickness range, the protective layer can effectively block heat from being conducted into the silicon substrate 1, reduce lattice damage caused by high temperature, reduce production materials and manufacturing costs, and avoid problems such as uneven stress during the cutting process caused by an excessively thick protective layer.

[0069] In some embodiments, the width of the cutting area 14 ranges from 0.55mm to 0.7mm, for example, 0.6mm.

[0070] In addition to longitudinal heat accumulation, thermal cracking lasers also accumulate heat laterally in back-contact solar cells. In related technologies, without a protective layer, back-contact solar cells require a cutting width of at least 1 mm to release lateral heat accumulation. In this embodiment, the cutting area 14 of the back-contact solar cell has an unoriented lattice arrangement and isotropic thermal conductivity. The space and time required for releasing both longitudinal and lateral heat accumulation are consistent. Therefore, the cutting area 14 does not require additional width to release lateral heat accumulation, allowing for a reduction in the width of the cutting area 14 while maintaining electrical performance.

[0071] In some embodiments, such as Figures 4 to 11 As shown, the back-contact solar cell also includes: A first carrier collection layer 210, having a first conductivity type, is disposed at least on the back side of the silicon substrate 1 and located in the first conductive region 11; and The second carrier collection layer, having a second conductivity type opposite to the first conductivity type, is disposed at least on the back side of the silicon substrate 1 and located in the second conductivity region 12.

[0072] Further reference Figure 11 The first carrier collection layer 210 is located within the first conductive region 11. The first carrier collection layer 210 has a first conductivity type, such as P-type, and can be formed by boron doping. + Emitter. The second carrier collection layer 220 is located within the second conductive region 12, and the second carrier collection layer 220 has a second conductivity type, such as N-type, or vice versa.

[0073] In some embodiments, such as Figures 4 to 11 As shown, the first carrier collection layer 210 includes a first tunneling layer 21 and a first doped polysilicon layer 3. The first doped polysilicon layer 3 is disposed on the side of the first tunneling layer 21 away from the silicon substrate 1. The protective layer includes at least one of the first tunneling layer 21 and the first doped polysilicon layer 3; and / or

[0074] The second carrier collection layer 220 includes a second tunneling layer 22 and a second doped polysilicon layer 5. The second doped polysilicon layer 5 is disposed on the side of the second tunneling layer 22 away from the silicon substrate 1. The protective layer includes at least one of the second tunneling layer 22 and the second doped polysilicon layer 5.

[0075] A first tunneling layer 21 is disposed on the back side of the silicon substrate 1 and located within the first conductive region 11 and the dicing region 14. A first doped polysilicon layer 3 is disposed on the side of the first tunneling layer 21 away from the silicon substrate 1 and has a first conductivity type. A second tunneling layer 22 is disposed on the back side of the silicon substrate 1 and located within the second conductive region 12 and the dicing region 14. A second doped polysilicon layer 5 is disposed on the side of the second tunneling layer 22 away from the silicon substrate 1, and the second doped polysilicon layer 5 has a second conductivity type opposite to the first conductivity type.

[0076] The first carrier collecting layer 210 and the second carrier collecting layer 220 are lattice isotropic. Therefore, the first carrier collecting layer 210 and the second carrier collecting layer 220 are conducive to the uniform distribution of heat accumulation in the longitudinal and transverse directions, which is beneficial to the generation of a smoother cutting cross section, reducing edge defects and thus reducing edge recombination. In addition, the first carrier collecting layer 210 and the second carrier collecting layer 220, as recombination layers, can also reduce the energy of the laser directly acting on the silicon substrate 1, thereby reducing laser damage.

[0077] In addition, the protective layer is a composite layer that includes both amorphous silicon and polycrystalline silicon layers. It is thicker and can further enhance the protection of the silicon substrate 1, and also better reduce the damage caused by laser heat.

[0078] The first tunneling layer 21 and the second tunneling layer 22 are ultrathin dielectric layers that allow electrons to pass through efficiently through the quantum tunneling effect while blocking the recombination loss of other charges such as holes. Silicon oxide (SiO2) and silicon nitride (SiN) can be used. x Or aluminum oxide, Al2O3, etc. For example, the thickness of the first tunneling layer 21 ranges from 1.2nm to 2nm, such as 1.2nm, 1.5nm, 1.7nm or 2nm, etc.

[0079] The first doped polysilicon layer 3 can be a P-type doped polysilicon layer, for example, forming a P-type doped polysilicon layer. + PolySi, i.e., the back side of the silicon substrate 1, has SiO2 / P2O3 / SiO2 ... + PolySi layered structure. The doping concentration of the first doped polysilicon layer 3 is 8 × 10⁻⁶. 19 -9×10 19 atoms / cm 3 .

[0080] The second doped polysilicon layer 5 can be an N-type doped polysilicon layer, for example, forming an N...+ PolySi, i.e., the back side of the silicon substrate 1, has SiO2 / N2 on the second conductive region 12 and the dicing region 14. + The structure is a PolySi multilayer structure. The doping concentration of the second doped polysilicon layer 5 is 4 × 10⁻⁶. 20 -5×10 20 atoms / cm 3 .

[0081] In some embodiments, such as Figure 11 As shown, the cutting area 14 is separated from the adjacent first conductive area 11 or second conductive area 12 by a spacer area 13.

[0082] Because laser cutting of back-contact solar cells and separation by mechanical force can easily generate defects at the cutting edge, and charge carriers can migrate to the cutting edge through the emitter, edge recombination problems can occur, and the recombination rate at defect surfaces is relatively high. Furthermore, the emitter has lateral conductivity, and charge carriers can diffuse along the emitter to the edge for recombination. By setting the spacer region 13 to separate the cutting region 14 from the adjacent first conductive region 11 or second conductive region 12, the lateral diffusion of charge carriers along the emitter to the edge for recombination can be prevented, thus helping to ensure the electrical performance of the cut back-contact solar cell.

[0083] In addition, the spacer region 13 completely separates the emitter from the second doped polysilicon layer 5, which also helps to avoid leakage problems.

[0084] In some embodiments, such as Figure 11 As shown, the back surface of the silicon substrate 1 is textured in the spacer region 13; and / or

[0085] The back surface of the silicon substrate 1 is a polished surface in the first conductive region 11 and / or the second conductive region 12; and / or

[0086] The protective layer also includes a passivation layer and / or an antireflection layer.

[0087] The back side of the silicon substrate 1 is textured in the spacer region 13. When light strikes the textured structure, it undergoes multiple reflections, allowing the back-contact solar cell to absorb more light energy and convert it into electrical energy, effectively improving the light utilization efficiency of the back side of the solar cell. Simultaneously, the textured surface possesses broad-band anti-reflection capabilities, reducing light reflection over a wide wavelength range and further minimizing light energy loss. Furthermore, the uneven textured structure extends the propagation distance of light within the back-contact solar cell, increasing the probability of photon interaction with the silicon substrate 1, thereby generating more charge carriers and enhancing the overall light absorption capacity.

[0088] The first conductive region 11 and / or the second conductive region 12 on the back surface of the silicon substrate 1 are set as polished surfaces, which can improve the surface passivation effect. The polished surface has a regular atomic arrangement, with surface atoms stably attached to the crystal lattice structure, a small surface area, and few internal crystal defects. This structure can also remove the process damage generated on the back surface of the silicon substrate 1 in the first conductive region 11 and the second conductive region 12 during the early processing stage, further reducing the number of crystal defects and reducing the recombination of charge carriers at the defect sites on the back surface. Moreover, the flat and smooth polished surface helps to ensure uniform growth of the passivation layer, enhances the bonding force between the passivation layer and the silicon substrate 1, keeps the passivation layer thickness consistent, and helps to prevent charge carrier recombination, thereby improving the passivation effect.

[0089] The protective layer also includes a passivation layer and / or an anti-reflection layer, which are located on the outermost layer. By selectively deploying such a film layer in the cutting area 14, the passivation effect of the cutting edge can be improved, the lattice damage and surface defects caused by the slab cutting process can be compensated, the carrier recombination caused by defects can be reduced, and the electrical performance of the battery slice can be optimized.

[0090] In some embodiments, a first metal grid line is provided on the back side of the silicon substrate 1 in the first conductive region 11 for collecting holes, and a second metal grid line is provided in the second conductive region 12 for collecting electrons.

[0091] Three specific embodiments will be given below. The structure of the protective layer is not limited to these; you may choose to retain any one or part of the film layer.

[0092] In the first embodiment, as Figure 11 As shown, the back side of the silicon substrate 1 schematically shows two cell cell regions and a cutting area 14 located between the two cell cell regions. More cell cell regions can be provided, with cutting areas 14 provided between adjacent cell cell regions. A protective layer is provided on the back side of the silicon substrate 1 and located in the cutting area 14 to reduce thermal damage to the back-contact solar cell caused by the thermal cracking laser during the cutting process. Each cell cell region includes a spacer region 13 and a first conductive region 11 and a second conductive region 12 with opposite polarities. Adjacent first conductive regions 11 and second conductive regions 12 are separated by the spacer region 13. Multiple first conductive regions 11 and second conductive regions 12 can be provided, and they are arranged alternately. The cutting area 14 is separated from the first conductive region 11 or the second conductive region 12 by the spacer region 13.

[0093] The first conductive region 11, the second conductive region 12, and the dicing region 14 are polished surfaces. The spacer region 13 and the front surface of the silicon substrate 1 are textured. The front surface of the silicon substrate 1 has no metal gate lines, while the back surface has metal gate lines.

[0094] Along the direction from the front to the back of the silicon substrate 1, the back contact solar cell has a passivation antireflection layer (silicon oxynitride), a passivation layer (aluminum oxide), silicon substrate 1, a first tunneling layer 21, a first doped polycrystalline silicon layer 3, a first by-product layer 4 (BSG), a second tunneling layer 22, a second doped polycrystalline silicon layer 5, a second by-product layer 6 (PSG), a passivation layer (aluminum oxide), and a passivation antireflection layer (silicon oxynitride) stacked sequentially in the cut area 14.

[0095] In this embodiment, the protective layer retains the various layer structures from the back-contact solar cell fabrication process. The increased thickness of the protective layer helps to minimize the heat generated by the laser reaching the silicon substrate 1 during laser slicing of the back-contact solar cell, reducing optical penetration damage caused by the laser and minimizing longitudinal heat accumulation during the cutting process. This avoids wavy lines on the cut cross-section of the back-contact solar cell, thus reducing pn junction damage and improving photoelectric conversion efficiency. Furthermore, no additional process steps are required to remove parts of the layer structure in the cut area 14 during the fabrication of the back-contact solar cell.

[0096] In the second embodiment (not shown), with Figure 11 The difference in the back-contact solar cell shown is that, along the direction from the front to the back of the silicon substrate 1, the back-contact solar cell has a passivation anti-reflection layer (silicon oxynitride), a passivation layer (aluminum oxide), silicon substrate 1, a first tunneling layer 21, a first doped polycrystalline silicon layer 3, a first by-product layer 4 (BSG), a passivation layer (aluminum oxide), and a passivation anti-reflection layer (silicon oxynitride) stacked sequentially in the cut area 14.

[0097] In the third embodiment (not shown), with Figure 11 The difference in the back-contact solar cell shown is that, along the direction from the front to the back of the silicon substrate 1, the back-contact solar cell has a passivation anti-reflection layer (silicon oxynitride), a passivation layer (alumina), silicon substrate 1, a second tunneling layer 22, a second doped polycrystalline silicon layer 5, a second byproduct layer 6 (PSG), a passivation layer (alumina), and a passivation anti-reflection layer (silicon oxynitride) stacked sequentially in the cut area 14.

[0098] Secondly, this disclosure provides a photovoltaic module comprising multiple back-contact solar cells from the above embodiments, cut into cell slices in the cutting area 14. Because a protective layer is provided in the cutting area 14, the edges of the cut cell slices are less affected by heat damage, have no wavy lines, and exhibit good electrical performance.

[0099] In some embodiments, at least a portion of the edges of the battery slice include a protective layer. For example, the battery slice is rectangular, and a protective layer is provided on some or all of its edges.

[0100] The protective layer can protect at least part of the edges of the battery slice to prevent wavy lines from forming on the cut surface, thereby helping to ensure the electrical performance of the battery slice.

[0101] For example, a photovoltaic module includes a laminate and a frame assembled to the edge of the laminate, wherein the laminate includes a cover plate, an encapsulating film, cell slices, an encapsulating film, and a backsheet stacked sequentially. Multiple cell slices may be provided, and the multiple cell slices may be arranged in series and / or parallel.

[0102] Because the edges of the battery cells are less affected by heat damage, they have good electrical performance. This also helps to improve the output power of photovoltaic modules.

[0103] Finally, this disclosure provides a method for fabricating a back-contact solar cell. In some embodiments, the method includes: Step S10: Provide a silicon substrate 1. The back side of the silicon substrate 1 has at least two cell regions and a dicing region 14. Each cell region includes a spacer region 13 and a first conductive region 11 and a second conductive region 12 with opposite polarities. Adjacent first conductive regions 11 and second conductive regions 12 are separated by the spacer region 13. The dicing region 14 is located between adjacent cell regions. Step S20: A layer structure is formed on the silicon substrate 1, and a protective layer is formed on the back side of the silicon substrate 1 at the cutting area 14 to form the back contact solar cell of the above embodiment.

[0104] The silicon substrate 1 provided can be an N-type single-crystal silicon substrate.

[0105] Before step S10, the silicon substrate 1 is first cleaned to remove surface oil, particles, and the natural oxide layer. Then, a low-concentration alkaline solution is used to texturize the front side of the silicon substrate 1 on one side, forming a uniform micron-scale pyramidal textured surface to reduce surface reflection and enhance light absorption. The resulting pyramidal structure is 10µm-50µm in size, for example, 30µm. After texturization, the silicon substrate 1 is cleaned, and then an alkaline solution is used to polish the back side of the silicon substrate 1 on one side to make the back side smooth and with low roughness.

[0106] In step S20, the thickness of the protective layer formed is 690um-710um, for example, 700um.

[0107] The method for preparing a back-contact solar cell based on the embodiments of this disclosure can prepare the back-contact solar cell described above, that is, a protective layer can be formed in the cutting area 14 of the back-contact solar cell, thereby reducing thermal damage to the cutting edge of the back-contact solar cell.

[0108] In some embodiments, such as Figures 4 to 7 As shown, step S20 includes: S1. A first carrier collection layer 210 is formed on the surface of the silicon substrate 1; S2. A first byproduct layer 4 is formed on the outer surface of the first carrier collection layer 210; S3, Remove the front side of the silicon substrate 1, the first carrier collection layer 210 of the second conductive region 12 and the spacer region 13, and the first by-product layer; S4. Retain at least a portion of the first carrier collection layer 210 and the first by-product layer 4 on the back side of the silicon substrate 1 in the dicing region 14 to form at least a partial protective layer; or remove the first carrier collection layer 210 and the first by-product layer 4 on the back side of the silicon substrate 1 in the dicing region 14.

[0109] Steps S1 to S4 are executed sequentially.

[0110] Specifically, the first carrier collection layer 210 may include a first tunneling layer 21 and a first doped polysilicon layer 3.

[0111] Specifically, an oxidation process can be used to oxidize the surface of the silicon substrate 1 to form a first tunneling layer 21 with a thickness ranging from 1.2 nm to 2 nm. The material of the first tunneling layer 21 includes SiO2.

[0112] Subsequently, a first intrinsic polysilicon layer is stacked outside the first tunneling layer 21 using a low-pressure chemical vapor deposition (LPCVD) process. The thickness of the first intrinsic polysilicon layer ranges from 250 nm to 260 nm, for example, 255 nm.

[0113] Subsequently, boron diffusion is performed on the back side of the silicon substrate 1. Specifically, under high temperature conditions, the boron-containing diffusion source decomposes to generate boron atoms, which gradually diffuse into the interior of the first intrinsic polycrystalline silicon layer, completing lattice doping and forming a P-type first doped polycrystalline silicon layer 3. Some of the boron atoms diffuse to the space between the first tunneling layer 21 and the silicon substrate 1 to form a diffusion layer 30, which is used to form a pn junction.

[0114] Specifically, in step S2, silicon and boron elements undergo an oxidation reaction with oxygen, and BSG, i.e., the first by-product layer 4, is stacked on the outer layer of the first doped polycrystalline silicon layer 3.

[0115] Specifically, such as Figure 6 As shown, the first byproduct layer 4 on the front side of the silicon substrate 1 is removed using a single-sided wet etching process. Subsequently, as... Figure 7 As shown, wet etching is used to remove the first carrier collection layer 210, the second conductive region 12, and the first carrier collection layer 210 and the first by-product layer 4 in the spacer region 13 on the front side of the silicon substrate 1.

[0116] In step S4, the first carrier collection layer 210 can be retained in the first conductive region 11 and the cutting region 14, and the first by-product layer 4 can be retained in the cutting region 14; or the first carrier collection layer 210 can be retained only in the first conductive region 11, the first by-product layer 4 in the first conductive region 11 can be removed, and the first carrier collection layer 210 and the first by-product layer 4 in the cutting region 14 can be removed. Alternatively, any one, two, or more film layers can be provided in the cutting region 14 as needed.

[0117] In some embodiments, such as Figures 8 to 11 As shown, S20 also includes: S5. A second carrier collection layer 220 is formed on the surface of the silicon substrate 1. The second carrier collection layer 220 has the opposite conductivity type to the first carrier collection layer 210. S6. A second byproduct layer 6 is formed on the outer surface of the second carrier collection layer 220. S7. Remove the front side of the silicon substrate 1, the second carrier collection layer 220 and the second byproduct layer 6 of the first conductive region 11 and the spacer region 13. S8. Retain at least a portion of the second carrier collection layer 220 and the second byproduct layer 6 on the back side of the silicon substrate 1 in the dicing region 14 to form at least a partial protective layer; or remove the second carrier collection layer 220 and the second byproduct layer 6 on the back side of the silicon substrate 1 in the dicing region 14.

[0118] Steps S5 to S8 are executed sequentially. Steps S5 to S8 may be performed after steps S1 to S4; or steps S5 to S8 may be performed before steps S1 to S4.

[0119] Specifically, the second carrier collection layer 220 may include a second tunneling layer 22 and a second doped polysilicon layer 5.

[0120] Specifically, an oxidation process can be used to oxidize the surface of the silicon substrate 1 to form a second tunneling layer 22 with a thickness ranging from 1.2 nm to 2 nm. The material of the second tunneling layer 22 includes SiO2.

[0121] Subsequently, a second intrinsic polysilicon layer is stacked outside the second tunneling layer 22 using an LPCVD process. The thickness of the second intrinsic polysilicon layer ranges from 250 nm to 260 nm, for example, 255 nm.

[0122] Subsequently, phosphorus diffusion is performed on the back side of the silicon substrate 1. Specifically, under high temperature conditions, the phosphorus-containing diffusion source decomposes to generate phosphorus atoms, which gradually penetrate into the interior of the second intrinsic polycrystalline silicon layer, completing lattice doping and forming an N-type second doped polycrystalline silicon layer 5, that is, forming a conductivity type opposite to that of the first carrier collection layer 210.

[0123] Specifically, in step S6, such as Figure 8 As shown, silicon and phosphorus elements undergo an oxidation reaction with oxygen, and PSG, i.e., the second by-product layer 6, is stacked outside the second doped polycrystalline silicon layer 5.

[0124] Specifically, such as Figure 10 As shown, the second byproduct layer 6 on the front side of the silicon substrate 1 is removed by single-sided wet etching.

[0125] In step S8, the second carrier collection layer 220 may be retained in the second conductive region 12 and the cutting region 14, and the second by-product layer 6 may be retained in the cutting region 14; or the second carrier collection layer 220 may be retained only in the second conductive region 12, the second by-product layer 6 in the second conductive region 12 may be removed, and the second carrier collection layer 220 and the second by-product layer 6 in the cutting region 14 may be removed.

[0126] In some embodiments, such as Figures 5 to 7 As shown, S3 includes: S31. A first laser 10 is used to remove at least a portion of the thickness of the first by-product layer 4 of the silicon substrate 1 in the second conductive region 12 and the spacer region 13 to form a first pattern; S32, Remove the first byproduct layer 4 on the front side of silicon substrate 1; S33. The first carrier collection layer 210 on the front side of the silicon substrate 1, the first carrier collection layer 210 and the first by-product layer 4 on the back side of the second conductive region 12 and the spacer region 13 are removed by wet etching.

[0127] Specifically, such as Figure 1 As shown, the first pattern is the area shown by the black area and the gray area, to obtain a protective layer including the first by-product layer 4 and the second by-product layer 6; or, the first pattern is the area where the black area, the gray area and the cutting area 14 are located, to obtain a protective layer including the second by-product layer 6.

[0128] Specifically, such as Figure 3 As shown, the first pattern includes multiple main paths and multiple branch paths. The main paths are spaced apart along the length of the cutting area 14, and each main path extends along the width of the cutting area 14. Multiple branch paths are corresponding to the same main path and intersect the corresponding main path perpendicularly. The distance between the branch paths on both sides of the main path in the width direction is equal.

[0129] The first pattern parameters include: the main path width k can range from 0.55mm to 0.65mm, for example, 0.6mm. The branch path width f can range from 0.6mm to 1.5mm, for example, 0.606mm, or even 1.47mm. The third distance g between the center lines of two adjacent branches extending along the length direction of the cutting area 14 is 1mm to 3mm, for example, 1.06mm, or even 2.74mm. The branches have a fourth distance h, which is half the branch path length minus half the main path width. The fourth distance h ranges from 0.95mm to 1mm, for example, 0.985mm.

[0130] In this design, the branch width *f* and the third distance *g* are matched. For example, if the branch width *f* is 0.606 mm, then the third distance *g* is 1.06 mm; or, if the branch width *f* is 1.47 mm, then the third distance *g* is 2.74 mm. That is, the wider the branch width *f*, the larger the third distance *g*, which helps ensure the cutting path is far from the core power generation area. This allows subsequent cross-section passivation repair processes to more fully and deeply affect the cut surface, thus helping to repair defects caused by cutting and improving the final conversion efficiency of the back-contact solar cell. Conversely, the narrower the branch width *f*, the smaller the third distance *g*, and the denser the branch layout, which helps to increase the effective light-receiving area, thereby increasing the power density per unit area of ​​the photovoltaic module and the overall power generation.

[0131] Among them, such as Figure 5 As shown, the first laser 10 scans along a preset trajectory, creating grooves or removing surface dielectric in the second conductive region 12 and spacer region 13 of the first by-product layer 4 to form a first pattern. The first by-product layer 4 can block alkaline solutions, but single-crystal silicon readily reacts with alkaline solutions. Therefore, the high energy of the first laser 10 is used to destroy the dense structure of the first by-product layer 4, forming micropores in the first pattern area. The alkaline solution can pass through these micropores, etching the first by-product layer 4 and the first tunneling layer 21, and directly contacting the first doped polycrystalline silicon layer 3 for etching until the silicon substrate 1 is exposed, thereby achieving precise removal. The depth of the first pattern is less than or equal to the thickness of the first by-product layer 4.

[0132] In step S32, such as Figure 6 As shown, the first byproduct layer 4 on the front side of the silicon substrate 1 can be removed using a single-sided wet etching process. For example, taking advantage of the difference in acid and alkali corrosion characteristics, namely that alkaline solutions easily corrode crystalline silicon and polycrystalline silicon, but corrode BSG or PSG very slowly, while hydrofluoric acid (HF) mainly corrodes BSG or PSG and does not corrode crystalline silicon, the first byproduct layer 4 on the front side can be etched using a chain-type single-sided wet etching process in a 25% mass concentration hydrofluoric acid solution.

[0133] In step S33, such as Figure 7As shown, the first carrier collection layer 210 and the first by-product layer 4 are removed from the second conductive region 12 and the spacer region 13 on the back side of the silicon substrate 1, and the first carrier collection layer 210 on the front side of the silicon substrate 1 is also removed, while the first carrier collection layer 210 and the first by-product layer 4 in the first conductive region 11 and the dicing region 14 are retained. The first carrier collection layer 210 in the first conductive region 11 can form an emitter.

[0134] In some embodiments, such as Figures 9 to 11 As shown, S7 includes: S71. A second laser 20 is used to remove at least a portion of the thickness of the second byproduct layer 6 of the silicon substrate 1 in the first conductive region 11 and the spacer region 13 to form a second pattern. S72, Remove the second byproduct layer 6 on the front side of silicon substrate 1; S73, wet etching is used to remove the second carrier collection layer 220 on the front side of the silicon substrate 1, the second carrier collection layer 220 on the back side of the first conductive region 11 and the spacer region 13, and the second byproduct layer 6.

[0135] Specifically, in step S71, such as Figure 1 and Figure 9 As shown, the second pattern is the area shown by the white area and the gray area, to obtain a protective layer including the first by-product layer 4 and the second by-product layer 6; or, the second pattern is the area where the white area, the gray area and the cutting area 14 are located, to obtain a protective layer including the first by-product layer 4.

[0136] Specifically, the second laser 20 includes a high-power laser (corresponding to...) Figure 9 The two states (solid arrow in the middle) and low power (corresponding to) Figure 9 (Dashed arrow). The second pattern includes a first region and a second region. The first region corresponds to the first conductive region 11 and the spacer region 13, and the second region corresponds to the second conductive region 12.

[0137] The first region of the second byproduct layer 6 is modified by a high-power second laser 20, enabling the second byproduct layer 6 within the first region to react with alkali. The second region of the second byproduct layer 6 is modified by a low-power second laser 20, enabling the second byproduct layer 6 within the second region to accelerate its reaction rate with acid.

[0138] When irradiated with the second laser 20, the first region is first modified using the high-power state of the second laser 20, and then the second region is modified using the low-power state. After scanning with the second laser 20 according to a preset trajectory, grooves are formed or the surface medium is removed on the second by-product layer 6 to form a second pattern. The depth of the second pattern is less than or equal to the thickness of the second by-product layer 6.

[0139] The second byproduct layer 6 can block alkaline solutions but can react with acidic solutions. Therefore, the high energy of the second laser 20 in its high-power state can destroy the dense structure of the second byproduct layer 6, forming micropores along the first region. The alkaline solution can pass through these micropores, directly contact the second doped polysilicon layer 5, and be etched.

[0140] Subsequently, an acid solution is used to remove the first byproduct layer 4, the second byproduct layer 6, and the second tunneling layer 22 in the first conductive region 11, as well as the second byproduct layer 6 in the second conductive region 12. Since the second byproduct layer 6 in the second region is modified to accelerate the reaction rate with the acid solution, after the second byproduct layer 6 in the second region is removed, the second byproduct layer 6 that has not been etched remains in the cutting region 14. Therefore, a layer of the second byproduct layer 6 can be retained, thereby achieving precise removal.

[0141] The parameters of the second laser 20 in high-power mode are as follows: laser wavelength range of 355-532nm, power of 35-40W, frequency of 250-500kHz, velocity of 33000-37500mm / s, and spot size of 150-200μm. The parameters of the second laser 20 in low-power mode are as follows: laser wavelength range of 355-532nm, power of 5-15W, frequency of 250-500kHz, velocity of 33000-37500mm / s, and spot size of 150-200μm.

[0142] Specifically, such as Figure 3 As shown, the parameters of the second pattern are the same as those of the first pattern.

[0143] In step S72, such as Figure 10 As shown, the second byproduct layer 6 on the front side of the silicon substrate 1 can be removed using a single-sided wet etching process.

[0144] In step S73, such as Figure 11 As shown, the second carrier collection layer 220 on the front side of the silicon substrate 1, the second carrier collection layer 220 and the second byproduct layer 6 in the first conductive region 11 and the spacer region 13 on the back side are removed, while the second carrier collection layer 220 in the second conductive region 12 and the dicing region 14 are retained. The second carrier collection layer 220 in the second conductive region 12 can be formed with a doping type opposite to that of the first carrier collection layer 210, and the second carrier collection layer 220 and the first carrier collection layer 210 collect electrons and holes respectively.

[0145] In some embodiments, such as Figure 1As shown, along the width direction of the cutting area 14, the distance between the irradiated areas of the first laser 10 on both sides of the cutting area 14 is the first distance e, and the distance between the irradiated areas of the second laser 20 on both sides of the cutting area 14 is the second distance d, where the second distance d ≥ the first distance e; preferably, the range of the first distance e and / or the second distance d is 0.5mm to 0.8mm, for example, the first distance e is 0.5mm and the second distance d is 0.8mm.

[0146] Make the second distance d ≥ the first distance e, so that the interval 13 can be formed on both sides of the width direction of the cutting area 14.

[0147] In some embodiments, the parameters of the first laser 10 include: a laser wavelength range of 355nm~1064nm, a power range of 35W~60W, a frequency range of 400kHz~600kHz, a velocity range of 15000mm / s~40000mm / s, and a spot diameter range of 100µm~200µm; and / or

[0148] The parameters of the second laser 20 include: laser wavelength range of 355nm~1064nm, power range of 5w~60w, frequency range of 200khz~500khz, speed range of 15000mm / s~40000mm / s, and spot diameter range of 100um~200um.

[0149] For example, the first laser 10 can have a wavelength of 532nm, a power of 40W, a frequency of 500kHz, a velocity of 37500mm / s, and a spot diameter of 150µm. The parameters of the second laser 20 can be the same as those of the first laser 10; or, the frequency of the second laser 20 can be lower than that of the first laser 10 to reduce the spot overlap rate.

[0150] In some embodiments, step S20 includes: A passivation layer and / or an antireflection layer are formed on the surface of the silicon substrate 1 to form at least a partial protective layer in the diced area 14.

[0151] For example, the passivation layer may include a silicon oxide layer, and the passivation antireflection layer may be a composite layer formed by at least one of silicon nitride and silicon oxynitride, and the silicon oxide layer, with a thickness of 60 nm to 130 nm, such as 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 120 nm, or 130 nm. Both silicon oxide and silicon nitride can serve as passivation agents, and silicon nitride can also serve as an antireflection agent. By setting a passivation antireflection layer, reflectivity can be reduced and light utilization can be improved.

[0152] In some embodiments, such as Figure 1 and Figure 2As shown, the fabrication method of this back-contact solar cell further includes: Within the cutting area 14, a thermal cracking laser is used to cut the back-contact solar cell along the length of the cutting area 14 to form at least two cell slices.

[0153] The protective layer of the cutting zone 14 can reduce the optical penetration of the hot cracking laser, thereby reducing thermal damage and the generation of wavy lines.

[0154] In some embodiments, such as Figure 2 As shown, the hot cracking laser uses a dashed line scanning cutting path, which includes alternating real-movement segments and empty-movement segments. The first length b of the actual walking segment is in the range of b≥20mm; the second length c of the empty walking segment is in the range of 2mm≤c≤5mm. The parameters of the thermal cracking laser are as follows: laser wavelength is 1064nm, pulse width is in the nanosecond range, and the laser spot is a circular spot with a diameter of 0.2mm-0.4mm, or an elliptical spot with major and minor axis dimensions within the range of 0.2mm-0.4mm. Adding a protective layer facilitates the use of thermal cracking lasers with smaller spot diameters.

[0155] For example, the first length b is 25mm, and the second length c is 4mm.

[0156] For example, the light spot is a circular light spot with a diameter of 0.3 mm.

[0157] In the active phase, the laser acts on the surface of the back-contact solar cell, while in the idle phase, the laser does not emit.

[0158] Employing a dashed scanning cutting path that includes alternating live and idle segments can reduce the contact area between the thermal cracking laser and the back-contact solar cell, thus reducing thermal damage. Furthermore, the heat accumulated by the thermal cracking laser in the live segment can be dissipated and homogenized through the idle segment, resulting in a more uniform instantaneous heat distribution. This suppresses the generation of wavy lines at the cut cross-section of the cell slice, further reducing the risk of thermal damage to the back-contact solar cell and ensuring the electrical performance of the cell slice.

[0159] In some embodiments, such as Figure 2 As shown, the fabrication method of this back-contact solar cell further includes: A grooving laser is used to form a grooving at at least one end of the dashed scanning cutting path; The range of the third length 'a' of the slot is 3mm ≤ a ≤ 7mm; The parameters of the slotting laser include: laser wavelength of 1064nm, pulse width of 100ns-400ns, and a circular spot size of 30um-50um.

[0160] For example, the third length 'a' is 4 mm, the pulse width of the slotted laser is 300 ns, and the diameter of the spot is 40 μm.

[0161] To better illustrate the preparation method and performance advantages of the embodiments of this disclosure, three specific embodiments are given below for explanation.

[0162] (1) Example 1: The front side of the N-type silicon substrate 1 is texturized, and the back side is polished. Then, the silicon substrate 1 is oxidized to form a first tunneling layer 21 (silicon dioxide layer) approximately 1.5 nm thick. Next, a first intrinsic polysilicon layer with a thickness of 255 nm is deposited using LPCVD. Boron diffusion is then performed on the first intrinsic polysilicon layer to form a P-type first doped polysilicon layer 3. Some boron atoms diffuse between the first tunneling layer 21 and the silicon substrate 1 to form a diffusion layer 30 for forming a pn junction. Furthermore, the byproducts of boron diffusion form a first byproduct layer 4 (BSG) outside the first doped polysilicon layer 3. The doping concentration of the first doped polysilicon layer 3 is 8 × 10⁻⁶. 19 atoms / cm 3 The thickness of the first by-product layer 4 is 28 nm. Subsequently, a first pattern is formed on the first by-product layer 4 using a first laser 10. The first pattern is... Figure 1 The areas shown are the black and gray regions. The first pattern parameters include: a first distance e of 0.5 mm, a fine grating main path width k of 0.6 mm, a fine grating branch path width f of 0.606 mm, a third distance g of 1.06 mm, and an interdigitated finger length h of 0.985 mm. The first laser 10 has a wavelength of 532 nm, a power of 40 W, a frequency of 500 kHz, a velocity of 37500 mm / s, and a spot diameter of 150 μm.

[0163] Subsequently, the first byproduct layer 4 on the front side of the silicon substrate 1 is removed by single-sided wet etching. After the first pattern is drawn using the first laser 10, the first byproduct layer 4 on the front side is removed by wet etching. Since the front side is in contact with the support stage when the back side is etched, the first byproduct layer 4 on the front side can play a protective role for the inner layer. Thus, the first byproduct layer 4 can be used to reduce the friction between the front side of the silicon substrate 1 and the support back side of the solar cell structure during the fabrication process.

[0164] Subsequently, an alkaline solution is used to remove the first byproduct layer 4 and the first carrier collection layer 210 in the second conductive region 12 and the spacer region 13, so as to expose the silicon substrate 1 in the second conductive region 12 and the spacer region 13 and retain the first carrier collection layer 210 in the first conductive region 11.

[0165] The silicon substrate 1 was then cleaned, and a second intrinsic polysilicon layer with a thickness of 255 nm was deposited on both the front and back sides. Phosphorus diffusion was then performed on the second intrinsic polysilicon layer to form an N-type second-doped polysilicon layer 5, and the byproducts of phosphorus diffusion formed a second byproduct layer 6 (PSG) outside the second-doped polysilicon layer 5. The doping concentration of the second-doped polysilicon layer 5 was 4 × 10⁻⁶. 20 atoms / cm 3 The thickness of the second by-product layer 6 is 40 nm. Subsequently, a second pattern is formed on the second by-product layer 6 using a second laser 20. The second pattern is... Figure 1 The areas shown are the white and gray regions. The second pattern parameters include: a second distance d of 0.8 mm to form a spacing region 13 with a width of 0.15 mm; a fine grating main path width k of 0.6 mm; a fine grating branch path width f of 0.606 mm; a third distance g of 1.06 mm; and an interdigitated finger length h of 0.985 mm. The second laser 20 has a wavelength of 532 nm, a power of 40 W, a frequency of 500 kHz, a velocity of 37500 mm / s, and a spot diameter of 150 μm.

[0166] Subsequently, a single-sided wet etching process was used to remove the second byproduct layer 6 on the front side of the silicon substrate 1.

[0167] Subsequently, an alkaline solution is used to remove the second byproduct layer 6 and the second carrier collection layer 220 in the first conductive region 11 and the spacer region 13, thereby exposing the silicon substrate 1 while retaining the second carrier collection layer 220 in the second conductive region 12. Simultaneously, an alkaline solution is used to remove the first byproduct layer 4 in the first conductive region 11 and the second byproduct layer 6 in the second conductive region 12.

[0168] Subsequently, texturing was performed on the spacer region 13 and the front side of the silicon substrate 1. Then, a passivation layer was deposited on both the front and back sides of the silicon substrate 1.

[0169] Subsequently, a conductive metal paste (typically silver paste) is screen-printed onto the first conductive region 11 and the second conductive region 12 on the back side of the silicon substrate 1, forming interlaced and insulated interdigitated metal grid lines. For example... Figure 3 As shown, the metal grid line includes a fine grid main path and fine grid branches. The width k of the fine grid main path is 0.6 mm, the width f of the fine grid branch is 0.606 mm, the third distance g is 1.06 mm, and the interdigitated finger length h is 0.985 mm.

[0170] Finally, the silicon substrate 1 is placed in a sintering furnace for high-temperature heat treatment to obtain a back-contact solar cell.

[0171] The back-contact solar cell prepared in Example 1 has the following protective layers stacked sequentially from the front to the back of the silicon substrate 1: a passivation antireflection layer (silicon oxynitride), a passivation layer (alumina), the silicon substrate 1, a first tunneling layer 21, a first doped polycrystalline silicon layer 3, a first byproduct layer 4 (BSG), a second tunneling layer 22, a second doped polycrystalline silicon layer 5, a second byproduct layer 6 (PSG), a passivation layer (alumina), and a passivation antireflection layer (silicon oxynitride).

[0172] Performance tests were conducted on the back-contact solar cells prepared according to Example 1 above, specifically the cell slices cut from the cutting area 14, and the cell slices cut from the back-contact solar cells without a protective layer in the cutting area 14. The test results are shown in Table 1 below: Table 1 Performance test results of Example 1 and Comparative Example

[0173] Here, EFF is the photoelectric conversion efficiency, which is the percentage of sunlight converted into electrical energy; Voc is the open-circuit voltage, which is the voltage across the solar cell when no load is connected; Isc is the short-circuit current, which is the current flowing when the positive and negative terminals of the cell are directly short-circuited; FF is the fill factor, which measures the efficiency of the solar cell at its maximum power point, that is, the ratio of the actual output power to the theoretical maximum power (Voc multiplied by Isc). A high fill factor means that the cell can convert light energy into electrical energy more effectively and reduce internal losses.

[0174] As can be seen from Table 1, the photoelectric conversion efficiency of the back-contact solar cell in Embodiment 1 of this disclosure, which is cut into cell slices in the cutting region 14, is better than that of the comparative example, and the fill factor is higher than that of the comparative example. This indicates that the protective layer in the cutting region 14 can reduce the thermal damage caused by the thermal cracking laser.

[0175] (2) Example 2: The front side of the N-type silicon substrate 1 is texturized, and the back side is polished. Then, the silicon substrate 1 is oxidized to form a first tunneling layer 21 (silicon dioxide layer) approximately 1.5 nm thick. Next, a first intrinsic polysilicon layer with a thickness of 255 nm is deposited using LPCVD. Boron diffusion is then performed on the first intrinsic polysilicon layer to form a P-type first doped polysilicon layer 3. Some boron atoms diffuse between the first tunneling layer 21 and the silicon substrate 1 to form a diffusion layer 30 for forming a pn junction. Furthermore, the byproducts of boron diffusion form a first byproduct layer 4 (BSG) outside the first doped polysilicon layer 3. The doping concentration of the first doped polysilicon layer 3 is 8 × 10⁻⁶. 19 atoms / cm 3The thickness of the first by-product layer 4 is 28 nm. Subsequently, a first pattern is formed on the first by-product layer 4 using a first laser 10. The first pattern is... Figure 1 The areas shown are the black and gray regions. The first pattern parameters include: a first distance e of 0.5 mm, a fine grating main path width k of 0.6 mm, a fine grating branch path width f of 0.606 mm, a third distance g of 1.06 mm, and an interdigital length h of 0.985 mm. The first laser 10 has a wavelength of 532 nm, a power of 40 W, a frequency of 500 kHz, a velocity of 37500 mm / s, and a spot size of 150 μm.

[0176] Subsequently, a single-sided wet etching process was used to remove the first byproduct layer 4 on the front side of the silicon substrate 1.

[0177] Subsequently, an alkaline solution is used to remove the first byproduct layer 4 and the first carrier collection layer 210 in the second conductive region 12 and the spacer region 13 to expose the silicon substrate 1 and retain the first carrier collection layer 210 in the first conductive region 11.

[0178] The silicon substrate 1 was then cleaned, and a second intrinsic polysilicon layer with a thickness of 255 nm was deposited on both the front and back sides. Phosphorus diffusion was then performed on the second intrinsic polysilicon layer to form an N-type second-doped polysilicon layer 5. The byproducts of phosphorus diffusion formed a second byproduct layer 6 (PSG) outside the second-doped polysilicon layer 5. The doping concentration of the second-doped polysilicon layer 5 was 4 × 10⁻⁶. 20 atoms / cm 3 The thickness of the second by-product layer 6 is 40 nm. Subsequently, a second pattern is formed on the second by-product layer 6 using a second laser 20. The second pattern is... Figure 1 The areas shown in white and gray are the regions where the cutting area 14 is located. The second pattern parameters include: a second distance d of 0.8 mm to form a spacing region 13 with a width of 0.15 mm; a fine grating main path width k of 0.6 mm; a fine grating branch path width f of 0.606 mm; a third distance g of 1.06 mm; and an interdigitated finger length h of 0.985 mm. The second laser 20 has a wavelength of 532 nm, a power of 40 W, a frequency of 500 kHz, a velocity of 37500 mm / s, and a spot size of 150 μm.

[0179] Subsequently, a single-sided wet etching process was used to remove the second byproduct layer 6 on the front side of the silicon substrate 1.

[0180] Subsequently, an alkaline solution is used to remove the second byproduct layer 6 and the second carrier collection layer 220 within the first conductive region 11, the spacer region 13, and the dicing region 14, thereby exposing the silicon substrate 1 within the spacer region 13 and retaining the second carrier collection layer 220 within the second conductive region 12. Simultaneously, an alkaline solution is used to remove the first byproduct layer 4 within the first conductive region 11 and the second byproduct layer 6 within the second conductive region 12.

[0181] The subsequent steps are the same as in Example 1, and will not be repeated here.

[0182] The back-contact solar cell prepared in Example 2 has a protective layer consisting of a passivation antireflection layer (silicon oxynitride), a passivation layer (aluminum oxide), a silicon substrate 1, a first tunneling layer 21, a first doped polycrystalline silicon layer 3, a first byproduct layer 4 (BSG), a passivation layer (aluminum oxide), and a passivation antireflection layer (silicon oxynitride) stacked sequentially from the front to the back of the silicon substrate 1.

[0183] Performance tests were conducted on the back-contact solar cells prepared according to Example 2 above, specifically the cell slices cut from the cutting area 14 and the cell slices cut from the back-contact solar cells without a protective layer in the cutting area 14. The test results are shown in Table 2 below. Table 2 Performance test results of the examples and comparative examples

[0184] As can be seen from Table 2, the fill factor of the battery slices cut from the cutting area 14 of the back contact solar cell of Embodiment 2 of this disclosure is higher than that of the comparative example. The battery slices cut from the back contact solar cell can more effectively convert light energy into electrical energy and reduce internal losses, indicating that the protective layer of the cutting area 14 can reduce the thermal damage caused by the thermal cracking laser.

[0185] (3) Example 3: The front side of the N-type silicon substrate 1 is texturized, and the back side is polished. Then, the silicon substrate 1 is oxidized to form a first tunneling layer 21 (silicon dioxide layer) approximately 1.5 nm thick. Next, a first intrinsic polysilicon layer with a thickness of 255 nm is deposited using LPCVD. Boron diffusion is then performed on the first intrinsic polysilicon layer to form a P-type first doped polysilicon layer 3. Some boron atoms diffuse between the first tunneling layer 21 and the silicon substrate 1 to form a diffusion layer 30 for forming a pn junction. Furthermore, the byproducts of boron diffusion form a first byproduct layer 4 (BSG) outside the first doped polysilicon layer 3. The doping concentration of the first doped polysilicon layer 3 is 8 × 10⁻⁶. 19 atoms / cm 3The thickness of the first by-product layer 4 is 28 nm. Subsequently, a first pattern is formed on the first by-product layer 4 using a first laser 10. The first pattern is... Figure 1 The pattern includes a black area, a gray area, and a cutting area 14. The first pattern parameters include: a first distance e of 0.5 mm, a fine grid main path width k of 0.6 mm, a fine grid branch path width f of 0.606 mm, a third distance g of 1.06 mm, and an interdigitated finger length h of 0.985 mm. The first laser 10 has a wavelength of 532 nm, a power of 40 W, a frequency of 500 kHz, a velocity of 37500 mm / s, and a spot size of 150 μm.

[0186] Subsequently, a single-sided wet etching process was used to remove the first byproduct layer 4 on the front side of the silicon substrate 1.

[0187] Subsequently, an alkaline solution is used to remove the first byproduct layer 4 and the first carrier collection layer 210 in the second conductive region 12, the spacer region 13 and the dicing region 14, so as to expose the silicon substrate 1 and retain the first carrier collection layer 210 in the first conductive region 11.

[0188] The silicon substrate 1 was then cleaned, and a second intrinsic polysilicon layer with a thickness of 255 nm was deposited on both the front and back sides. Phosphorus diffusion was then performed on the second intrinsic polysilicon layer to form an N-type second-doped polysilicon layer 5. The byproducts of phosphorus diffusion formed a second byproduct layer 6 (PSG) outside the second-doped polysilicon layer 5. The doping concentration of the second-doped polysilicon layer 5 was 4 × 10⁻⁶. 20 atoms / cm 3 The thickness of the second by-product layer 6 is 40 nm. Subsequently, a second laser 20 is used to form a second pattern on the second by-product layer 6. The second pattern is the area shown in the white and gray regions. The parameters of the second pattern include: a second distance d of 0.8 mm to form a spacing region 13 with a width of 0.15 mm; a fine gate main path width k of 0.6 mm; a fine gate branch path width f of 0.606 mm; a third distance g of 1.06 mm; and an interdigital length h of 0.985 mm. The laser wavelength of the second laser 20 is 532 nm, the power is 40 W, the frequency is 500 kHz, the velocity is 37500 mm / s, and the spot size is 150 μm.

[0189] Subsequently, a single-sided wet etching process was used to remove the second byproduct layer 6 on the front side of the silicon substrate 1.

[0190] Subsequently, an alkaline solution is used to remove the second byproduct layer 6 and the second carrier collection layer 220 in the first conductive region 11 and the spacer region 13, so as to expose the silicon substrate 1 in the spacer region 13 and retain the second carrier collection layer 220 in the second conductive region 12. At the same time, an alkaline solution is used to remove the first byproduct layer 4 in the first conductive region 11 and the second byproduct layer 6 in the second conductive region 12.

[0191] The subsequent steps are the same as in Example 1, and will not be repeated here.

[0192] The back-contact solar cell prepared in Example 3 has a protective layer consisting of a passivation antireflection layer (silicon oxynitride), a passivation layer (aluminum oxide), a silicon substrate 1, a second tunneling layer 22, a second doped polycrystalline silicon layer 5, a second byproduct layer 6 (PSG), a passivation layer (aluminum oxide), and a passivation antireflection layer (silicon oxynitride) stacked sequentially from the front to the back of the silicon substrate 1.

[0193] Performance tests were conducted on the back-contact solar cells prepared according to Example 3 above, specifically the cell slices cut from the cutting area 14 and the cell slices cut from the back-contact solar cells without a protective layer in the cutting area 14. The test results are shown in Table 3 below. Table 3 Performance test results of the examples and comparative examples

[0194] As can be seen from Table 3, the fill factor of the battery slices cut in the cutting area 14 of the back contact solar cell of Embodiment 3 of this disclosure is higher than that of the comparative example. The battery slices can more effectively convert light energy into electrical energy and reduce internal losses, indicating that the protective layer of the cutting area 14 can reduce the thermal damage caused by the thermal cracking laser.

[0195] The test results of Examples 1-3 are compared below, and the comparison results are shown in Table 4: Table 4 Comparison of performance test results for Examples 1-3

[0196] As shown in Table 4, the back-contact solar cell slices obtained by the preparation method of Example 1, cut in the cutting region 14, exhibit the highest photoelectric conversion efficiency and fill factor, demonstrating the best electrical performance. This indicates that the protective layers, including BSG and PSG, can most effectively improve the electrical performance of the cell slices. Furthermore, the back-contact solar cell slices obtained by the preparation method of Example 2, cut in the cutting region 14, show better results than those obtained by the preparation method of Example 3, indicating that BSG is more effective than PSG in improving the electrical performance of the cell slices.

[0197] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure and not to limit them; although this disclosure has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of this disclosure or equivalent substitutions can be made to some technical features, all of which should be covered within the scope of the technical solutions claimed in this disclosure.

Claims

1. A back-contact solar cell, characterized in that, include: A silicon substrate (1) has at least two cell regions and a dicing region (14) on its back side. Each cell region includes a spacer region (13) and a first conductive region (11) and a second conductive region (12) with opposite polarities. Adjacent first conductive regions (11) and second conductive regions (12) are separated by the spacer region (13). The dicing region (14) is located between adjacent cell regions. A protective layer is provided on the back side of the silicon substrate (1) and located in the dicing area (14).

2. The back-contact solar cell according to claim 1, characterized in that, The protective layer includes a first byproduct layer (4) and / or a second byproduct layer (6). Preferably, the first by-product layer (4) comprises a borosilicate glass layer; and / or the second by-product layer (6) comprises a phosphosilicate glass layer; Preferably, the thickness of the protective layer is in the range of 690um-710um; Preferably, the width of the cutting area (14) is in the range of 0.55mm-0.7mm.

3. The back-contact solar cell according to claim 1, characterized in that, Also includes: A first carrier collection layer (210) having a first conductivity type is disposed at least on the back side of the silicon substrate (1) and located in the first conductivity region (11). The second carrier collection layer (220) has a second conductivity type opposite to the first conductivity type and is disposed at least on the back side of the silicon substrate (1) and located in the second conductivity region (12). Preferably, the first carrier collection layer (210) includes a first tunneling layer (21) and a first doped polysilicon layer (3), the first doped polysilicon layer (3) being disposed on the side of the first tunneling layer (21) away from the silicon substrate (1), and the protective layer including at least one of the first tunneling layer (21) and the first doped polysilicon layer (3); and / or the second carrier collection layer (220) includes a second tunneling layer (22) and a second doped polysilicon layer (5), the second doped polysilicon layer (5) being disposed on the side of the second tunneling layer (22) away from the silicon substrate (1), and the protective layer including at least one of the second tunneling layer (22) and the second doped polysilicon layer (5).

4. The back-contact solar cell according to claim 1, characterized in that, The cutting area (14) is separated from the adjacent first conductive area (11) or second conductive area (12) by the spacing area (13).

5. The back-contact solar cell according to any one of claims 1-4, characterized in that, The back surface of the silicon substrate (1) is textured in the spacer region (13); and / or The back surface of the silicon substrate (1) is polished in the first conductive region (11) and / or the second conductive region (12); and / or The protective layer also includes a passivation layer and / or an antireflection layer.

6. A photovoltaic module, characterized in that, The photovoltaic module includes multiple battery slices cut from the back-contact solar cells as described in any one of claims 1-5 in the cutting area (14), preferably, at least a portion of the edges of the battery slices include the protective layer.

7. A method for fabricating a back-contact solar cell, characterized in that, include: S10. Provide a silicon substrate (1), the back side of which is provided with at least two battery cell regions and a cutting region (14). Each battery cell region includes a spacer region (13) and a first conductive region (11) and a second conductive region (12) with opposite polarities. Adjacent first conductive regions (11) and second conductive regions (12) are separated by the spacer region (13). The cutting region (14) is located between adjacent battery cell regions. and S20. A layer structure is provided on the silicon substrate (1), and a protective layer is provided on the back side of the silicon substrate (1) in the cutting area (14) to form the back contact solar cell.

8. The preparation method according to claim 7, characterized in that, S20 includes: S1. A first carrier collection layer (210) is formed on the surface of the silicon substrate (1). S2. A first byproduct layer (4) is formed on the outer surface of the first carrier collection layer (210). S3. Remove the first carrier collection layer (210) and the first by-product layer (4) from the front side of the silicon substrate (1), the second conductive region (12) and the spacer region (13). S4. Retain at least a portion of the first carrier collection layer (210) and the first by-product layer (4) on the back side of the silicon substrate (1) in the dicing region (14) to form at least a portion of the protective layer; or remove the first carrier collection layer (210) and the first by-product layer (4) on the back side of the silicon substrate (1) in the dicing region (14). Preferably, S20 further includes: S5. A second carrier collection layer (220) is formed on the surface of the silicon substrate (1), wherein the second carrier collection layer (220) has the opposite conductivity type to the first carrier collection layer (210); S6. A second byproduct layer (6) is formed on the outer surface of the second carrier collection layer (220). S7. Remove the second carrier collection layer 220 and the second byproduct layer (6) from the front side of the silicon substrate (1), the first conductive region (11) and the spacer region (13). S8. Retain at least a portion of the second carrier collection layer (220) and the second by-product layer (6) on the back side of the silicon substrate (1) in the dicing region (14) to form at least a portion of the protective layer; or remove the second carrier collection layer (220) and the second by-product layer (6) on the back side of the silicon substrate (1) in the dicing region (14).

9. The preparation method according to claim 8, characterized in that, S3 includes: S31. Using a first laser (10), at least a portion of the thickness of the first byproduct layer (4) of the silicon substrate (1) in the second conductive region (12) and the spacer region (13) is removed to form a first pattern; S32. Remove the first byproduct layer (4) on the front side of the silicon substrate (1). S33. Wet etching is used to remove the first carrier collection layer (210) on the front side of the silicon substrate (1), the second conductive region (12) on the back side, and the first carrier collection layer (210) and the first by-product layer (4) of the spacer region (13). And / or the S7 includes: S71. Using a second laser (20), at least a portion of the thickness of the second byproduct layer (6) of the silicon substrate (1) in the first conductive region (11) and the spacer region (13) is removed to form a second pattern; S72. Remove the second byproduct layer (6) on the front side of the silicon substrate (1). S73. Wet etching is used to remove the second carrier collection layer (220) on the front side of the silicon substrate (1), the second carrier collection layer (220) on the back side of the first conductive region (11) and the second byproduct layer (6) of the spacer region (13).

10. The preparation method according to claim 9, characterized in that, Along the width direction of the cutting area (14), the distance between the irradiated areas on both sides of the cutting area (14) by the first laser (10) is a first distance e, and the distance between the irradiated areas on both sides of the cutting area (14) by the second laser (20) is a second distance d, wherein the second distance d ≥ the first distance e; preferably, the range of the first distance e and / or the second distance d is 0.5 mm to 0.8 mm; and / or The parameters of the first laser (10) include: a laser wavelength range of 355nm~1064nm, a power range of 35W~60W, a frequency range of 400kHz~600kHz, a velocity range of 15000mm / s~40000mm / s, and a spot diameter range of 100µm~200µm; and / or The parameters of the second laser (20) include: laser wavelength range of 355nm~1064nm, power range of 5w~60w, frequency range of 200khz~500khz, speed range of 15000mm / s~40000mm / s, and spot diameter range of 100um~200um.

11. The preparation method according to claim 7, characterized in that, S20 includes: A passivation layer and / or an antireflection layer are formed on the surface of the silicon substrate (1) to form at least a portion of the protective layer in the cut area (14).

12. The preparation method according to any one of claims 7-11, characterized in that, Also includes: Within the cutting area (14), a thermal cracking laser is used to cut the battery cell along the length direction of the cutting area (14) to form at least two battery slices; Preferably, the thermal cracking laser uses a dashed line scanning cutting path, which includes alternating real-running segments and empty-running segments; Preferably, the first length b of the actual walking segment is in the range of b ≥ 20 mm; the second length c of the empty walking segment is in the range of 2 mm ≤ c ≤ 5 mm; Preferably, the parameters of the thermal cracking laser are as follows: the laser wavelength is 1064nm, the pulse width is on the order of nanoseconds, and the spot is a circular spot with a diameter in the range of 0.2mm-0.4mm, or an elliptical spot with the major axis and minor axis dimensions in the range of 0.2mm-0.4mm.

13. The preparation method according to claim 12, characterized in that, Also includes: A grooving laser is used to form a grooving at at least one end of the dashed scanning cutting path; Preferably, the third length 'a' of the slot is in the range of 3mm ≤ a ≤ 7mm; Preferably, the parameters of the slotting laser include: a laser wavelength of 1064nm, a pulse width of 100-400ns, and a circular spot of 30-50um.

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