Display device, method of manufacturing the same, and electronic device including the same

Abstract

A display device, a method of manufacturing the display device, and an electronic device including the display device are provided, the display device including: a base substrate; a transistor structure on the base substrate; a pixel electrode on the base substrate and electrically connected to the transistor structure; a pixel definition layer partially covering the pixel electrode and having an opening superposed with the pixel electrode; a sidewall structure at an outer lower portion of the pixel definition layer and including an outer recess; an emission portion on the pixel definition layer and the pixel electrode; and a counter electrode on the emission portion and contacting the sidewall structure.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0058131, filed on May 2, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Some aspects of embodiments of this disclosure relate to a display device, a method of manufacturing the display device, and an electronic device including the display device. Background Technology

[0003] In display devices such as organic light-emitting diode (OLED) display devices and liquid crystal display (LCD) devices, for example, a display substrate including thin-film transistors (TFTs) and various wirings can be provided, and a display structure including electrodes and an emission layer can be formed on the display substrate.

[0004] For example, pixel electrodes connecting the TFT and the display structure, as well as pixel defining layers that define pixel areas, can be utilized. Recently, various designs for the aforementioned TFT, pixel electrodes, and pixel defining layers have been investigated to achieve more stable high-resolution display devices.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section need not constitute prior art. Summary of the Invention

[0006] Some aspects of embodiments of this disclosure relate to a display device, a method of manufacturing the display device, and an electronic device including the display device. For example, some aspects of embodiments of this disclosure relate to a display device including a pixel electrode and a pixel defining layer, a method of manufacturing the display device, and an electronic device including the display device.

[0007] Some aspects of embodiments of this disclosure include a display device having relatively improved driving reliability and emission characteristics.

[0008] Some aspects of embodiments of this disclosure include a method of manufacturing a display device having relatively improved driving reliability and emission characteristics.

[0009] Some aspects of embodiments of this disclosure include electronic devices comprising a display device having relatively improved driving reliability and emission characteristics.

[0010] The display device may include: a substrate; a transistor structure on the substrate; a pixel electrode electrically connected to the transistor structure on the substrate; a pixel defining layer partially covering the pixel electrode and having an opening superimposed on the pixel electrode; a sidewall structure formed at the lower outer portion of the pixel defining layer and including an outer groove; an emitting portion formed on the pixel defining layer and the pixel electrode; and a counter electrode formed on the emitting portion and contacting the sidewall structure.

[0011] According to some embodiments, the sidewall structure may include a first conductive layer, a second conductive pattern, and a third conductive pattern sequentially stacked on a substrate. The outer recess may be defined by the upper surface of the first conductive layer, the side surfaces of the second conductive pattern, and the lower surface of the third conductive pattern.

[0012] According to some embodiments, the counter electrode can contact the side surface of the third conductive pattern.

[0013] According to some embodiments, the emitting portion may cover the outer surface of the pixel defining layer and not contact the second conductive pattern of the sidewall structure.

[0014] According to some embodiments, the emitting portion may not contact the lower surface of the third conductive pattern.

[0015] According to some embodiments, the counter electrode may not contact the first conductive layer.

[0016] According to some embodiments, at least one of the first conductive layer, the second conductive pattern, and the third conductive pattern may be located on the same layer or at the same level as the pixel electrode.

[0017] According to some embodiments, the second conductive pattern may include a metal different from the metal in each of the first conductive layer and the third conductive pattern.

[0018] According to some embodiments, the first conductive layer and the third conductive pattern may include titanium (Ti), and the second conductive pattern may include aluminum (Al).

[0019] According to some embodiments, the display device may include a plurality of pixels. The first conductive layer of the sidewall structure may be a common interconnect electrode formed by adjacent pixels across the plurality of pixels.

[0020] According to some embodiments, the plurality of pixels may include a first pixel, a second pixel, and a third pixel. Pixel electrodes may include a first pixel electrode, a second pixel electrode, and a third pixel electrode corresponding to the first pixel, the second pixel, and the third pixel, respectively. Counter electrodes may include a first pair of electrodes, a second pair of electrodes, and a third pair of electrodes respectively on the first pixel electrode, the second pixel electrode, and the third pixel electrode. The first pair of electrodes, the second pair of electrodes, and the third pair of electrodes may be electrically connected to each other through a first conductive layer of the sidewall structure.

[0021] According to some embodiments, the launching portion can extend continuously within the opening.

[0022] According to some embodiments, a recess may be formed between the outer portion of the upper surface of the pixel electrode and the pixel defining layer.

[0023] According to some embodiments, the emitting portion may include a hole injection layer, a hole transport layer, an emitting layer, and an electron transport layer sequentially stacked on a pixel electrode. The hole injection layer may be discontinuous due to recesses.

[0024] According to some embodiments, the display device may also include a sacrificial pattern formed in the recess.

[0025] A method for manufacturing a display device may include the following steps: forming a pixel electrode and a sidewall structure stack on a substrate; forming a pixel defining layer on the substrate that covers the pixel electrode and partially covers the sidewall structure stack; forming a sidewall structure by partially etching the sidewall structure stack exposed from the pixel defining layer; forming an emitting portion on the pixel defining layer and the pixel electrode; and forming a counter electrode that contacts the sidewall structure on the emitting portion.

[0026] According to some embodiments, the sidewall structure stack may include a first conductive layer, a second conductive layer, and a third conductive layer sequentially formed from a substrate. The steps of forming the sidewall structure may include: forming a third conductive pattern by removing a portion of the third conductive layer exposed from the pixel-defining layer via dry etching; and forming a second conductive pattern by selectively partially removing the second conductive layer via wet etching, thereby forming an outer groove.

[0027] According to some embodiments, the emitting portion and the counter electrode may be formed as discontinuous due to the external groove.

[0028] An electronic device may include: a display device; a memory; and a processor that controls the operation of the display device by executing data included in the memory, wherein the display device includes: a substrate; a transistor structure on the substrate; a pixel electrode electrically connected to the transistor structure on the substrate; a pixel defining layer that partially covers the pixel electrode and has an opening overlapping the pixel electrode; a sidewall structure at the lower outer portion of the pixel defining layer and including an outer groove; an emitting portion formed on the pixel defining layer and the pixel electrode; and a counter electrode formed on the emitting portion and contacting the sidewall structure.

[0029] According to some embodiments, the electronic device may be virtual reality glasses or augmented reality glasses, a smartphone, a tablet PC, a laptop computer, a television, a desktop monitor, smart glasses, a head-mounted display, a smartwatch, or an in-vehicle display.

[0030] In a display device according to some embodiments of the present invention, a sidewall structure with an external groove can be formed on one side of the pixel defining layer. The external groove of the sidewall structure allows for patterning of the emission region for each pixel, while maintaining a continuous emission region on the pixel electrode. Furthermore, the sidewall structure allows for maintaining cathode connectivity across multiple pixels.

[0031] At least a portion of the sidewall structure is at the same level as the pixel electrode, enabling pixel-by-pixel patterning of the emission region and cathode connectivity without introducing additional conductive structures. Attached Figure Description

[0032] Figure 1 This is a schematic plan view illustrating a display device according to some embodiments.

[0033] Figure 2 This is a pixel equivalent schematic diagram of a display device according to some embodiments.

[0034] Figure 3 This is a schematic cross-sectional view showing a display device according to some embodiments.

[0035] Figures 4 to 6 This is a schematic, partially enlarged cross-sectional view illustrating the stacked arrangement of the emitter portion, counter electrode, and encapsulation layer around the sidewall structure according to some embodiments.

[0036] Figures 7 to 11 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to some embodiments.

[0037] Figure 12 and Figure 13 These are schematic plan views and cross-sectional views illustrating a display device according to some embodiments.

[0038] Figures 14 to 16 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to some embodiments.

[0039] Figure 17 This is a schematic cross-sectional view showing a display device according to some embodiments.

[0040] Figure 18 This is a schematic, partially enlarged cross-sectional view illustrating the shape of the emitting portion separated by an inner groove according to some embodiments.

[0041] Figures 19 to 21 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to some embodiments.

[0042] Figure 22 This is an exploded perspective view of an electronic device according to some embodiments.

[0043] Figure 23 This is a block diagram of an electronic device according to some embodiments.

[0044] Figure 24 This is a schematic diagram of an electronic device according to some embodiments. Detailed Implementation

[0045] In the following description, embodiments of the invention will be presented in more detail with reference to the accompanying drawings. In doing so, the same reference numerals will be used for the same components in the drawings, and for the sake of brevity, some redundant descriptions of the same or similar components may be omitted. The embodiments disclosed in the drawings are and should be understood to include all modifications, equivalents, or substitutions within the spirit and scope of the invention.

[0046] As used herein, the terms “on,” “connect,” “join,” and “combination,” etc., include direct setting / direct connection / direct engagement as well as the insertion of other components.

[0047] The terms “first,” “second,” “below,” “on the bottom,” “on top,” “above,” and “on the top” are used as relative concepts to distinguish different constructions or positions and are not intended to specify absolute positions, orders, or anything else.

[0048] Figure 1 This is a schematic plan view illustrating a display device according to some embodiments.

[0049] exist Figure 1 In the middle, the first direction and the second direction can refer to the substrate 100 (see...). Figure 3 The two directions on the upper surface of the () are parallel and intersect each other. For example, the first direction and the second direction can be orthogonal to each other.

[0050] For example, the first direction may correspond to the X direction of the display device (e.g., the row direction or the length direction), and the second direction may correspond to the Y direction of the display device (the column direction or the width direction).

[0051] The third direction may be perpendicular to the plane defined by the first and second directions. The third direction may correspond to the Z-direction (thickness direction) of the display device, or it may correspond to a direction perpendicular to the plane of the display surface of the display device.

[0052] In the accompanying figures below, the above definition of direction can be applied equivalently.

[0053] Reference Figure 1The display device may include a display area DA and a non-display area NDA. The display area DA provides a surface on which an image of the display device is displayed and on which user touch / commands are input. The non-display area NDA may correspond to the bezel area or peripheral area of ​​the display device. According to some embodiments, the display area DA may be surrounded (or substantially surrounded) by the non-display area NDA. For example, the non-display area NDA may be on the periphery of the display area DA or outside the coverage area of ​​the display area DA.

[0054] The substrate 100 can also be divided into a display area DA and a non-display area NDA. Multiple pixels PX11 to PXnm can be arranged in the display area DA of the substrate 100, where n and m are natural numbers greater than 1.

[0055] According to some embodiments, pixel circuitry comprising scan lines (or gate lines) SL1 to SLn forming the first to nth rows of the display device and data lines DL1 to DLm forming the first to mth columns of the display device can be arranged on a substrate 100. Each of pixels PX11 to PXnm can be connected to n rows of scan lines corresponding to the plurality of scan lines SL1 to SLn and m rows of data lines corresponding to the plurality of data lines DL1 to DLm.

[0056] Each of pixels PX11 to PXnm may also include pixel circuitry containing transistors and light-emitting elements, as described later. According to some embodiments, the pixel circuitry may also include wiring such as power lines and ground lines.

[0057] exist Figure 1 In the diagram, data lines DL1 to DLm are shown extending in a second direction, and scan lines SL1 to SLn are shown extending in a first direction, but are not necessarily limited to this. Additionally, in Figure 1 In the illustration, for ease of explanation, the shape of each pixel PX11 to PXnm is shown as a circle, but is not limited to this.

[0058] In the non-display area NDA, which corresponds to the peripheral area relative to the display area DA, peripheral circuitry PC can be arranged. For example, the peripheral circuitry PC may include gate driving circuitry. The gate driving circuitry can be integrated into the display device using oxide semiconductor gate (OSG), amorphous silicon gate (ASG), or polysilicon gate (PSG) driving circuitry processes.

[0059] The peripheral circuit PC may also include data drivers, gate drivers, emitter drivers, power supply voltage generators, and timing controllers.

[0060] The display device may also include a printed circuit board 200. Pixel circuit pads (also referred to as solder pads or solder joints) 190 may be clustered on one side of the non-display area NDA. The printed circuit board 200 can be electrically connected to the pixel circuitry via the pads 190. For example, the printed circuit board 200 can be electrically connected to the pads 190 via a thermoforming process using a conductive insert structure such as an anisotropic conductive film (ACF).

[0061] Integrated circuits (ICs), such as data-driven circuits, can be located on printed circuit board 200. According to some embodiments, integrated circuit (IC) chips can be mounted on printed circuit board 200 in the form of chip-on-film (COF).

[0062] Figure 2 This is a pixel-equivalent schematic diagram of a display device according to some embodiments. Although Figure 2 Various components in a pixel according to some embodiments are shown, but the embodiments of this disclosure are not limited thereto, and according to various embodiments, a pixel may include additional components or fewer components without departing from the spirit and scope of the embodiments of this disclosure.

[0063] Reference Figure 2 Each pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor CST.

[0064] The first transistor T1 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may be connected to a storage capacitor CST. The first terminal may be connected to a second transistor T2. The second terminal may be connected to a sixth transistor T6. The first transistor T1 may generate a drive current ID based on the voltage difference between the gate terminal and the first terminal. For example, the first transistor T1 may be referred to as a drive transistor.

[0065] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor T2 may receive a first gate signal Gs1. The second transistor T2 may be turned on or off in response to the first gate signal Gs1. The first terminal of the second transistor T2 may receive a data voltage DATA. The second transistor T2 may provide the data voltage DATA to the first terminal of the first transistor T1 in response to the first gate signal Gs1. For example, the second transistor T2 may be referred to as a switching transistor.

[0066] The third transistor T3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a first gate signal Gs1. The first terminal may be connected to the gate terminal of the first transistor T1. The second terminal may be connected to the second terminal of the first transistor T1. The third transistor T3 may compensate for the threshold voltage of the first transistor T1. For example, the third transistor T3 may be configured as a compensation transistor.

[0067] The fourth transistor T4 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a second gate signal Gs2. The first terminal may be connected to the gate terminal of the first transistor T1. The second terminal may receive an initialization voltage VINT. The fourth transistor T4 can initialize the gate terminal of the first transistor T1.

[0068] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive the transmit control signal ELC. The first terminal may receive the high supply voltage ELVDD. The second terminal may be connected to the first terminal of the first transistor T1.

[0069] The sixth transistor T6 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive an emission control signal ELC. The first terminal may be connected to the second terminal of the first transistor T1. The second terminal may be connected to an organic light-emitting diode (OLED). The sixth transistor T6 may transmit a drive current ID to the OLED in response to the emission control signal ELC.

[0070] The seventh transistor T7 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may receive a third gate signal Gs3. The first terminal may be connected to an organic light-emitting diode (OLED). The second terminal may receive an initialization voltage VINT. The seventh transistor T7 can initialize the OLED. The storage capacitor CST may include a first terminal and a second terminal. The first terminal may receive a high supply voltage ELVDD. The second terminal may be connected to the gate terminal of the first transistor T1.

[0071] An organic light-emitting diode (OLED) may include a first terminal and a second terminal. The first terminal may be connected to the second terminal of a sixth transistor T6. The second terminal may receive a low supply voltage ELVSS. The OLED may emit light based on a drive current ID.

[0072] exist Figure 2 The diagram shows a 7T1C structure where each pixel PX has seven thin-film transistors and a storage capacitor CST, but the pixel structure of the display device disclosed herein is not limited to this.

[0073] For example, each pixel PX may include two or more transistors and may have a structure such as 2T1C, 5T1C, 6T1C, 5T2C, 6T2C, etc.

[0074] Figure 3 This is a cross-sectional view showing aspects of a display device according to some embodiments.

[0075] Reference Figure 3 The display device may include a substrate 100, a pixel circuit including a transistor structure TR, and a light-emitting element.

[0076] The substrate 100 can be configured as a backplane substrate for the display device. A glass substrate, ceramic substrate, or plastic substrate can be used as the substrate 100. According to some embodiments, the substrate 100 may comprise a polymer material having transparency and flexibility (e.g., a set or predetermined flexibility). In this case, the substrate 100 can be used in a transparent flexible display device.

[0077] For example, the substrate 100 may include polymeric materials such as polyimide, polysiloxane, epoxy resin, acrylic resin, or polyester. According to some embodiments, the substrate 100 may include polyimide.

[0078] According to some embodiments, the substrate 100 may be a glass substrate. According to some embodiments, the substrate 100 may be a silicon substrate manufactured from a silicon wafer.

[0079] A buffer layer 110 can be formed on the upper surface of the substrate 100. The buffer layer 110 can block moisture that permeates through the substrate 100 and can also prevent the diffusion of impurities between the substrate 100 and the structures formed on the substrate 100. The buffer layer 110 can be integrally formed across the display area DA and the non-display area NDA of the substrate 100 and can completely cover the upper surface of the substrate 100.

[0080] The buffer layer 110 may include inorganic insulating materials (such as silicon oxide, silicon nitride, or silicon oxynitride). These materials may be used alone or in combination of two or more.

[0081] According to some embodiments, the buffer layer 110 may have a stacked structure comprising a silicon oxide film and a silicon nitride film. The buffer layer 110 may be formed by a deposition process such as chemical vapor deposition (CVD), sputtering, or atomic layer deposition (ALD) to include the aforementioned inorganic insulating material.

[0082] According to some embodiments, the buffer layer 110 may include an organic layer and may have a multilayer structure of organic and inorganic layers.

[0083] Pixel circuitry may include, as referenced Figure 1 The description includes the wiring of scan lines and data lines, and the transistor structure TR that interacts electrically with the wiring. The transistor structure TR can be electrically connected to a light-emitting element.

[0084] The transistor structure TR may include an active layer ACT, a gate insulating layer 120, and a gate electrode GE. The transistor structure TR may also include contact electrodes CNT1 and CNT2.

[0085] The active layer ACT is located on the buffer layer 110 and can be patterned, for example, by a photolithography etching process, to have a repeating / regular arrangement for each pixel. The active layer ACT may include silicon compounds (such as polycrystalline silicon or amorphous silicon). Some regions of the active layer ACT may be doped with p-type or n-type dopant and may include source regions, drain regions, and channel regions.

[0086] The active layer ACT may also include oxide semiconductors such as indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or ITZO.

[0087] A gate insulating layer 120 is formed on top of the active layer ACT, and the gate electrode GE can be stacked on the gate insulating layer 120. For multiple transistor structures TR or pixels of different colors, the gate insulating layer 120 can be included continuously and in a common manner.

[0088] Optionally, the gate insulating layer 120 may partially cover each active layer ACT and may be formed in each of the transistor structures TR in an independent pattern.

[0089] The gate electrode GE can be stacked with the channel region of the active layer ACT in a third-order orientation. Scan signals from the scan lines can be transmitted through the gate electrode GE.

[0090] The gate insulating layer 120 can be formed by the above deposition process to include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride or metal oxide.

[0091] According to some embodiments, p-type or n-type dopant can be implanted into the active layer ACT using an ion implantation process that uses a gate electrode GE as an ion implantation mask. Therefore, a first contact region CR1 and a second contact region CR2 can be formed on one side and the other side of the active layer ACT, respectively. The first contact region CR1 and the second contact region CR2 can correspond to the source region and the drain region, respectively.

[0092] The portion of the active layer ACT that overlaps with the gate electrode GE in the vertical direction (the third direction shown above) between the first contact region CR1 and the second contact region CR2 can be defined as the channel region.

[0093] According to some embodiments, the gate insulating layer 120 can be formed into a pattern covering the channel region by an etching process using the gate electrode GE as an etching mask. If the active layer ACT comprises an oxide semiconductor, hydrogen (H) contained in the interlayer insulating layer 130 can diffuse or migrate into the active layer ACT during the formation of the interlayer insulating layer 130. Therefore, the carrier concentration can be increased by hydrogen, and contact regions CR1, CR2 can be formed on the side of the active layer ACT.

[0094] On the active layer ACT, an interlayer insulating layer 130 covering the gate insulating layer 120 and the gate electrode GE can be formed. The interlayer insulating layer 130 can be formed by the above-described deposition process to include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The interlayer insulating layer 130 can be formed as a single-layer structure or a multilayer structure including different materials.

[0095] Contact electrodes CNT1 and CNT2 that are in contact with or electrically connected to the active layer ACT can be formed on the interlayer insulating layer 130.

[0096] The contact electrodes may include a first contact electrode CNT1 that is in contact with or electrically connected to a first contact region CR1 of the active layer ACT, and a second contact electrode CNT2 that is in contact with or electrically connected to a second contact region CR2 of the active layer ACT. According to some embodiments, the first contact electrode CNT1 and the second contact electrode CNT2 may be respectively configured as a source electrode and a drain electrode.

[0097] According to some embodiments, the interlayer insulating layer 130 may be partially etched to form contact holes. For example, the contact holes may be formed to expose a first contact region CR1 and a second contact region CR2, respectively. The contact holes may also penetrate the gate insulating layer 120.

[0098] A metal layer filling the contact hole can be formed on the interlayer insulating layer 130, and then the metal layer can be partially etched to form a first contact electrode CNT1 and a second contact electrode CNT2. For example, data signals can be transmitted from the data line through the first contact electrode CNT1.

[0099] The gate electrode GE and contact electrodes CNT1 and CNT2 may comprise metals such as Ag, Mg, Al, W, Cu, Ni, Cr, Mo, Ti, Pt, Ta, Nd, Sc, or their alloys or nitrides. The gate electrode GE and contact electrodes CNT1 and CNT2 may be formed via a deposition process such as sputtering.

[0100] The gate electrode GE and the contact electrodes CNT1 and CNT2 can be formed as a multilayer structure (e.g., Ti layer, Al layer and Ti layer).

[0101] Figure 3 The transistor structure TR shown may include a pixel driving transistor connected to the pixel electrode PE. Multiple transistor structures TR may be formed to be included in each pixel PX to form a thin-film transistor (TFT) array.

[0102] A first via insulating layer VIA1 covering contact electrodes CNT1 and CNT2 can be formed on the interlayer insulating layer 130. A second via insulating layer VIA2 can be formed on top of the first via insulating layer VIA1. The first via insulating layer VIA1 and the second via insulating layer VIA2 can be configured as planarization layers for a thin-film transistor (TFT) array.

[0103] The via electrode VE can penetrate the first via insulating layer VIA1 and can be in contact with or electrically connected to the upper surface of the contact electrode (e.g., the second contact electrode CNT2).

[0104] For example, the first via insulating layer VIA1 can be partially etched to form a first via that exposes the upper surface of the contact electrode (e.g., the second contact electrode CNT2). The first via can be filled, and the via electrode layer comprising the aforementioned metal or alloy can be formed by a deposition process such as sputtering.

[0105] The via electrode layer formed on the upper surface of the first via insulating layer VIA1 can be partially etched to form the via electrode VE. Then, a second via insulating layer VIA2 covering the via electrode VE can be formed on the first via insulating layer VIA1.

[0106] The via insulating layers VIA1 and VIA2 can be formed from organic insulating layers. For example, the via insulating layers VIA1 and VIA2 can include organic polymer materials (such as polyimide, epoxy resin, acrylic resin, polyester, siloxane resin, and benzocyclobutene (BCB)). For example, the via insulating layers VIA1 and VIA2 can be formed by a coating process such as spin coating.

[0107] According to some embodiments, the first via insulating layer VIA1 or the second via insulating layer VIA2 can be formed from an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. For example, the first via insulating layer VIA1 or the second via insulating layer VIA2 can be formed by a deposition process such as CVD.

[0108] The pixel electrode PE, which is electrically connected to the transistor structure TR via the via electrode VE and the second contact electrode CNT2, can be formed on the second via insulating layer VIA2.

[0109] For example, the second via insulating layer VIA2 can be partially etched to form a second via exposing the upper surface of the via electrode VE. A pixel electrode layer filling the second via can be formed on the upper surface of the second via insulating layer VIA2 by a deposition process such as sputtering. Then, a portion of the pixel electrode layer formed on the upper surface of the second via insulating layer VIA2 can be partially etched to form the pixel electrode PE.

[0110] although Figure 3 A single-layer via insulating layer and a single-layer via electrode are shown, but the structure of the display device disclosed herein is not limited thereto. For example, it may include two, three, four or more layers of via insulating layer / via electrode.

[0111] Each of the pixel electrodes PE can be set as the anode of the light-emitting element of the corresponding pixel.

[0112] According to some embodiments, the pixel electrode PE can be configured as a transmission electrode. The pixel electrode PE may include a transparent conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), etc.).

[0113] According to some embodiments, the pixel electrode PE can be configured as a transmissive electrode or a reflective electrode. The pixel electrode PE may include a metal selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, Zn, or an alloy of two or more of these metals.

[0114] The pixel electrode PE can have a single-layer structure or a multi-layer structure. For example, the pixel electrode PE can have a three-layer structure of ITO layer / Ag layer / ITO layer or ITO layer / Al layer / ITO layer.

[0115] The pixel defining layer (PDL) can be formed on the second via insulating layer (VIA2) and around the pixel electrode (PE). For example, the PDL can cover the periphery of the pixel electrode (PE). The upper surface of the pixel electrode (PE) not covered by the PDL can be configured as a pixel region or an emission region.

[0116] Pixel defining layer (PDL) may include an opening (OP) that overlaps with or exposes the upper surface of pixel electrode PE that is not covered by the PDL (see [link to PDL]). Figure 11 The inner surface (sidewall of the opening OP) of the pixel-defining layer PDL can be tilted relative to a third direction (thickness direction) or relative to the upper surface of the pixel-defining layer PDL.

[0117] The outer surface of the pixel-defining layer (PDL) may have a smaller tilt angle relative to a third direction than the tilt angle of the inner surface. According to some embodiments, the outer surface of the PDL may be parallel to or substantially parallel to the third direction. For example, the tilt angle of the outer surface of the PDL relative to the third direction may be -10° to 10°, -5° to 5°, or 0° (zero) or approximately 0°.

[0118] The pixel defining layer (PDL) may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The PDL may have a single-layer structure comprising any of the aforementioned inorganic insulating materials, or a multilayer structure comprising two or more of the aforementioned inorganic insulating materials.

[0119] According to some embodiments of this disclosure, a sidewall structure SW can be formed at the lower outer portion of the pixel defining layer PDL. The sidewall structure SW can be inserted into the lower outer portion of the pixel defining layer PDL and can contact the lower outer portion of the pixel defining layer PDL.

[0120] The sidewall structure SW may include a conductive material. The sidewall structure SW may include a first conductive layer CL1, a second conductive pattern CLP2, and a third conductive pattern CLP3 sequentially stacked from the upper surface of the substrate 100 or a via insulating layer (e.g., a second via insulating layer VIA2). The second conductive pattern CLP2 may have a shape recessed into the interior of the pixel defining layer PDL.

[0121] The second conductive pattern CLP2 and the first conductive layer CL1 may comprise different metals. The second conductive pattern CLP2 and the third conductive pattern CLP3 may comprise different metals.

[0122] According to some embodiments, the second conductive pattern CLP2 may include a metal having an etch selectivity ratio relative to the first conductive layer CL1 and the third conductive pattern CLP3 for a wet etching process. According to some embodiments, the second conductive pattern CLP2 may include aluminum (Al). According to some embodiments, the first conductive layer CL1 and the third conductive pattern CLP3 may include titanium (Ti).

[0123] The emitting portion (EL) can be formed on the pixel defining layer (PDL) and the pixel electrode (PE). The emitting portion (EL) may include an emitting layer (EML) (see...). Figure 18 The emission layer (EML) comprises organic light-emitting materials that are independently patterned for each of the red, green, and blue pixel regions to produce a different color of light for each pixel.

[0124] For example, the emitter layer EML may include a fluorescent host and / or a host for a phosphorescent element, and may also include a fluorescent dopant, a phosphorescent dopant, and / or a thermally activated delayed fluorescence (TADF) dopant.

[0125] According to some embodiments, the emitting portion EL may include multiple emitting layers corresponding to multiple different colors of light or the same color of light, and may include a stacked body with a series structure.

[0126] The transmitting section (EL) may also include a hole transport layer (HTL) and an electron transport layer (ETL) (see...) Figure 18 According to some embodiments, the hole transport layer (HTL), the emitter layer (EML), and the electron transport layer (ETL) can be sequentially stacked from the upper surface of the pixel electrode (PE).

[0127] For example, the hole transport layer (HTL) can contain hole transport materials such as m-MTDATA (4,4',4''-[tris(3-methylphenyl)phenylamino]triphenylamine), TDATA (4,4',4''-tris(N,N-diphenylamino)triphenylamine), 2-TNATA (4,4',4''-tris[N-(2-naphthyl)-N-phenylamino]triphenylamine), NPB (N,N'-di(naphthyl-1-yl)-N,N'-diphenyl-benzidine), TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl[1,1'-biphenyl]-4,4'-diamine), TCTA (4,4',4''-tris(N-carbazolyl)triphenylamine), and PEDOT / PSS (poly(3,4-ethylenedioxythiophene) / poly(4-styrenesulfonate)).

[0128] For example, the electron transport layer (ETL) can include electron transport materials such as anthracene compounds, Alq3 (tris(8-hydroxyquinoline)aluminum), TPBi (1,3,5-tris(1-phenyl-1H-benzis[d]imidazol-2-yl)benzene), BCP (2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline), Bphen (4,7-diphenyl-1,10-phenanthroline), TAZ (3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole), and NTAZ (4-(naphthyl-1-yl)-3,5-diphenyl-4H-1,2,4-triazole). t Bu-PBD (2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole) and BAlq (bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum), etc.

[0129] According to some embodiments, a hole injection layer HIL can also be positioned between the pixel electrode PE and the hole transport layer HTL (see Figure 18 An electron injection layer can also be positioned between the counter electrode (CE) and the electron transport layer (ETL).

[0130] For example, the emitting element (EL) can be formed by processes such as vacuum deposition, spin coating, inkjet printing, laser printing, casting, and laser thermal transfer.

[0131] According to some embodiments, the emitting portion EL can be continuously formed along the outer surface, upper surface, and inner surface of the pixel defining layer PDL, as well as the upper surface of the pixel electrode PE that is not covered by the pixel defining layer PDL. The emitting portion EL is blocked by the sidewall structure SW, and the emitting portion EL can be selectively patterned for each pixel PX accordingly.

[0132] The counter electrode (CE) can be formed on the emitting portion (EL). The counter electrode (CE) can be configured as an electron injection electrode or a cathode. The counter electrode (CE) can include metals, alloys, or conductive compounds with low work function.

[0133] For example, the counter electrode CE may include a metal layer such as lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), and silver-ytterbium (Ag-Yb). The counter electrode CE may also include a transparent conductive oxide layer (such as ITO or IZO).

[0134] According to some embodiments, the counter electrode CE may have a multilayer structure including a metal layer (e.g., a Mg-Ag layer) and a transparent conductive oxide layer (e.g., an IZO layer).

[0135] The counter electrode (CE) can be configured as a transmission electrode, a semi-transmission electrode, or a reflection electrode. The counter electrode (CE) can have a single-layer structure or a multi-layer structure.

[0136] The counter electrode CE can completely cover the emitting portion EL and can be discontinuous on the sidewall structure SW. According to some embodiments, the end of the counter electrode CE can contact the third conductive pattern CLP3 and may not contact the first conductive layer CL1.

[0137] The encapsulation layer TFE can be formed on the counter electrode CE. The encapsulation layer TFE can be located on the pixel defining layer PDL and the light-emitting element to protect the light-emitting element from moisture or oxygen.

[0138] The encapsulation layer TFE may include an inorganic film, which may include silicon nitride (SiN). x ), silicon dioxide (SiO) x Indium tin oxide, indium zinc oxide, or any combination thereof.

[0139] The encapsulation layer TFE may include an organic film, including polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), epoxy resin (e.g., aliphatic glycidyl ether (AGE), etc.) or combinations thereof.

[0140] The encapsulation layer TFE can be formed as a single-layer structure or a multi-layer structure. According to some embodiments, the encapsulation layer TFE can have a sequentially stacked structure of a first inorganic layer, an organic layer, and a second inorganic layer.

[0141] According to some embodiments, the encapsulation layer TFE can be patterned independently for each pixel using the sidewall structure SW. According to some embodiments, the encapsulation layer TFE can contact the side of the second conductive pattern CLP2 of the sidewall structure SW, but can not contact the first conductive layer CL1.

[0142] According to some embodiments, a color control layer superimposed on the emitting portion (EL) may be located on the encapsulation layer (TFE). The color control layer may include a color conversion layer comprising quantum dots and / or color filters.

[0143] According to some embodiments, a sensor layer, such as a touch sensor layer, and / or an optical functional layer, such as a polarizer, an anti-reflective layer, or an antistatic layer, may be located on the encapsulation layer TFE.

[0144] According to the above embodiment, the emitting portion EL of each pixel can be separated by a sidewall structure SW formed on the lower outer part of the pixel defining layer PDL. Therefore, lateral leakage current between adjacent pixels can be blocked or reduced.

[0145] Furthermore, the emission layer (EML) can be formed continuously (or substantially continuously) on the pixel electrode (PE). This can prevent or reduce the occurrence of shadow areas caused by the absence of luminescent material in the emission or pixel regions.

[0146] At least a portion of the sidewall structure SW is located on the same layer or at the same level as the pixel electrode PE, and the sidewall structure SW can be spaced apart from the pixel electrode PE by the pixel defining layer PDL. The sidewall structure SW can contact the end of the counter electrode CE. Therefore, the sidewall structure SW can maintain electrical connection with the transistor structure TR without adding a separate via electrode.

[0147] As described above, the sidewall structure SW may include conductive material. Therefore, even if the counter electrode CE is discontinuous due to the sidewall structure SW, the counter electrode CE can still be used as a common electrode for multiple pixels through the first conductive layer CL1.

[0148] Figures 4 to 6This is a schematic, partially enlarged cross-sectional view illustrating the stacking of the emitter portion, counter electrode, and encapsulation layer around the sidewall structure according to some embodiments. For example, Figures 4 to 6 yes Figure 3 A partially enlarged sectional view of the area indicated by the dashed circle.

[0149] Reference Figure 4 The sidewall structure SW may include an outer groove OG. According to some embodiments, the outer groove OG may be defined by the upper surface of the first conductive layer CL1, the side surface of the second conductive pattern CLP2, and the lower surface of the third conductive pattern CLP3.

[0150] The emitting portion EL may not extend into the interior of the outer recess OG. According to some embodiments, the emitting portion EL may extend along the outer surface of the pixel defining layer PDL and may extend across the outer surface of the third conductive pattern CLP3. The emitting portion EL may contact the outer surface of the third conductive pattern CLP3 but may not contact the lower surface of the third conductive pattern CLP3. According to some embodiments, the emitting portion EL may contact a portion of the outer surface of the third conductive pattern CLP3.

[0151] Therefore, the emitting portion EL may be discontinuous due to the lower surface of the third conductive pattern CLP3 and may not contact the second conductive pattern CLP2.

[0152] The counter electrode CE can cover the surface of the emitting portion EL and can contact the outer surface of the third conductive pattern CLP3. According to some embodiments, the counter electrode CE can contact the remaining portion of the outer surface of the third conductive pattern CLP that is not covered by the emitting portion EL.

[0153] Therefore, the counter electrode CE can be fully electrically connected to the sidewall structure SW through the outer surface of the third conductive pattern CLP3.

[0154] The encapsulation layer TFE covers the counter electrode CE and can contact the sidewall of the second conductive pattern CLP2 in the outer recess OG. According to some embodiments, the encapsulation layer TFE may not contact the upper surface of the first conductive layer CL1.

[0155] Reference Figure 5 The end of the counter electrode CE can partially enter the outer groove OG. The end of the counter electrode CE can contact the lower surface of the third conductive pattern CLP3. Therefore, the contact area between the counter electrode CE and the sidewall structure SW can be increased, thereby reducing the contact resistance.

[0156] Reference Figure 6The end of the counter electrode CE can also contact the sidewall of the second conductive pattern CLP2. In this case, the counter electrode CE contacts the outer surface of the third conductive pattern CLP3, the lower surface of the third conductive pattern CLP3, and the side surface of the second conductive pattern CLP2 together, which can further reduce the contact resistance.

[0157] Figures 7 to 11 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to some embodiments. For ease of explanation, in... Figures 7 to 11 Detailed illustrations of the structure between the pixel electrode PE and the substrate 100 are omitted.

[0158] Reference Figure 7 , as reference Figure 3 As described, a pixel circuit including a transistor structure TR can be formed on the substrate 100. For example, a sidewall structure stack SWS and a pixel electrode PE electrically connected to the pixel circuit can be formed on a via insulating layer (e.g., a second via insulating layer VIA2).

[0159] According to some embodiments, the pixel electrode PE may include a first transparent conductive oxide layer TL1, a metal layer ML, and a second transparent conductive oxide layer TL2. The first transparent conductive oxide layer TL1, the metal layer ML, and the second transparent conductive oxide layer TL2 can be sequentially formed on a via insulating layer by a deposition process such as sputtering, and then the second transparent conductive oxide layer TL2, the metal layer ML, and the first transparent conductive oxide layer TL1 can be partially etched to form the pixel electrode PE.

[0160] According to some embodiments, the first transparent conductive oxide layer TL1, the metal layer ML, and the second transparent conductive oxide layer TL2 can be formed to include ITO, Ag, and ITO, respectively.

[0161] Then, a first conductive layer CL1, a second conductive layer CL2, and a third conductive layer CL3 covering the pixel electrode PE on the via insulating layer can be sequentially formed using a deposition process such as sputtering. The portions of the third conductive layer CL3, the second conductive layer CL2, and the first conductive layer CL1 covering the pixel electrode PE can be etched to form a sidewall structure stack SWS.

[0162] According to some embodiments, the first conductive layer CL1, the second conductive layer CL2, and the third conductive layer CL3 can be formed to include Ti, Al, and Ti, respectively.

[0163] According to some embodiments, pixel electrodes (PEs) can be formed after the sidewall structure stack (SWS) is formed.

[0164] Reference Figure 8It can form a pixel-defining layer (PDL) that covers the pixel electrode (PE) and partially covers the sidewall structure stack (SWS).

[0165] According to some embodiments, an inorganic insulating film comprising an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride and covering the sidewall structure stack (SWS) and pixel electrode (PE) can be formed by a deposition process such as CVD. The outer portion of the inorganic insulating film can then be etched to form the pixel defining layer (PDL).

[0166] The internal portion of the sidewall structure stack SWS can be covered by the pixel-defined layer (PDL). The external portion of the sidewall structure stack SWS can be exposed from the pixel-defined layer (PDL).

[0167] Reference Figure 9 The portion of the third conductive layer CL3 exposed from the pixel-defining layer PDL can be etched to form a third conductive pattern CLP3. According to some embodiments, the third conductive layer CL3 can be partially removed by performing dry etching at an etch selectivity ratio for the second conductive layer CL2.

[0168] The portion of the third conductive layer CL3 covered by the pixel-limiting layer PDL can be retained as the third conductive pattern CLP3.

[0169] Reference Figure 10 The second conductive layer CL2 can be partially etched to form the second conductive pattern CLP2.

[0170] According to some embodiments, the second conductive layer CL2 can be partially etched, for example, by using wet etching with an etchant having an etchant selectivity ratio for the second conductive layer CL2 including Al. Therefore, the second conductive layer CL2 can be recessed in the lateral direction of the pixel defining layer PDL to form a second conductive pattern CLP2.

[0171] According to some embodiments, the second conductive pattern CLP2 can be recessed to form a sidewall structure SW, which has an outer groove OG. As described above, the outer groove OG can be defined by the lower surface of the third conductive pattern CLP3, the side surface of the second conductive pattern CLP2, and the upper surface of the first conductive layer CL1.

[0172] like Figure 10 As shown, the side surface of the second conductive pattern CLP2 can be formed as an inclined plane.

[0173] Reference Figure 11 The portion of the pixel defining layer (PDL) overlapping with the pixel electrode (PE) can be etched to form an opening (OP) that exposes the pixel electrode (PE). The opening (OP) can partially expose the upper surface of the pixel electrode (PE), and the periphery of the pixel electrode (PE) can be covered by the pixel defining layer (PDL).

[0174] Then, as referenced Figure 3 As described, an emitter portion EL, a counter electrode CE, and an encapsulation layer TFE can be sequentially formed on the pixel defining layer PDL and the pixel electrode PE.

[0175] According to some embodiments, in Figure 11 The tilt angle of the sidewall of the opening OP formed in the process shown, relative to the upper surface of the substrate 100 or the upper surface of the pixel electrode PE (i.e., the tilt angle of the inner surface of the pixel defining layer PDL), can be smaller than that in the process shown. Figure 8 The tilt angle of the outer surface of the pixel-defining layer PDL formed in the process shown is relative to the upper surface of the substrate 100 or the upper surface of the pixel electrode PE.

[0176] Therefore, continuity of the emitting portion EL on the pixel electrode PE can be promoted, and discontinuity in the sidewall structure SW can be effectively induced. Furthermore, the counter electrode CE can also be continuous on the pixel electrode PE and physically discontinuous in the sidewall structure SW, facilitating electrical connection through contact in the sidewall structure SW.

[0177] According to some embodiments, as described above, the counter electrode CE can be formed by a sputtering process into a multilayer structure comprising a metal layer (e.g., a Mg-Ag layer) and a transparent conductive oxide layer (e.g., an IZO layer). Therefore, step coverage characteristics can be enhanced, and contact with the sidewall structure SW can be facilitated.

[0178] According to some embodiments, the tilt angle of the opening OP of the pixel defining layer PDL relative to the upper surface of the substrate 100 or the pixel electrode PE can be 30° to 60° or 40° to 50°. The tilt angle of the outer surface of the pixel defining layer PDL relative to the upper surface of the substrate 100 or the pixel electrode PE can be 80° to 100° or 85° to 95°. According to some embodiments, the outer surface of the pixel defining layer PDL can be perpendicular (or substantially perpendicular) to the upper surface of the substrate 100 or the pixel electrode PE.

[0179] Figure 12 and Figure 13 These are schematic plan views and cross-sectional views illustrating a display device according to an embodiment. For example, Figure 13 It is along Figure 12 A cross-sectional view cut along line I-I' in the third direction (thickness direction).

[0180] For ease of explanation, in Figure 13 Detailed illustrations of the structure between pixel electrodes PE1, PE2, PE3 and the substrate 100 are omitted. These can be omitted by referring to and incorporating... Figure 3 Some detailed descriptions of structures that are the same (or substantially the same) or similar to those described in the text.

[0181] Reference Figure 12 and Figure 13 The display device may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may each be formed by an opening OP in the pixel definition layer PDL (see [link to pixel definition layer]). Figure 11 The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are stacked together.

[0182] The first pixel PX1, the second pixel PX2, and the third pixel PX3 can be pixels of different colors. For example, the first pixel PX1, the second pixel PX2, and the third pixel PX3 can correspond to a green pixel, a red pixel, and a blue pixel, respectively.

[0183] like Figure 12 As shown, the second pixel PX2 and the third pixel PX3 can be arranged alternately and repeatedly along the first direction to form a first pixel row. The first pixel PX1 can be arranged repeatedly along the first direction to form a second pixel row.

[0184] The first and second pixel rows can be arranged alternately along the second direction. The first pixel PX1, the second pixel PX2, and the third pixel PX3 can be arranged in a zigzag pattern along the first or the second direction.

[0185] Figure 12 The pixel arrangement shown is an example and can be appropriately changed depending on the resolution, luminous efficiency, etc. of the display device.

[0186] For reference Figure 3 As described, each pixel may include a pixel electrode PE, a pixel defining layer PDL, a sidewall structure SW, an emitting portion EL, a counter electrode CE, and an encapsulation layer TFE.

[0187] The pixel definition layer (PDL) can be formed on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, respectively, and the sidewall structure SW including the first conductive layer CL1, the second conductive pattern CLP2, and the third conductive pattern CLP3 can be formed on the lower outer part of the pixel definition layer (PDL) of each pixel.

[0188] On the pixel definition layer PDL and the first pixel electrode PE1 of the first pixel PX1, a first emission portion EL1 including a first emission layer (e.g., a green emission layer), a first pair of electrodes CE1 and a first encapsulation layer TFE1 may be stacked sequentially.

[0189] On the pixel definition layer PDL and the second pixel electrode PE2 of the second pixel PX2, a second emission portion EL2 including a second emission layer (e.g., a red emission layer), a second pair of electrodes CE2, and a second encapsulation layer TFE2 may be stacked sequentially.

[0190] On the pixel definition layer PDL and the third pixel electrode PE3 of the third pixel PX3, a third emission portion EL3 including a third emission layer (e.g., a blue emission layer), a third pair electrode CE3 and a third encapsulation layer TFE3 may be stacked sequentially.

[0191] The sidewall structure SW allows for the selective patterning of the first emitting portion EL1, the first electrode pair CE1, and the first encapsulation layer TFE1 in the first pixel PX1. The sidewall structure SW also allows for the selective patterning of the second emitting portion EL2, the second electrode pair CE2, and the second encapsulation layer TFE2 in the second pixel PX2. Furthermore, the sidewall structure SW allows for the selective patterning of the third emitting portion EL3, the third electrode pair CE3, and the third encapsulation layer TFE3 in the third pixel PX3.

[0192] When in Figure 12 When viewed in a planar direction, the counter electrodes CE1, CE2, CE3 and the emitting portions EL1, EL2, EL3 can completely cover the pixel definition layer PDL and pixel electrodes PE1, PE2, PE3 of the corresponding pixels.

[0193] According to some embodiments of this disclosure, the sidewall structures SW of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be connected to each other through the first conductive layer CL1. According to some embodiments, the first conductive layer CL1 can be set as a common connection electrode of the first pixel PX1, the second pixel PX2, and the third pixel PX3, or as a bus-bar electrode.

[0194] Therefore, the first pair of electrodes CE1, the second pair of electrodes CE2, and the third pair of electrodes CE3 can be electrically connected to each other through the first conductive layer CL1 to provide a common cathode for the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0195] Figures 14 to 16 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to some embodiments. (The details may be omitted by reference to the incorporation of...) Figure 3 and Figures 7 to 11 Some detailed descriptions of processes that are the same as (or substantially the same as) or similar to those described in the document.

[0196] Now refer to Figure 14 It can be executed by referencing and Figures 7 to 11 The processes described herein are the same (or substantially the same) or similar.

[0197] Therefore, a first pixel electrode PE1, a second pixel electrode PE2, a third pixel electrode PE3, and a sidewall structure stack SWS (see [reference]) can be formed on the substrate 100. Figure 7 ).

[0198] For reference Figure 8 As described, the pixel definition layer PDL can be formed to cover the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3, and to partially cover the sidewall structure stack SWS.

[0199] For reference Figure 9 and Figure 10 As described, the third conductive layer CL3 and the second conductive layer CL2 of the sidewall structure stack SWS can be partially etched to form a sidewall structure SW including a first conductive layer CL1, a second conductive pattern CLP2 and a third conductive pattern CLP3.

[0200] For reference Figure 11 As described, portions of the pixel definition layer PDL that overlap with the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 can be etched to partially expose the upper surfaces of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, respectively.

[0201] Reference Figure 15 A first emission portion EL1, a first pair of electrodes CE1, and a first encapsulation layer TFE1 can be formed on the pixel limiting layer PDL and the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3.

[0202] The first emitting portion EL1 and the first pair of electrodes CE1 can be formed discontinuously from the sidewall structure SW of each pixel. The first encapsulation layer TFE1 can contact the side of the second conductive pattern CLP2 of the sidewall structure SW and fill the space between adjacent first pair of electrodes CE1.

[0203] Reference Figure 16 The first emission portion EL1, the first pair of electrodes CE1, and the first encapsulation layer TFE1 formed in the regions corresponding to the second pixel PX2 and the third pixel PX3 can be removed by photolithography etching process.

[0204] Therefore, the first emitting portion EL1, the first pair of electrodes CE1, and the first encapsulation layer TFE1 can be retained in the area corresponding to the first pixel PX1.

[0205] Then, the reference can be repeated in the region corresponding to the second pixel PX2 and in the region corresponding to the third pixel PX3. Figure 15 and Figure 16 The described process.

[0206] For example, after the second emission portion EL2, the second pair of electrodes CE2, and the second encapsulation layer TFE2 are formed sequentially, the portions of the second emission portion EL2, the second pair of electrodes CE2, and the second encapsulation layer TFE2 formed in the regions corresponding to the first pixel PX1 and the third pixel PX3 can be removed by photolithography etching process.

[0207] Then, after the third emission portion EL3, the third pair of electrodes CE3 and the third encapsulation layer TFE3 are formed sequentially, the portions of the third emission portion EL3, the third pair of electrodes CE3 and the third encapsulation layer TFE3 formed in the regions corresponding to the first pixel PX1 and the second pixel PX2 can be removed by photolithography etching process.

[0208] Therefore, as Figure 13 As shown, a stack of emitter EL, counter electrode CE and encapsulation layer TFE can be obtained by selectively patterning the first pixel PX1, the second pixel PX2 and the third pixel PX3 respectively.

[0209] Figure 17 This is a schematic cross-sectional view illustrating a display device according to some embodiments. References may be omitted. Figure 3 Some detailed descriptions of the same (or substantially the same) or similar constructions and structures.

[0210] Reference Figure 17 An indentation IG can be formed between the outer portion of the pixel electrode PE and the pixel defining layer PDL. A sacrificial pattern SP can be formed between the outer portion of the pixel electrode PE and the pixel defining layer PDL.

[0211] According to some embodiments, the recess IG may be defined by the upper surface of the pixel electrode PE (e.g., the upper surface of the second transparent conductive oxide layer TL2), the side surface of the sacrificial pattern SP, and the lower surface of the pixel defining layer PDL.

[0212] The sacrificial pattern SP may include a transparent conductive oxide that is different from the transparent conductive oxide included in the second transparent conductive oxide layer TL2. According to some embodiments, the sacrificial pattern SP may include IZO.

[0213] Figure 18 This is a schematic, partially enlarged cross-sectional view illustrating the shape of the emitting portion separated via an inner groove according to some embodiments. For example, Figure 18 It is by Figure 17 A partially enlarged sectional view of the area indicated by the dashed circle in the diagram.

[0214] Reference Figure 18The groove IG formed by the sacrificial pattern SP can cause breakage or discontinuity in at least one layer included in the emitting portion EL.

[0215] Reference Figure 18 The emitter portion (EL) may include a hole injection layer (HIL), a hole transport layer (HTL), an emitter layer (EML), and an electron transport layer (ETL) sequentially stacked on the pixel electrode (PE). The hole transport layer (HTL) and the electron transport layer (ETL) may each include the hole transport material and the electron transport material as described above. An electron injection layer may be further formed on top of the electron transport layer (ETL).

[0216] Hole injection layer (HIL) may include hole transport material containing dopants (e.g., p-type dopants).

[0217] According to some embodiments, the hole injection layer HIL may be interrupted or discontinuous in the groove IG. According to some embodiments, the hole injection layer HIL may be discontinuous due to sacrificing the sidewalls of the pattern SP.

[0218] According to some embodiments, the hole transport layer HTL, the emitter layer EML, and the electron transport layer ETL can extend continuously within the recess IG without including discontinuous regions (e.g., shaded regions).

[0219] According to some embodiments, the hole transport layer (HTL) may also be discontinuous within the recessed groove (IG) due to the sacrifice of the sidewalls of the pattern (SP). The emitter layer (EML) and the electron transport layer (ETL) may extend continuously within the recessed groove (IG) without including discontinuous regions (e.g., shaded regions).

[0220] According to some embodiments, the recess distance of the sacrificial pattern SP can be adjusted to induce discontinuities in the hole injection layer HIL, while maintaining the continuity of the emitter portion EL except for the hole injection layer HIL. Therefore, the hole injection layer HIL, which has relatively high conductivity, can be cut off by dopants, thereby suppressing or reducing horizontal leakage current between adjacent pixels. Furthermore, shadowed areas in the emitter layer EML can be avoided, and the luminescence reliability and efficiency of each pixel can be maintained.

[0221] Figures 19 to 21 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to some embodiments. Figures 19 to 21 It shows a reference. Figure 18 The cross-sectional view describing the formation of the groove IG and the sacrificial pattern SP. (This can be omitted by referring to and incorporating...) Figures 7 to 11 Some detailed descriptions of processes that are the same as (or substantially the same as) or similar to those described in the document.

[0222] Reference Figure 19In addition to adding the formation of a sacrificial layer SL on the second transparent conductive oxide layer TL2 during the formation of the pixel electrode PE, it is possible to perform the same operation as the reference. Figure 7 The processes described are the same (or substantially the same) or similar.

[0223] Therefore, the pixel electrode PE formed on the substrate 100 or the via insulating layer can have a sacrificial layer SL formed on its upper surface.

[0224] According to some embodiments, the sacrificial layer SL can be formed by a deposition process such as sputtering to include IZO.

[0225] Reference Figure 20 It can be executed and referenced. Figures 8 to 11 The processes described are the same (or substantially the same) or similar.

[0226] Therefore, a pixel-defining layer PDL can be formed that covers the sacrificial layer SL and the pixel electrode PE and partially covers the sidewall structure stack SWS. A third conductive layer CL3 and a second conductive layer CL2 included in the sidewall structure stack SWS can be partially etched to form an outer groove OG, and a sidewall structure SW including a first conductive layer CL1, a second conductive pattern CLP2, and a third conductive pattern CLP3 can be formed.

[0227] The pixel-defining layer (PDL) can be partially etched to form an opening (OP) that partially exposes the upper surface of the sacrificial layer (SL).

[0228] Reference Figure 21 The sacrificial layer SL can be partially removed by opening OP to form the sacrificial pattern SP.

[0229] According to some embodiments, a sacrificial pattern SP can be formed by injecting an etchant with an etch selectivity to IZO via an opening OP. Due to the isotropic nature of wet etching, the portion of the sacrificial layer SL exposed by the opening OP can be partially removed together with the portion of the sacrificial layer SL covered by the pixel-defining layer PDL.

[0230] Therefore, the sacrificial pattern SP can have a shape recessed from the sidewall of the opening OP, and can form a recess IG. The recess IG can be defined by the upper surface of the second transparent conductive oxide layer TL2, the side surface of the sacrificial pattern SP, and the lower surface of the pixel defining layer PDL.

[0231] Then, as Figure 17 As shown, an emitter portion (EL), a counter electrode (CE), and an encapsulation layer (TFE) can be sequentially formed on the pixel defining layer (PDL) and the pixel electrode (PE). (See reference...) Figure 18 As described, the discontinuity of the hole injection layer HIL can be caused by the groove IG.

[0232] Figure 22 This is an exploded perspective view of an electronic device according to some embodiments.

[0233] According to some embodiments, the electronic device ED can be implemented in the form of a mobile phone (smartphone), tablet computer, or PC, which includes the above-described display device.

[0234] Reference Figure 22 The electronic device ED may include a window structure WS, a display device DD, and a housing HS. The display device DD may include a display panel DP, which includes the transistor structure and light-emitting elements as described above. Along a third direction, the housing HS, the display device DD, and the window structure WS may be stacked sequentially.

[0235] A window structure (WS) provides an external display surface that is identifiable by the user (such as the viewing surface of an electronic device, such as a mobile phone), and may include a transparent material film. For example, a window structure (WS) may include glass (e.g., ultra-thin glass (UTG)), a hard-coated film, or a plastic film, etc.

[0236] The outer surface of the window structure WS may include an active area AA and a peripheral area PA. The active area AA can provide a surface on which the image of the display device DD is displayed and on which the user's touch / commands are input. The peripheral area PA may correspond to the border area of ​​the electronic device ED.

[0237] For reference Figure 1 As described, the display device DD or display panel DP may include a display area DA and a non-display area NDA. The display area DA of the display panel DP may correspond to or overlap with the effective area AA of the window structure WS. The non-display area NDA of the display panel DP may correspond to or overlap with the peripheral area PA of the window structure WS. According to some embodiments, the peripheral area PA may also include a boundary area that does not overlap with the non-display area NDA.

[0238] According to some embodiments, functional element regions E1 and E2 can be included within the effective area AA of the window structure WS. For example, the first functional element region E1 can be included at one end of the effective area AA and can be implemented, for example, in the form of a camera hole. The second functional element region E2 can be configured as a fingerprint sensing area.

[0239] For example, the sensor structure used for touch sensing or fingerprint sensing can be arranged inside the display panel DP, or between the window structure WS and the display panel DP.

[0240] The housing HS can be configured as the chassis structure or rear housing of the display device DD or electronic device ED. A cover panel can be located between the housing HS and the display panel DP. The housing HS or cover panel may include support for the display panel DP and the printed circuit board 200 (see...). Figure 1 Plates such as SUS plates. The housing HS or cover panel may also include a shock-absorbing elastomer for the display device DD.

[0241] Figure 23 This is a block diagram of an electronic device according to some embodiments.

[0242] Reference Figure 23 According to some embodiments, the electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0243] The processor 12 may include a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and / or a controller.

[0244] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals to output image information via the display screen.

[0245] The power module 14 may include a power module (such as a power adapter or battery cell) and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0246] At least one of the above-described configurations of the electronic device 10 may be included within the display device according to the above embodiments. Furthermore, some of the modules functionally included within the electronic device 10 may be included within the display device, while other modules may be disposed separately from the display device. For example, the display module 11 may be included in the display device, while the processor 12, memory 13, and power module 14 may be disposed as other devices within the electronic device 10 besides the display device.

[0247] Figure 24 This is a schematic diagram of an electronic device according to some embodiments.

[0248] Reference Figure 24Non-limiting examples of various electronic devices having a display device according to the above embodiments include: smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, desktop monitors, and other electronic devices for displaying images; wearable electronic devices including a display module, such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c; and automotive electronic devices 10_3 including a display module, such as a central information display (CID) on the dashboard, a central instrument panel or dashboard, and an interior mirror display. The electronic devices may also include virtual reality glasses or augmented reality glasses.

[0249] Although aspects of a display device, a method of manufacturing the display device, and an electronic device including the display device according to some embodiments have been described with reference to the accompanying drawings, the embodiments shown are examples and can be modified and altered by those skilled in the art without departing from the spirit of the technology described in the claims and their equivalents.

Claims

1. A display device, the display device comprising: Matrix substrate; A transistor structure on the substrate; Pixel electrodes are electrically connected to the transistor structure on the substrate; A pixel defining layer partially covers the pixel electrode and has an opening overlapping the pixel electrode; The sidewall structure is located at the lower outer portion of the pixel defining layer and includes an outer groove; The emitting portion is located on the pixel defining layer and the pixel electrode; as well as The electrode is located on the emitting portion and contacts the sidewall structure.

2. The display device according to claim 1, wherein, The sidewall structure includes a first conductive layer, a second conductive pattern, and a third conductive pattern sequentially stacked on the substrate. The outer groove is defined by the upper surface of the first conductive layer, the side surface of the second conductive pattern, and the lower surface of the third conductive pattern.

3. The display device according to claim 2, wherein, The counter electrode contacts the side surface of the third conductive pattern.

4. The display device according to claim 2, wherein, The emitting portion covers the outer surface of the pixel defining layer and does not contact the second conductive pattern of the sidewall structure.

5. The display device according to claim 4, wherein, The emitting portion does not contact the lower surface of the third conductive pattern.

6. The display device according to claim 2, wherein, The counter electrode does not contact the first conductive layer.

7. The display device according to claim 2, wherein, At least one of the first conductive layer, the second conductive pattern, and the third conductive pattern is located on the same layer or at the same level as the pixel electrode.

8. The display device according to claim 2, wherein, The second conductive pattern comprises a metal different from the metal in each of the first conductive layer and the third conductive pattern.

9. The display device according to claim 8, wherein, The first conductive layer and the third conductive pattern comprise titanium, and the second conductive pattern comprises aluminum.

10. The display device according to claim 2, wherein the display device comprises a plurality of pixels, in, The first conductive layer of the sidewall structure is a common interconnect electrode formed by adjacent pixels throughout the plurality of pixels.

11. The display device according to claim 10, wherein, The plurality of pixels includes a first pixel, a second pixel, and a third pixel. The pixel electrode includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, which correspond to the first pixel, the second pixel, and the third pixel, respectively. The electrode pair includes a first pair of electrodes, a second pair of electrodes, and a third pair of electrodes respectively located on the first pixel electrode, the second pixel electrode, and the third pixel electrode. The first pair of electrodes, the second pair of electrodes, and the third pair of electrodes are electrically connected to each other through the first conductive layer of the sidewall structure.

12. The display device according to claim 1, wherein, The launching portion extends continuously within the opening.

13. The display device according to claim 1, wherein, The recess is located between the outer portion of the upper surface of the pixel electrode and the pixel defining layer.

14. The display device according to claim 13, wherein, The emitting portion includes a hole injection layer, a hole transport layer, an emitting layer, and an electron transport layer sequentially stacked on the pixel electrode, and The hole injection layer is discontinuous due to the inner groove.

15. The display device according to claim 13, further comprising a sacrificial pattern formed in the recess.

16. A method of manufacturing a display device, the method comprising the following steps: A pixel electrode and sidewall structure stack is formed on a substrate; A pixel defining layer is formed on the substrate, covering the pixel electrode and partially covering the sidewall structure stack; The sidewall structure is formed by partially etching the sidewall structure stack exposed from the pixel-defining layer; An emitting portion is formed on the pixel defining layer and the pixel electrode; as well as A counter electrode is formed on the emitting portion to contact the sidewall structure.

17. The method of manufacturing a display device according to claim 16, wherein, The sidewall structure stack includes a first conductive layer, a second conductive layer, and a third conductive layer formed sequentially from the substrate. The steps for forming the sidewall structure include: A third conductive pattern is formed by dry etching to remove a portion of the third conductive layer exposed from the pixel defining layer; and The outer groove is formed by selectively partially removing the second conductive layer through wet etching to form a second conductive pattern.

18. The method of manufacturing a display device according to claim 17, wherein, The emitting portion and the counter electrode are discontinuous due to the outer groove.

19. An electronic device, the electronic device comprising: Display device; Memory; as well as The processor is configured to control the operation of the display device by executing data included in the memory. The display device includes: Matrix substrate; A transistor structure on the substrate; Pixel electrodes are electrically connected to the transistor structure on the substrate; A pixel defining layer partially covers the pixel electrode and has an opening overlapping the pixel electrode; The sidewall structure is located at the lower outer portion of the pixel defining layer and includes an outer groove; The emitting portion is located on the pixel defining layer and the pixel electrode; and The electrode is located on the emitting portion and contacts the sidewall structure.

20. The electronic device according to claim 19, wherein, The electronic device is one of the following: virtual reality glasses or augmented reality glasses, smartphone, tablet PC, laptop computer, television, desktop monitor, smart glasses, head-mounted display, smartwatch, and in-vehicle display.

Images