Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes a substrate including a display area and a non-display area; first, second, third, and fourth sub-pixel circuits sequentially disposed on the substrate in a first direction and each including a driving transistor and a switching transistor; a first insulating layer covering the first, second, third, and fourth sub-pixel circuits; a plurality of pixel electrodes spaced apart from each other on the first insulating layer; and a plurality of emission layers respectively disposed on the plurality of pixel electrodes in the display area, wherein the first sub-pixel circuit is not electrically connected to each of the plurality of pixel electrodes, and the fourth sub-pixel circuit is electrically connected to one of the plurality of pixel electrodes.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0058489, filed on May 2, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to an apparatus, and more specifically, to a display apparatus and an electronic apparatus. Background Technology

[0003] Portable electronic devices are now widely used. In addition to compact electronic devices such as mobile phones, tablet PCs have recently been adopted as portable electronic devices as well.

[0004] To support various functions, such portable electronic devices include display devices to provide users with visual information such as images or videos. As other components used to drive the display device are miniaturized, the proportion of the display device in electronic devices is gradually increasing, and structures that can be bent from a flat state have been developed. Summary of the Invention

[0005] One or more embodiments include a display device having improved degrees of freedom in the arrangement of the emitter layer at the boundary between the arcuate display area and the non-display area in a vertically merged pixel (VFP) structure, and an electronic device including the display device.

[0006] However, the benefits mentioned above are just examples, and other benefits may exist.

[0007] Additional aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0008] According to one or more embodiments, a display device includes: a substrate including a display area and a non-display area; a first sub-pixel circuit, a second sub-pixel circuit, a third sub-pixel circuit, and a fourth sub-pixel circuit sequentially disposed on the substrate in a first direction, and each including a driving transistor and a switching transistor; a first insulating layer covering the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, and the fourth sub-pixel circuit; a plurality of pixel electrodes spaced apart from each other on the first insulating layer; and a plurality of emission layers disposed on the plurality of pixel electrodes respectively in the display area, wherein the first sub-pixel circuit is not electrically connected to each of the plurality of pixel electrodes, and the fourth sub-pixel circuit is electrically connected to one of the pixel electrodes among the plurality of pixel electrodes.

[0009] In an embodiment, at least a portion of the first sub-pixel circuit may overlap with the non-display area, and at least a portion of the fourth sub-pixel circuit may overlap with the display area.

[0010] In an embodiment, the second sub-pixel circuit and the fourth sub-pixel circuit can be configured to receive data signals of light of the same color.

[0011] In an embodiment, the first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit can be configured to receive data signals of light of different colors.

[0012] In an embodiment, the display device may further include: a plurality of connecting electrodes disposed on a first insulating layer and electrically connected to a first sub-pixel circuit, a second sub-pixel circuit, a third sub-pixel circuit, and a fourth sub-pixel circuit, wherein the upper surface of the connecting electrode electrically connected to the sub-pixel circuit among the plurality of connecting electrodes is sealed by the first insulating layer, and the connecting electrode electrically connected to the fourth sub-pixel circuit among the plurality of connecting electrodes is electrically connected to one of the aforementioned pixel electrodes among the plurality of pixel electrodes.

[0013] In an embodiment, the display device may further include: a common electrode disposed on a plurality of emission layers, wherein the common electrode overlaps with each of the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, and the fourth sub-pixel circuit.

[0014] In an embodiment, the display device may further include: a fifth sub-pixel circuit, a sixth sub-pixel circuit, a seventh sub-pixel circuit, and an eighth sub-pixel circuit, which are sequentially disposed on the substrate in a first direction starting from the fourth sub-pixel circuit, and each includes a driving transistor and a switching transistor, wherein each of the fifth, sixth, seventh, and eighth sub-pixel circuits is electrically connected to a corresponding pixel electrode among a plurality of pixel electrodes and a corresponding emitter layer among a plurality of emitter layers.

[0015] In an embodiment, the first sub-pixel circuit and the seventh sub-pixel circuit can be configured to receive data signals of light of the same color, the second sub-pixel circuit, the fourth sub-pixel circuit, the sixth sub-pixel circuit and the eighth sub-pixel circuit can be configured to receive data signals of light of the same color, the third sub-pixel circuit and the fifth sub-pixel circuit can be configured to receive data signals of light of the same color, and the first sub-pixel circuit, the second sub-pixel circuit and the third sub-pixel circuit can be configured to receive data signals of light of different colors.

[0016] In an embodiment, the emitter layers that are electrically connected to the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, the fourth sub-pixel circuit, the fifth sub-pixel circuit, the sixth sub-pixel circuit, the seventh sub-pixel circuit, and the eighth sub-pixel circuit, respectively, can be configured in a PenTile structure.

[0017] In an embodiment, in a plan view, at least a portion of the boundary line between the display area and the non-display area may have a curved shape.

[0018] According to one or more embodiments, an electronic device includes: a substrate including a display area and a non-display area; a first sub-pixel circuit, a second sub-pixel circuit, a third sub-pixel circuit, a fourth sub-pixel circuit, a fifth sub-pixel circuit, a sixth sub-pixel circuit, a seventh sub-pixel circuit, and an eighth sub-pixel circuit, sequentially disposed on the substrate in a first direction, and each including a driving transistor and a switching transistor; a first insulating layer covering the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, the fourth sub-pixel circuit, the fifth sub-pixel circuit, the sixth sub-pixel circuit, the seventh sub-pixel circuit, and the eighth sub-pixel circuit; a plurality of pixel electrodes spaced apart from each other on the first insulating layer; and a plurality of emitting layers disposed on the plurality of pixel electrodes respectively in the display area, wherein the first sub-pixel circuit is not electrically connected to each of the plurality of pixel electrodes, the eighth sub-pixel circuit is electrically connected to one of the plurality of pixel electrodes, and the second sub-pixel circuit, the fourth sub-pixel circuit, the sixth sub-pixel circuit, and the eighth sub-pixel circuit are configured to receive data signals of light of the same color.

[0019] In an embodiment, each of the second sub-pixel circuit, the fourth sub-pixel circuit, the sixth sub-pixel circuit, and the eighth sub-pixel circuit can be configured to receive a data signal of red light.

[0020] In an embodiment, the first sub-pixel circuit and the seventh sub-pixel circuit can be configured to receive data signals of light of the same color, and the third sub-pixel circuit and the fifth sub-pixel circuit can be configured to receive data signals of light of the same color.

[0021] In an embodiment, each of the first sub-pixel circuit and the seventh sub-pixel circuit can be configured to receive a red light data signal, and each of the third sub-pixel circuit and the fifth sub-pixel circuit can be configured to receive a blue light data signal.

[0022] In an embodiment, the first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit can be configured to receive data signals of light of different colors.

[0023] In an embodiment, the emitter layers that are electrically connected to the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, the fourth sub-pixel circuit, the fifth sub-pixel circuit, the sixth sub-pixel circuit, the seventh sub-pixel circuit, and the eighth sub-pixel circuit, respectively, can be configured in a PenTile structure.

[0024] In an embodiment, at least a portion of the first sub-pixel circuit may overlap with the non-display area, and at least a portion of the eighth sub-pixel circuit may overlap with the display area.

[0025] In an embodiment, the electronic device may further include: a plurality of connecting electrodes disposed on a first insulating layer and electrically connected to a first sub-pixel circuit, a second sub-pixel circuit, a third sub-pixel circuit, a fourth sub-pixel circuit, a fifth sub-pixel circuit, a sixth sub-pixel circuit, a seventh sub-pixel circuit, and an eighth sub-pixel circuit, respectively.

[0026] In an embodiment, the upper surface of the connection electrode among the plurality of connection electrodes that is electrically connected to the first sub-pixel circuit can be sealed by the first insulating layer, and the connection electrode among the plurality of connection electrodes that is electrically connected to the eighth sub-pixel circuit can be electrically connected to the aforementioned pixel electrode among the plurality of pixel electrodes.

[0027] In an embodiment, the display device may further include: a common electrode disposed on a plurality of emission layers, wherein the common electrode overlaps with each of the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, the fourth sub-pixel circuit, the fifth sub-pixel circuit, the sixth sub-pixel circuit, the seventh sub-pixel circuit, and the eighth sub-pixel circuit.

[0028] In an embodiment, in a plan view, at least a portion of the boundary line between the display area and the non-display area may have a curved shape.

[0029] Other aspects, features, and advantages besides those described above will become apparent from the following drawings, claims, and specific embodiments of this disclosure. Attached Figure Description

[0030] The above and other aspects, features, and advantages of specific embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 and Figure 2 This is a schematic plan view of a display device according to an embodiment;

[0032] Figure 3 It is set in Figure 2 The equivalent circuit diagram of pixels in the display area of ​​the display device;

[0033] Figure 4 This is a schematic cross-sectional view of a display device according to an embodiment;

[0034] Figures 5 to 9 This is a schematic plan view of a display device according to an embodiment;

[0035] Figures 10 to 12 This is a schematic plan view of a display device according to an embodiment;

[0036] Figure 13 This is a schematic cross-sectional view of a display device according to an embodiment;

[0037] Figure 14 This is a block diagram of an electronic device according to an embodiment; and

[0038] Figure 15 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0039] Reference will now be made in detail to embodiments illustrated in the accompanying drawings, in which the same reference numerals consistently refer to the same elements. In this respect, present embodiments may take different forms and should not be construed as limited to the description set forth herein. Accordingly, embodiments are described below with reference to the accompanying drawings only to explain aspects of this description. As used herein, the term “and / or” includes any and all combinations of one or more of the listed associated items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0040] This disclosure can undergo various modifications and may have various embodiments, and specific embodiments are illustrated in the accompanying drawings and described in detail in the specific embodiments. The effects and features of this disclosure, as well as the methods for implementing them, will be referenced below and in the accompanying drawings. Figure 1 The embodiments described in detail below will become clear. However, this disclosure is not limited to the embodiments disclosed below and can be implemented in various forms.

[0041] In the following description, various embodiments will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, the same or corresponding parts are given the same reference numerals, and redundant descriptions are omitted.

[0042] In the following embodiments, the terms "first," "second," etc., are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0043] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0044] In the following embodiments, terms such as “comprising” or “having” mean that the features or components described in this specification are present, but do not preclude the possibility that one or more other features or components may be added.

[0045] In the following embodiments, when a portion such as a membrane, region, component, etc. is described as being on or above another portion, this includes not only the case where it is directly on top of the other portion, but also the case where another membrane, region, component, etc. is located between them.

[0046] In the accompanying drawings, the dimensions of components may be enlarged or reduced for ease of explanation. For example, the dimensions and thicknesses of each component shown in the drawings are arbitrarily illustrated for ease of explanation, and therefore this disclosure is not necessarily limited to what is shown.

[0047] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system, and can be interpreted in a broad sense that includes them. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0048] In some embodiments, where implementation is otherwise feasible, a particular process sequence may be performed in a different order than that described. For example, two processes described in the order may be performed substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0049] In this specification, "in a plan view" means perpendicular to the substrate 100 (see... Figure 2 The plane viewed from the direction of the substrate 100 (see...). That is, "A and B are spaced apart from each other in the plan view" means "A and B are perpendicular to the substrate 100 (see...)". Figure 2 When viewed from the direction of ( ), they are spaced apart.

[0050] In this specification, "in cross-sectional view" indicates the view perpendicular to the substrate 100 (see [reference]). Figure 2 A plane cut in the direction of the substrate. That is, "A and B are spaced apart in the cross-sectional view" indicates that "A and B are perpendicular to the substrate 100 (see...)". Figure 2 The planes cut along the direction of the plane are spaced apart from each other.

[0051] Figure 1 and Figure 2 This is a schematic plan view of the display device 1 according to an embodiment.

[0052] refer to Figure 1The display device 1 may include a display area DA and a non-display area NDA outside (or around) the display area DA. Since the display device 1 includes a substrate 100, this can be understood as the substrate 100 including the display area DA and the non-display area NDA. Alternatively, this can be understood as the display area DA and the non-display area NDA being defined on the substrate 100.

[0053] The display area DA is the portion on which the image is displayed, and multiple pixels P can be set within the display area DA. The display area DA can have various shapes such as circles, ellipses, polygons, or specific graphic shapes. Figure 1 The diagram illustrates, by way of example, that the display area DA has an approximately rectangular shape with rounded corners. The non-display area NDA can be located outside the display area DA. The non-display area NDA can be positioned to surround at least a portion of the display area DA. The emission layer 220 may not be located within the non-display area NDA.

[0054] In the following description, an organic light-emitting display device will be used as an example to illustrate the display device 1 according to an embodiment, but the display device of this disclosure is not limited thereto. In another embodiment, the display device 1 of this disclosure may be an inorganic light-emitting display (or an inorganic electroluminescent (EL) display) or a display device such as a quantum dot light-emitting display. For example, the emitting layer of the display element provided in the display device 1 may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0055] The substrate 100 included in the display device 1 may include glass, ceramic, metal, or polymer resin. The substrate 100 may include polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 may have a multilayer structure comprising two layers containing such polymer resin and an inorganic layer located between the two layers. Alternatively, the substrate 100 may have a structure in which the layers containing such polymer resin and the inorganic layer are alternately laminated. The inorganic layer may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0056] Pixel P can be disposed within display area DA, and display area DA can provide an image using light emitted from pixel P. Each pixel P can include multiple light-emitting diodes (LEDs), and the LEDs can be electrically connected to sub-pixel circuitry PC. Sub-pixel circuitry PC and LEDs can be disposed within display area DA. Figure 2In the diagram, for convenience, the sub-pixel circuit PC and the light-emitting diode (LED) are shown side by side, but in reality, the sub-pixel circuit PC and the LED can at least partially overlap. For example, the LED can be disposed on the sub-pixel circuit PC.

[0057] The gate drive circuit, pad 14, first power supply wiring 15, and second power supply wiring 16 can be located in the non-display area NDA. The gate drive circuit may include, for example, a first scan drive circuit 11, a second scan drive circuit 12, and / or an emission control drive circuit 13.

[0058] The first scan drive circuit 11 provides a scan signal to the sub-pixel circuit PC via the gate line SL. The second scan drive circuit 12 can be disposed opposite the first scan drive circuit 11, with the display area DA located between them. A portion of the sub-pixel circuit PC disposed in the display area DA can be electrically connected to the first scan drive circuit 11, and the remainder can be connected to the second scan drive circuit 12. However, in some cases, the second scan drive circuit 12 can be omitted.

[0059] The emission control drive circuit 13 can be arranged on one side of the display area DA, similar to the first scan drive circuit 11. The emission control drive circuit 13 can provide an emission control signal to pixel P via the emission control line EL. Figure 2 In this illustration, the emission control drive circuit 13 is shown as being disposed only on one side of the display area DA, but this disclosure is not limited thereto. For example, the display device 1 may have multiple emission control drive circuits 13 disposed along both sides of the display area DA. Alternatively, the first scan drive circuit 11 may be disposed on one side of the display area DA, and the emission control drive circuit 13 may be disposed on the other side of the display area DA.

[0060] Pad 14 can be disposed in the pad area of ​​the PDA outside the display area NDA. Pad 14 can be exposed by an insulating layer rather than covered by an insulating layer, and can be electrically connected to the display circuit board 30. Pad 34 of the display circuit board 30 can be electrically connected to pad 14 of the display device 1.

[0061] The display circuit board 30 can transmit signals or power from the control unit to the display device 1. Control signals generated by the control unit can be transmitted through the display circuit board 30 to each gate drive circuit. Additionally, the control unit can transmit the first power supply voltage ELVDD (see...) Figure 3 ) and the second power supply voltage ELVSS (see Figure 3 These are respectively supplied to the first power supply wiring 15 and the second power supply wiring 16. The first power supply voltage is ELVDD (see...). Figure 3(Hereinafter referred to as the “drive voltage”) can be supplied to each sub-pixel circuit PC via the drive voltage line PL connected to the first power supply wiring 15, and the second power supply voltage ELVSS (see Figure 3 A common voltage (hereinafter referred to as "common voltage") can be provided to the common electrode of the light-emitting diode (LED) connected to the second power supply wiring 16. The first power supply wiring 15 may extend in a first direction (x-axis direction). The second power supply wiring 16 may have a ring shape with one end open and may partially surround the display area DA.

[0062] The data signal of the data driver 20 can be transmitted to the sub-pixel circuit PC through the data line DL. The data line DL is electrically connected to the data driver 20 via the input line IL.

[0063] Figure 3 It is set in Figure 2 The equivalent circuit diagram of pixel P in the display area DA of display device 1.

[0064] refer to Figure 3 The sub-pixel circuit PC connected to the light-emitting diode (LED) may include multiple transistors and at least one capacitor. For example, the sub-pixel circuit PC may include at least one driving transistor, at least one switching transistor, and at least one capacitor. For example, the sub-pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a storage capacitor Cst, and a holding capacitor Chd.

[0065] The first transistor T1 can be a drive transistor configured to output a drive current corresponding to a data signal, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be switching transistors configured to transmit signals by turning on / off. The first terminal (first electrode) of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be a source region or a drain region, and the second terminal (second electrode) can be another region.

[0066] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (PMOS), and the rest can be N-channel MOSFETs (NMOS). For example, the fifth transistor T5 can be a PMOS, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 can be NMOS. Alternatively, the fifth transistor T5 and the sixth transistor T6 can be PMOS, and the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be NMOS. Alternatively, all transistors can be NMOS, or all transistors can be PMOS.

[0067] At least one of the transistors may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and the rest may be transistors having an oxide semiconductor layer. For example, the fifth transistor T5 may include a semiconductor layer comprising polycrystalline silicon with high reliability, and each of the remaining transistors may include an oxide semiconductor layer with high carrier mobility and low leakage current characteristics. The case where the fifth transistor T5 is a PMOS comprising a silicon semiconductor layer and the remaining transistors are NMOS comprising an oxide semiconductor layer is described below.

[0068] The sub-pixel circuit PC can be electrically connected to gate lines configured to transmit signals to the gate electrodes of transistors. For example, the sub-pixel circuit PC can be connected to a scan line GWL configured to transmit a scan signal GW, an initialization gate line GBL configured to transmit an initialization signal GB, a reference gate line GRL configured to transmit a reference signal GR, a first transmit control line EML configured to transmit a first transmit control signal EM, a second transmit control line EMBL configured to transmit a second transmit control signal EMB, and a data line DL configured to transmit a data signal DATA. Additionally, the sub-pixel circuit PC can be connected to a drive voltage line PL configured to transmit a drive voltage ELVDD, a reference voltage line VRL configured to transmit a reference voltage VREF, and an initialization voltage line VL configured to transmit an initialization voltage VINT.

[0069] The first transistor T1, which drives the LED, can be electrically connected between the driving voltage line PL and the second node N2. The first transistor T1 may include a first gate electrode G1 connected to the first node N1, a first terminal electrically connected to the driving voltage line PL, and a second terminal connected to the second node N2. The first terminal may be the drain region D, and the second terminal may be the source region S. The first terminal of the first transistor T1 can be electrically connected to the driving voltage line PL via a fifth transistor T5, and the second terminal of the first transistor T1 can be electrically connected to the pixel electrode of the light-emitting diode (LED). The first transistor T1 can receive the data signal DATA and control the amount of driving current Id flowing to the LED based on the switching operation of the second transistor T2.

[0070] The second transistor T2, which is the data writing transistor, can be electrically connected between the data line DL and the first node N1. The second transistor T2 may include a gate electrode connected to the scan line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second transistor T2 can be turned on by the scan signal GW received via the scan line GWL, and can electrically connect the data line DL to the first node N1, so that the data signal DATA from the data line DL can be transmitted to the first node N1.

[0071] The third transistor T3, which is the first initialization transistor, can be electrically connected between the first node N1 and the reference voltage line VRL. The third transistor T3 may include a gate electrode connected to the reference gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The third transistor T3 can be turned on by a reference signal GR received via the reference gate line GRL, so that the reference voltage VREF from the reference voltage line VRL can be transmitted to the first node N1.

[0072] The fourth transistor T4, which is the second initialization transistor, can be electrically connected between the first transistor T1 and the initialization voltage line VL. The fourth transistor T4 may include a gate electrode connected to the initialization gate line GBL, a first terminal connected to the second terminal of the light-emitting diode (LED) and the sixth transistor T6, and a second terminal connected to the initialization voltage line VL. The fourth transistor T4 can be turned on by the initialization signal GB received via the initialization gate line GBL, so that the initialization voltage VINT from the initialization voltage line VL can be transmitted to the pixel electrode of the LED. In other words, the fourth transistor T4 can initialize the potential of the pixel electrode of the LED to the initialization voltage VINT.

[0073] The fifth transistor T5, which is the emitter control transistor, can be electrically connected between the drive voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate electrode connected to the first emitter control line EML, a first terminal connected to the drive voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 can be turned on or off depending on the first emitter control signal EM from the first emitter control line EML.

[0074] The sixth transistor T6, which operates the control transistor, can be connected between the first transistor T1 and the light-emitting diode (LED). The sixth transistor T6 may include a gate electrode connected to the second emission control line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the LED. The sixth transistor T6 can be turned on by a second emission control signal EMB from the second emission control line EMBL, and can electrically connect the second node N2 to the pixel electrode of the LED.

[0075] exist Figure 3 In this embodiment, the fifth transistor T5 operates in response to the first transmit control signal EM, and the sixth transistor T6 operates in response to the second transmit control signal EMB, but this disclosure is not limited thereto. For example, the fifth transistor T5 and the sixth transistor T6 may operate in response to the same transmit control signal.

[0076] The reference signal GR can be substantially synchronized with the scan signal GW of the sub-pixel circuit PC located in the previous row. The initialization signal GB can be substantially synchronized with the scan signal GW. Alternatively, the initialization signal GB can be substantially synchronized with either the scan signal GW or the reference signal GR of the sub-pixel circuit PC located in the next row.

[0077] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2. That is, the sub-pixel circuit PC included in the display device 1 according to this embodiment can be a source follower type circuit in which the storage capacitor Cst is connected between the first node N1 and the second node N2. The first storage electrode CEs1 of the storage capacitor Cst can be connected to the first node N1, and the second storage electrode CEs2 can be connected to the second node N2. The storage capacitor Cst can store a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal DATA.

[0078] A holding capacitor Chd can be connected between the drive voltage line PL and the second node N2. The first holding electrode CEh1 of the holding capacitor Chd can be electrically connected to the drive voltage line PL, and the second holding electrode CEh2 can be electrically connected to the second node N2. The holding capacitor Chd ensures that the voltage at the second node N2 of the first transistor T1 does not fluctuate and has a constant voltage when the surrounding signal fluctuates.

[0079] A light-emitting diode (LED) may include a pixel electrode electrically connected to a second node N2 and a common electrode above the pixel electrode, and the common electrode may receive a common voltage ELVSS. The common electrode may be integrated for multiple LEDs.

[0080] exist Figure 3 In this embodiment, the subpixel circuit PC includes six transistors and two capacitors, but this disclosure is not limited thereto. For example, the subpixel circuit PC may include five transistors and two capacitors. The subpixel circuit PC may also include seven transistors and one capacitor.

[0081] Figure 4 This is a schematic cross-sectional view of the display device 1 according to an embodiment.

[0082] Specifically, Figure 4 This is a cross-sectional view of display device 1 in display area DA.

[0083] refer to Figure 4 The display device 1 may include a sub-pixel circuit PC comprising transistors and capacitors disposed on a substrate 100, a first insulating layer IL1 covering the sub-pixel circuit PC, and light-emitting diodes (LEDs) electrically connected to the sub-pixel circuit PC. Additionally, the display device 1 may include a plurality of connection electrodes CE1, CE2, and CE3 disposed in the first insulating layer IL1 and electrically connected to the sub-pixel circuit PC.

[0084] Figure 4 The diagram shows the first transistor T1, the fifth transistor T5, the storage capacitor Cst, and the holding capacitor Chd. Additionally, Figure 4 The first insulating layer IL1 is shown to include a buffer layer 101, a first gate insulating layer 103, a second gate insulating layer 105, a first interlayer insulating layer 107, a third gate insulating layer 109, a second interlayer insulating layer 111, a first organic insulating layer 113, a second organic insulating layer 115, and a third organic insulating layer 117.

[0085] The lower metal layer 1110 may be disposed on the substrate 100. The lower metal layer 1110 may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). For example, the lower metal layer 1110 may have a single-layer structure including Mo, a double-layer structure in which a Mo layer and a Ti layer are laminated, or a triple-layer structure in which a Ti layer, an Al layer, and a Ti layer are laminated.

[0086] The lower metal layer 1110 can have a constant voltage level. For example, the lower metal layer 1110 can have a voltage level similar to the reference mentioned above. Figure 3 The voltage level described is the same as the voltage level of the drive voltage line PL. That is, the drive voltage ELVDD (see...). Figure 3 ) can be applied to the lower metal layer 1110. For this purpose, the lower metal layer 1110 can be applied to the non-display area NDA (see... Figure 1 The electrical connection is, for example, a portion of the drive voltage line PL or the first power supply wiring 15 (see...). Figure 2 The lower metal layer 1110 can at least partially shield the light traveling to the fifth semiconductor layer A5 of the fifth transistor T5, and can protect the fifth transistor T5 from electrostatic discharge (ESD).

[0087] A buffer layer 101 may be disposed on the lower metal layer 1110 to cover the lower metal layer 1110. The buffer layer 101 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The buffer layer 101 may have a single-layer or multi-layer structure.

[0088] A silicon semiconductor layer can be disposed on the buffer layer 101. Figure 4 In the diagram, the fifth transistor T5 is shown as including a silicon semiconductor layer. That is, in... Figure 4 In the diagram, the fifth semiconductor layer A5 included in the fifth transistor T5 is shown located on the buffer layer 101. The fifth semiconductor layer A5 may include a channel region C5 and doped regions S5 and D5, which are doped with impurities and respectively disposed on opposite sides of the channel region C5. One of the doped regions S5 and D5 of the fifth semiconductor layer A5 may be a source region, and the other may be a drain region.

[0089] A first gate insulating layer 103 may be disposed on the fifth semiconductor layer A5 to cover the fifth semiconductor layer A5. The first gate insulating layer 103 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The first gate insulating layer 103 may have a single-layer or multi-layer structure.

[0090] The fifth gate electrode G5 may be disposed on the first gate insulating layer 103. The fifth gate electrode G5 may overlap with the channel region C5 of the fifth semiconductor layer A5. In addition to the fifth gate electrode G5, the sublayers (e.g., the first lower holding electrode CEh1a) of the first storage electrode CEs1 of the storage capacitor Cst and the first holding electrode CEh1 of the holding capacitor Chd may be disposed on the first gate insulating layer 103.

[0091] The fifth gate electrode G5, the first storage electrode CEs1 of the storage capacitor Cst, and the first lower holding electrode CEh1a of the holding capacitor Chd may comprise the same material. The fifth gate electrode G5, the first storage electrode CEs1 of the storage capacitor Cst, and the first lower holding electrode CEh1a of the holding capacitor Chd may comprise Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and / or Cu, and may have a single-layer or multi-layer structure comprising these materials. For example, the fifth gate electrode G5, the first storage electrode CEs1 of the storage capacitor Cst, and the first lower holding electrode CEh1a of the holding capacitor Chd may have a single-layer structure comprising Mo or a multi-layer structure comprising Mo / Al / Mo.

[0092] The second gate insulating layer 105 may be disposed on the fifth gate electrode G5, the first storage electrode CEs1 of the storage capacitor Cst, and the first lower holding electrode CEh1a of the holding capacitor Chd to cover them. The second gate insulating layer 105 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The second gate insulating layer 105 may have a single-layer or multi-layer structure. When necessary, the second gate insulating layer 105 may comprise a material different from that of the first gate insulating layer 103. For example, the first gate insulating layer 103 may comprise silicon oxide, and the second gate insulating layer 105 may comprise silicon nitride.

[0093] A conductive layer 1410 (hereinafter referred to as the "fifth conductive layer" for convenience) may be disposed on the second gate insulating layer 105. The fifth conductive layer 1410 may overlap with the first storage electrode CEs1 of the storage capacitor Cst and the first lower holding electrode CEh1a of the holding capacitor Chd. The fifth conductive layer 1410 may include the second storage electrode CEs2 of the storage capacitor Cst and the second holding electrode CEh2 of the holding capacitor Chd. That is, a portion of the fifth conductive layer 1410 may be the second storage electrode CEs2 of the storage capacitor Cst, and another portion of the fifth conductive layer 1410 may be the second holding electrode CEh2 of the holding capacitor Chd. In this way, the second storage electrode CEs2 of the storage capacitor Cst and the second holding electrode CEh2 of the holding capacitor Chd may be integrally provided as a single body.

[0094] The fifth conductive layer 1410 may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W and / or Cu, and may have a single-layer or multi-layer structure including these materials. For example, the fifth conductive layer 1410 may have a single-layer structure including Mo or a multi-layer structure having Mo / Al / Mo.

[0095] The first interlayer insulating layer 107 may be disposed on the fifth conductive layer 1410 to cover the fifth conductive layer 1410. The first interlayer insulating layer 107 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The first interlayer insulating layer 107 may have a single-layer or multi-layer structure. For example, the first interlayer insulating layer 107 may have a laminated structure comprising a layer comprising silicon oxide and a layer comprising silicon nitride.

[0096] The first semiconductor layer A1 of the first transistor T1 and the first upper holding electrode CEh1b of the holding capacitor Chd can be disposed on the first interlayer insulating layer 107. The first semiconductor layer A1 of the first transistor T1 and the first upper holding electrode CEh1b of the holding capacitor Chd can comprise the same material. Specifically, the first semiconductor layer A1 of the first transistor T1 and the first upper holding electrode CEh1b of the holding capacitor Chd can comprise an oxide semiconductor. The oxide semiconductor can be an oxide semiconductor comprising at least one element selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), Cr, Ti, Al, cesium (Cs), cerium (Ce), and zinc (Zn). For example, the oxide semiconductor can comprise InSnZnO (ITZO) or InGaZnO (IGZO).

[0097] The first semiconductor layer A1 may include a channel region C1 and conductive doped regions S1 and D1 disposed on opposite sides of the channel region C1. One of the doped regions S1 and D1 may be a source region, and the other may be a drain region. The first semiconductor layer A1 may be disposed on a different layer than the fifth semiconductor layer A5 described above. The vertical distance from the substrate 100 to the first semiconductor layer A1 may be greater than the vertical distance from the substrate 100 to the fifth semiconductor layer A5.

[0098] The first upper holding electrode CEh1b of the holding capacitor Chd may overlap with the fifth conductive layer 1410 and the first lower holding electrode CEh1a of the holding capacitor Chd below the fifth conductive layer 1410. The first upper holding electrode CEh1b of the holding capacitor Chd may be electrically connected to the first lower holding electrode CEh1a.

[0099] The third gate insulating layer 109 may be disposed on the first semiconductor layer A1 and the first holding electrode CEh1b of the holding capacitor Chd to cover them. The third gate insulating layer 109 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The third gate insulating layer 109 may have a single-layer or multi-layer structure. For example, the third gate insulating layer 109 may have a single-layer structure comprising silicon oxide.

[0100] although Figure 4 The diagram shows a third gate insulating layer 109 extending through the side surface of the first semiconductor layer A1 and contacting the upper surface of the first interlayer insulating layer 107, but this disclosure is not limited thereto. For example, the third gate insulating layer 109 may have a pattern and / or width substantially the same as the pattern and / or width of the first gate electrode G1 described below. That is, after forming an insulating layer for forming the third gate insulating layer 109 and forming a conductive layer for forming the first gate electrode G1 on the insulating layer, the insulating layer and the conductive layer may be simultaneously patterned to the same shape to form the third gate insulating layer 109 and the first gate electrode G1. In this case, the third gate insulating layer 109 may not contact the upper surface of the first interlayer insulating layer 107.

[0101] The first gate electrode G1 may be disposed on the third gate insulating layer 109. The first gate electrode G1 may overlap with the channel region C1 of the first semiconductor layer A1. The first gate electrode G1 may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W and / or Cu, and may have a single-layer or multi-layer structure comprising these materials. For example, the first gate electrode G1 may have a three-layer structure of Ti layer / Al layer / Ti layer.

[0102] The second interlayer insulating layer 111 may be disposed on the first gate electrode G1 to cover the first gate electrode G1. The second interlayer insulating layer 111 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The second interlayer insulating layer 111 may have a single-layer or multi-layer structure. For example, the second interlayer insulating layer 111 may have a laminated structure comprising a layer comprising silicon oxide and a layer comprising silicon oxynitride.

[0103] The first connecting electrode CE1 can be disposed on the second interlayer insulating layer 111. The first connecting electrode CE1 can be electrically connected to the sub-pixel circuit PC. The first connecting electrode CE1 can be electrically connected to at least one of the first transistor T1, the fifth transistor T5, and the holding capacitor Chd. The first connecting electrode CE1 can include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and / or Cu, and can have a single-layer or multi-layer structure including these materials. For example, the first connecting electrode CE1 can have a three-layer structure of Ti layer / Al layer / Ti layer.

[0104] A first organic insulating layer 113 may be disposed on the first connecting electrode CE1 to cover the first connecting electrode CE1. The first organic insulating layer 113 may include organic insulating materials such as acrylic acid, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0105] The data line DL, the initialization voltage line VL, and the second connection electrode CE2, electrically connected to the first connection electrode CE1, can be disposed on the first organic insulating layer 113. The data line DL, the initialization voltage line VL, and the second connection electrode CE2 can comprise Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and / or Cu, and can have a single-layer or multi-layer structure comprising these materials. For example, the data line DL, the initialization voltage line VL, and the second connection electrode CE2 can have a three-layer structure of Ti layer / Al layer / Ti layer.

[0106] A second organic insulating layer 115 may be disposed on the data line DL, the initialization voltage line VL, and the second connection electrode CE2 to cover them. The second organic insulating layer 115 may comprise an organic insulating material such as acrylic, BCB, polyimide, or HMDSO.

[0107] A voltage layer 1900 and a third connection electrode CE3 electrically connected to the second connection electrode CE2 can be disposed on the second organic insulating layer 115. The voltage layer 1900 can have a voltage level corresponding to the driving voltage line PL. The voltage layer 1900 and the third connection electrode CE3 can comprise Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and / or Cu, and can have a single-layer or multi-layer structure comprising these materials. For example, the voltage layer 1900 and the third connection electrode CE3 can have a three-layer structure of Ti layer / Al layer / Ti layer.

[0108] The third organic insulating layer 117 may be disposed on the voltage layer 1900 and the third connecting electrode CE3 to cover the voltage layer 1900 and the third connecting electrode CE3. The third organic insulating layer 117 may include an organic insulating material such as acrylic acid, BCB, polyimide or HMDSO.

[0109] The light-emitting diode (LED) can be disposed on the third organic insulating layer 117. The LED may include a pixel electrode 210, an emitting layer 220, and a common electrode 230 located on the third organic insulating layer 117.

[0110] Pixel electrode 210 can be a (semi-)transparent electrode or a reflective electrode. For example, pixel electrode 210 may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof, and a transparent or semi-transparent electrode layer located on the reflective layer. The transparent or semi-transparent electrode layer may include materials derived from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. x It is selected from at least one of the groups consisting of ZnO or ZnO2, indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). For example, the pixel electrode 210 may have a three-layer structure of ITO / Ag / ITO.

[0111] A dam layer 119 may be disposed on the third organic insulating layer 117. The dam layer 119 may cover the edge of the pixel electrode 210 and increase the distance between the pixel electrode 210 and the common electrode 230, thereby preventing arcing or the like at the edge of the pixel electrode 210. That is, the dam layer 119 may have an opening 119OP to expose the central portion of the pixel electrode 210. The dam layer 119 may be formed by a method such as spin coating and may comprise one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, BCB, and phenolic resin.

[0112] At least a portion of the emitting layer 220 of the light-emitting diode (LED) may be disposed within an opening 119OP defined in the diaphragm layer 119. The emitting region of the LED may be defined by the opening 119OP. The emitting layer 220 may comprise an organic material containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The emitting layer 220 may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be selectively disposed below and above the emitting layer 220.

[0113] The common electrode 230 can be a transparent electrode or a reflective electrode. For example, the common electrode 230 can be a transparent or semi-transparent electrode and can include a thin film of a metal (such as Li, Ca, Al, Ag, Mg) or its compound (e.g., lithium fluoride (LiF)) with a low work function. In addition, the common electrode 230 can further include a transparent conductive oxide (TCO) film containing ITO, IZO, ZnO, ZnO2, or In2O3 located on the metal thin film.

[0114] The common electrode 230 can be integrally formed as a single body across the entire surface of the display area DA to cover the display area DA, and can be disposed throughout the emitting layer 220 and the embankment layer 119. That is, the pixel electrodes 210 can be configured to correspond to light-emitting diodes (LEDs) respectively, and the common electrode 230 can be integrally formed as a single body to correspond to multiple light-emitting diodes (LEDs). Multiple light-emitting diodes (LEDs) can share the common electrode 230, and the laminated structure of the pixel electrode 210, the emitting layer 220, and the common electrode 230 can correspond to the light-emitting diodes (LEDs).

[0115] When needed, an encapsulation layer can be disposed on the light-emitting diode (LED). The encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer located therebetween.

[0116] Figures 5 to 9 This is a schematic plan view of the display device 1 according to an embodiment.

[0117] Specifically, Figures 5 to 9 This is a plan view of display device 1, illustrating the correspondence between a single pixel P in the display area DA (e.g., with...). Figure 2 The component corresponding to area A shown in the diagram.

[0118] For ease of explanation, Figures 5 to 9 The image shows only the sub-pixel circuit, the first connecting electrode CE1, the second connecting electrode CE2, the third connecting electrode CE3, the pixel electrode 210, and the emitter layer 220. In the overlapping positions of the components, the components located below are shown with lighter lines.

[0119] First, refer to Figure 5 The display device 1 may include a first sub-pixel circuit PC1, a second sub-pixel circuit PC2, a third sub-pixel circuit PC3, a fourth sub-pixel circuit PC4, a fifth sub-pixel circuit PC5, a sixth sub-pixel circuit PC6, a seventh sub-pixel circuit PC7, and an eighth sub-pixel circuit PC8 (collectively referred to herein as "first to eighth sub-pixel circuits PC1 to PC8"). In this case, the first to eighth sub-pixel circuits PC1 to PC8 may overlap with the display area DA, but may not overlap with the non-display area NDA (see [reference]). Figure 1 The first to eighth sub-pixel circuits PC1 to PC8 can be sequentially disposed on the substrate 100 in a first direction (e.g., the x-axis direction) (see [reference]). Figure 4 The first to eighth sub-pixel circuits PC1 to PC8 can each correspond to a reference. Figure 3 The described sub-pixel circuit PC (see Figure 3 Furthermore, the first to eighth sub-pixel circuits PC1 to PC8 can each include a driving transistor and a switching transistor. Because the first to eighth sub-pixel circuits PC1 to PC8 are provided in a structure (vertical fused pixel (VFP) structure) arranged sequentially in a first direction (e.g., the x-axis direction), the space efficiency of the first to eighth sub-pixel circuits PC1 to PC8 can be improved.

[0120] like Figure 5 As shown, the areas where the first to eighth sub-pixel circuits PC1 to PC8 are respectively located in the plan view can be simplified and shown in a rectangular shape. This rectangular shape is actually a simplified representation of the physical layout structure of the first to eighth sub-pixel circuits PC1 to PC8, and may not exactly match the actual shape of the first to eighth sub-pixel circuits PC1 to PC8.

[0121] In this case, in the planar diagram, the first to eighth sub-pixel circuits PC1 to PC8 can each have a rectangular shape where one side is longer than the other. For example, as Figure 5 As shown, the first to eighth sub-pixel circuits PC1 to PC8 can each have a rectangular shape with a length in a first direction (e.g., the x-axis direction) that is less than the length in a second direction (e.g., the y-axis direction). Because the first to eighth sub-pixel circuits PC1 to PC8 are arranged sequentially in the first direction (e.g., the x-axis direction), the overall shape of the first to eighth sub-pixel circuits PC1 to PC8 can be relatively closer to a square shape compared to the individual shapes of the first to eighth sub-pixel circuits PC1 to PC8.

[0122] First insulating layer IL1 (see...) Figure 4 ) can be set on substrate 100 (see Figure 4 The first to eighth sub-pixel circuits PC1 to PC8 are covered on top. A first insulating layer IL1 provides electrical insulation (see [link]). Figure 4 The buffer layer 101 can fully cover the area where the first to eighth sub-pixel circuits PC1 to PC8 are located, thereby preventing interference between the circuits and protecting each circuit from the influence of the external environment. Specifically, the buffer layer 101 (see...) Figure 4 ), first gate insulating layer 103 (see Figure 4 ), second gate insulation layer 105 (see Figure 4), first interlayer insulation layer 107 (see Figure 4 ), third gate insulation layer 109 (see Figure 4 ) and the second interlayer insulation layer 111 (see Figure 4 It can cover the first to eighth sub-pixel circuits PC1 to PC8.

[0123] The first connecting electrode CE1 can be disposed in the first insulating layer IL1 (see...). Figure 4 (Specifically, the second interlayer insulation layer 111 (see...) Figure 4 The first connecting electrode CE1 can be electrically connected to the first to eighth sub-pixel circuits PC1 to PC8. The first connecting electrode CE1 can contact the first to eighth sub-pixel circuits PC1 to PC8 through the first contact hole CNT1, which extends through the first insulating layer IL1 (see...). Figure 4 (Specifically, the first gate insulating layer 103 (see...) Figure 4 ), second gate insulation layer 105 (see Figure 4 ), first interlayer insulation layer 107 (see Figure 4 ), third gate insulation layer 109 (see Figure 4 ) and the second interlayer insulation layer 111 (see Figure 4 At least one of the following, which is simply described below as "second interlayer insulation layer 111" (see Figure 4 )”).

[0124] The first connecting electrode CE1 may include first-1 to first-8 connecting electrodes CE1-1 to CE1-8 corresponding to the first to eighth sub-pixel circuits PC1 to PC8, respectively. The first contact hole CNT1 may include first-1 to first-8 contact holes CNT1-1 to CNT1-8 corresponding to the first to eighth sub-pixel circuits PC1 to PC8, respectively.

[0125] The first-1 connecting electrode CE1-1 may be located at a position where at least a portion of the first-1 connecting electrode CE1-1 overlaps with the first sub-pixel circuit PC1. The first-1 contact hole CNT1-1 may extend through the first insulating layer IL1 at each overlapping position with the first sub-pixel circuit PC1 and the first-1 connecting electrode CE1-1 (see...). Figure 4 (Specifically, the second interlayer insulation layer 111 (see...) Figure 4 (etc.). The first-1 connecting electrode CE1-1 can contact the first sub-pixel circuit PC1 through the first-1 contact hole CNT1-1.

[0126] The first-2 connecting electrode CE1-2 may be located at a position where at least a portion of the first-2 connecting electrode CE1-2 overlaps with the second sub-pixel circuit PC2. The first-2 contact hole CNT1-2 may extend through the first insulating layer IL1 at each overlapping position with the second sub-pixel circuit PC2 and the first-2 connecting electrode CE1-2 (see...). Figure 4 (Specifically, the second interlayer insulation layer 111 (see...) Figure 4 (etc.). The first-2 connecting electrode CE1-2 can contact the second sub-pixel circuit PC2 through the first-2 contact hole CNT1-2.

[0127] The first-3 connecting electrode CE1-3 may be located at a position where at least a portion of the first-3 connecting electrode CE1-3 overlaps with the third sub-pixel circuit PC3. The first-3 contact hole CNT1-3 may extend through the first insulating layer IL1 at each overlapping position with the third sub-pixel circuit PC3 and the first-3 connecting electrode CE1-3 (see...). Figure 4 (Specifically, the second interlayer insulation layer 111 (see...) Figure 4 (etc.). The first-3 connecting electrode CE1-3 can contact the third sub-pixel circuit PC3 through the first-3 contact hole CNT1-3.

[0128] The first-4 connecting electrode CE1-4 may be located at a position where at least a portion of the first-4 connecting electrode CE1-4 overlaps with the fourth sub-pixel circuit PC4. The first-4 contact hole CNT1-4 may extend through the first insulating layer IL1 at each overlapping position with the fourth sub-pixel circuit PC4 and the first-4 connecting electrode CE1-4 (see...). Figure 4 (Specifically, the second interlayer insulation layer 111 (see...) Figure 4 (etc.). The first-4 connecting electrode CE1-4 can contact the fourth sub-pixel circuit PC4 through the first-4 contact hole CNT1-4.

[0129] The first-5 connecting electrode CE1-5 may be located at a position where at least a portion of the first-5 connecting electrode CE1-5 overlaps with the fifth sub-pixel circuit PC5. The first-5 contact hole CNT1-5 may extend through the first insulating layer IL1 at each overlapping position with the fifth sub-pixel circuit PC5 and the first-5 connecting electrode CE1-5 (see...). Figure 4 (Specifically, the second interlayer insulation layer 111 (see...) Figure 4 (etc.). The first-5 connecting electrode CE1-5 can contact the fifth sub-pixel circuit PC5 through the first-5 contact hole CNT1-5.

[0130] The first-6 connecting electrode CE1-6 may be located at a position where at least a portion of the first-6 connecting electrode CE1-6 overlaps with the sixth sub-pixel circuit PC6. The first-6 contact hole CNT1-6 may extend through the first insulating layer IL1 at each overlapping position with the sixth sub-pixel circuit PC6 and the first-6 connecting electrode CE1-6 (see...). Figure 4 (Specifically, the second interlayer insulation layer 111 (see...) Figure 4 (etc.). The first-6 connecting electrode CE1-6 can contact the sixth sub-pixel circuit PC6 through the first-6 contact hole CNT1-6.

[0131] The first-7 connecting electrode CE1-7 may be located at a position where at least a portion of the first-7 connecting electrode CE1-7 overlaps with the seventh sub-pixel circuit PC7. The first-7 contact hole CNT1-7 may extend through the first insulating layer IL1 at each overlapping position with the seventh sub-pixel circuit PC7 and the first-7 connecting electrode CE1-7 (see...). Figure 4 (Specifically, the second interlayer insulation layer 111 (see...) Figure 4 (etc.). The first-7 connecting electrode CE1-7 can contact the seventh sub-pixel circuit PC7 through the first-7 contact hole CNT1-7.

[0132] The first-8 connecting electrode CE1-8 may be located at a position where at least a portion of the first-8 connecting electrode CE1-8 overlaps with the eighth sub-pixel circuit PC8. The first-8 contact hole CNT1-8 may extend through the first insulating layer IL1 at each overlapping position with the eighth sub-pixel circuit PC8 and the first-8 connecting electrode CE1-8 (see...). Figure 4 (Specifically, the second interlayer insulation layer 111 (see...) Figure 4 (etc.). The first-8 connecting electrode CE1-8 can contact the eighth sub-pixel circuit PC8 through the first-8 contact hole CNT1-8.

[0133] The shapes of the first-1 to first-8 connecting electrodes CE1-1 to CE1-8 can be designed in various ways to take into account requirements (such as interference with other wiring and / or signal lines).

[0134] First insulating layer IL1 (see...) Figure 4 The first connecting electrode CE1 can be covered. Specifically, the first organic insulating layer 113 (see...) Figure 4 It can be set in the second interlayer insulation layer 111 (see Figure 4 The first connecting electrode CE1 is covered on top.

[0135] refer to Figure 6 The second connecting electrode CE2 can be disposed in the first insulating layer IL1 (see...). Figure 4 (Specifically, the first organic insulating layer 113 (see...) Figure 4 The second connecting electrode CE2 can be electrically connected to the first connecting electrode CE1. The second connecting electrode CE2 can be extended through the first insulating layer IL1 (see...). Figure 4 (Specifically, the first organic insulating layer 113 (see...) Figure 4 The second contact hole CNT2 is in contact with the first connecting electrode CE1.

[0136] The second connecting electrode CE2 may include second connecting electrodes CE2-1 to CE2-8, which correspond to the first connecting electrodes CE1-1 to CE1-8 respectively. The second contact hole CNT2 may include second contact holes CNT2-1 to CNT2-8, which correspond to the first connecting electrodes CE1-1 to CE1-8 respectively.

[0137] The second-1 connecting electrode CE2-1 may be located at a position where at least a portion of the second-1 connecting electrode CE2-1 overlaps with the first-1 connecting electrode CE1-1. The second-1 contact hole CNT2-1 may extend through the first insulating layer IL1 at each overlapping position with the first-1 connecting electrode CE1-1 and the second-1 connecting electrode CE2-1 (see...). Figure 4 (Specifically, the first organic insulating layer 113 (see...) Figure 4 The second-1 connecting electrode CE2-1 can contact the first-1 connecting electrode CE1-1 through the second-1 contact hole CNT2-1.

[0138] The second-2 connecting electrode CE2-2 may be located at a position where at least a portion of the second-2 connecting electrode CE2-2 overlaps with the first-2 connecting electrode CE1-2. The second-2 contact hole CNT2-2 may extend through the first insulating layer IL1 at each overlapping position with the first-2 connecting electrode CE1-2 and the second-2 connecting electrode CE2-2 (see...). Figure 4 (Specifically, the first organic insulating layer 113 (see...) Figure 4 The second-2 connecting electrode CE2-2 can contact the first-2 connecting electrode CE1-2 through the second-2 contact hole CNT2-2.

[0139] The second-3 connecting electrode CE2-3 may be located at a position where at least a portion of the second-3 connecting electrode CE2-3 overlaps with the first-3 connecting electrode CE1-3. The second-3 contact hole CNT2-3 may extend through the first insulating layer IL1 at each overlapping position with either the first-3 connecting electrode CE1-3 or the second-3 connecting electrode CE2-3 (see...). Figure 4(Specifically, the first organic insulating layer 113 (see...) Figure 4 The second-3 connecting electrode CE2-3 can contact the first-3 connecting electrode CE1-3 through the second-3 contact hole CNT2-3.

[0140] The second-4 connecting electrode CE2-4 may be located at a position where at least a portion of the second-4 connecting electrode CE2-4 overlaps with the first-4 connecting electrode CE1-4. The second-4 contact hole CNT2-4 may extend through the first insulating layer IL1 at each overlapping position with either the first-4 connecting electrode CE1-4 or the second-4 connecting electrode CE2-4 (see...). Figure 4 (Specifically, the first organic insulating layer 113 (see...) Figure 4 The second-4 connecting electrode CE2-4 can contact the first-4 connecting electrode CE1-4 through the second-4 contact hole CNT2-4.

[0141] The second-5 connecting electrode CE2-5 may be located at a position where at least a portion of the second-5 connecting electrode CE2-5 overlaps with the first-5 connecting electrode CE1-5. The second-5 contact hole CNT2-5 may extend through the first insulating layer IL1 at each overlapping position with the first-5 connecting electrode CE1-5 and the second-5 connecting electrode CE2-5 (see...). Figure 4 (Specifically, the first organic insulating layer 113 (see...) Figure 4 The second-5 connecting electrode CE2-5 can contact the first-5 connecting electrode CE1-5 through the second-5 contact hole CNT2-5.

[0142] The second-6 connecting electrode CE2-6 may be located at a position where at least a portion of the second-6 connecting electrode CE2-6 overlaps with the first-6 connecting electrode CE1-6. The second-6 contact hole CNT2-6 may extend through the first insulating layer IL1 at each overlapping position with the first-6 connecting electrode CE1-6 and the second-6 connecting electrode CE2-6 (see...). Figure 4 (Specifically, the first organic insulating layer 113 (see...) Figure 4 The second-6 connecting electrode CE2-6 can contact the first-6 connecting electrode CE1-6 through the second-6 contact hole CNT2-6.

[0143] The second-7 connecting electrode CE2-7 may be located at a position where at least a portion of the second-7 connecting electrode CE2-7 overlaps with the first-7 connecting electrode CE1-7. The second-7 contact hole CNT2-7 may extend through the first insulating layer IL1 at each overlapping position with the first-7 connecting electrode CE1-7 and the second-7 connecting electrode CE2-7 (see...). Figure 4(Specifically, the first organic insulating layer 113 (see...) Figure 4 The second-7 connecting electrode CE2-7 can contact the first-7 connecting electrode CE1-7 through the second-7 contact hole CNT2-7.

[0144] The second-8 connecting electrode CE2-8 may be located at a position where at least a portion of the second-8 connecting electrode CE2-8 overlaps with the first-8 connecting electrode CE1-8. The second-8 contact hole CNT2-8 may extend through the first insulating layer IL1 at each overlapping position with the first-8 connecting electrode CE1-8 and the second-8 connecting electrode CE2-8 (see...). Figure 4 (Specifically, the first organic insulating layer 113 (see...) Figure 4 The second-8 connecting electrode CE2-8 can contact the first-8 connecting electrode CE1-8 through the second-8 contact hole CNT2-8.

[0145] The shapes of the second-1 to second-8 connecting electrodes CE2-1 to CE2-8 can be designed in various ways to take into account requirements (such as interference with other wiring and / or signal lines).

[0146] First insulating layer IL1 (see...) Figure 4 The second organic insulating layer 115 can cover the second connecting electrode CE2. Specifically, the second organic insulating layer 115 (see...) Figure 4 ) can be disposed in the first organic insulating layer 113 (see Figure 4 The second connecting electrode CE2 is covered on top.

[0147] refer to Figure 7 The third connecting electrode CE3 can be disposed in the first insulating layer IL1 (see Figure 4 (Specifically, the second organic insulating layer 115 (see...) Figure 4 The third connecting electrode CE3 can be electrically connected to the second connecting electrode CE2. The third connecting electrode CE3 can be extended through the first insulating layer IL1 (see...). Figure 4 (Specifically, the second organic insulating layer 115 (see...) Figure 4 The third contact hole CNT3 is in contact with the second connecting electrode CE2.

[0148] The third connecting electrode CE3 may include third connecting electrodes CE3-1 to CE3-8, which correspond to the second connecting electrodes CE2-1 to CE2-8 respectively. The third contact hole CNT3 may include third contact holes CNT3-1 to CNT3-8, which correspond to the second connecting electrodes CE2-1 to CE2-8 respectively.

[0149] The third-1 connecting electrode CE3-1 may be located at a position where at least a portion of the third-1 connecting electrode CE3-1 overlaps with the second-1 connecting electrode CE2-1. The third-1 contact hole CNT3-1 may extend through the first insulating layer IL1 at each overlapping position with the second-1 connecting electrode CE2-1 and the third-1 connecting electrode CE3-1 (see...). Figure 4 (Specifically, the second organic insulating layer 115 (see...) Figure 4 The third-1 connecting electrode CE3-1 can contact the second-1 connecting electrode CE2-1 through the third-1 contact hole CNT3-1.

[0150] The third-2 connecting electrode CE3-2 may be located at a position where at least a portion of the third-2 connecting electrode CE3-2 overlaps with the second-2 connecting electrode CE2-2. The third-2 contact hole CNT3-2 may extend through the first insulating layer IL1 at each of the overlapping positions with the second-2 connecting electrode CE2-2 and the third-2 connecting electrode CE3-2 (see...). Figure 4 (Specifically, the second organic insulating layer 115 (see...) Figure 4 The third-2 connecting electrode CE3-2 can contact the second-2 connecting electrode CE2-2 through the third-2 contact hole CNT3-2.

[0151] The third-3 connecting electrode CE3-3 may be located at a position where at least a portion of the third-3 connecting electrode CE3-3 overlaps with the second-3 connecting electrode CE2-3. The third-3 contact hole CNT3-3 may extend through the first insulating layer IL1 at each of the overlapping positions with the second-3 connecting electrode CE2-3 and the third-3 connecting electrode CE3-3 (see...). Figure 4 (Specifically, the second organic insulating layer 115 (see...) Figure 4 The third-3 connecting electrode CE3-3 can contact the second-3 connecting electrode CE2-3 through the third-3 contact hole CNT3-3.

[0152] The third-4 connecting electrode CE3-4 may be located at a position where at least a portion of the third-4 connecting electrode CE3-4 overlaps with the second-4 connecting electrode CE2-4. The third-4 contact hole CNT3-4 may extend through the first insulating layer IL1 at each of the overlapping positions with the second-4 connecting electrode CE2-4 and the third-4 connecting electrode CE3-4 (see...). Figure 4 (Specifically, the second organic insulating layer 115 (see...) Figure 4 The third-4 connecting electrode CE3-4 can contact the second-4 connecting electrode CE2-4 through the third-4 contact hole CNT3-4.

[0153] The third-5 connecting electrode CE3-5 may be located at a position where at least a portion of the third-5 connecting electrode CE3-5 overlaps with the second-5 connecting electrode CE2-5. The third-5 contact hole CNT3-5 may extend through the first insulating layer IL1 at each overlapping position with the second-5 connecting electrode CE2-5 and the third-5 connecting electrode CE3-5 (see...). Figure 4 (Specifically, the second organic insulating layer 115 (see...) Figure 4 The third-5 connecting electrode CE3-5 can contact the second-5 connecting electrode CE2-5 through the third-5 contact hole CNT3-5.

[0154] The third-6 connecting electrode CE3-6 may be located at a position where at least a portion of the third-6 connecting electrode CE3-6 overlaps with the second-6 connecting electrode CE2-6. The third-6 contact hole CNT3-6 may extend through the first insulating layer IL1 at each overlapping position with either the second-6 connecting electrode CE2-6 or the third-6 connecting electrode CE3-6 (see...). Figure 4 (Specifically, the second organic insulating layer 115 (see...) Figure 4 The third-6 connecting electrode CE3-6 can contact the second-6 connecting electrode CE2-6 through the third-6 contact hole CNT3-6.

[0155] The third-7 connecting electrode CE3-7 may be located at a position where at least a portion of the third-7 connecting electrode CE3-7 overlaps with the second-7 connecting electrode CE2-7. The third-7 contact hole CNT3-7 may extend through the first insulating layer IL1 at each of the overlapping positions with the second-7 connecting electrode CE2-7 and the third-7 connecting electrode CE3-7 (see...). Figure 4 (Specifically, the second organic insulating layer 115 (see...) Figure 4 The third-7 connecting electrode CE3-7 can contact the second-7 connecting electrode CE2-7 through the third-7 contact hole CNT3-7.

[0156] The third-8 connecting electrode CE3-8 may be located at a position where at least a portion of the third-8 connecting electrode CE3-8 overlaps with the second-8 connecting electrode CE2-8. The third-8 contact hole CNT3-8 may extend through the first insulating layer IL1 at each overlapping position with either the second-8 connecting electrode CE2-8 or the third-8 connecting electrode CE3-8 (see...). Figure 4 (Specifically, the second organic insulating layer 115 (see...) Figure 4 The third-8 connecting electrode CE3-8 can contact the second-8 connecting electrode CE2-8 through the third-8 contact hole CNT3-8.

[0157] The shapes of the third-1 to third-8 connecting electrodes CE3-1 to CE3-8 can be designed in various ways to take into account requirements (such as interference with other wiring and / or signal lines).

[0158] First insulating layer IL1 (see...) Figure 4 The third connecting electrode CE3 can be covered. Specifically, the third organic insulating layer 117 (see...) Figure 4 ) can be disposed in the second organic insulating layer 115 (see Figure 4 The third connecting electrode CE3 is covered on top.

[0159] refer to Figure 8 The pixel electrode 210 can be located in the first insulating layer IL1 (see...) Figure 4 (Specifically, the third organic insulating layer 117 (see...) Figure 4 The pixel electrodes 210 are spaced apart from each other. The pixel electrodes 210 can be electrically connected to the third connection electrode CE3. The pixel electrodes 210 can be extended through the first insulating layer IL1 (e.g., the third organic insulating layer 117 (see...)). Figure 4 At least a portion (not explicitly shown) of the fourth contact hole CNT4 is in contact with the third connecting electrode CE3.

[0160] Pixel electrode 210 may include first to eighth pixel electrodes 210-1 to 210-8, respectively corresponding to the third-1 to third-8 connecting electrodes CE3-1 to CE3-8. Fourth contact hole CNT4 may include fourth-1 to fourth-8 contact holes CNT4-1 to CNT4-8, respectively corresponding to the third-1 to third-8 connecting electrodes CE3-1 to CE3-8. With this structure, the first to eighth sub-pixel circuits PC1 to PC8 can be electrically connected to a corresponding one of the pixel electrodes 210.

[0161] The first pixel electrode 210-1 may be located at a position where at least a portion of the first pixel electrode 210-1 overlaps with the third-1 connecting electrode CE3-1. The fourth-1 contact hole CNT4-1 may extend through the first insulating layer IL1 at each overlapping position with the third-1 connecting electrode CE3-1 and the first pixel electrode 210-1 (see...). Figure 4 (Specifically, the third organic insulating layer 117 (see...) Figure 4 The first pixel electrode 210-1 can contact the third connecting electrode CE3-1 through the fourth contact hole CNT4-1.

[0162] The second pixel electrode 210-2 may be located at a position where at least a portion of the second pixel electrode 210-2 overlaps with the third-2 connecting electrode CE3-2. The fourth-2 contact hole CNT4-2 may extend through the first insulating layer IL1 at each overlapping position with the third-2 connecting electrode CE3-2 and the second pixel electrode 210-2 (see...). Figure 4 (Specifically, the third organic insulating layer 117 (see...) Figure 4 The second pixel electrode 210-2 can contact the third connecting electrode CE3-2 through the fourth contact hole CNT4-2.

[0163] The third pixel electrode 210-3 may be located at a position where at least a portion of the third pixel electrode 210-3 overlaps with the third-3 connecting electrode CE3-3. The fourth-3 contact hole CNT4-3 may extend through the first insulating layer IL1 at each overlapping position with the third-3 connecting electrode CE3-3 and the third pixel electrode 210-3 (see...). Figure 4 (Specifically, the third organic insulating layer 117 (see...) Figure 4 The third pixel electrode 210-3 can contact the third connecting electrode CE3-3 through the fourth contact hole CNT4-3.

[0164] The fourth pixel electrode 210-4 may be located at a position where at least a portion of the fourth pixel electrode 210-4 overlaps with the third-4 connecting electrode CE3-4. The fourth-4 contact hole CNT4-4 may extend through the first insulating layer IL1 at each overlapping position with the third-4 connecting electrode CE3-4 and the fourth pixel electrode 210-4 (see [reference]). Figure 4 (Specifically, the third organic insulating layer 117 (see...) Figure 4 The fourth pixel electrode 210-4 can contact the third connecting electrode CE3-4 through the fourth-4 contact hole CNT4-4.

[0165] The fifth pixel electrode 210-5 may be located at a position where at least a portion of the fifth pixel electrode 210-5 overlaps with the third-5 connecting electrode CE3-5. The fourth-5 contact hole CNT4-5 may extend through the first insulating layer IL1 at each overlapping position with the third-5 connecting electrode CE3-5 and the fifth pixel electrode 210-5 (see...). Figure 4 (Specifically, the third organic insulating layer 117 (see...) Figure 4 The fifth pixel electrode 210-5 can contact the third connecting electrode CE3-5 through the fourth contact hole CNT4-5.

[0166] The sixth pixel electrode 210-6 may be located at a position where at least a portion of the sixth pixel electrode 210-6 overlaps with the third-6 connecting electrode CE3-6. The fourth-6 contact hole CNT4-6 may extend through the first insulating layer IL1 at each overlapping position with the third-6 connecting electrode CE3-6 and the sixth pixel electrode 210-6 (see...). Figure 4 (Specifically, the third organic insulating layer 117 (see...) Figure 4 The sixth pixel electrode 210-6 can contact the third-6 connecting electrode CE3-6 through the fourth-6 contact hole CNT4-6.

[0167] The seventh pixel electrode 210-7 may be located at a position where at least a portion of the seventh pixel electrode 210-7 overlaps with the third-7 connecting electrode CE3-7. The fourth-7 contact hole CNT4-7 may extend through the first insulating layer IL1 at each overlapping position with the third-7 connecting electrode CE3-7 and the seventh pixel electrode 210-7 (see...). Figure 4 (Specifically, the third organic insulating layer 117 (see...) Figure 4 The seventh pixel electrode 210-7 can contact the third-7 connecting electrode CE3-7 through the fourth-7 contact hole CNT4-7.

[0168] The eighth pixel electrode 210-8 may be located at a position where at least a portion of the eighth pixel electrode 210-8 overlaps with the third-8 connecting electrode CE3-8. The fourth-8 contact hole CNT4-8 may extend through the first insulating layer IL1 at each overlapping position with the third-8 connecting electrode CE3-8 and the eighth pixel electrode 210-8 (see...). Figure 4 (Specifically, the third organic insulating layer 117 (see...) Figure 4 The eighth pixel electrode 210-8 can contact the third-8 connecting electrode CE3-8 through the fourth-8 contact hole CNT4-8.

[0169] The shapes of the first to eighth pixel electrodes 210-1 to 210-8 can be designed in various ways to take into account requirements (such as interference with other wiring and / or signal lines).

[0170] refer to Figure 8 and Figure 9 The emission layers 220 can be disposed on the pixel electrodes 210 respectively, thus being spaced apart from each other. The emission layers 220 can be disposed on the pixel electrodes 210 in a one-to-one correspondence. The emission layers 220 can contact the pixel electrodes 210 and be electrically connected to the pixel electrodes 210.

[0171] The first sub-pixel circuit PC1 and the seventh sub-pixel circuit PC7 can receive data signals of light of the same color (e.g., red). The second sub-pixel circuit PC2, the fourth sub-pixel circuit PC4, the sixth sub-pixel circuit PC6, and the eighth sub-pixel circuit PC8 can receive data signals of light of the same color (e.g., green). The third sub-pixel circuit PC3 and the fifth sub-pixel circuit PC5 can receive data signals of light of the same color (e.g., blue). With this structure, the first sub-pixel circuit PC1, the second sub-pixel circuit PC2, and the third sub-pixel circuit PC3 can receive data signals of light of different colors from each other.

[0172] The emitting layer 220 may include first to eighth emitting layers 220-1 to 220-8, respectively, corresponding to the first to eighth pixel electrodes 210-1 to 210-8. The emitting layer 220 may be configured in a PenTile structure. For example, the first emitting layer 220-1 may emit red light, the second emitting layer 220-2 may emit green light, the third emitting layer 220-3 may emit blue light, the fourth emitting layer 220-4 may emit green light, the fifth emitting layer 220-5 may emit blue light, the sixth emitting layer 220-6 may emit green light, the seventh emitting layer 220-7 may emit red light, and the eighth emitting layer 220-8 may emit green light. When the emitting layers 220 emitting green light with relatively good visibility are arranged in high density, the overall color balance of the display device 1 can be maintained while improving energy efficiency.

[0173] A virtual first row, second row, third row, and fourth row can be defined, extending in a first direction (e.g., the x-axis direction) and spaced apart from each other in a second direction (e.g., the y-axis direction). Additionally, a virtual first column, second column, third column, and fourth column can be defined, extending in the second direction (e.g., the y-axis direction) and spaced apart from each other in the first direction (e.g., the x-axis direction).

[0174] like Figure 9 As shown, the third emission layer 220-3 and the seventh emission layer 220-7 can be spaced apart from each other in the first row. In the second row, the fourth emission layer 220-4 and the eighth emission layer 220-8 can be spaced apart from each other. In the third row, the first emission layer 220-1 and the fifth emission layer 220-5 can be spaced apart from each other. In the fourth row, the second emission layer 220-2 and the sixth emission layer 220-6 can be spaced apart from each other.

[0175] Additionally, in the first column, the third emission layer 220-3 and the first emission layer 220-1 can be spaced apart from each other. In the second column, the fourth emission layer 220-4 and the second emission layer 220-2 can be spaced apart from each other. In the third column, the seventh emission layer 220-7 and the fifth emission layer 220-5 can be spaced apart from each other. In the fourth column, the eighth emission layer 220-8 and the sixth emission layer 220-6 can be spaced apart from each other.

[0176] exist Figure 9 In the diagram, the shape of the emission layer 220 is circular in the plan view. However, this is just an example, and the shape of the emission layer 220 can be changed.

[0177] With this structure, the first pixel electrode 210-1 may include a first-1 electrode portion 211-1 and a first-2 electrode portion 212-1. The first-1 electrode portion 211-1 may be configured to overlap with and contact the first emitter layer 220-1. The first-1 electrode portion 211-1 may be provided in a shape corresponding to the first emitter layer 220-1. The first-2 electrode portion 212-1 may connect the first-1 electrode portion 211-1 to the fourth-1 contact hole CNT4-1.

[0178] The second pixel electrode 210-2 may include a second-1 electrode portion 211-2 and a second-2 electrode portion 212-2. The second-1 electrode portion 211-2 may be configured to overlap with and contact the second emission layer 220-2. The second-1 electrode portion 211-2 may be provided in a shape corresponding to the second emission layer 220-2. The second-2 electrode portion 212-2 may connect the second-1 electrode portion 211-2 to the fourth-2 contact hole CNT4-2.

[0179] The third pixel electrode 210-3 may include a third-1 electrode portion 211-3 and a third-2 electrode portion 212-3. The third-1 electrode portion 211-3 may be configured to overlap with and contact the third emission layer 220-3. The third-1 electrode portion 211-3 may be provided in a shape corresponding to the third emission layer 220-3. The third-2 electrode portion 212-3 may connect the third-1 electrode portion 211-3 to the fourth-3 contact hole CNT4-3.

[0180] The fourth pixel electrode 210-4 may include a fourth-1 electrode portion 211-4 and a fourth-2 electrode portion 212-4. The fourth-1 electrode portion 211-4 may be configured to overlap with and contact the fourth emitter layer 220-4. The fourth-1 electrode portion 211-4 may be provided in a shape corresponding to the fourth emitter layer 220-4. The fourth-2 electrode portion 212-4 may connect the fourth-1 electrode portion 211-4 to the fourth-4 contact hole CNT4-4.

[0181] The fifth pixel electrode 210-5 may include a fifth-1 electrode portion 211-5 and a fifth-2 electrode portion 212-5. The fifth-1 electrode portion 211-5 may be configured to overlap with and contact the fifth emitter layer 220-5. The fifth-1 electrode portion 211-5 may be provided in a shape corresponding to the fifth emitter layer 220-5. The fifth-2 electrode portion 212-5 may connect the fifth-1 electrode portion 211-5 to the fourth-5 contact hole CNT4-5.

[0182] The sixth pixel electrode 210-6 may include a sixth-1 electrode portion 211-6 and a sixth-2 electrode portion 212-6. The sixth-1 electrode portion 211-6 may be configured to overlap with and contact the sixth emitter layer 220-6. The sixth-1 electrode portion 211-6 may be provided in a shape corresponding to the sixth emitter layer 220-6. The sixth-2 electrode portion 212-6 may connect the sixth-1 electrode portion 211-6 to the fourth-6 contact hole CNT4-6.

[0183] The seventh pixel electrode 210-7 may include a seventh-1 electrode portion 211-7 and a seventh-2 electrode portion 212-7. The seventh-1 electrode portion 211-7 may be configured to overlap with and contact the seventh emitter layer 220-7. The seventh-1 electrode portion 211-7 may be provided in a shape corresponding to the seventh emitter layer 220-7. The seventh-2 electrode portion 212-7 may connect the seventh-1 electrode portion 211-7 to the fourth-7 contact hole CNT4-7.

[0184] The eighth pixel electrode 210-8 may include an eighth-1 electrode portion 211-8 and an eighth-2 electrode portion 212-8. The eighth-1 electrode portion 211-8 may be configured to overlap with and contact the eighth emitter layer 220-8. The eighth-1 electrode portion 211-8 may be provided in a shape corresponding to the eighth emitter layer 220-8. The eighth-2 electrode portion 212-8 may connect the eighth-1 electrode portion 211-8 to the fourth-8 contact hole CNT4-8.

[0185] The first-2 electrode section 212-1, the second-2 electrode section 212-2, the third-2 electrode section 212-3, the fourth-2 electrode section 212-4, the fifth-2 electrode section 212-5, the sixth-2 electrode section 212-6, the seventh-2 electrode section 212-7, and the eighth-2 electrode section 212-8 can be provided in different shapes to avoid interference with other wiring.

[0186] Common electrode 230 (see) Figure 4 The common electrode 230 (see [reference]) can be disposed on the emitter layer 220. Figure 4 It can overlap with each of the first to eighth sub-pixel circuits PC1 to PC8.

[0187] Figures 10 to 12 This is a schematic plan view of the display device 1 according to an embodiment.

[0188] Specifically, Figures 10 to 12 This is a plan view of display device 1, showing a pixel P corresponding to a position at the boundary between display area DA and non-display area NDA (e.g., with). Figure 2 The component corresponding to area B shown in the diagram.

[0189] exist Figures 10 to 12 In, with Figures 5 to 9 In the accompanying drawings, the same reference numerals denote the same elements, and redundant descriptions are omitted.

[0190] For ease of explanation, Figures 10 to 12 Only the sub-pixel circuit and the first connecting electrode CE1 are shown in the image (see [link]). Figure 5 ), second connecting electrode CE2 (see Figure 6 The third connecting electrode CE3, pixel electrode 210 and emitter layer 220 are shown, and the components located below are shown with lighter lines at the overlapping positions of the components.

[0191] refer to Figure 10 The display device 1 may include first to eighth sub-pixel circuits PC1 to PC8. Each of the first sub-pixel circuit PC1 and the second sub-pixel circuit PC2 may have at least a portion overlapping with the non-display area NDA. Each of the third to eighth sub-pixel circuits PC3 to PC8 may have at least a portion overlapping with the display area DA. For example, each of the first to eighth sub-pixel circuits PC1 to PC8 may overlap with each of the non-display area NDA and the display area DA.

[0192] In a plan view, the boundary between the display area DA and the non-display area NDA can be defined as the first line LN1. For example... Figure 10As shown, at least a portion of the first line LN1 can be provided in a curved shape. For example, the first line LN1 can be provided in a protruding shape oriented from the display area DA toward the non-display area NDA.

[0193] Figure 10 The first to eighth sub-pixel circuits PC1 to PC8 and the first connecting electrode CE1 shown in the figure (see Figure 5 ), second connecting electrode CE2 (see Figure 6 ), Figure 10 The third connecting electrode CE3 shown is Figure 10 The construction of the third contact hole CNT3 shown above has been referenced. Figures 5 to 7 It has been described, and therefore its detailed description will be omitted.

[0194] First insulating layer IL1 (see...) Figure 4 The third connecting electrode CE3 can be covered. Specifically, the third organic insulating layer 117 (see...) Figure 4 ) can be disposed in the second organic insulating layer 115 (see Figure 4 The third connecting electrode CE3 is covered on top.

[0195] refer to Figure 10 and Figure 11 The pixel electrode 210 can be located in the first insulating layer IL1 (see...) Figure 4 (Specifically, the third organic insulating layer 117 (see...) Figure 4 The pixel electrodes 210 are spaced apart from each other. The pixel electrodes 210 can be electrically connected to the third connection electrode CE3. The pixel electrodes 210 can be extended through the first insulating layer IL1 (see...). Figure 4 (Specifically, the third organic insulating layer 117 (see...) Figure 4 The fourth contact hole CNT4 contacts the third connecting electrode CE3.

[0196] Pixel electrode 210 may include third to eighth pixel electrodes 210-3 to 210-8, respectively corresponding to the third to third-8 connecting electrodes CE3-3 to CE3-8. Fourth contact hole CNT4 may include fourth-3 to fourth-8 contact holes CNT4-3 to CNT4-8, respectively corresponding to the third to third-8 connecting electrodes CE3-3 to CE3-8. With this structure, the third to eighth sub-pixel circuits PC3 to PC8 can be electrically connected to a corresponding one of the pixel electrodes 210.

[0197] The third pixel electrode 210-3 can contact the third-3 connecting electrode CE3-3 through the fourth-3 contact hole CNT4-3; the fourth pixel electrode 210-4 can contact the third-4 connecting electrode CE3-4 through the fourth-4 contact hole CNT4-4; the fifth pixel electrode 210-5 can contact the third-5 connecting electrode CE3-5 through the fourth-5 contact hole CNT4-5; the sixth pixel electrode 210-6 can contact the third-6 connecting electrode CE3-6 through the fourth-6 contact hole CNT4-6; the seventh pixel electrode 210-7 can contact the third-7 connecting electrode CE3-7 through the fourth-7 contact hole CNT4-7; and the eighth pixel electrode 210-8 can contact the third-8 connecting electrode CE3-8 through the fourth-8 contact hole CNT4-8.

[0198] Pixel electrode 210 may not be electrically connected to the third-1 connecting electrode CE3-1 and the third-2 connecting electrode CE3-2. (Refer to the above reference.) Figure 8 As described, the fourth contact hole CNT4 may not include the fourth-1 contact hole CNT4-1 and the fourth-2 contact hole CNT4-2. The upper surface of the third-1 connecting electrode CE3-1, electrically connected to the first sub-pixel circuit PC1, can be sealed by the first insulating layer IL1 (specifically, the third organic insulating layer 117). Additionally, the upper surface of the third-2 connecting electrode CE3-2, electrically connected to the second sub-pixel circuit PC2, can be sealed by the first insulating layer IL1 (specifically, the third organic insulating layer 117). With this structure, the first sub-pixel circuit PC1 and the second sub-pixel circuit PC2 may not be electrically connected to each of the pixel electrodes 210.

[0199] refer to Figure 11 and Figure 12 The emitting layers 220 can be disposed on the pixel electrodes 210 respectively, thus spaced apart from each other. The emitting layers 220 can be disposed on the pixel electrodes 210 in a one-to-one correspondence. The emitting layers 220 can contact and be electrically connected to the pixel electrodes 210. As described above, the pixel electrodes 210 may not be connected to each of the first sub-pixel circuit PC1 and the second sub-pixel circuit PC2. The first sub-pixel circuit PC1 and the second sub-pixel circuit PC2 can be electrically isolated from the pixel electrodes 210. Therefore, the emitting layers 220 may also not be connected to each of the first sub-pixel circuit PC1 and the second sub-pixel circuit PC2.

[0200] Figure 13 This is a schematic cross-sectional view of the display device 1 according to an embodiment.

[0201] Specifically, Figure 13 This is a cross-sectional view of display device 1 in the non-display area NDA.

[0202] exist Figure 13 In, with Figure 4 In the accompanying drawings, the same reference numerals denote the same elements, and redundant descriptions are omitted.

[0203] refer to Figure 13 The display device 1 may include a sub-pixel circuit PC comprising transistors and capacitors disposed on a substrate 100, and a first insulating layer IL1 covering the sub-pixel circuit PC. In this case, the sub-pixel circuit PC may be a reference... Figures 10 to 12 Either the first sub-pixel circuit PC1 or the second sub-pixel circuit PC2 described.

[0204] The dam layer 119 can be disposed on the third organic insulating layer 117 to cover the third organic insulating layer 117. Pixel electrode 210 (see...) Figure 4 ) and launch layer 220 (see Figure 4 The common electrode 230 may not be located in the non-display area NDA. In the non-display area NDA, no opening may be formed in the dam layer 119. The common electrode 230 may be located on the dam layer 119 and may cover the dam layer 119.

[0205] The common electrode 230 can be disposed in the emitter layer 220 (see Figure 4 The common electrode 230 can be connected to the first to eighth sub-pixel circuits PC1 to PC8 (see above). Figure 10 Each overlap in ).

[0206] Figure 14 This is a block diagram of the electronic device 10 according to an embodiment.

[0207] refer to Figure 14 The electronic device 10 according to the embodiment may include a display module 111, a processor 121, a memory 131, and a power module 141.

[0208] The processor 121 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0209] The data information necessary for the operation of the processor 121 or the display module 111 can be stored in the memory 131. When the processor 121 executes the application program stored in the memory 131, image data signals and / or input control signals can be transmitted to the display module 111, and the display module 111 can process the received signals and output image information through the display screen.

[0210] The power module 141 may include a power supply module such as a power adapter or battery device, and a power conversion module configured to convert the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0211] At least one of the components of the electronic device 10 described above may be included in the display device according to the embodiments described above. Additionally, some modules that are functionally included in a single module may be included in the display device, while other modules may be provided independently of the display device. For example, the display device may include a display module 111, and the processor 121, memory 131, and power module 141 may be provided within the electronic device 10 as other devices besides the display device.

[0212] Figure 15 These are schematic diagrams of electronic devices according to various embodiments.

[0213] refer to Figure 15 Various electronic devices that utilize the display device according to the embodiments may include not only image display electronic devices (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e), but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) that include display modules, and vehicle electronic devices 10_3 that include display modules (such as instrument clusters, center consoles, central information displays (CIDs) on dashboards, and in-vehicle mirror displays).

[0214] The display device according to the embodiment has improved freedom in the arrangement of the emission layer at the boundary between the arc-shaped display area and the non-display area. Furthermore, according to the embodiment, the visibility and display quality of the display device can be improved.

[0215] The effects of this disclosure are not limited to those described above, and those skilled in the art will clearly understand other effects not described in the claims.

[0216] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. Descriptions of features or aspects within various embodiments should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the spirit and scope defined by the claims.

Claims

1. A display device, comprising: The substrate includes a display area and a non-display area; The first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, and the fourth sub-pixel circuit are sequentially disposed on the substrate in a first direction, and each includes a driving transistor and a switching transistor. A first insulating layer covers the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, and the fourth sub-pixel circuit; Multiple pixel electrodes are spaced apart from each other on the first insulating layer; as well as Multiple emission layers are respectively disposed on the multiple pixel electrodes in the display area. Wherein, the first sub-pixel circuit is electrically isolated from the plurality of pixel electrodes, and The fourth sub-pixel circuit is electrically connected to one of the plurality of pixel electrodes.

2. The display device according to claim 1, wherein, At least a portion of the first sub-pixel circuit overlaps with the non-display area, and At least a portion of the fourth sub-pixel circuit overlaps with the display area.

3. The display device according to claim 1, wherein, The second sub-pixel circuit and the fourth sub-pixel circuit are configured to receive data signals of light of the same color.

4. The display device according to claim 1, wherein, The first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit are configured to receive data signals of light of different colors.

5. The display device according to claim 1, further comprising: Multiple connecting electrodes are disposed on the first insulating layer and are electrically connected to the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, and the fourth sub-pixel circuit, respectively. Among these, the upper surface of the connecting electrode among the plurality of connecting electrodes that is electrically connected to the first sub-pixel circuit is sealed by the first insulating layer, and The connection electrode among the plurality of connection electrodes that is electrically connected to the fourth sub-pixel circuit is electrically connected to one of the plurality of pixel electrodes.

6. The display device according to claim 1, further comprising: A common electrode is disposed on the plurality of emitter layers. The common electrode overlaps with each of the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, and the fourth sub-pixel circuit.

7. The display device according to claim 1, further comprising: The fifth, sixth, seventh, and eighth sub-pixel circuits are sequentially disposed on the substrate in the first direction, starting from the fourth sub-pixel circuit, and each includes a driving transistor and a switching transistor. Each of the fifth sub-pixel circuit, the sixth sub-pixel circuit, the seventh sub-pixel circuit, and the eighth sub-pixel circuit is electrically connected to a corresponding pixel electrode among the plurality of pixel electrodes and a corresponding emission layer among the plurality of emission layers.

8. The display device according to claim 7, wherein, The first sub-pixel circuit and the seventh sub-pixel circuit are configured to receive data signals of light of the same color. The second sub-pixel circuit, the fourth sub-pixel circuit, the sixth sub-pixel circuit, and the eighth sub-pixel circuit are configured to receive data signals of light of the same color. The third sub-pixel circuit and the fifth sub-pixel circuit are configured to receive data signals of light of the same color, and The first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit are configured to receive data signals of light of different colors.

9. The display device according to claim 7, wherein, The emitter layers, which are electrically connected to the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, the fourth sub-pixel circuit, the fifth sub-pixel circuit, the sixth sub-pixel circuit, the seventh sub-pixel circuit, and the eighth sub-pixel circuit respectively, are configured in a PenTile structure.

10. The display device according to any one of claims 1 to 9, wherein, In the plan view, at least a portion of the boundary line between the display area and the non-display area has a curved shape.

11. An electronic device comprising: The substrate includes a display area and a non-display area; The first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, the fourth sub-pixel circuit, the fifth sub-pixel circuit, the sixth sub-pixel circuit, the seventh sub-pixel circuit, and the eighth sub-pixel circuit are sequentially disposed on the substrate in a first direction, and each includes a driving transistor and a switching transistor. A first insulating layer covers the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, the fourth sub-pixel circuit, the fifth sub-pixel circuit, the sixth sub-pixel circuit, the seventh sub-pixel circuit, and the eighth sub-pixel circuit; Multiple pixel electrodes are spaced apart from each other on the first insulating layer; as well as Multiple emission layers are respectively disposed on the multiple pixel electrodes in the display area. The first sub-pixel circuit is electrically isolated from each of the plurality of pixel electrodes. The eighth sub-pixel circuit is electrically connected to one of the plurality of pixel electrodes, and The second sub-pixel circuit, the fourth sub-pixel circuit, the sixth sub-pixel circuit, and the eighth sub-pixel circuit are configured to receive data signals of light of the same color.

12. The electronic device according to claim 11, wherein, Each of the second sub-pixel circuit, the fourth sub-pixel circuit, the sixth sub-pixel circuit, and the eighth sub-pixel circuit is configured to receive a data signal of red light.

13. The electronic device according to claim 11, wherein, The first sub-pixel circuit and the seventh sub-pixel circuit are configured to receive data signals of light of the same color, and The third sub-pixel circuit and the fifth sub-pixel circuit are configured to receive data signals of light of the same color.

14. The electronic device according to claim 13, wherein, Each of the first sub-pixel circuit and the seventh sub-pixel circuit is configured to receive a data signal of red light, and Each of the third and fifth sub-pixel circuits is configured to receive blue light data signals.

15. The electronic device according to claim 11, wherein, The first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit are configured to receive data signals of light of different colors.

16. The electronic device according to claim 11, wherein, The emitter layers, which are electrically connected to the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, the fourth sub-pixel circuit, the fifth sub-pixel circuit, the sixth sub-pixel circuit, the seventh sub-pixel circuit, and the eighth sub-pixel circuit respectively, are configured in a PenTile structure.

17. The electronic device according to claim 11, wherein, At least a portion of the first sub-pixel circuit overlaps with the non-display area, and At least a portion of the eighth sub-pixel circuit overlaps with the display area.

18. The electronic device of claim 11, further comprising: Multiple connecting electrodes are disposed on the first insulating layer and are electrically connected to the first sub-pixel circuit, the second sub-pixel circuit, the third sub-pixel circuit, the fourth sub-pixel circuit, the fifth sub-pixel circuit, the sixth sub-pixel circuit, the seventh sub-pixel circuit, and the eighth sub-pixel circuit, respectively.

19. The electronic device according to claim 18, wherein, The upper surface of the connecting electrode among the plurality of connecting electrodes that is electrically connected to the first sub-pixel circuit is sealed by the first insulating layer, and The connection electrode among the plurality of connection electrodes that is electrically connected to the eighth sub-pixel circuit is electrically connected to the pixel electrode among the plurality of pixel electrodes.

20. The electronic device according to any one of claims 11 to 19, wherein, In the plan view, at least a portion of the boundary line between the display area and the non-display area has a curved shape.

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