Display device and electronic device

Abstract

Disclosed are display devices and electronic devices. A display device includes a substrate including a display area and a non-display area adjacent to the display area; at least one first power line provided in the non-display area, the at least one first power line extending in a first direction, and the at least one first power line connected to a pixel positioned in the display area; and at least one second power line extending in a second direction intersecting the first direction and positioned adjacent to an end of the at least one first power line. The at least one first power line includes a first pattern spaced apart from the at least one second power line in the first direction, and a second pattern electrically connected to the first pattern and relatively closer to the at least one second power line than the first pattern. The first pattern and the second pattern include different materials, respectively.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0053811, filed on April 24, 2025, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The embodiments of this disclosure generally relate to display devices and electronic devices including display devices. Background Technology

[0003] With the development of information technology, display devices, as the connection medium between users and information, have become increasingly important. In response, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) is increasing.

[0004] During the manufacturing process of a display device, static electricity may be introduced into the internal circuitry of the display panel. This introduced static electricity can damage electrical components within the display panel. Specifically, in display panels with irregular circular shapes (e.g., irregular arc shapes), static electricity introduced into the power lines to which the driving power is supplied can damage pixels.

[0005] The above disclosure is intended only to help understand the background technology of the technical ideas of this disclosure and should not be construed as prior art known to those skilled in the art constituting this disclosure. Summary of the Invention

[0006] The embodiments provide display devices and electronic devices including display devices that can improve reliability. For example, in a display device having an irregular circular shape (e.g., an irregular arc shape), static electricity flow into the power lines can be prevented (or reduced), thereby improving pixel defects.

[0007] According to an embodiment of the present invention, a display device includes: a substrate including a display area and a non-display area adjacent to the display area; at least one first electric line, provided in the non-display area, the at least one first electric line extending in a first direction and connected to a pixel positioned in the display area; and at least one second electric line extending in a second direction intersecting the first direction and positioned adjacent to one end of the at least one first electric line. The at least one first electric line includes: a first pattern spaced apart from the at least one second electric line in the first direction; and a second pattern electrically connected to the first pattern and relatively closer to the at least one second electric line than the first pattern. The first pattern and the second pattern comprise different materials.

[0008] In one embodiment, the pixels may be arranged with steps at the edges of the display area.

[0009] In an embodiment, the first pattern may include a metallic material, and the second pattern may include a conductive material.

[0010] In one embodiment, at least one first power line may be electrically connected to a bus that supplies the first drive power.

[0011] In one embodiment, at least one first power line may overlap with a portion of the bus.

[0012] In one embodiment, one end of the bus may be floating at the edge of a non-display area.

[0013] In an embodiment, at least one first power line may further include at least one insulating layer between the first pattern and the second pattern in the thickness direction of the display device, and the at least one insulating layer may have at least one first contact hole connecting the first pattern and the second pattern.

[0014] In an embodiment, one end of the first pattern may be connected to the second pattern via at least one first contact hole, and the other end of the first pattern may be connected to the bus via at least one second contact hole different from the at least one first contact hole.

[0015] In an embodiment, at least one second contact hole may be further spaced apart in a first direction from at least one first contact hole relative to at least one second electric field line.

[0016] In an embodiment, the display device may further include: at least one data line, which extends in a first direction and is disposed adjacent to at least one first power line in a second direction.

[0017] In an embodiment, at least one data line may include: a third pattern spaced apart from at least one second power line in a first direction; and a fourth pattern electrically connected to the third pattern and relatively close to the at least one second power line than the third pattern, wherein the third pattern and the fourth pattern may include different materials.

[0018] In an embodiment, the third pattern may include a metallic material, and the fourth pattern may include a conductive material.

[0019] In an embodiment, the third pattern and the fourth pattern may be electrically connected via at least one third contact hole.

[0020] According to an embodiment of the present invention, an electronic device includes: a processor; and a display device that displays an image according to control of the processor. The display device includes: a substrate including a display area and a non-display area adjacent to the display area; at least one first power line, provided in the non-display area, the at least one first power line extending in a first direction and connected to a pixel positioned in the display area; and at least one second power line extending in a second direction intersecting the first direction and positioned adjacent to one end of the at least one first power line. The at least one first power line includes: a first pattern spaced apart from the at least one second power line in the first direction; and a second pattern electrically connected to the first pattern and relatively closer to the at least one second power line than the first pattern. The first pattern and the second pattern comprise different materials.

[0021] In one embodiment, the pixels may be arranged with steps at the edges of the display area.

[0022] In an embodiment, the first pattern may include a metallic material, and the second pattern may include a conductive material.

[0023] In one embodiment, at least one first power line may be electrically connected to a bus that supplies the first drive power.

[0024] In an embodiment, at least one first power line may further include at least one insulating layer between the first pattern and the second pattern in the thickness direction of the display device, and the at least one insulating layer may have at least one first contact hole connecting the first pattern and the second pattern.

[0025] In an embodiment, one end of the first pattern may be connected to the second pattern via at least one first contact hole, and the other end of the first pattern may be connected to the bus via at least one second contact hole different from the at least one first contact hole.

[0026] In an embodiment, at least one second contact hole may be further spaced apart in a first direction from at least one first contact hole relative to at least one second electric field line. Attached Figure Description

[0027] The above and other features of the embodiments of this disclosure will become more apparent from the further detailed description of the embodiments with reference to the accompanying drawings.

[0028] Figure 1 This is a perspective view schematically illustrating a display device according to an embodiment of the present invention.

[0029] Figure 2 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0030] Figure 3This illustrates an embodiment of the invention. Figure 2 A circuit diagram for any one of the pixels.

[0031] Figure 4 This illustrates an embodiment of the invention. Figure 2 A floor plan of the display panel.

[0032] Figure 5 This illustrates an embodiment of the invention. Figure 4 A magnified view of region A.

[0033] Figure 6 This illustrates an embodiment of the invention. Figure 4 A magnified view of region B.

[0034] Figure 7 It is along the embodiment of the present invention Figure 6 A cross-sectional view of line I-I'.

[0035] Figure 8 This illustrates an embodiment of the invention. Figure 6 A plan view of the lines.

[0036] Figure 9 This illustrates an embodiment of the invention. Figure 4 A magnified view of region B'.

[0037] Figure 10 This illustrates an embodiment of the invention. Figure 9 A plan view of the lines.

[0038] Figure 11 This is a block diagram illustrating an electronic device according to an embodiment of the present invention.

[0039] Figure 12 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0040] In the following, preferred embodiments according to the present disclosure are described in detail with reference to the accompanying drawings. It should be understood that the following description focuses on those parts that support the understanding of operation according to the present disclosure, and other parts may be omitted so as not to obscure the nature of the disclosure. Furthermore, the present disclosure is not limited to the embodiments described herein and may be implemented in other forms. However, the embodiments described herein are provided to illustrate the technical ideas of the present disclosure in sufficient detail to enable practice by a person skilled in the art to which this disclosure pertains.

[0041] Throughout this specification, when a component is "connected" to another component, this can include not only cases where the component is "directly connected" to the other component, but also cases where the component is "indirectly connected" to the other component and the other component is located between the two components. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the invention. Throughout this specification, unless otherwise stated, when a component is referred to as "comprising" an element, this may mean that other components may be further included rather than excluded. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, ZX). Here, "and / or" can include all combinations of one or more of the corresponding configurations.

[0042] As used herein, various components may be described using terms such as first and second, but such components are not limited to these terms. These terms are used to distinguish one component from another. Therefore, without departing from the disclosure herein, a first component may be referred to as a second component.

[0043] For descriptive purposes, spatial relative terms such as “below” and “above” may be used, and in doing so, the relationship of one element or feature as depicted in the accompanying drawings to another element (or multiple elements) or another feature (or multiple features) may be described. In addition to the orientations depicted in the accompanying drawings, spatial relative terms are also intended to include different orientations in use, operation, and / or manufacture. For example, when the device shown in the accompanying drawings is inverted, an element depicted as positioned “below” other elements or features is oriented “above” other elements or features. Thus, in embodiments, the term “below” may include both upward and downward directions. Furthermore, the device may be oriented in other directions (e.g., rotated 90 degrees or otherwise oriented), and the spatial relative terms used herein should be interpreted accordingly.

[0044] Various embodiments are described with reference to the accompanying drawings, which illustrate exemplary embodiments. Therefore, it should be anticipated that the geometry may vary, for example, due to tolerances and / or manufacturing techniques. Consequently, the embodiments disclosed herein should not be construed as limited to the specific geometries shown, but should be interpreted as including variations in geometry, for example, due to manufacturing processes. Thus, the shapes shown in the drawings may not represent the actual shape of a region of the device, and the embodiments are not limited thereto.

[0045] Figure 1 This is a perspective view schematically illustrating a display device according to an embodiment of the present invention.

[0046] Reference Figure 1 The display device 100 may include a display area DA and a non-display area NDA. The display area DA may be an area for displaying an image, and the non-display area NDA may be provided on the periphery of the display area DA. The non-display area NDA may be an area where no image is displayed. According to an embodiment, the shape of the display area DA and the shape of the non-display area NDA may be designed to be related.

[0047] The display device 100 can be provided in various shapes (e.g., as a rectangular plate with two pairs of parallel sides), but the embodiments are not limited to this. In the case where the display device 100 is provided as a rectangular plate, either pair of sides can be provided such that one pair is longer than the other pair. Figure 1 In the illustration, the display device 100 is shown with a rounded edge where a long side and a short side are adjacent, but the embodiment is not limited to this. For example, the display device 100 may have an angled edge that is a straight line.

[0048] In embodiments of this disclosure, for ease of explanation, the display device 100 is shown as a rectangle having a pair of long sides and a pair of short sides. The extending direction of the long sides can be represented as a first direction DR1, the extending direction of the short sides can be represented as a second direction DR2, and the direction perpendicular to the long and short sides can be represented as a third direction DR3. The first direction DR1, the second direction DR2, and the third direction DR3 can refer to the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3, respectively.

[0049] Figure 2 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0050] Reference Figure 2 The display device 100 may include a display panel 110, a gate driver 120, a transmitter driver 130, a data driver 140, a voltage generator 150, and a controller 160.

[0051] The display panel 110 may include pixels PX. Pixels PX may be connected to gate driver 120 via a first gate line GL1, a second gate line GL2, ... and an m-th gate line GLm (where m is a positive integer). Pixels PX may be connected to transmit driver 130 via a first transmit control line EL1 to an m-th transmit control line ELm. Pixels PX may be connected to data driver 140 via a first data line DL1 to an n-th data line DLn (where n is a positive integer).

[0052] Each of a pixel PX may include at least one light-emitting element configured to generate light. Therefore, each pixel PX can generate light of one of a variety of colors, such as red, green, blue, cyan, magenta, and yellow. Two or more pixels PX can constitute a single pixel unit PXU. For example, as... Figure 2 As shown, three pixels PX can form a single pixel unit PXU.

[0053] Gate driver 120 can be connected to pixels PX arranged in the row direction via first gate line GL1 to m-th gate line GLm. Pixels PX arranged in the row direction can form a pixel row, and gate driver 120 can be connected to the pixel row via a corresponding gate line from GL1 to GLm. Gate driver 120 can output a scan signal to first gate line GL1 to m-th gate line GLm in response to scan control signal SCS. In an embodiment, each gate line may include multiple sub-gate lines, and sub-scan signals can be output through multiple sub-gate lines. In this case, scan signal can be understood to include sub-scan signals. In an embodiment, scan control signal SCS may include a clock signal and a scan start signal indicating the start of each frame.

[0054] Transmit driver 130 can be connected to pixels PX arranged in the row direction via a first transmit control line EL1, a second transmit control line EL2, ... and an m-th transmit control line ELm. Transmit driver 130 can be connected to the pixel row via a corresponding one of the transmit control lines EL1 to ELm. Transmit driver 130 can output an optical transmit control signal to the first transmit control line EL1 to the m-th transmit control line ELm in response to a transmit control signal ECS. Each transmit control line may include multiple sub-transmit control lines, and sub-transmit control signals may be output via multiple sub-transmit control lines. In this case, the optical transmit control signal can be understood to include sub-optical transmit control signals. In an embodiment, the transmit control signal ECS may include a clock signal and a transmit start signal indicating the start of each frame.

[0055] The gate driver 120 may be positioned on one side of the display panel 110, and the emitter driver 130 may be positioned on the opposite side of the display panel 110. However, the embodiments are not limited thereto. According to embodiments, the gate driver 120 and the emitter driver 130 may be arranged in various configurations around the periphery of the display panel 110.

[0056] Data driver 140 can be connected to pixels PX arranged in the column direction via first data lines DL1 to nth data lines DLn. Pixels PX arranged in the column direction can form a pixel column, and data driver 140 can be connected to the pixel column via a corresponding one of the data lines DL1 to DLn. Data driver 140 can receive image data DATA and data control signal DCS from controller 160. Data driver 140 can operate in response to data control signal DCS. In an embodiment, data control signal DCS may include a clock signal and a start pulse, etc.

[0057] The data driver 140 can use the voltage from the voltage generator 150 to apply a data voltage (or data signal) having a grayscale value corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn. In the example where a scan signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data voltage corresponding to the image data DATA can be applied to the first data lines DL1 to the nth data line DLn. Therefore, the corresponding pixel PX can emit light corresponding to the data voltage, and the image can be displayed in the display panel 110.

[0058] Voltage generator 150 may be capable of operating in response to a voltage control signal VCS from controller 160. Voltage generator 150 may be configured to generate multiple voltages and provide the generated voltages to the display device 100. For example, voltage generator 150 may be configured to generate multiple voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0059] Voltage generator 150 can generate a first driving power VDD, a second driving power VSS, a reference power VREF, a first initialization power VINT, a second initialization power VAINT1, and a third initialization power VAINT2, and these power values ​​can be provided to pixel PX. However, the embodiment is not limited thereto. For example, at least one of the first driving power VDD, the second driving power VSS, the reference power VREF, the first initialization power VINT, the second initialization power VAINT1, and the third initialization power VAINT2 can be provided by an external device of display device 100.

[0060] The first driving power VDD can have a relatively high voltage level. The second driving power VSS can have a lower voltage level than the first driving power VDD. For example, the second driving power VSS can have a negative voltage level. The first initialization power VINT can have a voltage level between the first driving power VDD and the second driving power VSS, can have the same voltage level as the second driving power VSS, or can have a lower voltage level than the second driving power VSS.

[0061] The controller 160 can control various operations of the display device 100. The controller 160 can receive input image data IMG and control signals CTRL for controlling the input image data IMG from an external source. In response to the control signal CTRL, the controller 160 can generate scan control signal SCS, transmit control signal ECS, data control signal DCS, and voltage control signal VCS.

[0062] The controller 160 can convert the input image data IMG into a format suitable for the display device 100 or the display panel 110 and output the image data DATA to the data driver 140. For example, the controller 160 can arrange the input image data IMG according to the arrangement of the pixels PX to output the image data DATA.

[0063] Two or more of the components in the data driver 140, voltage generator 150, and controller 160 can be mounted on a single integrated circuit. For example... Figure 2 As shown, the data driver 140, voltage generator 150, and controller 160 can be included in a driver integrated circuit (DIC). In this case, the data driver 140, voltage generator 150, and controller 160 can be functionally distinct components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 140, voltage generator 150, and controller 160 can be provided as a component separate from the driver integrated circuit (DIC).

[0064] Figure 3 This illustrates an embodiment of the invention. Figure 2 A circuit diagram for any one of the pixels.

[0065] exist Figure 3 The example illustrates this. Figure 2 The pixels PXij in the pixel PX are arranged in the i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (where j is an integer greater than or equal to 1 and less than or equal to n).

[0066] Reference Figure 2 and Figure 3 Pixel PXij can include pixel circuit PC and light-emitting element LD.

[0067] A light-emitting element (LD) may include an anode electrode AE, a cathode electrode CE, and a light-emitting layer. The light-emitting layer may be physically disposed between the anode electrode AE ​​and the cathode electrode CE. The light-emitting layer may be configured to emit light in response to the amount of current flowing from the anode electrode AE ​​through the light-emitting layer to the cathode electrode CE. The anode electrode AE ​​of the LD may be electrically connected to a first driving power node VDDN via a pixel circuit PC. The cathode electrode CE of the LD may be electrically connected to a second driving power node VSSN. The LD may emit light according to the amount of current flowing from the first driving power node VDDN through the pixel circuit PC to the second driving power node VSSN.

[0068] A light-emitting element (LD) may include an organic light-emitting diode (OLED). However, embodiments are not limited to this. For example, a light-emitting element (LD) may include an inorganic light-emitting diode. For instance, a light-emitting element (LD) may be a light-emitting element comprising both organic and inorganic materials. Figure 3 In the diagram, pixel PXij is shown as comprising a single light-emitting element LD, but pixel PXij may comprise two or more light-emitting elements. In this case, the two or more light-emitting elements may be connected in series or in parallel with each other.

[0069] Pixel circuit PC can be connected Figure 2 The i-th gate line GLi from the first gate line GL1 to the m-th gate line GLm Figure 2 The first transmit control line EL1 to the m-th transmit control line ELm, including the i-th transmit control line ELi and Figure 2 The first data line DL1 to the nth data line DLn, specifically the j-th data line DLj. The pixel circuit PC can be configured to control the light-emitting element LD based on signals received via these signal lines.

[0070] The i-th gate line GLi may include first sub-gate lines SGL1 to fourth sub-gate lines SGL4. The pixel circuit PC may operate in response to first sub-scan signals to fourth sub-scan signals received via the first sub-gate lines SGL1 to fourth sub-gate lines SGL4. The pixel circuit PC may include first transistors TR1 to seventh transistors TR7 and a first capacitor C1 and a second capacitor C2. However, the embodiments are not limited thereto. The pixel circuit PC may be implemented in any of various forms of circuits including multiple transistors and one or more capacitors. For example, the pixel circuit PC may include two transistors and one capacitor. Depending on the embodiment of the pixel circuit PC, the number of sub-gate lines included in the i-th gate line GLi and the number of sub-emission control lines included in the i-th emission control line ELi may be variable. The first transistors TR1 to seventh transistors TR7 may be P-type transistors. Each of the first transistors TR1 to seventh transistors TR7 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). However, the embodiments are not limited thereto. For example, at least one of the first transistors TR1 to seventh transistors TR7 may be replaced by an N-type transistor.

[0071] In the embodiments, the first transistor TR1 to the seventh transistor TR7 may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, and oxide semiconductors, etc.

[0072] A first transistor TR1 can be connected between a first drive power node VDDN and a first node N1. The first transistor TR1 may include a drain electrode connected to the first node N1, a source electrode connected to the first drive power node VDDN, and a gate electrode connected to the second node N2. The first transistor TR1 can turn on in response to a voltage difference between its drain and source electrodes. The first drive power node VDDN may be provided with… Figure 2 The first driving power node is VDD. The second driving power node VSSN can be provided with... Figure 2 The second driving power VSS. The second driving power VSS can have a lower level than the first driving power VDD. In the example where the first transistor TR1 and the sixth transistor TR6 are turned on, the first transistor TR1 can control the amount of current flowing from the first driving power node VDDDN through the light-emitting element LD to the second driving power node VSSN based on the voltage difference between the first node N1 and the second node N2.

[0073] The second transistor TR2 can be connected between the j-th data line DLj and the third node N3. The gate electrode of the second transistor TR2 can be connected to the first sub-gate line SGL1. The second transistor TR2 can be turned on when the first sub-scan signal with gate turn-on voltage is applied to the first sub-gate line SGL1, thereby electrically connecting the j-th data line DLj and the third node N3. Therefore, the data voltage of the j-th data line DLj can be transmitted to the third node N3.

[0074] The third transistor TR3 can be connected between the first node N1 and the second node N2. The gate electrode of the third transistor TR3 can be connected to the first sub-gate line SGL1. The third transistor TR3 can be turned on when the first sub-scan signal of the gate turn-on voltage is applied to the first sub-gate line SGL1, thereby electrically connecting the first node N1 and the second node N2.

[0075] A fourth transistor TR4 can be connected between the second node N2 and the first initialization power node VINTN. The gate electrode of the fourth transistor TR4 can be connected to the second sub-gate line SGL2. The fourth transistor TR4 can be turned on when a second sub-scan signal with a gate on-state voltage is applied to the second sub-gate line SGL2, thereby connecting the second node N2 to the first initialization power node VINTN. The first initialization power node VINTN can be provided with... Figure 2 The first initialization power VINT. Therefore, when the fourth transistor TR4 is turned on, the first initialization power VINT can be passed to the second node N2.

[0076] The fifth transistor TR5 can be connected between the reference power node VREFN and the third node N3. The gate electrode of the fifth transistor TR5 can be connected to the third sub-gate line SGL3. The fifth transistor TR5 can be turned on when a third sub-scan signal with a gate on-state voltage is applied to the third sub-gate line SGL3, thereby electrically connecting the third node N3 to the reference power node VREFN. The reference power node VREFN can be provided with... Figure 2 The reference power VREF. Therefore, when the fifth transistor TR5 is turned on, the reference power VREF can be transferred to the third node N3.

[0077] The sixth transistor TR6 can be connected between the first node N1 and the fourth node N4. Here, the fourth node N4 can be the anode electrode AE ​​of the light-emitting element LD. The gate electrode of the sixth transistor TR6 can be connected to the i-th emission control line ELi. The sixth transistor TR6 can be turned on when the light emission control signal of the gate turn-on voltage is applied to the i-th emission control line ELi.

[0078] The seventh transistor TR7 can be connected between the fourth node N4 and the second initialization power node VAINTN1 (or the third initialization power node VAINTN2). The gate electrode of the seventh transistor TR7 can be connected to the fourth sub-gate line SGL4. The seventh transistor TR7 can be turned on when the fourth sub-scan signal with a gate turn-on voltage is applied to the fourth sub-gate line SGL4, thereby connecting the anode electrode AE ​​to the second initialization power node VAINTN1 (or the third initialization power node VAINTN2). The seventh transistor TR7 can be connected to either the second initialization power node VAINTN1 or the third initialization power node VAINTN2 according to pixel PXij. The second initialization power node VAINTN1 can be provided with… Figure 2 The second initialization power node, VAINT1, and the third initialization power node, VAINTN2, can be provided. Figure 2 The third initialization power VAINT2. Therefore, when the seventh transistor TR7 is turned on, the second initialization power VAINT1 (or the third initialization power VAINT2) can be transferred to the anode electrode AE.

[0079] A first capacitor C1 can be connected between a second node N2 and a third node N3. The first capacitor C1, or the third node N3 which is one end of the first capacitor C1, can store the data voltage supplied via the j-th data line DLj. Furthermore, a second capacitor C2 can be connected between the third node N3 and the first drive power node VDDN.

[0080] Figure 4 This illustrates an embodiment of the invention. Figure 2 A floor plan of the display panel.

[0081] Reference Figure 2 and Figure 4 , Figure 2 The display panel 110 may include a substrate SUB, pixels PX, and pads PD.

[0082] The base SUB can have a generally rectangular shape. The base SUB may include a pair of long sides parallel to each other in a first direction DR1 and a pair of short sides parallel to each other in a second direction DR2. However, the shape of the base SUB is not limited to this and can have various shapes.

[0083] For base SUBs with straight edges, at least some of the edges of each base SUB shape can be curved. For example, in the case of a rectangular base SUB, the portion where adjacent straight edges meet can be replaced by a curve with a preset curvature. Specifically, on the underside of the base SUB, the base SUB can have various shapes, such as semicircles and semi-ellipses including straight and curved edges. For example, the base SUB can have shapes such as polygons, circles, semicircles, and ellipses.

[0084] The base SUB may include a display area DA and a non-display area NDA positioned around the periphery of the display area DA. The display area DA may have various shapes, such as semicircles and semi-ellipses including straight and curved edges. For example, the display area DA may have a shape corresponding to the base SUB.

[0085] Pixels PX can be arranged on a substrate SUB within the display area DA. Pixels PX can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments are not limited to this. For example, pixels PX can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, pixels PX can be arranged in a pentiline pattern. ® Pattern arrangement.

[0086] In the non-display area NDA on the substrate SUB, components for controlling pixels PX can be arranged. For example, wiring associated with pixels PX (such as...) Figure 2 The first gate lines GL1 to the m-th gate line GLm, the first data lines DL1 to the n-th data lines DLn, and the first transmit control lines EL1 to the m-th transmit control lines ELm can be arranged in the non-display area NDA. In some aspects, such as Figure 2 The power bus BL of the first drive power VDD, the second drive power VSS, the reference power VREF, the first initialization power VINT, the second initialization power VAINT1, and the third initialization power VAINT2 (see Figure 5 ) and power line PL (see Figure 5 It can be placed in the non-display area NDA.

[0087] In the non-display area NDA on the substrate SUB, pads PD can be positioned. Pads PD can be electrically connected to pixels PX via wiring. For example, pads PD can be connected to pixels PX via first data lines DL1 to nth data lines DLn.

[0088] The pads (PDs) can bond the display panel 110 to other components of the display device 100. In an embodiment, the pads (PDs) can be used to connect the display panel 110 to other components of the display device 100. Figure 2The driver integrated circuit (DIC) provides voltages and signals to support the operation of components included in the display panel 110. For example, first data lines DL1 to nth data lines DLn can be connected to the driver integrated circuit (DIC) via pads PD. For example, a first drive power VDD and a second drive power VSS can be received from the driver integrated circuit (DIC) via pads PD. For example, in the case where the gate driver 120 is mounted on the display panel 110, a scan control signal SCS can be transmitted from the driver integrated circuit (DIC) to the gate driver 120 via pads PD.

[0089] In this embodiment, the circuit board can be electrically connected to the pads (PD) using a conductive adhesive such as anisotropic conductive film. Here, the circuit board can be a flexible circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit (DIC) can be mounted on the circuit board and electrically connected to the pads (PD).

[0090] Figure 5 This illustrates an embodiment of the invention. Figure 4 A magnified view of region A.

[0091] Reference Figure 4 and Figure 5 In the display panel 110, power lines PL and power buses BL can be arranged in the non-display area NDA. The power bus BL can carry power to the power lines PL. The power bus BL can supply power to the pixels PX via the power lines PL.

[0092] The power bus BL may include a first bus BUS1, a second bus BUS2, a third bus BUS3, a fourth bus BUS4, and a fifth bus BUS5. The power lines PL may include a first drive power line VDDL, a second drive power line VSSL, a first initialization power line VinTL, a second initialization power line VAINT1L, and a third initialization power line VAINT2L. For example, the first bus BUS1 can carry the first drive power VDD to the first drive power line VDDL. The second bus BUS2 can carry the second drive power VSS to the second drive power line VSSL. The third bus BUS3 can carry the first initialization power VinT to the first initialization power line VinTL. The fourth bus BUS4 can carry the second initialization power VAINT1 to the second initialization power line VAINT1L. The fifth bus BUS5 can carry the third initialization power VAINT2 to the third initialization power line VAINT2L.

[0093] The power bus BL can be arranged on the underside of the display panel 110. Furthermore, the power lines PL that electrically connect the power bus BL and the pixels PX can be arranged on the underside of the display panel 110. For example, on the underside of the display panel 110, the power buses BL can be spaced apart from each other in a first direction DR1. On the underside of the display panel 110, the power buses BL can extend in a second direction DR2. On the underside of the display panel 110, the power lines PL can be spaced apart from each other in the second direction DR2. On the underside of the display panel 110, the power lines PL can extend in the first direction DR1. Additionally, the power lines PL can overlap with the power bus BL.

[0094] The data line DL can be located on the lower side of the display panel 110. For example, the data line DL can extend along a first direction DR1 on the lower side of the display panel 110. The data line DL can be arranged adjacent to at least one of the power lines PL along a second direction DR2. Furthermore, the data line DL can overlap with the power bus BL.

[0095] Figure 6 This illustrates an embodiment of the invention. Figure 4 A magnified view of region B.

[0096] Reference Figure 4 and Figure 6 The display panel 110 may include a first pixel PX1 arranged with a stepped shape at the edge of the display area DA. Because the lower side of the display panel 110 has a rounded shape, the first pixel PX1 can be stepped from the edge of the display area DA to follow the curvature of the display area DA. For example, the number of pixels included in the pixel column and pixel row at the edge of the display area DA may be different for each row and each column. For example, in the direction closer to the edge of the display area DA, the number of pixels included in the pixel column may be the same or less. In the direction closer to the edge of the display area DA, the number of pixels included in the pixel row may be the same or less. Therefore, the arrangement of the first pixel PX1 may include a step in the form of a staircase.

[0097] The first pixel PX1 may be electrically connected to at least one data line DL and at least one first power line PL1 extending in the first direction DR1. For example, the first pixel PX1 may be electrically connected to a first driving power line VDDL and a first initialization power line VinTL extending in the first direction DR1. For example, at least one first power line PL1 may be connected to the first pixel PX1 located in the display area DA. Furthermore, the first pixel PX1 may be electrically connected to the data line DL extending in the first direction DR1. In this case, the data line DL may be arranged adjacent to at least one of the first driving power line VDDL and the first initialization power line VinTL in the second direction DR2.

[0098] The first pixel PX1 may overlap with at least one second power line PL2 extending in the second direction DR2. The at least one second power line PL2 may be adjacent to one end of at least one data line DL and one end of at least one first power line PL1. In this case, one end of at least one data line DL and one end of at least one first power line PL1 may be adjacent to the first pixel PX1. For example, the first initialization power line VINTL, the second initialization power line VAINT1L, the third initialization power line VAINT2L, and the second drive power line VSSL extending in the second direction DR2 may be adjacent to one end of the first drive power line VDDL extending in the first direction DR1 and one end of the first initialization power line VINTL extending in the first direction DR1.

[0099] At least one first power line PL1 can be electrically connected to at least one bus BUS1 or BUS2. At least one first power line PL1 can overlap with a portion of at least one bus BUS1 or BUS2. For example, a first drive power line VDDL can be electrically connected to a first bus BUS1 supplying first drive power VDD. The first drive power line VDDL and the first bus BUS1 can cross each other, and the first drive power line VDDL can overlap with a portion of the first bus BUS1. The first drive power line VDDL can be electrically connected to the first bus BUS1 via at least one second contact hole CNT2. Furthermore, a first initialization power line VINTL can be electrically connected to a second bus BUS2 supplying first initialization power VINT. The first initialization power line VINTL and the second bus BUS2 can cross each other, and the first initialization power line VINTL can overlap with a portion of the second bus BUS2.

[0100] At least one of the buses BUS1 or BUS2 may be floating at the edge of the non-display area NDA. For example, one end of at least one bus BUS1 or BUS2 may be floating at the edge of the non-display area NDA. Because the lower side of the display panel 110 has a rounded shape, at least one bus BUS1 or BUS2 arranged on the lower side of the display panel 110 may be electrically disconnected from the edge of the non-display area NDA. Therefore, the at least one floating bus BUS1 or BUS2 may be electrically unstable. For example, the at least one floating bus BUS1 or BUS2 may be susceptible to externally generated potential differences or electrical interference, which may cause voltage spikes or sudden voltage changes.

[0101] For example, in the case of a second contact hole CNT2 forming a connection between the first drive power line VDDL and the first bus BUS1, there may be a relatively high potential for electrostatic discharge (ESD) transmitted through the first drive power line VDDL. For instance, unstable voltage generated on the floating first bus BUS1 may cause ESD at electrical contacts such as the second contact hole CNT2. The induced ESD can be transmitted through the second contact hole CNT2 to the first drive power line VDDL, potentially causing the pixel PX to overheat and damage it.

[0102] According to an embodiment, the first drive power line VDDL may include a first pattern PT1 and a second pattern PT2 made of a different material than the first pattern PT1. The first pattern PT1 may be spaced apart from at least one second power line PL2 extending in a first direction DR1 and in a second direction DR2. The first pattern PT1 may include a metallic material. The second pattern PT2 may be electrically connected to the first pattern PT1 and may be relatively closer to at least one second power line PL2 than the first pattern PT1. The second pattern PT2 may be electrically connected to the first pattern PT1 via at least one first contact hole CNT1. The second pattern PT2 may include a conductive material having a relatively lower conductivity than the first pattern PT1.

[0103] In this way, by placing a second pattern PT2 made of a different material than the first pattern PT1 forming the second contact hole CNT2 in the first drive electric line VDDL, which is prone to electrostatic discharge (ESD), a sufficient separation distance can be ensured between the first pattern PT1 and at least one second electric line PL2. Therefore, electrostatic discharge (ESD) transmitted to at least one second electric line PL2 via the first drive electric line VDDL extending in the first direction DR1 can be minimized, thereby preventing damage to the pixel PX.

[0104] Figure 7 It is along the embodiment of the present invention Figure 6 A cross-sectional view of line I-I'.

[0105] Reference Figure 4 , Figure 6 and Figure 7 The display panel 110 may include a first driving power line VDDL that electrically connects the first pixel PX1 and the first bus BUS1. For example, the first driving power line VDDL may be formed as a multi-layer structure on the underside of the display panel 110. The first driving power line VDDL may include a first pattern PT1 and a second pattern PT2 disposed in different layers.

[0106] The following describes the structure in which the components included in the first drive power line VDDL are stacked.

[0107] A gate insulating layer GI can be disposed on a substrate SUB. The gate insulating layer GI can be formed such that it covers an active pattern (not shown). The gate insulating layer GI can have a single-layer or multi-layer structure including an inorganic insulator. For example, the inorganic insulator can include, but is not limited to, silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

[0108] The first pattern PT1 of the first drive power line VDDL can be disposed on the gate insulating layer GI. For example, the first pattern PT1 can include the same material as the material used to form the gate electrode GAT. For example, the first pattern PT1 can include, but is not limited to, indium zinc oxide (InZnO), zinc (Zn), magnesium (Mg), aluminum (Al), gold (Au), and titanium (Ti).

[0109] A first insulating layer IL1 may be disposed on a first pattern PT1. The first insulating layer IL1 may be configured such that it covers the first pattern PT1. The first insulating layer IL1 may have a single-layer or multi-layer structure including an inorganic insulator. For example, the inorganic insulator may include, but is not limited to, silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (Al2O3) and titanium oxide (TiO2), etc.

[0110] One or more insulating layers may be disposed on the first insulating layer IL1. Figure 7 The diagram shows a second insulating layer IL2 disposed on a first insulating layer IL1, but is not limited thereto. The second insulating layer IL2 may include, but is not limited to, silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (Al2O3) and titanium oxide (TiO2), etc.

[0111] On the second insulating layer IL2, a second pattern PT2 and a first bus BUS1 connected to the first pattern PT1 can be disposed. Furthermore, the second pattern PT2 and the first bus BUS1 can be disposed in the same layer. The second pattern PT2 can comprise the same material as the first bus BUS1. For example, the second pattern PT2 can comprise the same conductive material as the material used to form the source electrode SD and the drain electrode. For example, the second pattern PT2 can include, but is not limited to, titanium / aluminum / titanium (Ti / Al / Ti), indium tin oxide (ITO), titanium nitride (TiN), and indium oxide (In2O3).

[0112] As the thickness D of the first insulating layer IL1 and the second insulating layer IL2 increases, their ability to withstand electrostatic discharge (ESD) voltages can be improved. For example, as the thickness D between the first pattern PT1 and the second pattern PT2 connected to the first pattern PT1 increases, ESD generated by the formation of the second contact hole CNT2 can be further blocked from being transmitted to the second pattern PT2. By increasing the thickness D between the first pattern PT1 and the second pattern PT2 connected to the first pattern PT1, ESD transmitted to the second pattern PT2 can be reduced.

[0113] A third insulating layer IL3 can be disposed on the second pattern PT2 and the first bus BUS1. The third insulating layer IL3 can be configured to cover both the second pattern PT2 and the first bus BUS1. The third insulating layer IL3 can have a single-layer or multi-layer structure including an inorganic insulator. For example, the inorganic insulator can include, but is not limited to, silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (Al2O3) and titanium oxide (TiO2), etc.

[0114] In an embodiment, at least one insulating layer (e.g., a first insulating layer IL1 and a second insulating layer IL2) may have at least one first contact hole CNT1 connecting a first pattern PT1 and a second pattern PT2. The first pattern PT1 may be connected to the second pattern PT2 and the first bus BUS1 via the first contact hole CNT1 and the second contact hole CNT2 penetrating the first insulating layer IL1 and the second insulating layer IL2, respectively. One end of the first pattern PT1 may be connected to the second pattern PT2 via at least one first contact hole CNT1. The other end of the first pattern PT1 may be connected to the first bus BUS1 via at least one second contact hole CNT2, which is different from the at least one first contact hole CNT1.

[0115] Figure 7An example of a first power line PL1 extending in the first direction DR1 on the underside of the display panel 110 is shown, and the first initialization power line VINTL may have the same multi-layer structure as the first drive power line VDDL. Therefore, its description is omitted.

[0116] Figure 8 This illustrates an embodiment of the invention. Figure 6 A plan view of the lines.

[0117] Reference Figure 8 In the first drive power line VDDL, one end of the first pattern PT1 can be electrically connected to the first drive power VDD (see...). Figure 2 The first bus BUS1. Moreover, the other end of the first pattern PT1 can be electrically connected to a second pattern PT2 which is made of a different material than the first pattern PT1.

[0118] For example, the first pattern PT1 of the first drive power line VDDL and the first bus BUS1, which are disposed in different layers, can be connected via the second contact hole CNT2. When the second contact hole CNT2 is formed such that it electrically connects the first drive power line VDDL and the first bus BUS1, since the second contact hole CNT2 comprises a metallic material, it can provide a path for electrostatic discharge (ESD) to be transmitted. The ESD generated by the formation of the second contact hole CNT2 can be transmitted along the metallic material through the second contact hole CNT2 to the first pattern PT1 of the first drive power line VDDL.

[0119] The first pattern PT1 of the first drive power line VDDL can extend a predetermined length from the first bus BUS1 toward the first direction DR1. Then, at a predetermined point thereafter, the first pattern PT1 can be changed to a second pattern PT2 of a different material. The first pattern PT1 can be connected to the second pattern PT2, which is disposed in a different layer from the first pattern PT1, via the first contact hole CNT1. For example, the first pattern PT1 of the first drive power line VDDL can be disposed in the same layer as the second initialization power line VAINT1L and the third initialization power line VAINT2L extending in the second direction DR2. Furthermore, the second pattern PT2 of the first drive power line VDDL can be disposed in the same layer as the first bus BUS1 and the second drive power line VSSL extending in the second direction DR2. However, the embodiment is not limited to this.

[0120] The second contact hole CNT2 can be further spaced apart from the first contact hole CNT1 and at least one second electric field line PL2 in the first direction DR1. Therefore, the first pattern PT1 can be further spaced apart in the first direction DR1 than the second pattern PT2 and at least one second electric field line PL2 extending in the second direction DR2. In this way, by changing the first drive electric field line VDDL from the first pattern PT1 to the second pattern PT2, a sufficient separation distance can be ensured between the first pattern PT1 and at least one second electric field line PL2. For example, in the case where the second contact hole CNT2 is formed to electrically connect the first drive electric field line VDDL and the first bus BUS1, electrostatic discharge (ESD) can be transmitted along the metallic material through the second contact hole CNT2 to the first pattern PT1 of the first drive electric field line VDDL. Conversely, for example, electrostatic discharge (ESD) may not be transmitted to the second pattern PT2, which is made of a different material than the first pattern PT1. Therefore, in the first driving electric line VDDL, electrostatic discharge (ESD) can be blocked from traveling along the metallic material to at least one second electric line PL2 by arranging a second pattern PT2 of a different material from the first pattern PT1 forming the second contact hole CNT2. The first driving electric line VDDL can be implemented with a structure robust to electrostatic discharge (ESD). Therefore, by minimizing the electrostatic discharge (ESD) transmitted through the first driving electric line VDDL extending in the first direction DR1, damage to multiple pixels PX (see...) can be prevented. Figure 4 In the display area DA (see) Figure 4 The first pixel PX1 with a stepped arrangement at the edge of the edge (see) Figure 6 Damage to ).

[0121] Reference Figure 8 In the first initialization power line VINTL, one end of the first pattern PT1' can be electrically connected to the first initialization power VINT (see...). Figure 2 The second bus BUS2. Moreover, the other end of the first pattern PT1' can be electrically connected to the second pattern PT2' which has a different material from the first pattern PT1'.

[0122] For example, the first pattern PT1' of the first initialization power line VinTL and the second bus BUS2, which are disposed in different layers, can be connected via the second contact hole CNT2'. The first pattern PT1' of the first initialization power line VinTL can extend from the second bus BUS2 for a predetermined length in the first direction DR1. At a predetermined point thereafter, the first pattern PT1' can be changed to a second pattern PT2' of a different material. The first pattern PT1' can be connected to the second pattern PT2', which is disposed in a different layer from the first pattern PT1', via the first contact hole CNT1'. Therefore, by changing the first initialization power line VinTL from the first pattern PT1' to the second pattern PT2', a sufficient separation distance between the first pattern PT1' and at least one second power line PL2 can be ensured. This can block the path of electrostatic discharge (ESD) being transmitted to at least one second power line PL2. The first initialization power line VinTL can be implemented with a structure robust to electrostatic discharge (ESD). Therefore, electrostatic discharge (ESD) transmitted through the first initialization power line VinTL extending in the first direction DR1 can be minimized, thereby preventing damage to the pixel PX.

[0123] However, although Figure 8 The first driving power line VDDL and the first initialization power line VINTL are shown as examples, but the embodiments are not limited thereto. For example, power lines extending in the first direction DR1 and connected to pixels arranged in a stepped manner at the edge of the display area DA on the lower side of the display panel 110 can be configured similarly to the first driving power line VDDL.

[0124] Figure 9 This illustrates an embodiment of the invention. Figure 4 A magnified view of region B'.

[0125] Reference Figure 4 and Figure 9 The display panel 110 may include at least one first power line PL1, at least one second power line PL2, and at least one bus BUS1 or BUS2.

[0126] The first drive power line VDDL and the first initialization power line VINTL can be connected to Figure 6 The first drive power line VDDL and the first initialization power line VINTL are configured similarly.

[0127] At least one second power line PL2 may be adjacent to one end of at least one data line DL and one end of at least one first power line PL1. In this case, one end of at least one data line DL and one end of at least one first power line PL1 may be adjacent to the first pixel PX1. For example, the first initialization power line VINTL, the second initialization power line VAINT1L, the third initialization power line VAINT2L, and the second drive power line VSSL extending in the second direction DR2 may be adjacent to one end of at least one data line DL extending in the first direction DR1.

[0128] At least one data line DL can extend in the first direction DR1 and can be arranged adjacent to at least one first power line PL1 in the second direction DR2. Therefore, electrostatic discharge (ESD) of the first pattern PT1 transmitted to the first drive power line VDDL via the second contact hole CNT2 can be transmitted to at least one data line DL arranged adjacent to the first drive power line VDDL. Electrostatic discharge (ESD) can be transmitted through at least one data line DL extending in the first direction DR1 and may cause pixel PX to overheat and damage pixel PX.

[0129] According to an embodiment, at least one data line DL may include a third pattern PT3 and a fourth pattern PT4 of a different material from the third pattern PT3. The third pattern PT3 may be spaced apart on a first direction DR1 from at least one second power line PL2 extending on a second direction DR2. The third pattern PT3 may include a metallic material. The fourth pattern PT4 may be electrically connected to the third pattern PT3 and may be relatively closer to the at least one second power line PL2 than the third pattern PT3. The fourth pattern PT4 may be electrically connected to the third pattern PT3 via at least one third contact hole CNT3. The fourth pattern PT4 may include a conductive material with a relatively lower conductivity than the third pattern PT3.

[0130] In this way, in the data line DL arranged adjacent to the first driving electric line VDDL, which is prone to electrostatic discharge (ESD), a sufficient separation distance between the third pattern PT3 and at least one second electric line PL2 can be ensured by arranging a fourth pattern PT4 made of a different material than the third pattern PT3. Therefore, electrostatic discharge (ESD) transmitted to at least one second electric line PL2 via at least one data line DL extending in the first direction DR1 can be minimized, thereby preventing damage to the pixel PX.

[0131] Figure 10 This illustrates an embodiment of the invention. Figure 9 A plan view of the lines.

[0132] Reference Figure 9 and Figure 10 The display panel 110 may include a first drive power line VDDL, a first initialization power line VINTL, at least one data line DL, at least one second power line PL2, and at least one bus BUS1 or BUS2.

[0133] The first drive power line VDDL, the first initialization power line VINTL, at least one second power line PL2, and at least one bus BUS1 or BUS2 can be connected to... Figure 8 The first drive power line VDDL, the first initialization power line VINTL, at least one second power line PL2, and at least one bus BUS1 or BUS2 are configured similarly.

[0134] Reference Figure 10 The data line DL may include a third pattern PT3 and a fourth pattern PT4 made of a different material than the third pattern PT3. For example, the third pattern PT3 may include the same metallic material used to form the gate electrode. The fourth pattern PT4 may include the same conductive material used to form the source and drain electrodes, such as the conductive material used to form the second pattern PT2 of the first drive power line VDDL.

[0135] For example, the third pattern PT3 and the fourth pattern PT4 of the data line DL, which are disposed in different layers, can be connected via the third contact hole CNT3. The third pattern PT3 of the data line DL can extend a predetermined length in the first direction DR1. At a predetermined point thereafter, the third pattern PT3 can be changed to the fourth pattern PT4, which has a different material. The third pattern PT3 can be connected via the third contact hole CNT3 to the fourth pattern PT4, which is disposed in a different layer than the third pattern PT3. For example, the third pattern PT3 of the data line DL can be disposed in the same layer as the first initialization power line VINTL extending in the second direction DR2. Furthermore, the fourth pattern PT4 of the data line DL can be disposed in the same layer as the second pattern PT2 of the first drive power line VDDL and the second drive power line VSSL extending in the second direction DR2. However, the embodiments are not limited to this.

[0136] The third pattern PT3 can be a pattern arranged adjacent to the first pattern PT1 of the first drive power line VDDL. Furthermore, the third pattern PT3 can be further spaced in the first direction DR1 than the fourth pattern PT4 and at least one second power line PL2 extending in the second direction DR2. In this way, by changing the data line DL from the third pattern PT3 to the fourth pattern PT4, a sufficient separation distance can be obtained between the third pattern PT3 and the at least one second power line PL2. For example, electrostatic discharge (ESD) can be transmitted from the first pattern PT1 of the first drive power line VDDL to the third pattern PT3 of the data line DL. Conversely, for example, ESD can be prevented from being transmitted to the fourth pattern PT4, which is made of a different material than the third pattern PT3. Therefore, in the data line DL, the path of ESD transmission along the metallic material to the at least one second power line PL2 can be blocked by arranging the fourth pattern PT4, which is made of a different material than the third pattern PT3. The data line DL can be implemented with a robust structure against ESD. Therefore, electrostatic discharge (ESD) transmitted via the data line DL extending in the first direction DR1 can be minimized, thereby preventing damage to the pixel PX (refer to...). Figure 4 Damage to ).

[0137] The display device according to the embodiments can be applied to various electronic devices. The electronic device according to the embodiments includes the display device described herein, and may also include modules or devices with other additional functions in addition to the display device.

[0138] Figure 11 This is a block diagram illustrating an electronic device according to an embodiment of the present invention.

[0139] Reference Figure 11 The electronic device 10 according to the embodiment may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0140] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0141] The memory 13 can store data information that supports the operation of the processor 12 or the display module 11. In an example where the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals to output image information via the display screen.

[0142] The power module 14 may include a power supply module such as a power adapter or battery cell, and a power conversion module that converts the power supplied by the power supply module to generate power to support the operation of the electronic device 10.

[0143] At least one of the configurations of electronic device 10 described herein may be included within a display device according to the embodiments described herein. Furthermore, some modules that are functionally contained within a single module may be included within the display device, and other modules may be provided separately from the display device. For example, the display device may include display module 11, while processor 12, memory 13, and power module 14 may be provided as other devices within electronic device 10 other than the display device.

[0144] Figure 12 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0145] Reference Figure 12 According to the embodiments, various electronic devices having display devices include electronic devices such as smartphones 10_1a, tablet computers 10_1b, laptop computers 10_1c, televisions 10_1d, and desktop monitors 10_1e for displaying images; wearable electronic devices such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c that include display modules; and automotive electronic devices 10_3 that include display modules, such as central information displays (CIDs) installed on the dashboard, central instrument panel, or dashboard of a car, and rearview mirror displays.

[0146] This invention should not be construed as limited to the embodiments set forth herein. Rather, exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0147] While the invention has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device, wherein, The display device includes: The substrate includes a display area and a non-display area adjacent to the display area; At least one first electric field line extends in a first direction in the non-display area and is connected to a pixel positioned in the display area; and At least one second electric field line extends in a second direction intersecting the first direction and is adjacent to one end of the at least one first electric field line. Wherein, the at least one first power line includes: A first pattern, spaced apart from the at least one second electric field line in the first direction; and The second pattern is electrically connected to the first pattern and is relatively closer to the at least one second electric field line than the first pattern. The first pattern and the second pattern each comprise different materials.

2. The display device according to claim 1, wherein, The pixels are arranged in a stepped manner at the edge of the display area.

3. The display device according to claim 1, wherein: The first pattern includes a metallic material, and The second pattern includes a conductive material.

4. The display device according to claim 1, wherein, The at least one first power line is electrically connected to the bus that supplies the first drive power.

5. The display device according to claim 4, wherein, The at least one first power line overlaps with a portion of the bus.

6. The display device according to claim 4, wherein, One end of the bus is floating at the edge of the non-display area.

7. The display device according to claim 4, wherein: The at least one first electric field line further includes at least one insulating layer in the thickness direction of the display device between the first pattern and the second pattern, and The at least one insulating layer has at least one first contact hole that connects the first pattern and the second pattern.

8. The display device according to claim 7, wherein: One end of the first pattern is connected to the second pattern via the at least one first contact hole, and The other end of the first pattern is connected to the bus via at least one second contact hole, which is different from the at least one first contact hole.

9. The display device according to claim 8, wherein, The at least one second contact hole is further spaced apart from the at least one first contact hole relative to the at least one second electric field line in the first direction.

10. The display device according to any one of claims 1 to 9, wherein, The display device further includes: at least one data line extending in the first direction and adjacent to the at least one first power line in the second direction.

11. The display device according to claim 10, wherein, The at least one data line includes: A third pattern, spaced apart from the at least one second electric field line in the first direction; and The fourth pattern is electrically connected to the third pattern and is relatively closer to the at least one of the second electric lines than the third pattern. The third pattern and the fourth pattern each consist of different materials.

12. The display device according to claim 11, wherein: The third pattern includes a metallic material, and The fourth pattern includes a conductive material.

13. The display device according to claim 11, wherein, The third pattern and the fourth pattern are electrically connected via at least one third contact hole.

14. An electronic device, wherein, The electronic device includes: Processor; and The display device according to any one of claims 1 to 13 displays an image under the control of the processor.

Images