Display panel, preparation method thereof and display device

Abstract

The application discloses a display panel and a preparation method thereof and a display device. The display panel comprises a first substrate, a first signal transmission layer located on one side of the first substrate and comprising a first signal transmission part, a blocking layer located on a side of the first signal transmission layer away from the first substrate, a second opening provided in the blocking layer, the second opening comprising a first side surface, a second substrate located on a side of the blocking layer away from the first substrate, a third opening provided in the second substrate, the third opening comprising a second side surface and a first bottom surface, the second side surface being non-coplanar with the first side surface, an insulating layer located on a side of the second substrate away from the first substrate, at least one insulating layer opening provided in the insulating layer, and a second signal transmission layer covering the sidewall of the insulating layer opening and the first side surface and comprising a second signal transmission part, the second signal transmission part being electrically connected with the first signal transmission part. Thus, the narrow frame design of the display panel is realized, and the performance of the display panel is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel, its manufacturing method, and a display device. Background Technology

[0002] With the continuous development of information technology, display panels are widely used in automotive electronics, industrial and medical fields, smart homes, and the Internet.

[0003] Currently, the fan-out traces at the bottom edge of the display panel are bent 180° towards the back and bonded to the driver chip using a bonding method. However, even with this method, the bottom bezel of the display panel is still relatively large, therefore, further improvements are needed to reduce the size of the bottom bezel. Summary of the Invention

[0004] This invention provides a display panel and its manufacturing method and display device to achieve a frame-finding design for the display panel. By setting the second side to be non-coplanar with the first side, the stability of the electrical connection between the second signal transmission unit and the first signal transmission unit can be guaranteed, thereby improving the performance of the display panel.

[0005] In a first aspect, embodiments of the present invention provide a display panel, comprising: A first substrate, wherein a first opening is provided in the first substrate; A first signal transmission layer is located on one side of the first substrate and includes a first signal transmission portion; along a first direction, the first signal transmission portion at least partially overlaps with the first opening; the first direction is the thickness direction of the display panel; A barrier layer is located on the side of the first signal transmission layer away from the first substrate; a second opening is provided in the barrier layer; along the first direction, the second opening at least partially overlaps with the first signal transmission portion; the second opening includes a first side surface; A second substrate is located on the side of the barrier layer away from the first substrate, and a third opening is provided in the second substrate; along the first direction, the orthographic projection of the third opening on the first substrate overlaps the orthographic projection of the second opening on the second substrate; the third opening includes a second side surface and a first bottom surface; the second side surface and the first side surface are not coplanar; An insulating layer is located on the side of the second substrate away from the first substrate, the insulating layer covering the second side surface and at least a portion of the first bottom surface; the insulating layer has at least one insulating layer opening, the insulating layer opening penetrating the insulating layer and communicating with the second opening; The second signal transmission layer covers the sidewall of the opening in the insulating layer and the first sidewall and includes a second signal transmission section; and the second signal transmission section is electrically connected to the first signal transmission section.

[0006] Secondly, embodiments of the present invention also provide a method for manufacturing a display panel, comprising: Provide a first substrate; A first signal transmission layer is formed on one side of the first substrate; the first signal transmission layer includes a first signal transmission portion; A barrier layer is prepared on the side of the first signal transmission layer away from the first substrate; A second substrate is prepared on the side of the barrier layer away from the first substrate, and a third opening is prepared in the second substrate; the third opening includes a second side surface and a first bottom surface; An insulating layer is formed on the side of the second substrate away from the first substrate, the insulating layer covering the second side surface and at least a portion of the first bottom surface; The insulating layer and the barrier layer are patterned to form at least one insulating layer opening in the insulating layer and a second opening in the barrier layer; the insulating layer opening penetrates the insulating layer and communicates with the second opening; along a first direction, the second opening at least partially overlaps with the first signal transmission portion; the second opening includes a first side surface; along the first direction, the orthographic projection of the third opening on the first substrate covers the orthographic projection of the second opening on the second substrate; the second side surface is not coplanar with the first side surface. A second signal transmission layer is prepared; the second signal transmission layer includes a second signal transmission section; the second signal transmission layer covers the sidewall of the opening of the insulating layer and the first side surface, and the second signal transmission section is electrically connected to the first signal transmission section; The first substrate is patterned to form a first opening in the first substrate; the first signal transmission portion at least partially overlaps with the first opening along a first direction; the first direction is the thickness direction of the display panel.

[0007] Thirdly, embodiments of the present invention also provide a display device, including the display panel described in the first aspect.

[0008] The technical solution provided in this invention includes a second opening in the barrier layer comprising a first side surface, and a third opening in the second substrate comprising a second side surface. The second side surface and the first side surface are not coplanar, meaning they are not on the same horizontal plane but are staggered. This reduces the slope between the second and first sides, creating a stepped effect at the second and third openings, thus preventing a large slope from causing a break in the second signal transmission section at the opening. During the display panel fabrication process, the third and second openings are not fabricated in a single etching step but are fabricated separately. This prevents side etching of the barrier layer, ensuring the stability of the connection between the second and first metal transmission sections, and consequently, the stability and reliability of the display panel. Furthermore, the second and first signal transmission sections are electrically connected, eliminating the need to bend the display panel for normal display and reducing the bezel size, which facilitates miniaturization and integration of the display panel. Attached Figure Description

[0009] Figure 1 A top view schematic diagram of a display panel provided in an embodiment of the present invention; Figure 2 for Figure 1 A schematic diagram of a cross-sectional structure of the corresponding display panel along section line A-A'; Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure of the corresponding display panel along section line B-B'; Figure 4 for Figure 2 A magnified structural diagram of region aa in the middle; Figure 5 An electrical schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 6 for Figure 5 The diagram shows the driving timing of the pixel circuit during one driving cycle. Figure 7 A top view schematic diagram of another display panel provided in an embodiment of the present invention; Figure 8 for Figure 7 A schematic diagram of the cross-sectional structure of the corresponding display panel along section line C-C'; Figure 9 An electrical schematic diagram of a pixel driving circuit provided in an embodiment of the present invention; Figure 10 A schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present invention; Figure 11A schematic flowchart illustrating another method for manufacturing a display panel according to an embodiment of the present invention; Figure 12 A schematic flowchart illustrating another method for manufacturing a display panel according to an embodiment of the present invention; Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0010] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0011] In the description of this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0012] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above" or "on the upper surface" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature.

[0013] In the description of this embodiment, the terms "upper," "lower," "left," and "right," etc., refer to the orientation or positional relationship shown in the accompanying drawings. They are used only for ease of description and simplification of operation, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive distinction and have no special meaning.

[0014] The inventors discovered that in existing technologies, the bottom bezel of display panels is still relatively large. Furthermore, in existing display panels, the second opening within the barrier layer and the third opening within the second substrate are fabricated using a single etching process. This results in the first side of the second opening and the second side of the third opening being coplanar. Consequently, the barrier layer exhibits side etching, which can lead to broken lines in the second signal transmission layer during subsequent fabrication of the insulating layer and the second signal transmission layer, thus affecting the performance of the display panel.

[0015] Based on the above research findings, the inventors further developed the technical solution in the embodiments of the present invention. By connecting the second signal transmission unit to the first signal transmission unit, the display panel can be displayed normally without bending it, and the size of the small bezel of the display panel can be reduced, which is beneficial for miniaturization and integration of the display panel. In addition, by ensuring that the second side is not coplanar with the first side, the connection effect between the second signal transmission unit and the first signal transmission unit can be guaranteed, thereby improving the stability and reliability of the display panel.

[0016] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0017] Figure 1 This is a top view schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 for Figure 1 The corresponding display panel along section line A-A' is shown in the first cross-sectional structure diagram, as follows: Figure 1 and Figure 2 As shown, the display panel 100 includes: a first substrate 10, in which a first opening 101 is provided; a first signal transmission layer 20, located on one side of the first substrate 10 and including a first signal transmission portion 201; and a first signal transmission layer along a first direction (e.g., along the first direction). Figure 2In the Z direction shown, the first signal transmission section 201 and the first opening 101 at least partially overlap; the first direction Z is the thickness direction of the display panel; a barrier layer 30 is located on the side of the first signal transmission layer 20 away from the first substrate 10; a second opening 301 is provided in the barrier layer 30; along the first direction Z, the second opening 302 at least partially overlaps with the first signal transmission section 201; the second opening 301 includes a first side surface a1; a second substrate 40 is located on the side of the barrier layer 30 away from the first substrate 10, and a third opening 401 is provided in the second substrate 40; along the first direction Z, the orthographic projection of the third opening 401 on the first substrate 10 covers the second opening 301. 1. Orthographic projection on the second substrate 40; the third opening 401 includes a second side surface a2 and a first bottom surface b1; the second side surface a2 and the first side surface a1 are not coplanar; an insulating layer 50 is located on the side of the second substrate 40 away from the first substrate 10, the insulating layer 50 covers the second side surface a2 and at least part of the first bottom surface b1; at least one insulating layer opening 501 is provided in the insulating layer 50, the insulating layer opening 501 penetrates the insulating layer 50 and communicates with the second opening 301; a second signal transmission layer 60 covers the sidewall of the opening of the insulating layer 50 and the first side surface a1 and includes a second signal transmission part 601; and the second signal transmission part 601 is electrically connected to the first signal transmission part 201.

[0018] Specifically, the display area AA can be equipped with multiple light-emitting elements 200, pixel circuits 300, and signal traces 400. The pixel circuits 300 are electrically connected to the light-emitting elements 200 and are used to provide display signals to the light-emitting elements 200 to realize the display function of the display panel 100. The signal traces 400 can be electrically connected to the pixel circuits 300 or serve as signal traces for other auxiliary functions. For example, the signal traces 400 can include scan signal traces 4001 and data signal traces 4002. The scan signal trace 4001 can provide scan signals to the pixel circuits 300 to control the conduction and cutoff of the transistors in the pixel circuits 300. The data signal trace 4002 can provide data signals to the pixel circuits 300 to control the transistors in the pixel circuits 300 to generate drive current signals based on the data signals and write the drive current signals into the first electrode (such as the anode) in the light-emitting element 200, so as to realize the normal light emission or light emission of the light-emitting element 200 and realize the display function of the display panel.

[0019] For details, please refer to [link / reference]. Figures 1-3The first signal transmission layer 20 includes multiple independently configured first signal transmission units 201. For example, the first signal transmission unit 201 may include a first clock signal transmission unit CK for transmitting a clock signal ck, a second clock signal transmission unit XCK for transmitting an inverted clock signal xck, a first level power signal transmission unit VGH for transmitting a high-level signal vgh, a second level power signal transmission unit VGL for transmitting a low-level signal vgl, and a data signal transmission unit Vdata for transmitting a data signal data.

[0020] Continue to refer to Figure 2 The first signal transmission unit 201 may be a data signal transmission unit Vdata. The data signal data output by the driving structure 70 is transmitted to the pixel circuit 300 through the data signal transmission unit Vdata, so that the pixel circuit 300 outputs a display signal to the light-emitting element 200 based on the data signal data.

[0021] Figure 3 for Figure 1 A cross-sectional view of the corresponding display panel along section line B-B' is shown below. Figure 3 As shown, a first-level power signal transmission unit VGH or a second-level power signal transmission unit VGL. For example, Figure 3 Taking the first-level power signal transmission unit VGH being electrically connected to the source in the pixel driving circuit 80 as an example, it can be understood that the first signal transmission unit 201 can also be a first clock signal transmission unit CK or a second clock signal transmission unit XCK. Thus, the display driving signal output by the driving structure 70 is transmitted to the pixel driving circuit 80 through at least one first signal transmission unit 201, so that the pixel driving circuit 80 drives the pixel circuit 300 to provide a display signal to the light-emitting element 200.

[0022] For example, the pixel driving circuit 80 can be a vertical shift register (VSR). Furthermore, the driving method of the pixel driving circuit 80 can be divided into single-sided driving and double-sided driving based on the location and operation of the driving circuit. Single-sided driving (not shown in the figure) involves placing the pixel driving circuit 80 only on one side of the display panel, outputting scan signals line by line to drive the scanning of the pixel circuits in the display panel. Double-sided driving involves placing the pixel driving circuit 80 on both sides of the display panel, such as... Figure 1 As shown, the driving circuits located on both sides of the display panel output scanning signals simultaneously or in a time-division manner to realize the scanning drive of the pixel circuits in the display panel.

[0023] For details, please refer to [link / reference]. Figure 2The first substrate 10 can support the film structure on the film layer. The second substrate 40 is located on the side of the first signal transmission layer 20 away from the first substrate 10. The second substrate 40 has a third opening 401 so that the second signal transmission part 601 can be electrically connected to the first signal transmission part 201 through the third opening 401. For example, both the first substrate 10 and the second substrate 40 can be made of polyimide. On the one hand, polyimide has high temperature resistance, which can meet the requirements of high temperature processes in the manufacturing of display panels. On the other hand, polyimide has good ductility, which can ensure the bendability of the display panel.

[0024] For details, please refer to [link / reference]. Figure 2 The barrier layer 30 is located on the side of the first signal transmission layer 20 away from the first substrate 10. In this way, by setting the barrier layer 30, it can isolate the substrate surface defects on the one hand, and block impurities such as water and oxygen on the other hand. The barrier layer 30 is provided with a second opening 301, and the first side a1 can be understood as the sidewall of the second opening 301.

[0025] Furthermore, the second side a2 of the third opening 401 is not coplanar with the first side a1 of the second opening 301; that is, the second side a2 and the first side a1 are not on the same plane but are staggered. This reduces the slope between the second side a2 and the first side a1, thus preventing a large slope from causing a break in the second signal transmission unit 601 at the opening position. During the manufacturing process of the display panel, the third opening 301 and the second opening 301 are not fabricated using a single etching process but are fabricated separately. This prevents side etching of the barrier layer 30, which helps ensure the stability of the connection between the second metal transmission unit 601 and the first metal transmission unit 201, thereby contributing to the stability and reliability of the display panel.

[0026] For details, please refer to [link / reference]. Figure 2 The insulating layer 50 is located on the side of the second substrate 40 away from the first substrate 10, thus providing electrical isolation and preventing short circuits between different metal traces. The insulating layer 50 covers the second side surface a2 and at least part of the first bottom surface b1, meaning that the insulating layer 50 covers the sidewall and bottom surface of the third opening 401, but does not cover the second opening 301 within the barrier layer 30. At least one insulating layer opening 501 is provided in the insulating layer 50, penetrating the insulating layer 50 and communicating with the second opening 301, so that the subsequent second metal transport section 601 can connect to the first metal transport section 201 through the insulating layer opening 501 and the second opening 301.

[0027] For details, please refer to [link / reference]. Figure 2The second signal transmission layer 60 includes a second signal transmission unit 601, which is used to write a driving current signal into the first electrode (such as the anode) of the light-emitting element 200, so as to realize the normal light emission or light emission of the light-emitting element 200 and realize the display function of the display panel. The second signal transmission unit 601 is electrically connected to the first signal transmission unit 201, so that the first signal transmission unit 201 can transmit the signal to the first electrode in the light-emitting element 200 to realize the normal light emission or light emission of the light-emitting element 200. In this way, the display panel can be displayed normally without bending the display panel, and the size of the small bezel of the display panel can be reduced. The size of the bottom bezel of the display panel in the prior art can be reduced from 0.8mm to less than 0.5mm, which is conducive to the miniaturization and integration of the display panel.

[0028] The display panel provided in this embodiment of the invention, by setting the second side to be non-coplanar with the first side, can reduce the slope between the second side and the first side, thereby preventing the second signal transmission part from breaking at the opening position due to the large slope between the second side and the first side. This is beneficial to ensuring the connection effect between the second signal transmission part and the first signal transmission part, thereby improving the stability and reliability of the display panel.

[0029] Optional, continue to refer to Figure 2 At least one insulating layer opening 501 includes a first insulating layer opening 5011 and a second insulating layer opening 5012, the first insulating layer opening 5011 and the second insulating layer opening 5012 are connected; the insulating layer 50 includes multiple insulator layers 51; the first insulating layer opening 5012 penetrates at least one insulator layer 51, and the second insulating layer opening 5012 penetrates at least one insulator layer 51 and is connected to the second opening 301.

[0030] Specifically, the first insulating layer opening 5011 is located above the second insulating layer opening 5012. The first insulating layer opening 5011 penetrates at least one insulator layer, and the second insulating layer opening 5012 penetrates at least one insulator layer 51. The first insulating layer opening 5011 can be formed by patterning a portion of the insulating layer 50 using a Split-Contact Normal-etch (SCNT) process. The second insulating layer opening 5012 and the second opening 301 can be formed using the same etching process, thus simplifying the manufacturing process of the display panel. For example, the second insulating layer opening 5012 and the second opening 301 can be formed using an Array Pad Break (APB) process or a One-Contact Normal-etch (OCNT) process.

[0031] Optional, Figure 4 for Figure 2 A magnified structural diagram of region aa in the middle, as shown below. Figure 2 and Figure 4 As shown, the second insulating layer opening 5012 includes the first insulating layer side surface a3; the angle between the first insulating layer side surface a3 and the first direction Z is θ1, and the angle between the first side surface a1 and the first direction Z is θ2; wherein, |θ1-θ2|≤5°.

[0032] Specifically, the angle θ1 between the first insulating layer side a3 and the first direction Z and the angle θ2 between the first side a1 and the first direction Z satisfy |θ1-θ2|≤5°, that is, θ1 is approximately equal to θ2, that is, the first insulating layer side a3 and the first side a1 are almost coplanar. In other words, the second insulating layer opening 5012 and the second opening 301 are prepared using the same etching process step. Thus, the manufacturing process of the display panel is simple and does not require the addition of a new mask.

[0033] Optional, continue to refer to Figure 2 The display panel also includes a display area AA and a pixel circuit 300 located in the display area; the pixel circuit 300 includes a first transistor 31, the first transistor 31 including a first input electrode 311, a first output electrode 312, a first gate 313 and a first active layer 314; the first input electrode 311 and the first output electrode 312 are both connected to the first active layer 314; the multilayer insulator layer 51 includes a first insulator layer 511 and a second insulator layer 512, the first input electrode 311 is located on the side of the first insulator layer 511 away from the first substrate 10 and is in contact with the first insulator layer 511, and the first active layer 314 is located on the side of the first insulator layer 511 away from the first substrate 10. The second insulator layer 512 is located on the side away from the first substrate 10 and is in contact with the second insulator layer 512; the multilayer insulator layer 51 further includes at least one third insulator layer 513 and at least one fourth insulator layer 514. Along the first direction Z, the third insulator layer 513 is located between the first insulator layer 511 and the second insulator layer 512, and the fourth insulator layer 514 is located between the second insulator layer 512 and the barrier layer 30; the first insulating layer opening 5011 penetrates the first insulator layer 51 and the multilayer third insulator layer 513, and the second insulating layer opening 5012 penetrates the second insulator layer 512 and the multilayer fourth insulator layer 514.

[0034] Specifically, the pixel circuit 300 includes a first transistor 31. For example, the first input electrode 311 can be a source, and the first output electrode 312 can be a drain. The first gate 313 is disposed corresponding to the channel region of the first active layer 314, the source is disposed corresponding to the source region of the first active layer 314, and the drain is disposed corresponding to the drain region of the first active layer 314. Under the action of the signal of the first gate 313, the channel region is turned on, changing from a non-conductor state to a conductor state, forming a path between the corresponding source and drain, and the data signal can be sequentially written to the drain through the source and the channel region. For example, the first gate 313 provided in this embodiment of the invention can be located on the side of the first active layer 314 away from the first substrate 10, that is, the first gate 311 can be a top gate.

[0035] Specifically, the first input electrode 311 is located on the upper surface of the first insulator layer 511 and is in contact with the first insulator layer 511; the first active layer 314 is located on the upper surface of the second insulator layer 512 and is in contact with the second insulator layer 512. At least one third insulator layer 513 is located between the first insulator layer 511 and the second insulator layer 512; and at least one fourth insulator layer 514 is located between the second insulator layer 512 and the barrier layer 30. The first insulating layer opening 5011 penetrates the first insulator layer 51 and the multilayer third insulator layer 513, thus patterning the first insulator layer 511 and the multilayer third insulator layer 513 to form the first insulating layer opening 5011 and the first connection via 500 in the insulating layer 50. The first input electrode 311 and the first output electrode 312 are both connected to the first active layer 314 through the first connection via 500. That is to say, the first insulating layer opening 5011 and the first connection via 500 can be prepared by the same etching process, thus simplifying the manufacturing process of the display panel and eliminating the need for additional photomasks.

[0036] In addition, the pixel circuit 300 may also include a fourth transistor 32, which includes a fourth input electrode 321, a fourth output electrode 322, a fourth gate 323, and a second active layer 324. The fourth input electrode 321 is located on the side of the first insulator layer 511 away from the first substrate 10 and is in contact with the first insulator layer 511. The second active layer 324 is located in the third insulator layer 513. The second insulating layer opening 5012 penetrates the second insulator layer 512 and the multilayer fourth insulator layer 514. Thus, through the first insulating layer opening 5011, the second insulator layer 512, the multilayer fourth insulator layer 514, and the barrier layer 30 are patterned to form the second insulator layer opening 5012 and the second connection via 600 in the insulating layer 50, and the second opening 301 in the barrier layer 30. The fourth input electrode 321 and the fourth output electrode 322 are both connected to the second active layer 324 through the second connection via 600. That is to say, the second insulator layer opening 5012 and the second connection via 600 can be prepared by the same etching process, thus simplifying the manufacturing process of the display panel and eliminating the need for additional photomasks.

[0037] Optional, continue to refer to Figure 2 Along the second direction (such as) Figure 2 The minimum distance between the first side a1 and the second side a2 is D (as shown in the X direction); the second direction X is parallel to the plane where the first substrate 10 is located and intersects with the thickness direction of the display panel; where D > 2μm.

[0038] Specifically, the minimum distance between the first side a1 and the second side a2 can be understood as the distance between the left side wall of the second opening 301 and the left side wall of the third opening 401, or the distance between the right side wall of the second opening 301 and the right side wall of the third opening 401.

[0039] In the prior art, since the second substrate 40 and the barrier layer 30 are etched simultaneously, the sides of the two etched openings are coplanar, resulting in a small minimum distance between the first side a1 and the second side a2. However, in the embodiment of the present invention, the second substrate 40 and the barrier layer 30 are etched separately, so the first side a1 and the second side a2 are not coplanar, and the minimum distance D between them is greater than 2 μm. This allows for the formation of stepped structures at the positions of the second opening 301 and the third opening 401, which helps to ensure the stability of the connection between the second metal transmission part 601 and the first metal transmission part 201, thereby ensuring the signal transmission effect.

[0040] Optional, continue to refer to Figure 2The angle between the first side a1 and the second direction X is θ3, and the angle between the second side a2 and the second direction X is θ4; the second direction X is parallel to the plane where the first substrate 10 is located and intersects the thickness direction of the display panel; wherein, θ3 > θ4.

[0041] Specifically, the angle θ3 between the first side a1 and the second direction X is greater than the angle θ4 between the second side a2 and the second direction X, so as to form a stepped step at the corresponding position of the third opening 401 and the second opening 301, which is conducive to the second signal transmission unit 601 contacting and connecting with the first signal transmission unit 201 in the second opening 301, and the connection between the two is stable, thereby improving the performance of the display panel.

[0042] Optional, continue to refer to Figure 2 , 70°≤θ4≤80°.

[0043] For example, when θ4 < 70°, the slope of the second side a2 is relatively gentle, resulting in a larger opening size of the third opening 401 in the first direction X, which in turn affects the resolution of the display panel. When θ4 > 80°, the fabrication process of the third opening 401 becomes more difficult. However, by setting 70° ≤ θ4 ≤ 80°, this embodiment of the invention matches the fabrication process of the third opening 401 on the one hand, and ensures that the opening size of the third opening 401 in the first direction X is moderate on the other hand, thereby preventing the third opening 401 from being too large in the first direction X and affecting the resolution of the display panel.

[0044] Optional, continue to refer to Figure 2 The orthographic projection of the first insulating layer opening 5011 on the first substrate 10 covers the orthographic projection of the second insulating layer opening 5012 on the first substrate 10.

[0045] Specifically, the orthographic projection of the first insulating layer opening 5011 on the first substrate 10 covers the orthographic projection of the second insulating layer opening 5012 on the first substrate 10. That is, the opening size of the first insulating layer opening 5011 is larger than the opening size of the second insulating layer opening 5012, which facilitates the patterning of the remaining insulating layer 50 through the first insulating layer opening 5011 to form the second insulating layer opening 5012, thus facilitating the preparation of the second insulating layer opening 5012.

[0046] Optional, continue to refer to Figure 1 and Figure 2 The display panel 100 also includes a display area AA and a pixel circuit 300 located in the display area AA; the pixel circuit 300 includes a first transistor 31, the first transistor 31 includes a first input electrode 311, a first output electrode 312 and a first gate 313; the first input electrode 311 is electrically connected to the second signal transmission unit 601.

[0047] Specifically, the first input electrode 301 is electrically connected to the second signal transmission unit 601. Thus, the data signal output by the driving structure 70 is transmitted to the first input electrode 311 through the first signal transmission unit 201 and the second signal transmission unit 601 in sequence, so that the pixel circuit 300 outputs a display signal to the light-emitting element 200 based on the data signal data, thereby realizing the display function of the display panel.

[0048] Optional, continue to refer to Figure 2 The first signal transmission unit 201 includes a first data signal transmission unit Vdata, and the second signal transmission unit 601 includes a second data signal transmission unit 6011; the first data signal transmission unit Vdata and the second data signal transmission unit 6011 are electrically connected.

[0049] Specifically, the data signal data output by the driving structure 70 is transmitted to the second data signal transmission unit 6011 through the first data signal transmission unit Vdata, and then transmitted by the second data signal transmission unit 6011 to the first input electrode 311, so that the pixel circuit 300 outputs a display signal to the light-emitting element 200 based on the data signal data, thereby realizing the display function of the display panel.

[0050] For example, Figure 5 This is an electrical schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 6 for Figure 5 The diagram shown illustrates the driving timing of the pixel circuit within one driving cycle, as follows: Figure 5 and Figure 6 As shown, the transistors in the pixel circuit 300 can be of various types. For example, transistors can include low-temperature polysilicon (LTPS) transistors, which have advantages such as high switching speed, high carrier mobility, and low power consumption. Transistors can also include indium gallium zinc oxide (IGZO) transistors, which have advantages such as low leakage current. Figure 5 The pixel circuit is illustrated using "7T1C" as an example, where "T" represents a transistor and "C" represents a capacitor. This embodiment of the invention is only illustrated using this example. Other pixel circuits, such as "6T1C" and "8T1C" pixel circuits, are within the scope of the technical solutions protected by this embodiment of the invention.

[0051] For details, please refer to [link / reference]. Figure 5 and Figure 6The pixel circuit may include a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization transistor T5, a second light-emitting control transistor T6, a reset transistor T7, and a storage capacitor Cst. Specifically, for the operation process of the pixel circuit, refer to... Figure 5 and Figure 6 For example, the first scan signal line S1 controls the on / off state of the initialization transistor T5 of the pixel circuit. When the initialization transistor T5 is on, it resets the gate potential of the driving transistor T3, that is, it transmits the initialization signal of the initialization signal line VREF1 to the initialization transistor T5 and resets the connection node (first node N1) of the driving transistor T3, the initialization transistor T5, the threshold compensation transistor T4, and the storage capacitor Cst. The third scan signal line SP' controls the on / off state of the data writing transistor T2 of the pixel circuit. When the data writing transistor T2 is on, it writes the data signal on the data signal line Data to the gate of the driving transistor T3. The second scan signal line S2 controls the on / off state of the threshold compensation transistor T4, and compensates the threshold voltage of the driving transistor T3 when the threshold compensation transistor T4 is on. At the same time, the fourth scan signal line SP controls the on / off state of the reset transistor T7, and resets the anode of the light-emitting element connected to the pixel circuit when the reset transistor T7 is on, that is, it transmits the reset signal of the reset signal line VREF2 to the anode of the light-emitting element. The light-emitting control signal line EMIT controls the on and off of the first light-emitting control transistor T1 and the second light-emitting control transistor T6. When the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on, the power signal transmitted by the power signal line PVDD is transmitted to the light-emitting element, thereby realizing the display and light emission of the light-emitting element.

[0052] For example, continue to refer to Figure 5 and Figure 6Taking the initialization transistor T5 and threshold compensation transistor T4 in the pixel circuit as N-type transistors, and the remaining transistors as P-type transistors as an example, the enable level turns the transistor on, and the disable level turns it off (or cuts off). Specifically, the disable level of the light emission control signal EMIT is high, and the enable level is low; the enable level of the signals transmitted by the first scan signal line S1 and the second scan signal line S2 is high, and the disable level is low; the enable level of the signals transmitted by the fourth scan signal line SP and the third scan signal line SP' is low, and the disable level is high. Specifically, in one driving cycle Y of the pixel circuit, the gate signal transmitted by the light emission control signal line EMIT includes multiple disable level stages and multiple enable level stages, which are arranged alternately. When the light emission control signal line EMIT is at the disable level, the first light emission control transistor T1 and the second light emission control transistor T6 are cut off; when the light emission control signal line EMIT is at the enable level, the first light emission control transistor T1 and the second light emission control transistor T6 are turned on.

[0053] Furthermore, in one driving cycle Y of the pixel circuit, there are a data writing stage Y1, an emission stage Y2, and an emission holding stage Y3. The data writing stage Y1 includes a disabled level stage of the emission control signal EMIT; the emission stage Y2 includes an enabled level stage of the emission control signal EMIT; and in the emission holding stage Y3, the emission control signal EMIT includes multiple disabled level stages and at least one enabled level stage. Figure 5 (Taking an enable level stage as an example for illustration). Meanwhile, the magnitude of the bias voltage signal line DVH in the data writing stage Y1 and the light emission stage Y2 can be the same as or different from the magnitude of the bias voltage signal line DVH in the light emission holding stage Y3. Figure 6 (Illustration in Chinese).

[0054] Furthermore, the data writing stage Y1 includes a first bias adjustment stage Y11. In the first bias adjustment stage Y11, the signal transmitted by the fourth scan signal line SP includes at least one low-level period, and during this period, the signal transmitted by the second scan signal line S2 includes at least one high-level period. That is, in the first bias adjustment stage Y11, the bias signal can adjust the bias of both the first node N1 and the second node N2. The data writing stage Y1 also includes an initialization and second bias adjustment stage Y12. In the initialization and second bias adjustment stage Y12, the signal transmitted by the second scan signal line S2 includes at least one high-level period. In other words, in the initialization and second bias adjustment stage Y12, the initialization transistor T5 is turned on, and the subsequent threshold compensation transistor T4 is also turned on. The initialization signal line VREF1 can adjust the gate of the driving transistor T3 through the initialization transistor T5. The initialization signal line VREF1 can also adjust the second node N2 through the initialization transistor T5 and the threshold compensation transistor T4.

[0055] The data writing stage Y1 also includes a data signal writing stage Y13. In the data signal writing stage Y13, the signal transmitted by the second scan signal line S2 includes a high-level period, while the signal transmitted by the third scan signal line SP' includes at least one low-level period. In other words, in the data signal writing stage Y13, the data writing transistor T2 and the threshold compensation transistor T4 are turned on, and the data signal can be transmitted to the gate of the driving transistor T3 through the data writing transistor T2 and the threshold compensation transistor T4. The data writing stage Y1 also includes a third bias adjustment stage Y14. In the third bias adjustment stage Y14, the signal transmitted by the fourth scan signal line SP includes at least one low-level period, during which the bias transistor T8 can further adjust the bias of the second stage N2.

[0056] Furthermore, if a driving cycle Y of the pixel circuit is a low-frequency cycle, then the driving cycle Y includes a data writing phase Y1, a light emission phase Y2, and a light emission holding phase Y3. If a driving cycle Y of the pixel circuit is a high-frequency cycle, then the driving cycle Y includes a data writing phase Y1 and a light emission phase Y2.

[0057] Exemplarily, the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the second light-emitting control transistor T6, and the reset transistor T7 can all be PMOS transistors; the threshold compensation transistor T4 and the initialization transistor T5 can be at least one PMOS transistor or at least one NMOS transistor. This embodiment of the invention only illustrates the example where both the threshold compensation transistor T4 and the initialization transistor T5 are NMOS transistors. This embodiment of the invention is not limited to any specific type of display panel and can be adapted to meet actual production needs.

[0058] Furthermore, the threshold compensation transistor T4 and the initialization transistor T5 can be either single-gate transistors or dual-gate transistors. When a dual-gate transistor is used, the leakage current of the transistor is reduced, thus improving the display effect of the display panel. This invention is illustrated only with the example where both the threshold compensation transistor T4 and the initialization transistor T5 are top-bottom dual-gate transistors.

[0059] like Figure 5 As shown, reset transistor T7 and second light-emitting control transistor T6 are connected to the anode of the light-emitting element. The connection node between reset transistor T7, second light-emitting control transistor T6 and the anode of the light-emitting element is the third node N3. The pixel circuit is connected to the anode of the light-emitting element through the third node N3. The connection node between the light-emitting element 200 and the pixel circuit 300 is the third node N3. The anode of the light-emitting element 200 is connected to the third node N3 of the corresponding pixel circuit 300.

[0060] Optional, Figure 7 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention. Figure 8 for Figure 7 The corresponding cross-sectional structural diagram of the display panel along section line D-D' is shown below. Figure 7 and Figure 8 As shown, the display panel also includes a display area AA and a pixel driving circuit 80 located in the display area AA; the pixel driving circuit 80 includes a second transistor 81, the second transistor 81 includes a second input electrode 811, a second output electrode 812 and a second gate 813; the second input electrode 811 is electrically connected to the second signal transmission unit 601.

[0061] Specifically, in the prior art, the pixel driving circuit is usually located in the non-display area, which results in a large bezel of the display panel and makes it impossible to achieve a narrow bezel design. However, the present invention sets the pixel driving circuit 80 in the display area AA, that is, changes the setting position of the pixel driving circuit 80 in the prior art, changing the setting of the pixel driving circuit 80 from the non-display area to the display area. This can reduce the size of the non-display area NA, which is beneficial to achieving a narrow bezel design of the display panel.

[0062] Specifically, the second input electrode 811 is electrically connected to the second signal transmission unit 601. Thus, the high-level signal vgh output by the driving structure 70 is transmitted to the second input electrode 811 sequentially through the first level power signal transmission unit VGH and the second signal transmission unit 601, or the low-level signal vgl output by the driving structure 70 is transmitted to the second input electrode 811 sequentially through the second level power signal transmission unit VGL and the second signal transmission unit 601, and then transmitted to the pixel driving circuit 80, so that the pixel driving circuit 80 drives the pixel circuit 300 to provide display signals to the light-emitting element 200.

[0063] Optional, continue to refer to Figure 1 and Figure 3 The display panel 100 also includes a display area AA and a non-display area NA; the non-display area NA surrounds at least a portion of the display area AA; the display panel also includes a pixel driving circuit 80; the pixel driving circuit 80 is located in the non-display area NA; the pixel driving circuit 80 includes a third transistor 82; the third transistor 82 includes a third input electrode 821, a third output electrode 822 and a third gate 823; the second signal transmission unit 601 includes a first signal transmission unit 601-1 located in the non-display area NA and a second signal transmission unit 601-2 located in the display area AA; the first signal transmission unit 601-1 is electrically connected to the third input electrode 821 and the second signal transmission unit 601-2 respectively.

[0064] Specifically, the display panel 100 also includes a pixel driving circuit 80; the pixel driving circuit 80 is located in the non-display area NA, and the second signal transmission unit 601 includes a first signal transmission unit 601-1 located in the non-display area NA and a second signal transmission unit 601-2 located in the display area NA. That is, in order to achieve electrical connection with the input terminal of the pixel driving circuit 80 located in the non-display area NA, the second signal transmission layer 60 needs to extend to the non-display area NA, that is, it is electrically connected to the third input electrode 821 through the first signal transmission unit 601-1 located in the non-display area NA. In this way, the driving structure 7 can be connected to the third input electrode 821. The high-level signal vgh output from 0 is transmitted sequentially through the first level power signal transmission unit VGH, the first signal transmission unit 601-1, and the second signal transmission unit 601-2 to the third input electrode 821. Alternatively, the low-level signal vgl output from the driving structure 70 is transmitted sequentially through the second level power signal transmission unit VGL, the first signal transmission unit 601-1, and the second signal transmission unit 601-2 to the third input electrode 821, and then transmitted to the pixel driving circuit 80, so that the pixel driving circuit 80 drives the pixel circuit 300 to provide display signals to the light-emitting element 200.

[0065] Optional, Figure 9 This is an electrical schematic diagram of a pixel driving circuit provided in an embodiment of the present invention, such as... Figure 9 As shown, the pixel driving circuit 80 includes a clock control transistor M1, an inverting clock control transistor M2, a first-level power supply transistor M3, and a second-level power supply transistor M4; the first signal transmission unit 201 includes a first clock signal transmission unit CK, a second clock signal transmission unit XCK, a first-level power supply signal transmission unit VGH, and a second-level power supply signal transmission unit VGL; the first clock signal transmission unit CK is electrically connected to the clock control transistor M1; the second clock signal transmission unit XCK is electrically connected to the inverting clock control transistor M2; the first-level power supply signal transmission unit VGH is electrically connected to the first-level power supply transistor M3; and the second-level power supply signal transmission unit VGL is electrically connected to the second-level power supply transistor M4. This facilitates the transmission of the electrical signals output by the driving structure to the pixel driving circuit 80, so that the pixel driving circuit 80 drives the pixel circuit 300 to provide display signals to the light-emitting element 200, thereby realizing the display panel function.

[0066] Optional, continue to refer to Figure 2 The display panel 100 also includes a driving structure 70; along the first direction Z, a first opening 101 penetrates the first substrate 10, and the driving structure 70 and the first signal transmission layer 20 both overlap with the first opening 101; the display panel also includes a conductive structure 90 located in the first opening 101, the conductive structure 90 connecting the driving structure 70 and the first signal transmission layer 20.

[0067] Specifically, a first opening 101 is formed in the first substrate 10, extending through the first substrate 10 along the first direction Z. Both the driving structure 70 and the first signal transmission layer 20 overlap with the first opening 101. Thus, within the first opening 101, the driving structure 70 and the first signal transmission layer 20 can be electrically connected through a conductive structure 110. The signal output by the driving structure 70 is then transmitted to the pixel driving circuit 80 and the pixel circuit 300 through the conductive structure 90. Furthermore, during the fabrication of the first opening 101, a portion of the first signal transmission layer 20 can be exposed, which facilitates the electrical connection between the driving structure 70 and the first signal transmission layer 20 at the overlapping position with the first opening 101, ensuring a simple connection method between the driving structure 70 and the first signal transmission layer 20.

[0068] Specifically, the display panel 100 also includes a conductive structure 90 located in the first opening 101. The conductive structure 90 can be correspondingly configured with the pad pins in the driving structure 70 and the first signal transmission section 201 in the first signal transmission layer 20, so that the electrical connection between the driving structure 70 and the first signal transmission layer 20 can be realized through the conductive structure 90, so that the electrical signal output by the driving structure 80 can be transmitted to the first signal transmission layer 20, ensuring that the electrical signal is subsequently transmitted to the pixel driving circuit 80 and / or the pixel circuit 300 through the first signal transmission layer 20, thereby ensuring the display function of the display panel.

[0069] For example, the material of the conductive structure 90 can be conductive ink, so the conductive structure 90 is low in cost and simple to manufacture.

[0070] Optional, continue to refer to Figure 2 The driving structure 70 includes a flip-chip thin film 701 and a driving chip 702; the driving chip 702 is bonded to the flip-chip thin film 701; and the conductive structure 90 connects the flip-chip thin film 701 and the first signal transmission layer 20.

[0071] Specifically, Chip On Flex (COF) technology is a technique that uses thermoforming to bond pads on the driver chip 702 to pins on a flexible circuit board. The COF film 701 includes multiple gold fingers, which are bonded to the pads on the driver chip 702, thus enabling signal transmission between the driver chip 702 and the COF film 701. Furthermore, the driving structure includes the COF film 701 and the driver chip 702. The COF film 701 serves as a connection structure between the driver chip 702 and the conductive structure 90, reducing the difficulty of connecting the driver chip 702 and the conductive structure 90 while ensuring the stability of the connection between them.

[0072] Specifically, the flip-chip thin film technology can be completed using a low-temperature process, which can reduce the impact of thermal stress on the performance of transistors in the pixel circuit and pixel driving circuit, thereby ensuring the stability and reliability of the display panel.

[0073] Optional, continue to refer to Figure 2 The display panel 100 includes a plurality of first signal transmission units 201, and the conductive structure 90 includes a plurality of conductive portions 901; the conductive portions are arranged correspondingly to the first signal transmission units 201.

[0074] As a feasible implementation, the number of conductive portions 901 and the number of first signal transmission portions 201 are the same, and they are arranged in a one-to-one correspondence. That is, each conductive portion 901 corresponds to one first signal transmission portion 201. In this way, the driving signal output by the driving structure 70 is transmitted to the corresponding first signal transmission portion 201 through the conductive portion 901.

[0075] As another feasible implementation, the number of conductive portions 901 can be greater than the number of first signal transmission portions 201. For example, the number of conductive portions 901 can be twice the number of first signal transmission portions 201, that is, every two first signal transmission portions 201 correspond to one first signal transmission portion 201, thereby ensuring the stability of electrical signal transmission between the driving structure 70 and the first signal transmission portions 201, which is beneficial to improving the stability and reliability of the display panel.

[0076] It should be noted that continued reference is necessary. Figure 2 By enclosing the exposed conductive portion 901 with sealant 110, the conductive portion 901 can be protected, preventing the conductive portion 901 from having its conductivity affected by contamination or damage.

[0077] It should also be noted that continued reference... Figure 2 The driving structure 70 and the first signal transmission layer 20 can be fixed by the adhesion structure 120, that is, the driving structure 70 and the first signal transmission layer 20 include the adhesion structure 120. For example, the adhesion structure 120 can be a pressure-sensitive adhesive. Since the adhesion between the driving structure 70 and the first signal transmission layer 20 is achieved by using pressure-sensitive adhesive, a high temperature is not required, thereby preventing the high temperature from affecting the performance of the first substrate, the transistors in the pixel circuit, and the transistors in the pixel driving circuit, thereby improving the performance of the display panel.

[0078] Optional, continue to refer to Figure 2 The display panel 100 also includes a virtual trace 130; the virtual trace 130 is set on the same layer as the first signal transmission layer 20.

[0079] Specifically, the virtual trace 130 is set on the same layer as the first signal transmission layer 20. By setting the virtual trace 130, it can achieve a planarization effect, which helps to ensure the stability of the film layer structure above the virtual trace 130 and the first signal transmission layer 20, preventing problems such as warping, and thus ensuring the stability and reliability of the display panel. On the other hand, by setting the virtual trace 130, the metal density at the edge of the display panel is adjusted, ensuring the consistency of the optical performance of the display panel and achieving uniformity of the display display.

[0080] Based on the same inventive concept, embodiments of the present invention also provide a method for manufacturing a display panel. Figure 10 This is a schematic flowchart of a method for manufacturing a display panel according to an embodiment of the present invention, as shown below. Figure 10 As shown, the method for manufacturing this display panel includes: S101, Provide a first substrate.

[0081] Specifically, a first substrate is provided. For example, the first substrate may be made of polyimide.

[0082] S102. A first signal transmission layer is prepared on one side of the first substrate; the first signal transmission layer includes a first signal transmission section.

[0083] For details, please refer to [link / reference]. Figures 1-3The first signal transmission layer 20 is located on the upper surface of the first substrate 10, and the first signal transmission layer 20 includes multiple independently arranged first signal transmission sections 201. For example, the first signal transmission section 201 may include a first clock signal transmission section CK for transmitting a clock signal ck, a second clock signal transmission section XCK for transmitting an inverted clock signal xck, a first level power signal transmission section VGH for transmitting a high-level signal vgh, a second level power signal transmission section VGL for transmitting a low-level signal vgl, and a data signal transmission section Vdata for transmitting a data signal data.

[0084] S103. A barrier layer is prepared on the side of the first signal transmission layer away from the first substrate.

[0085] For details, please refer to [link / reference]. Figure 2 The barrier layer 30 is located on the side of the first signal transmission layer 20 away from the first substrate 10. Thus, by setting the barrier layer 30, it can isolate the substrate surface defects on the one hand, and block impurities such as water and oxygen on the other hand.

[0086] S104. A second substrate is prepared on the side of the barrier layer away from the first substrate, and a third opening is prepared in the second substrate; the third opening includes a second side surface and a first bottom surface.

[0087] For details, please refer to [link / reference]. Figure 2 A second substrate 30 is prepared on the upper surface of the barrier layer 30, and a third opening 401 is prepared in the second substrate. The second side surface a2 is the sidewall of the third opening 401, and the first bottom surface b1 is the bottom surface of the third opening 401.

[0088] S105. An insulating layer is prepared on the side of the second substrate away from the first substrate, the insulating layer covering the second side surface and at least part of the first bottom surface.

[0089] For details, please refer to [link / reference]. Figure 2 The insulating layer 50 is located on the side of the second substrate 40 away from the first substrate 10, thus providing electrical isolation and preventing short circuits between different metal traces. The insulating layer 50 covers the second side a2 and at least part of the first bottom surface b1, meaning that the insulating layer 50 covers the sidewall and bottom surface of the third opening 401, but does not cover the second opening 301 within the barrier layer 30.

[0090] S106. A patterned insulating layer and a barrier layer are formed to form at least one insulating layer opening in the insulating layer and a second opening in the barrier layer; the insulating layer opening penetrates the insulating layer and communicates with the second opening; along a first direction, the second opening at least partially overlaps with the first signal transmission section; the second opening includes a first side surface; along the first direction, the orthographic projection of a third opening on the first substrate covers the orthographic projection of the second opening on the second substrate; the second side surface is not coplanar with the first side surface.

[0091] For details, please refer to [link / reference]. Figure 2 The insulating layer 50 and the barrier layer 30 are etched to form at least one insulating layer opening 501 in the insulating layer 50 and a second opening 301 in the barrier layer 30. The insulating layer opening 501 penetrates the insulating layer 50 and communicates with the second opening 301 so that the subsequent second metal transmission section 601 can be connected to the first metal transmission section 201 through the insulating layer opening 501 and the second opening 301. Along the first direction Z, the second opening 301 at least partially overlaps with the first signal transmission section 201 to ensure that the subsequent second signal transmission section 601 within the second opening 301 is electrically connected to the first signal transmission section 201.

[0092] For details, please refer to [link / reference]. Figure 2 The second side a2 of the third opening 401 is not coplanar with the first side a1 of the second opening 301. That is, the second side a2 and the first side a1 are not on the same plane, but are staggered. This can reduce the slope between the second side a2 and the first side a1, thereby preventing the second signal transmission unit 601 from breaking at the opening position due to the large slope between the second side a2 and the first side a1.

[0093] S107. Prepare a second signal transmission layer; the second signal transmission layer includes a second signal transmission section; the second signal transmission layer covers the sidewall of the opening of the insulating layer and the first side surface, and the second signal transmission section is electrically connected to the first signal transmission section.

[0094] For details, please refer to [link / reference]. Figure 2 The second signal transmission layer 60 includes a second signal transmission unit 601, which is used to write a driving current signal into the first electrode (such as the anode) of the light-emitting element 200, so as to realize the normal light emission or light emission of the light-emitting element 200 and realize the display function of the display panel. The second signal transmission unit 601 is electrically connected to the first signal transmission unit 201, so that the first signal transmission unit 201 can transmit the signal to the first electrode in the light-emitting element 200 to realize the normal light emission or light emission of the light-emitting element 200. In this way, the display panel can be displayed normally without bending the display panel, and the size of the small bezel of the display panel can be reduced. The size of the bottom bezel of the display panel in the prior art can be reduced from 0.8mm to less than 0.5mm, which is conducive to the miniaturization and integration of the display panel.

[0095] S108. Pattern the first substrate to form a first opening in the first substrate; the first signal transmission section overlaps at least partially with the first opening along a first direction; the first direction is the thickness direction of the display panel.

[0096] For details, please refer to [link / reference]. Figure 2The first substrate 10 is etched on the side of the first substrate 10 away from the first signal transmission layer 20 to form a first opening 101 in the first substrate 10. Along the first direction Z, the first signal transmission section 201 and the first opening 101 at least partially overlap, so that the display driving signal output by the driving structure 70 is transmitted to the pixel circuit 300 or the pixel driving circuit 80 through at least one first signal transmission section 201 to realize the display function of the display panel.

[0097] The method for manufacturing a display panel provided in this embodiment of the invention does not use a one-step etching process to prepare the third opening and the second opening, but prepares them separately. This can prevent side etching of the barrier layer, which is beneficial to ensuring the stability of the connection between the second metal transport part and the first metal transport part, and thus helps to ensure the stability and reliability of the display panel.

[0098] Optional, Figure 11 This is a schematic flowchart illustrating another method for manufacturing a display panel according to an embodiment of the present invention. Figure 11 Based on the above embodiments, the operation of the patterned insulating layer and the barrier layer will be described in detail, such as... Figure 11 As shown, the fabrication of this display panel includes: S201, Provide a first substrate.

[0099] S202, A first signal transmission layer is prepared on one side of the first substrate; the first signal transmission layer includes a first signal transmission section.

[0100] S203. A barrier layer is prepared on the side of the first signal transmission layer away from the first substrate.

[0101] S204. A second substrate is prepared on the side of the barrier layer away from the first substrate, and a third opening is prepared in the second substrate; the third opening includes a second side surface and a first bottom surface.

[0102] S205. An insulating layer is prepared on the side of the second substrate away from the first substrate, the insulating layer covering the second side surface and at least part of the first bottom surface.

[0103] S206. Pattern a portion of the insulating layer to form a first insulating layer opening in the insulating layer.

[0104] For details, please refer to [link / reference]. Figure 2 A portion of the insulating layer 50 is patterned to form a first insulating layer opening 5011 in the insulating layer. For example, the first insulating layer opening 5011 can be formed by patterning a portion of the insulating layer 50 using a silicon nitride contact hole etching (SCNT) process.

[0105] S207. Patterning is performed on the remaining insulating layer and the barrier layer through the first insulating layer opening to form a second insulating layer opening in the insulating layer and a second opening in the barrier layer; the second insulating layer opening communicates with the second opening; along the first direction, the second opening at least partially overlaps with the first signal transmission section; the second opening includes a first side surface; along the first direction, the orthographic projection of the third opening on the first substrate covers the orthographic projection of the second opening on the second substrate; the second side surface is not coplanar with the first side surface.

[0106] For details, please refer to [link / reference]. Figure 2 The remaining insulating layer 50 and barrier layer 30 are patterned through the first insulating layer opening 5011 to form a second insulating layer opening 5013 in the insulating layer 50. The second insulating layer opening 5012 and the second opening 301 can be etched using the same fabrication process, thus simplifying the fabrication process of the display panel. For example, the second insulating layer opening 5012 and the second opening 301 can be etched using an array pad break (APB) etching process.

[0107] S208. Prepare a second signal transmission layer; the second signal transmission layer includes a second signal transmission section; the second signal transmission layer covers the sidewall of the opening of the insulating layer and the first side surface, and the second signal transmission section is electrically connected to the first signal transmission section.

[0108] S209. Pattern the first substrate to form a first opening in the first substrate; the first signal transmission section at least partially overlaps with the first opening along a first direction; the first direction is the thickness direction of the display panel.

[0109] The method for fabricating a display panel provided in this invention first patterns a portion of the insulating layer to form a first insulating layer opening. Then, the remaining insulating layer and barrier layer are patterned through the first insulating layer opening to form a second insulating layer opening in the insulating layer and a second opening in the barrier layer. This two-step etching process etches the insulating layer and barrier layer, which on the one hand forms a step at the position of the third opening and the second opening, thereby helping to ensure the fabrication effect of the subsequent second signal transmission layer. On the other hand, the second insulating layer opening and the second opening are formed by a one-step etching process, thus simplifying the fabrication process of the display panel.

[0110] Optional, Figure 12 This is a schematic flowchart illustrating another method for manufacturing a display panel according to an embodiment of the present invention. Figure 12 Based on the above embodiments, the operation of preparing an insulating layer on the side of the second substrate away from the first substrate is described in detail, such as... Figure 12 As shown, the fabrication of this display panel includes: S301, Provide a first substrate.

[0111] S302. A first signal transmission layer is prepared on one side of the first substrate; the first signal transmission layer includes a first signal transmission section.

[0112] S303. A barrier layer is prepared on the side of the first signal transmission layer away from the first substrate.

[0113] S304. A second substrate is prepared on the side of the barrier layer away from the first substrate, and a third opening is prepared in the second substrate; the third opening includes a second side surface and a first bottom surface.

[0114] S305. Prepare a fourth insulator layer on the side of the second substrate away from the first substrate.

[0115] For details, please refer to [link / reference]. Figure 2 A fourth insulator layer 514 is prepared on the upper surface of the second substrate 40.

[0116] S306. Prepare a second insulator layer on the side of the fourth insulating layer away from the first substrate.

[0117] For details, please refer to [link / reference]. Figure 2 A second insulator layer 512 is prepared on the upper surface of the fourth insulator layer 514.

[0118] S307. Prepare a third insulator layer on the side of the second insulating layer away from the first substrate.

[0119] For details, please refer to [link / reference]. Figure 2 A third insulator layer 513 is prepared on the upper surface of the second insulator layer 512.

[0120] S308. Prepare a first insulator layer on the side of the third insulating layer away from the first substrate.

[0121] For details, please refer to [link / reference]. Figure 2 A first insulator layer 511 is prepared on the upper surface of the third insulator layer 513.

[0122] S309. Fabricate a pixel circuit, the pixel circuit including a first transistor and a fourth transistor. The first transistor includes a first input electrode, a first output electrode, a first gate, and a first active layer. The first input electrode is located on the side of the first insulator layer away from the first substrate and is in contact with the first insulator layer. The first active layer is located on the side of the second insulator layer away from the first substrate and is in contact with the second insulator layer. The fourth transistor includes a fourth input electrode, a fourth output electrode, a fourth gate, and a second active layer. The fourth input electrode is located on the side of the first insulator layer away from the first substrate and is in contact with the first insulator layer. The second active layer is located in the third insulator layer.

[0123] For details, please refer to [link / reference]. Figure 2The pixel circuit 300 includes a first transistor 31. Exemplarily, the first input electrode 311 may be a source, and the first output electrode 312 may be a drain. The first input electrode 311 is located on the upper surface of the first insulator layer 511 and is in contact with it. The first active layer 314 is located on the upper surface of the second insulator layer 512 and is in contact with it. The pixel circuit 300 also includes a fourth transistor 32, which includes a fourth input electrode 321, a fourth output electrode 322, a fourth gate 323, and a second active layer 324. The fourth input electrode 321 is located on the side of the first insulator layer 511 away from the first substrate 10 and is in contact with it. The second active layer 324 is located within the third insulator layer 513.

[0124] S310, patterning the first insulator layer and the multilayer third insulator layer to form a first insulating layer opening and a first connection via in the insulating layer; the first input electrode and the first output electrode are both connected to the first active layer through the first connection via.

[0125] For details, please refer to [link / reference]. Figure 2 The first insulating layer 511 and the multilayer third insulating layer 513 are patterned to form a first insulating layer opening 5011 and a first connecting via 500 in the insulating layer 50. That is, the first insulating layer opening 5011 and the first connecting via 500 can be prepared by the same etching process, thus simplifying the manufacturing process of the display panel and eliminating the need for additional photomasks, thereby saving costs.

[0126] S311. Through the opening in the first insulating layer, a second insulator layer, multiple layers of the fourth insulator layer, and a barrier layer are patterned to form a second insulator layer opening and a second connection via in the insulating layer, and a second opening in the barrier layer; the fourth input electrode and the fourth output electrode are both connected to the second active layer through the second connection via; the second insulating layer opening communicates with the second opening; along the first direction, the second opening at least partially overlaps with the first signal transmission section; the second opening includes a first side surface; along the first direction, the orthographic projection of the third opening on the first substrate covers the orthographic projection of the second opening on the second substrate; the second side surface and the first side surface are not coplanar.

[0127] For details, please refer to [link / reference]. Figure 2 The second insulator layer 512, the multilayer fourth insulator layer 514, and the barrier layer 30 are patterned to form a second insulator layer opening 5012 and a second connection via 600 in the insulator layer 50, and a second opening 301 in the barrier layer 30. In other words, the second insulator layer opening 5012 and the second connection via 600 can be fabricated using the same etching process, thus simplifying the display panel fabrication process and eliminating the need for additional photomasks, thereby saving costs.

[0128] S312. Prepare a second signal transmission layer; the second signal transmission layer includes a second signal transmission section; the second signal transmission layer covers the sidewall of the opening of the insulating layer and the first side surface, and the second signal transmission section is electrically connected to the first signal transmission section.

[0129] S313. Pattern the first substrate to form a first opening in the first substrate; the first signal transmission section overlaps at least partially with the first opening along a first direction; the first direction is the thickness direction of the display panel.

[0130] The display panel manufacturing method provided in this embodiment of the invention involves simultaneously manufacturing the first insulating layer opening and the first connecting via, as well as simultaneously manufacturing the second insulating layer opening and the second connecting via. This simplifies the manufacturing process of the display panel and eliminates the need for additional photomasks, thereby saving costs.

[0131] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 13 As shown, the display device 1000 includes the display panel 100 described in any of the above embodiments. Therefore, the display device 1000 provided in this embodiment of the invention has the corresponding beneficial effects of the above embodiments, which will not be repeated here. For example, the display device 1000 can be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device.

[0132] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art will be able to make various obvious changes, readjustments, and substitutions without departing from the scope of protection of the present invention. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A display panel, characterized in that, include: A first substrate, wherein a first opening is provided in the first substrate; A first signal transmission layer is located on one side of the first substrate and includes a first signal transmission section; Along a first direction, the first signal transmission section at least partially overlaps with the first opening; the first direction is the thickness direction of the display panel. A barrier layer is located on the side of the first signal transmission layer away from the first substrate; a second opening is provided in the barrier layer; along the first direction, the second opening at least partially overlaps with the first signal transmission portion; the second opening includes a first side surface; The second substrate is located on the side of the barrier layer away from the first substrate, and a third opening is provided in the second substrate; Along the first direction, the orthographic projection of the third opening on the first substrate overlaps the orthographic projection of the second opening on the second substrate; the third opening includes a second side surface and a first bottom surface; the second side surface and the first side surface are not coplanar; An insulating layer is located on the side of the second substrate away from the first substrate, the insulating layer covering the second side surface and at least a portion of the first bottom surface; the insulating layer has at least one insulating layer opening, the insulating layer opening penetrating the insulating layer and communicating with the second opening; The second signal transmission layer covers the sidewall of the opening in the insulating layer and the first sidewall and includes a second signal transmission section; and the second signal transmission section is electrically connected to the first signal transmission section.

2. The display panel according to claim 1, characterized in that, At least one of the insulating layer openings includes a first insulating layer opening and a second insulating layer opening, wherein the first insulating layer opening and the second insulating layer opening are in communication; The insulating layer comprises multiple insulator layers; The first insulating layer opening penetrates at least one layer of the insulator layer, and the second insulating layer opening penetrates at least one layer of the insulator layer and is in communication with the second opening.

3. The display panel according to claim 2, characterized in that, The second insulating layer opening includes the side of the first insulating layer; The angle between the side surface of the first insulating layer and the first direction is θ1, and the angle between the side surface of the first insulating layer and the first direction is θ2. Where |θ1-θ2|≤5°.

4. The display panel according to claim 2, characterized in that, The display panel also includes a display area and pixel circuits located in the display area; The pixel circuit includes a first transistor, which includes a first input electrode, a first output electrode, a first gate, and a first active layer; both the first input electrode and the first output electrode are connected to the first active layer. The multilayer insulator includes a first insulator and a second insulator. The first input electrode is located on the side of the first insulator away from the first substrate and is in contact with the first insulator. The first active layer is located on the side of the second insulator away from the first substrate and is in contact with the second insulator. The multilayer insulator further includes at least one third insulator layer and at least one fourth insulator layer. Along the first direction, the third insulator layer is located between the first insulator layer and the second insulator layer, and the fourth insulator layer is located between the second insulator layer and the barrier layer. The opening in the first insulating layer penetrates the first insulator layer and multiple layers of the third insulator layer, and the opening in the second insulating layer penetrates the second insulator layer and multiple layers of the fourth insulator layer.

5. The display panel according to claim 1, characterized in that, Along the second direction, the minimum distance between the first side and the second side is D; the second direction is parallel to the plane where the first substrate is located and intersects the thickness direction of the display panel; Where D > 2μm.

6. The display panel according to claim 1, characterized in that, The angle between the first side and the second direction is θ3, and the angle between the second side and the second direction is θ4; the second direction is parallel to the plane where the first substrate is located and intersects the thickness direction of the display panel; Where θ3 > θ4.

7. The display panel according to claim 6, characterized in that, 70°≤θ4≤80°.

8. The display panel according to claim 2, characterized in that, The orthographic projection of the opening of the first insulating layer on the first substrate covers the orthographic projection of the opening of the second insulating layer on the first substrate.

9. The display panel according to claim 1, characterized in that, The display panel also includes a display area and pixel circuits located in the display area; The pixel circuit includes a first transistor, which includes a first input electrode, a first output electrode, and a first gate. The first input electrode is electrically connected to the second signal transmission unit.

10. The display panel according to claim 9, characterized in that, The first signal transmission unit includes a first data signal transmission unit, and the second signal transmission unit includes a second data signal transmission unit; The first data signal transmission unit and the data signal transmission unit are electrically connected.

11. The display panel according to claim 1, characterized in that, The display panel also includes a display area and a pixel driving circuit located in the display area; The pixel driving circuit includes a second transistor, which includes a second input electrode, a second output electrode, and a second gate. The second input electrode is electrically connected to the second signal transmission unit.

12. The display panel according to claim 1, characterized in that, The display panel further includes a display area and a non-display area; the non-display area surrounds at least a portion of the display area. The display panel further includes a pixel driving circuit; the pixel driving circuit is located in the non-display area; the pixel driving circuit includes a third transistor; the third transistor includes a third input electrode, a third output electrode, and a third gate; The second signal transmission unit includes a first signal transmission unit located in the non-display area and a second signal transmission unit located in the display area; the first signal transmission unit is electrically connected to the third input electrode and the second signal transmission unit, respectively.

13. The display panel according to claim 11 or 12, characterized in that, The plurality of the first signal transmission units include a first clock signal transmission unit, a second clock signal transmission unit, a first level power supply signal transmission unit, and a second level power supply signal transmission unit.

14. The display panel according to claim 1, characterized in that, The display panel also includes a driving structure; Along the first direction, the first opening penetrates the first substrate, and both the driving structure and the first signal transmission layer overlap with the first opening; The display panel further includes a conductive structure located in the first opening, the conductive structure connecting the driving structure and the first signal transmission layer.

15. The display panel according to claim 14, characterized in that, The driving structure includes a flip-chip film and a driving chip; The driver chip is bonded to the flip-chip film; the conductive structure connects the flip-chip film and the first signal transmission layer.

16. The display panel according to claim 15, characterized in that, The display panel includes a plurality of first signal transmission sections, and the conductive structure includes a plurality of conductive portions; The conductive portion is provided corresponding to the first signal transmission portion.

17. The display panel according to claim 1, characterized in that, The display panel also includes virtual wiring; The virtual trace is set on the same layer as the first signal transmission layer.

18. A method for manufacturing a display panel, characterized in that, include: Provide a first substrate; A first signal transmission layer is formed on one side of the first substrate; the first signal transmission layer includes a first signal transmission portion; A barrier layer is prepared on the side of the first signal transmission layer away from the first substrate; A second substrate is prepared on the side of the barrier layer away from the first substrate, and a third opening is prepared in the second substrate; the third opening includes a second side surface and a first bottom surface; An insulating layer is formed on the side of the second substrate away from the first substrate, the insulating layer covering the second side surface and at least a portion of the first bottom surface; The insulating layer and the barrier layer are patterned to form at least one opening in the insulating layer and a second opening in the barrier layer; The opening in the insulating layer penetrates the insulating layer and communicates with the second opening; Along the first direction, the second opening at least partially overlaps with the first signal transmission section; the second opening includes a first side surface; along the first direction, the orthographic projection of the third opening on the first substrate covers the orthographic projection of the second opening on the second substrate; the second side surface is not coplanar with the first side surface; A second signal transmission layer is prepared; the second signal transmission layer includes a second signal transmission section; the second signal transmission layer covers the sidewall of the opening of the insulating layer and the first side surface, and the second signal transmission section is electrically connected to the first signal transmission section; The first substrate is patterned to form a first opening in the first substrate; Along a first direction, the first signal transmission section at least partially overlaps with the first opening; the first direction is the thickness direction of the display panel.

19. The preparation method according to claim 18, characterized in that, Patterning the insulating layer and the barrier layer includes: The insulating layer is patterned to form a first insulating layer opening in the insulating layer; The remaining insulating layer and the barrier layer are patterned through the first insulating layer opening to form a second insulating layer opening in the insulating layer and a second opening in the barrier layer; the second insulating layer opening communicates with the second opening.

20. The preparation method according to claim 19, characterized in that, An insulating layer is prepared on the side of the second substrate away from the first substrate, comprising: A fourth insulator layer is prepared on the side of the second substrate away from the first substrate; A second insulator layer is prepared on the side of the fourth insulating layer away from the first substrate; A third insulator layer is prepared on the side of the second insulating layer away from the first substrate; A first insulator layer is prepared on the side of the third insulating layer away from the first substrate; The method for manufacturing the display panel further includes: A pixel circuit is fabricated, the pixel circuit including a first transistor and a fourth transistor. The first transistor includes a first input electrode, a first output electrode, a first gate, and a first active layer. The first input electrode is located on the side of the first insulator layer away from the first substrate and is in contact with the first insulator layer. The first active layer is located on the side of the second insulator layer away from the first substrate and is in contact with the second insulator layer. The fourth transistor includes a fourth input electrode, a fourth output electrode, a fourth gate, and a second active layer. The fourth input electrode is located on the side of the first insulator layer away from the first substrate and is in contact with the first insulator layer. The second active layer is located within the third insulator layer. Patterning a portion of the insulating layer to form a first insulating layer opening in the insulating layer includes: The first insulator layer and multiple layers of the third insulator layer are patterned to form a first insulator layer opening and a first connection via in the insulator layer; the first input electrode and the first output electrode are both connected to the first active layer through the first connection via; Patterning the remaining insulating layer and the barrier layer through the first insulating layer opening to form a second insulating layer opening in the insulating layer and a second opening in the barrier layer; including: The second insulator layer and multiple layers of the fourth insulator layer and the barrier layer are patterned through the opening in the first insulating layer to form the second insulator layer opening and the second connection via in the insulating layer, and to form the second opening in the barrier layer; the fourth input electrode and the fourth output electrode are both connected to the second active layer through the second connection via.

21. A display device, characterized in that, Includes the display panel as described in any one of claims 1-17.

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