A low-defect chip scribe method suitable for D2W hybrid bonding

Abstract

The application relates to a low-defect chip scribing method suitable for D2W hybrid bonding, and belongs to the field of semiconductor packaging, which solves at least one of the problems of poor chip quality, insufficient cleanliness, low process efficiency, unstable cutting quality and the like in chip cutting in the D2W hybrid bonding process. The low-defect chip scribing method suitable for the D2W hybrid bonding comprises the following steps: providing a wafer, wherein the wafer comprises a substrate and a medium layer on the surface of the substrate, and the medium layer constitutes a medium layer on the surface of the wafer; first performing medium layer cutting and then performing substrate cutting; wherein the medium layer cutting is completed by adopting a twice laser slotting mode. The application realizes low-defect and high-quality cutting of the chip, improves the overall process efficiency, and improves the quality stability of the chips obtained by cutting of different batches.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a low-defect chip dicing method suitable for D2W hybrid bonding. Background Technology

[0002] Hybrid bonding eliminates traditional metal solder joints, overcoming bandwidth interconnection limits and serving as a crucial method for achieving 3D integrated chip packaging. Hybrid bonding can be divided into wafer-to-wafer (W2W) and die-to-wafer (D2W) methods. D2W hybrid bonding involves mounting diced chips onto a substrate wafer. D2W hybrid bonding demands extremely high cleanliness of the chip surface; traditional blade dicing processes generate significant particulate contamination (see...). Figure 1 This severely contaminates the chip surface; furthermore, because the materials of the chip surface and the substrate may differ, the chip cutting method and process may introduce problems such as edge breakage, dielectric layer peeling, and particle accumulation, leading to delamination between the dielectric layer and the substrate (see...). Figure 1 This reduces chip strength and stability, further affecting subsequent chip cleaning, pick-up, flipping and mounting processes, and reducing or destroying the chip-to-wafer bonding process.

[0003] Compared to blade cutting, advanced cutting methods developed in recent years, such as laser stealth dicing and plasma scribing, have improved cutting quality to some extent. However, when dealing with wafers containing dense dielectric layers, these advanced cutting methods also reveal significant disadvantages, such as low cutting efficiency and the tendency for the dielectric layer and substrate to delaminate during the cutting process. These problems also seriously affect the quality of subsequent D2W bonding and the overall process efficiency. Summary of the Invention

[0004] Based on the above analysis, the present invention aims to provide a low-defect chip dicing method suitable for D2W hybrid bonding, in order to solve at least one of the following problems in chip dicing in D2W hybrid bonding process: poor chip quality, insufficient cleanliness, low process efficiency, and unstable dicing quality.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] This invention provides a low-defect chip dicing method suitable for D2W hybrid bonding, comprising:

[0007] A wafer is provided, the wafer including a substrate and a dielectric layer located on the surface of the substrate, the dielectric layer constituting a dielectric layer on the surface of the wafer;

[0008] First, cut the dielectric layer, then cut the substrate;

[0009] The dielectric layer is cut using a two-stage laser grooving method, which includes the following steps:

[0010] (a) Apply a protective liquid to the surface of the dielectric layer on the wafer surface for the first time;

[0011] (b) First laser grooving: Using a first laser, the dielectric layer on the wafer surface is laser-grooved along the wafer dicing path until the dicing path groove etched by the first laser penetrates the dielectric layer on the wafer surface.

[0012] (c) Clean the first coating of protective liquid to expose the surface of the dielectric layer and the etched cutting grooves;

[0013] (d) A protective liquid is applied a second time to the dielectric layer surface on the wafer surface, so that the protective liquid covers the dielectric layer surface and the inner wall of the etched dicing trench, and accumulates in the dicing trench.

[0014] (e) Second laser grooving: Using a second laser, the protective liquid accumulated in the groove of the cutting track is removed, while the surface of the medium layer and the edge of the cutting track are covered with protective liquid.

[0015] The depth of the second laser grooving is less than or equal to the depth of the first laser grooving, and the width of the second laser grooving is less than or equal to the width of the first laser grooving.

[0016] Furthermore, the thickness of the first protective coating is t1, and the thickness of the second protective coating is t2, satisfying: t2 = (50% - 100%) × t1.

[0017] Furthermore, the depth of the second laser grooving is d2, which satisfies: d2 = (100-110%) × t2; t2 is the thickness of the second protective coating.

[0018] Furthermore, the width of the first laser grooving is w1, and the width of the second laser grooving is w2, satisfying w2 = (85% - 99%) × w1.

[0019] Furthermore, the laser power of the second laser grooving is less than the laser power of the first laser grooving.

[0020] Furthermore, the laser power for the first laser grooving is P1, and the laser power for the second laser grooving is P2, satisfying P2 = (20% - 50%) × P1.

[0021] Furthermore, the projected area of ​​the first laser grooving is S1, and the projected area of ​​the second laser grooving is S2, satisfying S2 = (95% - 99%) × S1, and the overlap of the projected areas of the first laser grooving and the second laser grooving is above 95-99%.

[0022] Furthermore, the second laser has a wavelength of 300-600 nm, a pulse frequency of 10 Hz-500 kHz, and a pulse width of 1-500 ns; and / or,

[0023] The laser used for the second laser grooving is a green nanosecond or ultraviolet nanosecond laser.

[0024] Furthermore, the substrate cutting includes: using plasma to create a groove downwards along the bottom of the etched cutting channel to complete the cutting of the substrate; in plasma cutting, the surface of the dielectric layer and the edge of the cutting channel are covered by a protective liquid.

[0025] Furthermore, after the dielectric layer and substrate are cut, before cleaning with the protective liquid, the height of slag or accumulation at the edge of the dicing channel and the edge of the chip is ≤0.5μm; after cleaning with the protective liquid, the height of slag or accumulation at the edge of the dicing channel and the edge of the chip is ≤0.5μm, and the number of particles on the chip surface is ≤100 particles @90nm.

[0026] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0027] The core idea of ​​this invention lies in employing a two-stage laser grooving process for dielectric layers, which are notoriously difficult to cut. This significantly reduces chip defects and improves the quality and reliability of wafer dicing. Specifically, after the first application of a protective coating, a first laser grooving is performed. Its primary purpose is to remove the dielectric layer (and in some cases, the metal structure within the dielectric layer) from the wafer surface. After this initial operation, a second protective coating is applied to re-cover and protect areas around the dicing track that may have been affected during the first laser grooving, such as the dicing track edges and exposed areas on the dielectric layer surface. Subsequently, the second laser grooving removes any excess protective coating that accumulated in the dicing track grooves during the second coating process.

[0028] (1) For dielectric layers in wafers that are difficult to cut, this invention avoids the chip edge exposure and a series of problems common in one-step laser grooving by using two laser grooving processes. The "one-step laser grooving process" here refers to cutting the dielectric layer by one-step or multi-step laser grooving after applying a protective liquid. However, during the entire grooving process, there is a lack of secondary protection for the cutting path and its surrounding area (re-applying the protective liquid and removing excess protective liquid), which often leads to exposure of the cutting path edge, and thus causes a series of problems, such as a lot of slag and residue accumulation on the chip surface, especially at the chip edge, and chip edge ablation, which seriously affects the quality of subsequent D2W bonding.

[0029] This invention proposes an innovative two-step laser grooving process to address the challenges of cutting dielectric layers in wafers. This process fully leverages the high speed of laser cutting while significantly improving the overall quality of the resulting chip through two precise laser grooving operations. Specifically, after the first laser grooving, this invention adds secondary protection measures to the area surrounding the grooving channel, including recoating with a protective solution and removing excess protective solution from the trench. These measures effectively prevent the high energy of the subsequent substrate cutting from directly impacting the exposed areas at the grooving channel edges, thereby reducing chip defects such as slag and residue accumulation, and edge ablation, especially at the chip edges. Compared to existing methods, this invention significantly improves the overall quality of the chip. In the embodiments of this invention, after the dielectric layer and substrate are cut, there are no obvious ablation marks at the grooving channel edges and chip edges, and the height of slag or accumulation at the grooving channel edges and chip edges is ≤0.5μm.

[0030] (2) For the dielectric layer in wafers that is difficult to cut, the present invention adopts a two-step laser grooving process. After the first laser grooving completes the cutting of the dielectric layer, a second protection is added to the area around the grooving. That is, a second coating of protective liquid and a second laser grooving are introduced to remove excess protective liquid in the grooving groove. This ensures that the surface of the dielectric layer and the edge of the grooving are always under the effective coverage of the protective liquid during the subsequent substrate cutting process. This avoids the problem of a large amount of slag and residual particles accumulating in the exposed area of ​​the grooving edge. In addition, since the edge of the grooving is effectively protected, the honeycomb-like ablation marks caused by edge exposure are significantly reduced. The edge of the grooving and the chip edge formed after cutting are flat. In the protective liquid cleaning stage after cutting, since the chip edge is flat after cutting, the cleaning residue is not easy to accumulate in the recessed structure, thereby reducing residual adhesive and improving the cleanliness of the chip surface.

[0031] (3) For dielectric layers in wafers that are difficult to cut, this invention reduces the exposed area at the edge of the dicing track through a fine operation of two laser grooving steps, thereby improving the overall process efficiency. In subsequent processes, exposed areas at the edge of the dicing track often cause numerous problems, such as expansion of the heat-affected zone, accumulation of slag and residual particles, reduced cutting accuracy, increased wear on cutting tools, decreased energy utilization efficiency, and obstruction of subsequent processes during substrate cutting. These problems not only reduce chip quality but also significantly slow down the overall process efficiency. This invention optimizes the process, such as by using two laser grooving steps and secondary protection with a protective liquid. After two laser grooving steps, the edge of the dicing track is neat, and both the surface of the dielectric layer and the edge of the dicing track are below the protective liquid, ensuring that there are no exposed areas on the surface of the dielectric layer and the edge of the dicing track. This effectively reduces the occurrence of the above-mentioned problems in subsequent substrate cutting, thereby improving the overall process efficiency.

[0032] (4) For the dielectric layer in the wafer that is difficult to cut, the present invention reduces the quality fluctuation caused by the difference in the exposure of the cutting edge during the cutting of each batch by performing two laser grooving operations, and significantly improves the quality stability of the chips obtained from different batches.

[0033] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0034] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0035] Figure 1 This is a schematic diagram of chip defects obtained by the cutting method in the prior art. (a) is before cutting, and (b) is after cutting.

[0036] Figure 2 This is a flowchart illustrating the low-defect chip dicing method provided in Embodiments 1-9 of the present invention;

[0037] Figure 3 This is a flowchart illustrating the low-defect chip dicing method provided in Embodiment 10 of the present invention;

[0038] Figure 4 This is a chip surface topography image obtained by the low-defect chip dicing method described in this embodiment of the invention;

[0039] Figure 5This is a flowchart illustrating the chip dicing method in Comparative Example 1.

[0040] Figure 6 This is a chip surface topography image obtained by the chip dicing method described in Comparative Example 1;

[0041] Figure label:

[0042] 100 - Wafer; 10a - Single chip after dicing; 11 - Dielectric layer; 11a - Dielectric layer on the front side; 11b - Dielectric layer on the back side; 12 - Substrate; 13 - Drill track; 200 - Carrier; 20a - First carrier; 20b - Second carrier; 300 - Laser protective fluid; 31 - Protective fluid on the surface of the dielectric layer and the edge of the dicing track; 32 - Protective fluid accumulated in the dicing track groove; 4 - Laser; 5 - Plasma; 6 - Particle contamination; 7 - Delamination of the dielectric layer and the substrate. Detailed Implementation

[0043] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0044] In D2W hybrid bonding technology, the chip to be bonded consists of a dielectric layer and a substrate layer. The dielectric layer is either the upper layer or both layers above and below the chip, while the substrate layer is located below the chip or sandwiched between the upper and lower dielectric layers. The dielectric layer is typically made of dense materials such as silicon oxide and may contain metal structures. The substrate layer is usually made of silicon. Common low-defect chip dicing methods include laser stealth dicing and plasma dicing. However, due to the differences in structure and materials between the dielectric layer and the substrate layer, the effects of lasers or plasmas on the dielectric layer, its internal metal structures, and the substrate vary significantly. This can easily lead to defects such as delamination and cracks in the dielectric layer and substrate, while also resulting in low dicing efficiency, especially when the dielectric layer contains metal structures.

[0045] To improve cutting efficiency and reduce defects such as delamination and cracks, the inventors attempted to pre-treat the dielectric layer or the dielectric layer containing a metal structure with laser grooving before cutting the substrate. The main process flow is: applying laser protective liquid - laser grooving - plasma scribing - cleaning the protective liquid. However, the inventors found that this solution still has the following drawbacks:

[0046] (1) Due to the high energy of the laser, the laser grooving will not only act on the cutting path, but also damage the laser protective liquid around the cutting path, resulting in the exposure of some dielectric layers and loss of protection. (2) The exposed area is damaged in the plasma etching stage, which damages the bonding dielectric layer material on the surface and affects the subsequent chip edge bonding quality. (3) Excessive laser grooving will cause a large amount of slag and residual particles in the exposed area. The height of these uneven defects can reach micrometers to tens of micrometers, making it difficult for the chip to be pre-bonded with the wafer. (4) The chip cutting path edge of this scheme shows honeycomb-shaped ablation marks. During the laser protection cleaning stage, the cleaning residue can easily accumulate in the recessed structure, forming residual glue, which damages the surface cleaning effect and affects the cleanliness of the chip.

[0047] Based on this, the present invention provides a low-defect chip dicing method suitable for D2W hybrid bonding, comprising:

[0048] A wafer is provided, the wafer including a substrate and a dielectric layer located on the surface of the substrate, the dielectric layer constituting a dielectric layer on the surface of the wafer;

[0049] First, cut the dielectric layer, then cut the substrate;

[0050] The dielectric layer is cut using a two-stage laser grooving method, which includes the following steps:

[0051] (a) Apply a protective liquid to the dielectric layer surface on the wafer surface for the first time;

[0052] (b) First laser grooving: Using a first laser, the dielectric layer on the wafer surface is laser-grooved along the wafer dicing path until the dicing path groove etched by the first laser penetrates the dielectric layer on the wafer surface.

[0053] (c) Clean the first coating of protective liquid to expose the surface of the dielectric layer and the etched cutting grooves;

[0054] (d) A protective liquid is applied a second time to the dielectric layer surface on the wafer surface, so that the protective liquid covers the dielectric layer surface and the inner wall of the etched dicing trench, and accumulates in the dicing trench.

[0055] (e) Second laser grooving: Using a second laser, the protective liquid accumulated in the grooving groove is removed, while the surface of the dielectric layer and the edge of the wafer grooving are covered by the protective liquid.

[0056] The depth of the second laser grooving is less than or equal to the depth of the first laser grooving, and the width of the second laser grooving is less than or equal to the width of the first laser grooving.

[0057] It can be understood that in step (a), the wafer surface refers to the wafer surface on the side where the dielectric layer to be cut is located.

[0058] Specifically, step (a) includes: before the first application of the protective solution, combining the wafer with a carrier for supporting the wafer, with the dielectric layer on the wafer surface facing upwards. For example, the carrier is a UV blue film, which is supported by a stainless steel metal frame. For example, the carrier is a silicon-based wafer carrier or a transparent glass carrier, and the wafer is combined with the silicon-based wafer carrier or transparent glass carrier by fusion bonding or temporary bonding.

[0059] Compared with existing technologies, this invention first cuts the dielectric layer and then cuts the substrate. The dielectric layer cutting uses a laser, which has higher cutting efficiency and quality than traditional blade cutting. Compared with current methods such as plasma cutting and laser stealth cutting, which cut from the wafer surface to the bottom, this invention effectively avoids problems such as delamination and peeling of the dielectric layer and substrate by cutting the dielectric layer and substrate in stages, and the cutting efficiency is higher. Based on this, the present invention addresses the problems of edge exposure during dielectric layer laser cutting, which can easily lead to edge ablation, large amounts of slag and residual particles in the exposed area during subsequent substrate cutting. It proposes an effective solution: a two-stage laser grooving process is used during dielectric layer laser cutting. Compared to a single-stage laser grooving, the present invention adds a second step of applying a protective liquid and a second laser grooving after the first laser grooving completes the grooving of the dielectric layer. This provides effective secondary protection for the exposed areas on the cutting edge and dielectric layer surface that may occur during the first laser grooving. This ensures that the high energy used for cutting the substrate does not affect areas outside the cutting path during subsequent substrate cutting, thus guaranteeing neat chip edges, reducing slag and residue accumulation at the chip edges, and minimizing particulate impurities on the chip surface. This achieves low-defect, high-quality chip cutting, providing a reliable guarantee for subsequent D2W bonding.

[0060] It should be noted that this invention employs two precise laser grooving operations. The first laser grooving removes the dielectric layer, etching out the cutting grooves. The second laser grooving removes the protective fluid within the cutting grooves. The depth and width of the second laser grooving are no greater than those of the first laser grooving to remove the protective fluid while avoiding damage to the protective layer surrounding the cutting path.

[0061] It can be understood that "around the dicing track" mainly includes the edge of the dicing track and the surface area of ​​the dielectric layer on both sides of the dicing track. The edge of the dicing track mainly refers to the boundary area on both sides of the dicing track (i.e., the boundary line between the dicing track and the chip area).

[0062] Specifically, the thickness of the second protective coating should be less than or equal to the thickness of the first protective coating.

[0063] In some embodiments, the thickness of the first protective coating is t1, and the thickness of the second protective coating is t2, satisfying: t2 = (50% - 100%) × t1. The thickness of the second protective coating is thinner than or equivalent to that of the first protective coating to reduce the heat-affected zone, ensuring that the second laser grooving can remove the protective coating accumulated in the groove, while avoiding exposure at the cutting edge. However, the thickness of the second protective coating cannot be too thin to ensure effective protection of the area around the cutting kerf, which helps reduce thermal damage and slag accumulation during subsequent substrate cutting, thereby improving cutting quality and stability.

[0064] For example, t2 = 55% × t1, t2 = 60% × t1, t2 = 65% × t1, t2 = 70% × t1, t2 = 75% × t1, t2 = 80% × t1, t2 = 85% × t1, t2 = 90% × t1, t2 = 95% × t1. Preferably, t2 = (70% - 90%) × t1, to balance protective effect and removal efficiency.

[0065] In some embodiments, the depth of the second laser grooving is d2, satisfying: d2 = (100-110%) × t2; t2 is the thickness of the second protective coating. By precisely controlling the depth of the second laser grooving, it is possible to better ensure the complete removal of the protective coating accumulated in the groove, while also taking into account process efficiency, reducing the heat-affected zone, and avoiding excessive laser input from affecting the protective layer around the cutting path.

[0066] In some embodiments, the width of the first laser grooving is w1, and the width of the second laser grooving is w2, satisfying w2 = (85% - 99%) × w1. By precisely controlling the width of the second laser grooving, it is better ensured that the protective fluid accumulated in the cutting groove can be completely removed, and damage to the protective layer around the cutting track is avoided. In addition, controlling the width of the second laser grooving is beneficial to coordinating with the energy parameters of the second laser grooving (such as power, pulse width, etc.), better ensuring that the second laser can accurately remove the protective fluid, while reducing the heat-affected zone, improving cutting quality and balancing efficiency.

[0067] For example, w2 = 87% × w1, w2 = 90% × w1, w2 = 92% × w1, w2 = 95% × w1, w2 = 97% × w1. Preferably, w2 = (90% - 95%) × w1, which better balances removal efficiency and protective effect.

[0068] Preferably, the laser power of the second laser grooving is less than that of the first laser grooving. The main purpose of the second laser grooving is to remove excess protective fluid accumulated in the cutting groove. Since the second grooving is less difficult than the first, a lower laser power can effectively remove the accumulated protective fluid in the groove, reduce damage to the protective layer around the cutting track, ensure the integrity and effectiveness of the protective layer, and reduce energy consumption.

[0069] In some embodiments, the laser power for the first laser grooving is P1, and the laser power for the second laser grooving is P2, satisfying P2 = (20% - 50%) × P1. By precisely controlling the power of the second laser grooving, it is better possible to remove the protective liquid in the groove while avoiding unnecessary damage to the protective layer around the dicing track, thereby reducing defects at the edge of the dicing track and the chip edge, and improving cutting quality and stability. If the power is too low (<20% P1), the laser energy may not be sufficient to completely remove the protective liquid in the dicing track groove, increasing the difficulty of subsequent cleaning and processing, affecting the cleanliness of the chip surface, and due to insufficient laser energy, it may take longer to remove the protective liquid, reducing process efficiency. If the power is too high (>50% P1), the heat-affected zone expands, which may cause partial damage to the protective layer around the dicing track.

[0070] For example, P2 = 25% × P1, P2 = 30% × P1, P2 = 35% × P1, P2 = 40% × P1, P2 = 45% × P1. Preferably, P2 = (30-40%) × P1, which better balances removal efficiency and protective effect.

[0071] In some embodiments, the projected area of ​​the first laser grooving is S1, and the projected area of ​​the second laser grooving is S2, satisfying S2 = (90% - 99%) × S1. Further, S2 = (95% - 99%) × S1. Preferably, the overlap of the projected areas of the two laser grooving operations, i.e., the first and second laser grooving operations, is above 95%-99%. Here, an overlap of 95%-99% or higher means starting from 95% and continuing up to 99% and above. By controlling the ratio and overlap of the projected areas of the two laser grooving operations, it is better ensured that the energy of the second laser grooving is sufficient to remove the protective liquid in the dicing groove, while the second laser grooving does not damage the protective layer formed by the protective liquid at the edge of the dicing groove and the surface of the dielectric layer, thereby reducing defects at the edge of the dicing groove and the chip edge, and ensuring the dicing quality and stability of the chip.

[0072] It is understandable that the projected area of ​​laser grooving refers to the area of ​​the wafer surface actually irradiated by the laser beam.

[0073] In some embodiments, the second laser has a wavelength of 200-600nm, a power of 10-200W, a pulse frequency of 10Hz-100MHz, a pulse width of 10fs-500ns, and a laser spot diameter of 10-100μm.

[0074] Preferably, the second laser has a wavelength of 300-600nm, a pulse frequency of 10Hz-500kHz, a pulse width of 1ns-500ns, and a laser spot diameter of 20-50μm.

[0075] Preferably, the laser used for the second laser grooving is a green nanosecond or ultraviolet nanosecond laser.

[0076] By controlling the parameters of the second laser (such as wavelength, frequency, pulse width, etc.) and utilizing the synergistic effect between these parameters, combined with a suitable laser, the protective liquid accumulated in the cutting groove can be efficiently removed, and the influence of the heat-affected zone on the protective layer (formed by the protective liquid) around the cutting groove can be reduced. This better ensures that after the second laser grooving, the surface of the medium layer and the edge of the cutting groove are still covered by the protective liquid and are fully protected in the subsequent substrate cutting process.

[0077] For example, the laser wavelength of the second laser is 248nm, 257nm, 266nm, 308nm, 355nm, 365nm, 405nm, 436nm, 515nm, 520nm, 532nm, 543nm, 555nm, or 561nm. Preferably, the laser wavelength of the second laser is 500nm-600nm.

[0078] For example, the pulse frequency of the second laser is 20Hz, 50Hz, 100Hz, 250Hz, 500Hz, 800Hz, 1kHz, 2kHz, 5kHz, 10kHz, 20kHz, 50kHz, 80kHz, 100kHz, 120kHz, 150kHz, 170kHz, 200kHz, 300kHz, 400kHz, 500kHz, 1MHz, 2MHz, 5MHz, 10MHz, 50MHz, or 80MHz. Preferably, the pulse frequency of the second laser is 1kHz-200kHz.

[0079] For example, the pulse width of the second laser is 20fs, 50fs, 80fs, 100fs, 200fs, 300fs, 400fs, 500fs, 1ps, 5ps, 20ps, 50ps, 80ps, 100ps, 500ps, 2ns, 5ns, 10ns, 20ns, 50ns, 80ns, 100ns, 120ns, 150ns, 180ns, 200ns, 250ns, 300ns, 350ns, 400ns, or 450ns. Preferably, the pulse width of the second laser is 5ns-200ns.

[0080] For example, the spot diameter of the second laser is 25μm, 30μm, 35μm, 40μm, or 45μm.

[0081] Preferably, in the first laser grooving, the depth of the first laser grooving is equal to the thickness of the first protective coating plus 100%-120% of the thickness of the dielectric layer on the wafer surface. By precisely controlling the depth of the first laser grooving, it ensures that the dielectric layer is completely grooved while minimizing the heat-affected zone. This avoids an increase in the exposed area around the dicing track due to excessive laser grooving, effectively reducing problems such as chip edge slag and residual particles generated in the exposed area, thereby helping to ensure the quality and cleanliness of the chip.

[0082] For example, the protective liquid described in this invention is a laser protective liquid.

[0083] It is understandable that protective coating methods include spin coating, blade coating, and immersion coating. For example, the principle of spin coating is to place the wafer on a high-speed rotating platform, drop the protective coating onto the center of the wafer, and use centrifugal force to distribute the coating evenly. By controlling the rotation speed, rotation time, and drop volume, the thickness of the protective coating can be precisely controlled. The principle of blade coating is to use a blade to evenly coat the protective coating onto the wafer surface. By adjusting the height and pressure of the blade, the thickness of the protective coating can be controlled. The principle of immersion coating is to immerse the wafer in the protective coating. By controlling the immersion speed and time, as well as the pull-out speed and the temperature of the protective coating, the thickness of the protective coating can be precisely controlled. After coating, the thickness of the coated protective coating can be measured and determined using existing optical measurement methods (such as ellipsometers and optical interferometers).

[0084] Preferably, in the first laser grooving, the width of the cutting path is 10μm-400μm.

[0085] For example, the width of the cutting channel is 20μm, 50μm, 80μm, 100μm, 150μm, 200μm, 250μm, 300μm, or 350μm.

[0086] Preferably, in the first laser grooving, the width of the first laser grooving is (30%-80%) × the width of the cutting track. Further, the centerline of the first laser grooving and the centerline of the cutting track deviate by no more than 10 μm. By precisely controlling the grooving width and centerline position, both the depth and accuracy of the grooving can be guaranteed, while over-cutting can be avoided, reducing cutting deviations and improving the uniformity and consistency of cutting quality. Simultaneously, the heat-affected zone is minimized, avoiding an increase in the exposed area around the cutting track due to excessive laser grooving. This effectively reduces problems such as chip edge slag and residual particles generated in the exposed area, thereby helping to ensure the quality and cleanliness of the chip.

[0087] For example, for harder or more brittle materials, a narrower groove width is selected; preferably, when the dielectric layer is at least one of SiO2, SiNx, SiCN, and TEOS, the width of the first laser grooving is (30%-50%) × the width of the cutting path.

[0088] For example, a wider groove width is selected for softer or tougher materials; preferably, when the medium layer is a polymer material, such as polyimide or benzocyclobutene, the width of the first laser grooving is (50%-80%) × the width of the cutting path.

[0089] In some embodiments, the low-defect chip dicing method of the present invention is applicable to wafers with a size of 4-12 inches and a thickness of 5-800 μm.

[0090] Optionally, in the wafer to be cut, the substrate is made of at least one of silicon, glass, and diamond. The dielectric layer is made of at least one of silicon oxide, silicon nitride, silicon carbide, SiCO, SiCN, SiCON, lithium niobate, InP, AsGaIn, GaN, and alumina.

[0091] For example, in the wafer to be cut, the thickness of the dielectric layer is 10nm-20μm, and the thickness of the substrate is 10μm-780μm.

[0092] For example, the dielectric layer is made of at least one of SiO2, SiNx, SiCN, and TEOS.

[0093] In some embodiments, the wafer is a dielectric layer wafer with a metal structure. Specifically, the wafer includes a substrate and a dielectric layer located on the surface of the substrate, the dielectric layer constituting the dielectric layer on the wafer surface; the dielectric layer also includes a metal structure, such as metal pads or a metal wiring layer. The metal pads are located on the surface of the dielectric layer, and the metal wiring layer is located inside the dielectric layer. The dicing surface of the wafer does not include metal pads, but in some possible designs, the dicing includes a metal wiring layer.

[0094] For example, the area of ​​each metal pad is 0.03 μm. 2 -100μm 2 The pad pitch is 0.4μm-20μm, and the pad depth is 10nm-1000nm.

[0095] For example, the metal pads are made of copper or aluminum.

[0096] In some embodiments, during the first laser grooving, the laser wavelength of the first laser is 200-600nm, the power is 10-200W, the pulse frequency is 1kHz-100MHz, the pulse width is 10fs-100ns, and the laser spot diameter is 10-100μm.

[0097] In some embodiments, the laser used for the first laser grooving is an ultraviolet picosecond, ultraviolet femtosecond, ultraviolet nanosecond, green picosecond, green femtosecond, or green nanosecond laser.

[0098] Preferably, the laser used for the first laser grooving is a UV picosecond or UV femtosecond laser, which can reduce slag residue.

[0099] For example, the laser wavelength of the first laser is 248nm, 257nm, 266nm, 308nm, 355nm, 365nm, 405nm, 436nm, 515nm, 520nm, 532nm, 543nm, 555nm, or 561nm.

[0100] For example, the power of the first laser is 20W, 50W, 80W, 100W, 120W, 140W, 160W, or 180W.

[0101] For example, the pulse frequency of the first laser is 5kHz, 10kHz, 25kHz, 50kHz, 75Hz, 100kHz, 250kHz, 500kHz, 750kHz, 1MHz, 2MHz, 5MHz, 8MHz, 10MHz, 50MHz, or 80MHz.

[0102] For example, the pulse width of the first laser is 20fs, 50fs, 80fs, 100fs, 150fs, 200fs, 250fs, 300fs, 350fs, 400fs, 450fs, 500fs, 1ps, 5ps, 10ps, 20ps, 50ps, 80ps, 100ps, 500ps, 1ns, 5ns, 10ns, 50ns, or 80ns.

[0103] For example, the spot diameter of the first laser is 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 50μm, 70μm, or 90μm.

[0104] Preferably, in the first laser grooving, the wavelength of the first laser is 200-400 nm. Further, the wavelength of the first laser is 200-365 nm. More preferably, the wavelength of the first laser is 200-350 nm.

[0105] Preferably, in the first laser grooving, the pulse width of the first laser is 10 fs-500 ps. Further, the pulse width of the first laser is 10 fs-100 ps. More preferably, the pulse width of the first laser is 10 fs-500 fs.

[0106] Preferably, in the first laser grooving, the laser wavelength of the first laser is 200-350nm, the power is 100-200W, the pulse frequency is 1kHz-10MHz, the pulse width is 10fs-500fs, and the laser spot diameter is 10-40μm.

[0107] By precisely controlling the parameters of the first laser grooving and selecting a suitable laser, it is beneficial to obtain better laser grooving quality. While ensuring complete cutting of the dielectric layer, the heat-affected zone is minimized, and the exposed area around the cutting path caused by excessive laser grooving is avoided. This effectively reduces problems such as chip edge slag and residual particles generated in the exposed area, thereby helping to ensure the quality and cleanliness of the chip.

[0108] In some embodiments, the thickness of the first protective coating is 0.05-100 μm. Exemplarily, the thickness of the first protective coating is 0.1 μm, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 20 μm, 40 μm, 60 μm, or 80 μm. Preferably, the thickness of the first protective coating is 1-10 μm, more preferably 2-10 μm.

[0109] In some embodiments, during the first and second applications of the protective liquid, the coating method includes spin coating, blade coating, and immersion coating, preferably spin coating. Exemplarily, the spin coating speed is 200-5000 rpm. Preferably, the spin coating speed is 1000-3000 rpm.

[0110] By precisely controlling the thickness of the protective liquid, selecting spin coating and controlling its speed, while taking into account both coating efficiency and cost, it can effectively buffer the thermal and mechanical stress generated during laser cutting, capture particles generated during cutting, avoid excessive cutting resistance, and further improve cutting quality. It is especially suitable for dielectric layer wafers with metal structures (such as metal pads) in the above embodiments.

[0111] Preferably, the cleaning of the protective solution applied during the first coating includes: cleaning within 48 hours, preferably within 24 hours, using a spin coating combined with mega-acoustic or two-fluid method after the first coating; after cleaning, the surface of the dielectric layer and the etched dicing trenches are exposed, and the number of particles on the surface of the dielectric layer and in the etched dicing trenches is ≤100 particles @ 500nm. Here, ≤100 particles @ 500nm means: the number of particles with a size of 500nm or larger is ≤100 particles.

[0112] Specifically, the step of cleaning using spin coating combined with megasonic or two-fluid methods includes: applying cleaning solution by spin coating and then cleaning by combining it with megasonic or two-fluid cleaning.

[0113] For example, the cleaning solution includes deionized water or deionized water combined with other solutions, such as at least one of dilute acid, dilute alkali, or dilute salt. When the cleaning solution contains deionized water and a solution, the concentration of the solution in the cleaning solution is 0.1-10% (mass fraction). For example, the concentration of the solution in the cleaning solution is 0.5%, 1.0%, 2.0%, 4.0%, 6.0%, or 8.0%.

[0114] In some embodiments, after rinsing off the first-coated protective solution, the wafer is dried. Specifically, the drying is achieved through a combination of rotation and air blowing; wherein the blowing gas is at least one of nitrogen or argon; during drying, the wafer rotates at a speed of 2000-7000 rpm. After drying, no obvious water residue remains on the wafer surface.

[0115] In some embodiments, for the spin coating combined with megasonic method, preferably, during cleaning, the spin coating speed is 2000-5000 rpm, the megasonic frequency is 0.1-4.0 MHz, the flow rate of the cleaning solution is 10-2000 mL / min, the cleaning time is 30 s-5 min, and the temperature of the cleaning solution is 20-60 ℃.

[0116] In some embodiments, for the spin coating combined with two fluids, preferably, during cleaning, the spin coating speed is 2000-5000 rpm, the two fluid gas pressure is 0.1-2 MPa, the cleaning fluid flow rate is 10-2000 mL / min, the cleaning time is 30 s-5 min, and the cleaning fluid temperature is 20-60 °C.

[0117] For example, during cleaning, the spin coating speed is 2500 rpm, 3000 rpm, 3500 rpm, 4000 rpm, or 4500 rpm. Preferably, the spin coating speed is 2000-3000 rpm.

[0118] For example, during cleaning, the megaphonic frequency is 0.5MHz, 1.0MHz, 1.5MHz, 2.0MHz, 2.5MHz, 3.0MHz, or 3.5MHz. Preferably, the megaphonic frequency is 0.5-2.0MHz.

[0119] For example, during cleaning, the pressure of the two-fluid gas is 0.3 MPa, 0.5 MPa, 0.8 MPa, 1.0 MPa, or 1.5 MPa. Preferably, the pressure of the two-fluid gas is 0.3-1 MPa.

[0120] For example, the flow rate of the cleaning solution is 50 mL / min, 100 mL / min, 500 mL / min, 800 mL / min, 1000 mL / min, 1200 mL / min, 1500 mL / min, or 1800 mL / min. Preferably, the flow rate of the cleaning solution is 800-1500 mL / min.

[0121] For example, in the cleaning process, the cleaning time is 1 min, 1.5 min, 2 min, 3 min, or 4 min. The temperature of the cleaning solution is 25°C, 30°C, 40°C, or 50°C. Preferably, the cleaning time is 1 min to 2 min. Preferably, the temperature of the cleaning solution is 20 to 30°C.

[0122] In some embodiments, the substrate cutting includes: using plasma to create a groove downwards along the bottom of the etched cutting channel to complete the cutting of the substrate; in plasma cutting, the surface of the dielectric layer and the edge of the cutting channel are covered with a protective liquid.

[0123] For example, the etching rate of the plasma cutting is 100-1000 nm / min. Preferably, in plasma cutting, the etching depth = (90%-100%) × substrate thickness. After etching, the perpendicularity of the sidewall of the cutting path is 80-100°.

[0124] For example, the protective liquid described in this invention is a water-soluble protective liquid, which is used to protect the surface of the dielectric layer and the area around the kerf from laser etching during the first and second laser grooving processes. In plasma cutting, the etching process does not damage the water-soluble protective liquid on the wafer surface; therefore, after the second laser grooving, the retained protective liquid serves as a mask for plasma cutting.

[0125] For example, the main components of the water-soluble protective liquid include a basic solvent (such as deionized water), an antioxidant (such as organic acid salts), a surfactant (such as polyethylene glycol), a corrosion inhibitor, and other additives; several protective liquids can be compounded to obtain better results.

[0126] It is understandable that the etching process of plasma cutting has an endpoint detection function. When the endpoint is approached, the etching speed is slowed down or the etching power is reduced to avoid damage to the carrier (such as UV blue film) used to support the wafer by over-etching of plasma.

[0127] For example, the etching gas used in plasma cutting primarily comprises a fluorine-containing gas, such as at least one of CF4, C4F6, and SF6. In some embodiments, the etching gas is also doped with oxygen or helium.

[0128] After the substrate is cut, the process further includes: cleaning to remove the protective solution, the steps and parameters of which are similar to those for cleaning the protective solution applied for the first time; after cleaning to remove the protective solution, the substrate is expanded.

[0129] It is understandable that after the dielectric layer and substrate of the wafer are cut, the wafer has been divided into small chips of a specific size. However, at this point, the chip spacing is still relatively small, and it is necessary to increase the chip spacing by wafer expansion to facilitate subsequent processes such as pick-up.

[0130] The wafer expansion methods include mechanical wafer expansion and temperature-controlled wafer expansion. Specifically, after the substrate is diced, the chip is placed on or transferred onto a UV blue film, and wafer expansion is performed using either mechanical or temperature-controlled methods. Mechanical wafer expansion involves placing the diced chip and UV blue film together on the wafer expansion machine stage, and then lifting the stage upwards to expand the UV blue film and increase the chip spacing. Temperature-controlled wafer expansion uses temperature regulation to change the elasticity of the UV blue film, combined with the wafer expansion stage, to control the chip spacing; the process temperature for temperature-controlled wafer expansion is between 0-80℃.

[0131] In some embodiments, the chip spacing after wafer expansion is 50-500 μm, and the chip spacing after wafer expansion = (1.1-10 times) × the chip spacing before wafer expansion. For example, the chip spacing after wafer expansion is 2 times, 4 times, 6 times, or 8 times the chip spacing before wafer expansion.

[0132] Preferably, the chip spacing after wafer expansion is 110%-300% of the chip spacing before wafer expansion.

[0133] It should be noted that in the low-defect chip dicing method described in the embodiments of the present invention, the substrate is cleaned after dicing. After cleaning, the number of particles larger than 2μm on the carrier (such as UV blue film) used to support the wafer does not exceed 100.

[0134] In some embodiments, the wafer is a single-sided dielectric layer wafer. Specifically, the wafer includes a substrate and a dielectric layer located on the upper surface of the substrate, the dielectric layer on the upper surface of the substrate constituting the dielectric layer on the front side of the wafer. In this case, the steps of the low-defect chip dicing method include:

[0135] (1) The dielectric layer on the front side of the wafer is cut by using the two-stage laser grooving method;

[0136] (2) Plasma is used to cut the substrate by grooving downwards along the bottom of the etched grooves in the dielectric layer on the front side of the wafer.

[0137] In some embodiments, the wafer is a double-sided dielectric layer wafer. Specifically, the wafer includes a substrate and dielectric layers located on the upper and lower surfaces of the substrate, respectively. The dielectric layer on the upper surface of the substrate constitutes the dielectric layer on the front side of the wafer, and the dielectric layer on the lower surface of the substrate constitutes the dielectric layer on the back side of the wafer. In this case, the steps of the low-defect chip dicing method include:

[0138] (1) The dielectric layer surface on the back side of the wafer is bonded to the first carrier, with the dielectric layer on the front side of the wafer facing upward; Steps (a) to (c) in the two-laser grooving method are used to complete the cutting of the dielectric layer on the front side of the wafer.

[0139] (2) Flipping: Decouple the dielectric layer surface on the back side of the wafer from the first carrier, cover the dielectric layer surface on the front side of the wafer with the second carrier, flip the wafer so that the dielectric layer on the back side of the wafer faces upward; after the flipping, ensure that the dielectric layer surface on the front side of the wafer is bonded to the second carrier.

[0140] (3) Using steps (a) to (e) of the two-laser grooving method, the dielectric layer cutting on the back side of the wafer is completed;

[0141] (4) Using plasma, grooves are cut downwards along the bottom of the etched grooves in the dielectric layer on the back side of the wafer in step (3) to complete the cutting of the substrate.

[0142] For example, in the above embodiments of single-sided dielectric layer wafers or double-sided dielectric layer wafers, the dielectric layer further includes a metal structure, such as a metal pad or a metal wiring layer.

[0143] In some embodiments, in steps (1) and (2), the first carrier and the second carrier are selected from one of UV blue film, silicon-based wafer carrier, and transparent glass carrier, and their area is large enough to cover the surface of the wafer to be cut.

[0144] For example, the UV blue film is bonded to the dielectric layer on the front or back side of the wafer via an adhesion layer on the surface of the UV blue film. The adhesion force of the UV blue film to the wafer is 1000-6000mN / 20mm.

[0145] For example, the silicon-based wafer carrier is bonded to the dielectric layer on the front or back side of the wafer by fusion bonding or temporary bonding, preferably fusion bonding.

[0146] For example, the transparent glass substrate is bonded to a dielectric layer on the front or back side of the wafer via temporary bonding.

[0147] In one embodiment, in step (1), when the first carrier is a UV blue film, the step of bonding the dielectric layer surface on the back side of the wafer with the first carrier includes: attaching a UV blue film to the dielectric layer surface on the back side of the wafer.

[0148] In one embodiment, in step (2), when the second carrier is a UV blue film, the step of ensuring that the dielectric layer surface on the front side of the wafer is bonded to the second carrier includes: attaching a UV blue film to the grooved dielectric layer surface on the front side of the wafer to ensure that the grooved dielectric layer surface on the front side of the wafer is bonded to the UV blue film; and removing the first carrier.

[0149] In one embodiment, in step (1), when the first carrier is a silicon-based wafer carrier, the step of bonding the dielectric layer surface on the back side of the wafer with the first carrier includes: placing the back side of the wafer on the silicon-based wafer carrier and fixing the dielectric layer surface on the back side of the wafer to the silicon-based wafer carrier by means of fusion bonding or temporary bonding.

[0150] In one embodiment, in step (2), when the second carrier is a silicon-based wafer carrier, the step of ensuring that the dielectric layer surface on the front side of the wafer is bonded to the second carrier includes: covering the grooved dielectric layer surface on the front side of the wafer with the silicon-based wafer carrier, flipping the wafer so that the dielectric layer on the back side of the wafer faces upward; after the flipping, bonding the grooved dielectric layer surface on the front side of the wafer to the silicon-based wafer carrier by fusion bonding or temporary bonding; and removing the first carrier.

[0151] In one embodiment, in step (1), when the first carrier is a transparent glass substrate, the step of bonding the dielectric layer surface on the back side of the wafer with the first carrier includes: placing the back side of the wafer on the transparent glass substrate and fixing the dielectric layer surface on the back side of the wafer to the transparent glass substrate by temporary bonding.

[0152] In one embodiment, in step (2), when the second carrier is a transparent glass substrate, the step of ensuring that the dielectric layer surface on the front side of the wafer is bonded to the second carrier includes: covering the grooved dielectric layer surface on the front side of the wafer with the transparent glass substrate, flipping the wafer so that the dielectric layer on the back side of the wafer faces upward; after the flipping, bonding the grooved dielectric layer surface on the front side of the wafer to the transparent glass substrate through temporary bonding; and removing the first carrier.

[0153] In one embodiment, in step (2), when the first carrier is a UV blue film, the step of debonding the dielectric layer surface on the back side of the wafer from the first carrier includes: irradiating the back side of the wafer with UV light to perform UV debonding treatment on the dielectric layer surface on the back side of the wafer and the first carrier. Specifically, in the UV debonding treatment, the UV wavelength range is 300-400nm, and the irradiation intensity is 50-300mW / cm². 2 The irradiation time is 10-60 seconds, and the irradiation distance is 5-20 cm. After UV debonding treatment, the adhesion force between the dielectric layer surface on the back of the wafer and the first carrier is 10-500 mN / 20 mm, and there is no residual adhesive on the wafer surface. Exemplarily, the atmosphere for UV debonding treatment includes at least one of oxygen, nitrogen, argon, and ozone, or a vacuum condition.

[0154] In one embodiment, in step (2), when the first carrier is a silicon-based wafer carrier, the step of debonding the dielectric layer surface on the back side of the wafer from the first carrier includes: using mechanical debonding or laser debonding to debond the dielectric layer surface on the back side of the wafer from the silicon-based wafer carrier.

[0155] In one embodiment, in step (2), when the first carrier is a transparent glass substrate, the step of debonding the dielectric layer surface on the back side of the wafer from the first carrier includes: using laser debonding to debond the dielectric layer surface on the back side of the wafer from the transparent glass substrate.

[0156] In the above embodiments, the mechanical debonding includes: creating initial cracks at the bonding interface using a blade, and separating the silicon-based wafer carrier and the wafer using the mechanical cracks. Specifically, the blade thickness is 50-200 μm, the blade insertion angle is 10-30°, the insertion speed is 0.1-5 mm / s, and the insertion force is 0.1-10 N. For example, the blade material is stainless steel or titanium alloy.

[0157] For example, the blade thickness is 100μm or 150μm. The blade insertion angle is 15°, 20°, or 25°. The insertion speed is 0.5mm / s, 1.0mm / s, 2.0mm / s, 3.0mm / s, or 4.0mm / s. The insertion force is 0.5N, 1.0N, 2.0N, 5.0N, or 8.0N.

[0158] In the above embodiments, the laser debonding includes: irradiating one side of a carrier substrate (such as a silicon-based wafer carrier or a transparent glass carrier) with a laser, acting on the bonding interface to destroy the temporary bonding adhesive between the carrier substrate and the wafer, thereby reducing the interfacial adhesion. In laser debonding, the laser spot size is 10-200 μm, and the scanning speed is 10-1000 mm / s. Exemplarily, the laser spot size is 20 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, or 180 μm. Exemplarily, the scanning speed in laser debonding is 20 mm / s, 50 mm / s, 100 mm / s, 200 mm / s, 400 mm / s, 600 mm / s, or 800 mm / s. Exemplarily, in laser debonding, the laser is ultraviolet 355 nm, green 532 nm, or infrared 1064 nm.

[0159] It should be noted that in the low-defect chip dicing method described in this embodiment of the invention, after the dielectric layer and substrate are diced, there are no obvious slag or particle residues at the dicing edge, chip edge, and surface. Specifically, before cleaning with the protective solution, the slag or accumulation height at the dicing edge and chip edge is ≤0.5μm; after cleaning with the protective solution, the slag or accumulation height at the dicing edge and chip edge is ≤0.5μm, and the number of particles on the chip surface is ≤100 particles @90nm.

[0160] The present invention also provides a chip obtained by the above-mentioned low-defect chip dicing method, wherein the chip edge serpentine is less than 2μm, the slag or accumulation height at the chip edge is ≤0.5μm, the number of contaminant particles on the chip surface is ≤100 @90nm, and the layer width between the dielectric layer and the substrate of the chip is ≤1μm.

[0161] The term ≤100 particles @ 90nm here means that the number of particles with a particle size of 90nm or larger is ≤100.

[0162] In some embodiments, the chip area is 1 mm². 2 -900mm 2 For example, the chip is square or rectangular, with a side length ranging from 1mm to 30mm. For example, the side lengths are 2mm, 4mm, 6mm, 8mm, 10mm, 15mm, 20mm, and 25mm.

[0163] In some embodiments, the thickness of the chip is 10μm-800μm.

[0164] In some embodiments, the chip includes a substrate and a dielectric layer located on the upper surface of the substrate, the dielectric layer on the upper surface of the substrate constituting the dielectric layer on the front side of the chip.

[0165] In some embodiments, the chip includes a substrate and dielectric layers located on an upper surface and a lower surface of the substrate, respectively. The dielectric layer on the upper surface of the substrate constitutes the dielectric layer on the front side of the chip, while the dielectric layer on the lower surface of the substrate constitutes the dielectric layer on the back side of the chip.

[0166] For example, the dielectric layer on the front side of the chip and / or the dielectric layer on the back side of the chip includes a metal structure. The thickness of the dielectric layer is 10nm-20μm, and the thickness of the substrate is 10μm-780μm.

[0167] In some embodiments, the metal structure includes metal pads. Specifically, each metal pad has an area of ​​0.03 μm. 2 -100μm 2 The pad pitch is 0.4μm-20μm, and the pad depth is 10nm-1000nm. For example, the metal pad structure is circular, square, or rectangular. The diameter of the circular pad is 0.2μm-10μm, and the side length of the square or rectangular pad is 0.2μm-10μm.

[0168] It is understood that the metal pads are located on the surface of the dielectric layer. After processes such as chemical mechanical polishing, the metal pad structure is exposed, and the chip surface exhibits a metal-dielectric topology.

[0169] In some embodiments, the metal structure includes a metal wiring layer located within the dielectric layer. The metal wiring layer is suitable for memory devices, logic devices, etc. For example, the number of metal wiring layers can be 1 to 5.

[0170] In some embodiments, the dielectric layer is made of at least one of silicon oxide, silicon nitride, silicon carbide, SiCO, SiCN, SiCON, lithium niobate, InP, AsGaIn, GaN, alumina, and TEOS (tetraethoxysilane). The substrate is made of at least one of silicon, glass, and diamond.

[0171] The technical solution of the present invention will be further described in detail below with reference to specific embodiments and comparative examples.

[0172] Example 1:

[0173] This embodiment provides a low-defect chip dicing method suitable for D2W hybrid bonding, including the following steps:

[0174] S0. A wafer 100 is provided, the wafer 100 having a size of 12 inches and a thickness of 200 μm. The wafer 100 includes a substrate 12 and a dielectric layer 11 located on the upper surface of the substrate 12, the dielectric layer 11 on the upper surface of the substrate 12 constituting the dielectric layer on the front side of the wafer. The substrate 12 is made of silicon, the dielectric layer 11 is made of silicon oxide, the dielectric layer 11 has a thickness of 1 μm, and the surface of the dielectric layer 11 includes circular copper pads, each pad having a diameter of 5 μm, a pad pitch of 10 μm, and a pad depth of 100 nm. Each dicing track 13 of the wafer 100 has a width of 400 μm. The diced individual chip 10a is required to be square, with a length of 10 mm and a width of 10 mm.

[0175] The back side of wafer 100 is attached to the carrier 200 (i.e., UV blue film) used to support wafer 100. The blue film is supported by a stainless steel metal frame, with the dielectric layer 11 on the front side of the wafer facing upwards.

[0176] S1. The dielectric layer 11 is cut using a two-stage laser grooving method; the two-stage laser grooving method includes the following steps:

[0177] (a) First coating of protective liquid: A water-soluble laser protective liquid is first coated on the dielectric layer 11 on the front side of the wafer by spin coating; wherein, the spin coating speed is 1000 rpm and the thickness of the first coating of laser protective liquid is 40 μm.

[0178] (b) First laser grooving: Using a first laser, the dielectric layer 11 on the front side of the wafer is laser-grooved along the dicing groove of the wafer until the dicing groove etched by the first laser penetrates the dielectric layer 11 on the front side of the wafer; wherein, the laser for the first laser grooving is an ultraviolet picosecond laser with a wavelength of 355nm, a power of 100W, a pulse frequency of 100MHz, a pulse width of 100ps, and a laser spot diameter of 10μm; each dicing groove 13 has a width of 50μm, the width of the first laser grooving = 90% × the width of the dicing groove; the depth of the first laser grooving = the thickness of the first protective coating + the thickness of the dielectric layer 11 on the front side of the wafer = 41μm.

[0179] (c) Clean the first-coated protective solution to expose the surface of the dielectric layer 11 and the etched dicing grooves; specifically, within 24 hours after the first coating of the protective solution, deionized water is coated by spin coating and combined with megason cleaning to remove the first-coated laser protective solution; during cleaning, the spin coating speed is 5000 rpm, the megason frequency is 4 MHz, the cleaning solution flow rate is 1000 mL / min, the cleaning time is 30 s, and the cleaning solution temperature is 30 ℃; after cleaning, the number of particles on the surface of the dielectric layer 11 of the wafer and in the etched dicing grooves is ≤100 particles @ 500 nm.

[0180] (d) Second coating of protective liquid: The laser protective liquid is coated a second time on the surface of the dielectric layer 11 on the front side of the wafer by spin coating, so that the protective liquid covers the surface of the dielectric layer 11 and the inner wall of the etched dicing groove, and the protective liquid accumulates at the bottom of the dicing groove; wherein, the spin coating speed is 2000 rpm, and the thickness of the second coating of laser protective liquid is 15 μm.

[0181] (e) Second laser grooving: Using a second laser, the protective liquid 32 accumulated in the groove of the cutting track is removed, while the surface of the dielectric layer 11 and the edge of the cutting track are covered by the protective liquid 31; wherein, the laser for the second laser grooving is a green nanosecond laser with a wavelength of 532nm, a power of 70W (70% of the power of the first laser grooving), a pulse frequency of 500kHz, a pulse width of 500ns, and a laser spot diameter of 20μm; the width of the second laser grooving = 75% × the width of the first laser grooving; the projected area of ​​the second laser grooving S2 = 85% × S1; the depth of the second laser grooving = the thickness of the second laser protective liquid coating = 15μm.

[0182] S2. Plasma is used to cut downwards along the bottom of the groove etched in step S1, completing the cutting of the substrate. The plasma cutting etching rate is 1000 nm / min, the etching depth is 100% × substrate thickness 12, and the etching gas is CF4. After etching, the verticality of the sidewall of the etched track is 88°.

[0183] After the substrate is cut, the protective solution is removed by cleaning. After cleaning, the number of particles larger than 2μm on the UV blue film does not exceed 100.

[0184] Furthermore, mechanical wafer expansion is used. The cut chips and UV blue film are placed together on the wafer expansion machine stage. The stage is lifted upward to expand the UV blue film and increase the chip spacing. After expansion, the chip spacing is 500μm.

[0185] In this embodiment, the chip edge serpentine shape is less than 2μm, the number of contaminant particles on the chip surface is less than 100 @ 90nm, and the layer width between the dielectric layer 11 and the substrate 12 is ≤ 1μm. For example... Figure 4 In this embodiment, the cutting path boundary is clear, there are no obvious traces of ablation on the chip edge, and the height of slag or accumulation on the chip edge is ≤0.5μm.

[0186] Example 2

[0187] The difference between this embodiment and Embodiment 1 is that, in step S1, the power of the second laser grooving is 50W (50% of the power of the first laser grooving). The remaining steps and parameters are similar to those in Embodiment 1.

[0188] In this embodiment, the chip edge serpentine shape is less than 1.6 μm, the slag or accumulation height at the chip edge is ≤0.5 μm, the number of contaminated particles on the chip surface is less than 90 particles @90 nm, and the layer width between the dielectric layer 11 and the substrate 12 of the chip is ≤0.8 μm.

[0189] Example 3

[0190] The difference between this embodiment and Embodiment 1 is that, in step S1, the power of the second laser grooving is 20W (20% of the power of the first laser grooving). The remaining steps and parameters are similar to those in Embodiment 1.

[0191] In this embodiment, the chip edge serpentine shape is less than 1.7 μm, the slag or accumulation height at the chip edge is ≤0.5 μm, the number of contaminated particles on the chip surface is less than 85 particles @90 nm, and the layer width between the dielectric layer 11 and the substrate 12 of the chip is ≤0.9 μm.

[0192] Example 4

[0193] The difference between this embodiment and Embodiment 1 is that, in step S1, the power of the second laser grooving is 35W (35% of the power of the first laser grooving). The remaining steps and parameters are similar to those in Embodiment 1.

[0194] In this embodiment, the chip edge serpentine shape is less than 1.5 μm, the slag or accumulation height at the chip edge is ≤0.4 μm, the number of contaminated particles on the chip surface is less than 80 particles @90 nm, and the layer width between the dielectric layer 11 and the substrate 12 of the chip is ≤0.9 μm.

[0195] Example 5

[0196] The difference between this embodiment and Embodiment 1 is that, in step S1, the width of the second laser grooving is 85% × the width of the first laser grooving; the projected area S2 of the second laser grooving is 90% × S1. The remaining steps and parameters are similar to those in Embodiment 1.

[0197] In this embodiment, the chip edge serpentine shape is less than 1.8 μm, the slag or accumulation height at the chip edge is ≤0.5 μm, the number of contaminated particles on the chip surface is less than 100 particles @90 nm, and the layer width between the dielectric layer 11 and the substrate 12 of the chip is ≤0.9 μm.

[0198] Example 6

[0199] The difference between this embodiment and Embodiment 1 is that, in step S1, the width of the second laser grooving is 99% × the width of the first laser grooving; the projected area S2 of the second laser grooving is 99% × S1. The remaining steps and parameters are similar to those in Embodiment 1.

[0200] In this embodiment, the chip edge serpentine shape is less than 1.9 μm, the slag or accumulation height at the chip edge is ≤0.5 μm, the number of contaminated particles on the chip surface is less than 90 particles @90 nm, and the layer width between the dielectric layer 11 and the substrate 12 of the chip is ≤1 μm.

[0201] Example 7

[0202] The difference between this embodiment and Embodiment 1 is that, in step S1, the width of the second laser grooving is 90% × the width of the first laser grooving; the projected area S2 of the second laser grooving is 95% × S1. The remaining steps and parameters are similar to those in Embodiment 1.

[0203] In this embodiment, the chip edge serpentine shape is less than 1.5 μm, the slag or accumulation height at the chip edge is ≤0.4 μm, the number of contaminated particles on the chip surface is less than 80 particles @90 nm, and the layer width between the dielectric layer 11 and the substrate 12 of the chip is ≤0.6 μm.

[0204] Example 8

[0205] The difference between this embodiment and Embodiment 1 is that, in step S1, the thickness of the second coating of the laser protective liquid is 20 μm. The remaining steps and parameters are similar to those in Embodiment 1.

[0206] In this embodiment, the chip edge serpentine shape is less than 1.4 μm, the slag or accumulation height at the chip edge is ≤0.4 μm, the number of contaminated particles on the chip surface is less than 70 particles @90 nm, and the layer width between the dielectric layer 11 and the substrate 12 of the chip is ≤1 μm.

[0207] Example 9

[0208] The difference between this embodiment and Embodiment 1 is that, in step S1, the laser used for the first laser grooving is an ultraviolet femtosecond laser, the wavelength of the first laser grooving is 266nm, the power is 150W, the pulse frequency is 10MHz, the pulse width is 500fs, and the laser spot diameter is 20μm; the width of the first laser grooving is 80% × the width of the cutting path; the pulse frequency of the second laser grooving is 100kHz, the pulse width is 200ns, and the laser spot diameter is 20μm; the remaining steps and parameters are similar to those in Embodiment 1.

[0209] In this embodiment, the chip edge serpentine shape is less than 2μm, the slag or accumulation height at the chip edge is ≤0.3μm, the number of contaminant particles on the chip surface is less than 90 particles @90nm, and the layer width between the dielectric layer 11 and the substrate 12 of the chip is ≤1μm.

[0210] Example 10:

[0211] This embodiment provides a low-defect chip dicing method suitable for D2W hybrid bonding, including the following steps:

[0212] S0. A wafer 100 is provided, the wafer 100 having a size of 12 inches and a thickness of 200 μm. The wafer 100 includes a substrate 12 and a dielectric layer 11a on the upper surface and a dielectric layer 11b on the lower surface of the substrate 12. The dielectric layer on the upper surface of the substrate constitutes the dielectric layer 11a on the front side of the wafer, and the dielectric layer on the lower surface of the substrate constitutes the dielectric layer 11b on the back side of the wafer. The substrate 12 is made of silicon, and both dielectric layers 11a and 11b are made of silicon oxide. The thickness of both dielectric layers 11a and 11b is 1 μm. The surfaces of both dielectric layers 11a and 11b contain circular copper pads, each with a diameter of 5 μm, a pad pitch of 10 μm, and a pad depth of 100 nm. The width of each dicing track 13 of the wafer 100 is 400 μm. Each diced chip is required to be square, with a length of 10 mm and a width of 10 mm.

[0213] S1, Dielectric layer dicing on the front side of the wafer:

[0214] The back side of the wafer is attached to the first carrier 20a (i.e., UV blue film), which is supported by a stainless steel metal frame, with the dielectric layer 11a on the front side of the wafer facing upwards; the dielectric layer 11a on the front side of the wafer is cut by using steps (a) to (c) in the two-laser grooving method.

[0215] (a) Initial coating of laser protective solution: A water-soluble laser protective solution is coated on the dielectric layer 11a on the front side of the wafer by spin coating; wherein the spin coating speed is 1000 rpm and the thickness of the laser protective solution is 40 μm.

[0216] (b) Initial laser grooving: Using a first laser, laser grooving is performed on the dielectric layer 11a on the front side of the wafer along the etch path 13 until the etched etch path groove penetrates the dielectric layer 11a; wherein, the laser for the initial laser grooving is an ultraviolet picosecond laser with a wavelength of 355nm, a power of 200W, a pulse frequency of 10MHz, a pulse width of 100ps, and a laser spot diameter of 40μm; the etch path width is 400μm, and the width of the first laser grooving = 80% × the width of the etch path; the depth of the initial laser grooving = the thickness of the initial laser protective liquid + the thickness of the dielectric layer 11a on the front side of the wafer = 41μm.

[0217] (c) Clean the initial protective solution to expose the surface of the dielectric layer 11a on the front side of the wafer and the etched grooves. Specifically, within 24 hours after the initial protective solution is applied, deionized water is applied by spin coating and then cleaned by megasonic cleaning to remove the laser protective solution. During cleaning, the spin coating speed is 5000 rpm, the megasonic frequency is 4 MHz, the flow rate of the cleaning solution is 1000 mL / min, the cleaning time is 30 s, and the temperature of the cleaning solution is 30 ℃. After cleaning, the number of particles on the surface of the dielectric layer 11a on the front side of the wafer and in the etched grooves is ≤100 particles @ 500 nm.

[0218] S2, Flip:

[0219] After the dielectric layer on the front side of the wafer is cut, the wafer is attached to the UV blue film frame. A UV debonding machine is used to irradiate the back side of the wafer with UV light to break the adhesion between the blue film and the back side of the wafer, thus detaching the dielectric layer 11b surface on the back side of the wafer from the UV blue film (first carrier 20a). In the UV debonding process, the UV wavelength is 300nm, the irradiation intensity is 100mW / cm2, the irradiation time is 20s, and the irradiation distance is 10cm. The adhesion after UV debonding is 100mN / 20mm.

[0220] Another UV blue film (second carrier 20b) is attached to the surface of the dielectric layer 11a on the front side of the wafer. The UV blue film on the back side is peeled off, and the wafer is flipped so that the dielectric layer 11b on the back side of the wafer faces upward.

[0221] S3, Dielectric layer dicing on the back side of the wafer:

[0222] The dielectric layer 11b is cut using a two-stage laser grooving method; the two-stage laser grooving method includes the following steps:

[0223] (a) A water-soluble laser protective liquid is first coated on the dielectric layer 11b on the back side of the wafer by spin coating; wherein the spin coating speed is 1000 rpm and the thickness of the laser protective liquid is 40 μm.

[0224] (b) First laser grooving: Using a first laser, laser grooving is performed on the dielectric layer 11b on the back side of the wafer along the etched groove until the etched groove penetrates the dielectric layer 11b; wherein, the laser for the first laser grooving is an ultraviolet picosecond laser with a wavelength of 355nm, a power of 200W, a pulse frequency of 10MHz, a pulse width of 100ps, and a laser spot diameter of 40μm; the etched groove width is 400μm, and the width of the first laser grooving = 80% × the width of the etched groove; the projected area S1 of the first laser grooving is 30cm². 2 The depth of laser grooving = the thickness of the first laser protective liquid coating + the thickness of the dielectric layer on the back of the wafer = 41μm.

[0225] (c) Clean the first protective solution to expose the dielectric layer 11b surface on the back of the wafer and the etched grooves; specifically, within 24 hours after the first protective solution is applied, deionized water is coated by spin coating and combined with megasonic cleaning to remove the laser protective solution; during cleaning, the spin coating speed is 5000 rpm, the megasonic frequency is 4 MHz, the flow rate of the cleaning solution is 1000 mL / min, the cleaning time is 30 s, and the temperature of the cleaning solution is 30 ℃; after cleaning, the number of particles in the dielectric layer 11b on the back of the wafer and in the laser-etched grooves is ≤100 particles @ 500 nm.

[0226] (d) A laser protective liquid is applied a second time to the surface of the dielectric layer 11b on the back side of the wafer by spin coating, so that the protective liquid covers the surface of the dielectric layer 11b and the inner wall of the dicing groove, and accumulates at the bottom of the dicing groove; wherein, the spin coating speed is 2000 rpm and the thickness of the laser protective liquid is 15 μm.

[0227] (e) Second laser grooving: Using a second laser, the protective liquid 32 accumulated in the groove of the cutting track is removed, while the surface of the dielectric layer 11b and the edge of the cutting track are covered by the protective liquid 31; wherein, the laser for the second laser grooving is a green nanosecond laser with a wavelength of 532nm, a power of 70% of the power of the first laser grooving, a pulse frequency of 500kHz, a pulse width of 500ns, and a laser spot diameter of 50μm; the width of the second laser grooving = 75% × the width of the first laser grooving; the projected area of ​​the second laser grooving S2 = 85% × S1; the depth of the second laser grooving = the thickness of the second laser protective liquid coating = 15μm.

[0228] S3. Plasma is used to cut downwards along the bottom of the groove etched in step S2, completing the cutting of the substrate. The plasma cutting etching rate is 1000 nm / min, the etching depth is 100% × substrate thickness 12, and the etching gas is CF4. After etching, the verticality of the sidewall of the etched track is 88°.

[0229] After the substrate is cut, the protective solution is removed by cleaning. After cleaning, the number of particles larger than 2μm on the UV blue film does not exceed 100.

[0230] Furthermore, mechanical wafer expansion is used. The cut chips and UV blue film are placed together on the wafer expansion machine stage. The stage is lifted upward to expand the UV blue film and increase the chip spacing. After expansion, the chip spacing is 500μm.

[0231] In this embodiment, the chip edge serpentine shape is less than 2μm, the slag or accumulation height at the chip edge is <0.05μm, the number of contaminated particles on the chip surface is less than 100 @90nm, and the layer width between the dielectric layer 11a, dielectric layer 11b and substrate 12 is ≤1μm.

[0232] Comparative Example 1

[0233] This comparative example provides a chip dicing method that, compared to Example 1, omits steps (d) and (e) in S1; the remaining steps and parameters are similar to those in Example 1.

[0234] like Figure 6 The cut boundary of this comparative example is not clear enough, there are black ablation marks on the chip edge, and there is obvious residue accumulation with a height of 1.0-2.0μm.

[0235] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A low-defect chip dicing method suitable for D2W hybrid bonding, characterized in that, include: A wafer is provided, the wafer including a substrate and a dielectric layer located on the surface of the substrate, the dielectric layer constituting a dielectric layer on the surface of the wafer; First, cut the dielectric layer, then cut the substrate; The dielectric layer is cut using a two-stage laser grooving method, which includes the following steps: (a) Apply a protective liquid to the surface of the dielectric layer on the wafer surface for the first time; (b) First laser grooving: Using a first laser, the dielectric layer on the wafer surface is laser-grooved along the wafer dicing path until the dicing path groove etched by the first laser penetrates the dielectric layer on the wafer surface. (c) Clean the first coating of protective liquid to expose the surface of the dielectric layer and the etched cutting grooves; (d) A protective liquid is applied a second time to the dielectric layer surface on the wafer surface, so that the protective liquid covers the dielectric layer surface and the inner wall of the etched dicing trench, and accumulates in the dicing trench. (e) Second laser grooving: Using a second laser, the protective liquid accumulated in the groove of the cutting track is removed, while the surface of the medium layer and the edge of the cutting track are covered with protective liquid. The depth of the second laser grooving is less than or equal to the depth of the first laser grooving, and the width of the second laser grooving is less than or equal to the width of the first laser grooving.

2. The low-defect chip dicing method according to claim 1, characterized in that, The thickness of the first protective coating is t1, and the thickness of the second protective coating is t2, satisfying: t2 = (50% - 100%) × t1.

3. The low-defect chip dicing method according to claim 1, characterized in that, The depth of the second laser grooving is d2, which satisfies: d2 = (100-110%) × t2; t2 is the thickness of the second protective coating.

4. The low-defect chip dicing method according to claim 1, characterized in that, The width of the first laser grooving is w1, and the width of the second laser grooving is w2, satisfying w2 = (85% - 99%) × w1.

5. The low-defect chip dicing method according to claim 1, characterized in that, The laser power of the second laser grooving is less than the laser power of the first laser grooving.

6. The low-defect chip dicing method according to claim 1, characterized in that, The laser power for the first laser grooving is P1, and the laser power for the second laser grooving is P2, satisfying P2 = (20% - 50%) × P1.

7. The low-defect chip dicing method according to claim 1, characterized in that, The projected area of ​​the first laser grooving is S1, and the projected area of ​​the second laser grooving is S2, satisfying S2 = (95% - 99%) × S1, and the overlap of the projected areas of the first laser grooving and the second laser grooving is above 95%-99%.

8. The low-defect chip dicing method according to claim 1, characterized in that, The second laser has a wavelength of 300-600nm, a pulse frequency of 10Hz-500kHz, and a pulse width of 1-500ns; and / or, The laser used for the second laser grooving is a green nanosecond or ultraviolet nanosecond laser.

9. The low-defect chip dicing method according to claim 1, characterized in that, The substrate cutting includes: using plasma to create grooves downwards along the bottom of the etched cutting channel to complete the cutting of the substrate; in plasma cutting, the surface of the dielectric layer and the edge of the cutting channel are covered by a protective liquid.

10. The low-defect chip dicing method according to claim 1, characterized in that, After the dielectric layer and substrate are cut, before cleaning with the protective solution, the height of slag or accumulation at the edge of the dicing track and the edge of the chip is ≤0.5μm; after cleaning with the protective solution, the height of slag or accumulation at the edge of the dicing track and the edge of the chip is ≤0.5μm, and the number of particles on the chip surface is ≤100 particles @90nm.

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