Package substrate with cavity and method of making the same
Patent Information
- Application Number
- CN202610972282.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-30
- Publication Date
- 2026-11-03
AI Technical Summary
Existing technologies suffer from low processing efficiency, poor dimensional accuracy, and poor bottom flatness when forming the cavity of the packaging substrate. In particular, when the design includes pads, a metal barrier layer is required, which complicates the process and makes the pads prone to detachment.
By setting a second dielectric layer at the bottom of the sacrificial copper pillar, the use of a metal barrier layer alone is avoided. The dielectric layer protects the pads, improving processing efficiency when etching to form cavities and ensuring the dimensional accuracy and bottom flatness of the cavities.
It enables cavity machining without a metal barrier layer, improves machining efficiency, and obtains a cavity structure with high precision and good flatness.
Smart Images
Figure CN123035965A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor packaging technology, and in particular to a packaging substrate with a cavity and a method for manufacturing the same. Background Technology
[0002] With the continuous development of electronic information technology, multifunctionality and miniaturization are the main drivers for the upgrading and iteration of electronic products. To achieve multifunctionality, the design of key components such as integrated circuits and packaging modules is becoming increasingly complex; to achieve portability, electronic products are required to be smaller and thinner. Packaging structures that embed components within a substrate have become an important solution for miniaturization, thinning, and modularization. However, how to simplify processes, improve efficiency, reduce the manufacturing cost of packaging substrates, and reduce the size of the package remains a problem to be solved. Summary of the Invention
[0003] In view of this, the purpose of this disclosure is to provide a packaging substrate with a cavity and a method for manufacturing the same.
[0004] To achieve the above objectives, this disclosure provides a method for fabricating a packaging substrate with a cavity, comprising:
[0005] (a) A substrate is provided; wherein the substrate includes a first circuit layer, a sacrificial copper pillar, and a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked thereon; the first circuit layer is located between the first dielectric layer and the second dielectric layer; the sacrificial copper pillar is formed on the surface of the second dielectric layer away from the first dielectric layer; and the third dielectric layer exposes the end face of the sacrificial copper pillar. (b) Etching the sacrificial copper pillar to form a cavity; (c) A blind via is formed in the second dielectric layer at a position corresponding to the cavity; the blind via exposes the pads of the first circuit layer; (d) Installing components in the cavity, wherein the terminal bumps of the components are soldered to the pads.
[0006] In some embodiments, step (a) includes: (a1) Provide a support plate; (a2) A first conductive copper pillar is formed on the bearing plate; (a3) A first dielectric layer is laminated on the carrier plate; wherein the first dielectric layer exposes the end face of the first conductive copper pillar; (a4) The first circuit layer is formed on the first dielectric layer; (a5) A second conductive copper pillar is formed on the first line layer; (a6) The second dielectric layer is laminated on the first dielectric layer, the first circuit layer and the second conductive copper pillar; the second dielectric layer exposes the end face of the second conductive copper pillar; (a7) A third conductive copper pillar and the sacrificial copper pillar are formed on the second dielectric layer; the third conductive copper pillar is connected to the second conductive copper pillar; (a8) A third dielectric layer is laminated on the second dielectric layer; the third dielectric layer exposes the end faces of the third conductive copper pillar and the sacrificial copper pillar; (a9) Remove the support plate.
[0007] In some embodiments, prior to step (b), the method further includes: A film is laminated on both sides of the substrate, and the end faces of the sacrificial copper pillars are exposed by exposure and development.
[0008] In some embodiments, the substrate further includes an outer circuit layer, a solder mask layer, and a surface treatment layer; wherein the outer circuit layer and the solder mask layer are located on the surfaces of the first dielectric layer and the third dielectric layer; and the surface treatment layer is located on the surface of the outer circuit layer.
[0009] In some embodiments, step (a) further includes: (a10) The outer circuit layer and the solder mask layer are formed on the surfaces of the first dielectric layer and the third dielectric layer; (a11) The surface treatment layer is formed on the outer circuit layer.
[0010] In some embodiments, the blind hole is obtained using a laser drilling process.
[0011] In some embodiments, step (a2) includes: A first seed layer is formed on the support plate; A first photosensitive layer is formed by attaching a film to the first seed layer, exposing it, and developing it. The first conductive copper pillar is formed by electroplating on the first seed layer exposed by the first photosensitive layer; Remove the first photosensitive layer.
[0012] In some embodiments, step (a3) includes: Press the first dielectric layer; Thinning the first dielectric layer exposes the end face of the first conductive copper pillar.
[0013] In some embodiments, the substrate includes a plurality of packaging units; some of the packaging units are arranged along a predetermined direction and their respective sacrificial copper pillars are connected to each other to form a sacrificial copper strip.
[0014] Based on the same inventive concept, this disclosure also provides a packaging substrate with a cavity, including: a first circuit layer, a cavity, components, and a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked thereon; the first circuit layer is located between the first dielectric layer and the second dielectric layer; the cavity is located on the surface of the second dielectric layer away from the first dielectric layer and penetrates the third dielectric layer; the components are mounted in the cavity and the terminal bumps of the components are conductively soldered to the pads of the first circuit layer.
[0015] In some embodiments, the packaging substrate includes a plurality of packaging units; some of the packaging units are arranged along a predetermined direction and the cavities corresponding to each unit penetrate each other.
[0016] In some embodiments, the system further includes an outer circuit layer, a first conductive copper pillar, a second conductive copper pillar, and a third conductive copper pillar; wherein the first conductive copper pillar is located in the first dielectric layer and connects the first circuit layer and the outer circuit layer located on the first dielectric layer; the second conductive copper pillar is located in the second dielectric layer; the third conductive copper pillar is located in the third dielectric layer; the second conductive copper pillar and the third conductive copper pillar are interconnected and connect the first circuit layer and the outer circuit layer located on the third dielectric layer.
[0017] As can be seen from the above, the present disclosure provides a cavity-type packaging substrate and its manufacturing method. By setting a second dielectric layer at the bottom of the sacrificial copper pillar, a separate metal barrier layer is not required when etching the sacrificial copper pillar to form a cavity. This not only greatly improves the processing efficiency, but also produces a cavity with high dimensional accuracy and good bottom flatness. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figures 1(a) to 1(o) show cross-sectional schematic diagrams of the intermediate structures of each step in a method for manufacturing a cavity-containing packaging substrate provided in the present disclosure embodiment; it should be noted that only one packaging unit is shown in the figures. Figure 1(p) shows a top view of the overall structure of a packaging substrate provided in an embodiment of this disclosure; Figure 1(q) shows a top view of a packaging unit provided in an embodiment of the present disclosure; Figure 2 This diagram illustrates a structural schematic of a packaging substrate with a cavity provided in an embodiment of the present disclosure. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings. In the drawings, for better understanding and ease of description, the thickness and shape of some layers and regions may be exaggerated.
[0021] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Words such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Words such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. When terms such as "above," "over," "below," and "beside" are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used in conjunction with the terms "immediately" or "directly." When one element or layer is disposed "on" another element or layer, the additional layer or element may be directly inserted onto or between the other element.
[0022] In related technologies, the cavities of packaging substrates are typically formed using mechanical depth-controlled machining and laser ablation. When the bottom of the cavity has solder pads, this method requires the use of copper or other metals as a barrier layer to prevent over-etching by laser energy, which could lead to the solder pads being ablated and detached. If the barrier layer is omitted and ablation or sandblasting is performed directly, problems such as poor flatness of the groove bottom, poor depth accuracy, and easy detachment of the solder pads can easily occur. In addition, the entire cavity needs to be laser ablated or subjected to depth-controlled machining, resulting in low processing efficiency.
[0023] In view of this, the present disclosure provides a packaging substrate with a cavity and a method for manufacturing the same. By setting a second dielectric layer at the bottom of the sacrificial copper pillar, a separate metal barrier layer is not required when etching the sacrificial copper pillar to form a cavity. This not only greatly improves processing efficiency but also results in a cavity with high dimensional accuracy and good bottom flatness.
[0024] Figures 1(a) to 1(o) show cross-sectional schematic diagrams of the intermediate structures of each step in a method for fabricating a cavity-containing packaging substrate according to an embodiment of the present disclosure. As shown in Figures 1(a) to 1(o), the fabrication method includes: First, a support plate 100 is provided—step (a1), as shown in Figure 1(a).
[0025] Next, a first conductive copper pillar 202 is formed on the carrier plate 100—step (a2), as shown in Figure 1(a).
[0026] In some embodiments, step (a2) may include: A first seed layer 101 is formed on the carrier plate 100; here, the first seed layer 101 can be prepared by chemical plating or sputtering, and the first seed layer 101 may include titanium, copper, titanium-tungsten alloy or a combination thereof. For example, the first seed layer 101 is prepared by sputtering titanium and copper. A first photosensitive layer 201 is formed by attaching a film to the first seed layer 101, exposing it, and developing it. A first conductive copper pillar 202 is formed by electroplating on the first seed layer 101 exposed by the first photosensitive layer 201; Remove the first photosensitive layer 201.
[0027] It should be noted that when the carrier plate 100 has a first seed layer 101, the step of making the first seed layer 101 can be omitted.
[0028] Then, a first dielectric layer 203 is formed on the carrier plate 100; wherein the first dielectric layer 203 exposes the end face of the first conductive copper pillar 202—step (a3), as shown in FIG1(b).
[0029] In some embodiments, step (a3) may include: The first dielectric layer 203 is pressed together; and the first dielectric layer 203 is thinned to expose the end face of the first conductive copper pillar 202.
[0030] It should be noted that pretreatment may be included before laminating the first medium layer 203. Here, pretreatment may include cleaning the surface of the first seed layer, removing the oxide layer, increasing the surface roughness, etc.
[0031] For example, the first dielectric layer 203 is thinned overall by grinding, plasma etching or sandblasting to expose the end of the first conductive copper pillar 202.
[0032] Next, a first circuit layer 302 is formed on the first dielectric layer 203—step (a4), as shown in FIG1(c).
[0033] Here, the manufacturing method of the first circuit layer 302 is similar to that of the first conductive copper pillar 202, including the formation of the second seed layer 301, etc., which will not be described in detail here.
[0034] Then, a second conductive copper pillar 303 is formed on the first line layer 302—step (a5), as shown in Figure 1(d).
[0035] It should be noted that, considering that the second conductive copper pillar 303 is set on the first circuit layer 302, the difference between the method of forming the second conductive copper pillar 303 and the method of forming the first conductive copper pillar 202 is that the seed layer can be omitted.
[0036] Next, a second dielectric layer 304 is formed on the first dielectric layer 203, the first circuit layer 302, and the second conductive copper pillar 303; the second dielectric layer 304 exposes the end face of the second conductive copper pillar 303—step (a6), as shown in FIG1(e).
[0037] In some embodiments, step (a6) may include: etching the second seed layer 301 to remove the area of the second seed layer 301 not covered by the first circuit layer 302; then performing pretreatment and laminating the second dielectric layer 304; and finally thinning the second dielectric layer 304 to expose the end face of the second conductive copper pillar 303.
[0038] Then, a third conductive copper pillar 305 and a sacrificial copper pillar 306 are formed on the second dielectric layer 304; the third conductive copper pillar 305 is connected to the second conductive copper pillar 303—step (a7), as shown in Figure 1(f).
[0039] It should be noted that the method for forming the third conductive copper pillar 305 and the sacrificial copper pillar 306 is similar to the method for forming the first conductive copper pillar 202, and will not be described again.
[0040] Based on the panel design, a substrate including multiple packaging units, as shown in Figure 1(p), can be obtained. As shown in Figure 1(p), the multiple packaging units can be arranged along an intersecting first direction (e.g., x axial direction) and second direction (e.g.) y (Axial direction) array arrangement.
[0041] In some embodiments, the sacrificial copper pillars 306 corresponding to a plurality of packaging units arranged in a predetermined direction (e.g., a second direction) are connected to each other to form sacrificial copper strips, so as to facilitate the subsequent formation of interpenetrating cavities as shown in FIG1(p).
[0042] Next, a third dielectric layer 307 is formed on the second dielectric layer 304; the third dielectric layer 307 exposes the end faces of the third conductive copper pillar 305 and the sacrificial copper pillar 306—step (a8), as shown in FIG1 (g).
[0043] It should be noted that the method for forming the third dielectric layer 307 is similar to the method for forming the second dielectric layer 304, and will not be described in detail here.
[0044] Then, remove the support plate 100—step (a9), as shown in Figure 1(f).
[0045] As can be seen, the substrate includes a first circuit layer 302, sacrificial copper pillars 306, and a first dielectric layer 203, a second dielectric layer 304, and a third dielectric layer 307 stacked together; the first circuit layer 302 is located between the first dielectric layer 203 and the second dielectric layer 304; the sacrificial copper pillars 306 are disposed on the surface of the second dielectric layer 304 away from the first dielectric layer 203; and the third dielectric layer 307 exposes the end face of the sacrificial copper pillars 306.
[0046] It should be noted that the materials of the first dielectric layer 203, the second dielectric layer 304, and the third dielectric layer 307 can be the same or different.
[0047] For example, the materials of the first dielectric layer 203, the second dielectric layer 304, and the third dielectric layer 307 can each be independently a glass fiber-free resin material, such as selected from the group consisting of liquid crystal polymers, BT (bismaleimide triazine) resin, prepreg, ABF (Ajinomoto build-up) film, epoxy resin, and polyimide resin.
[0048] Next, an outer circuit layer 401 and a solder mask layer 402 are formed on the surfaces of the first dielectric layer 203 and the third dielectric layer 307—step (a10), as shown in FIG1(h) and FIG1(i).
[0049] Here, the manufacturing method of the outer circuit layer 401 is similar to that of the first conductive copper pillar 202, and will not be described in detail here.
[0050] It should be noted that the seed layer for forming the outer circuit layer 401 is etched away before the solder mask layer 402 is formed.
[0051] Then, a surface treatment layer 403 is formed on the outer circuit layer 401—step (a11), as shown in Figures 1(j) and 1(k).
[0052] Optionally, step (a11) may include: referring to FIG1(j), firstly applying a film to cover the sacrificial copper pillar 306; then forming a surface treatment layer 403; referring to FIG1(k), finally removing the film layer.
[0053] Thus, a substrate as shown in FIG1(k) is formed. The substrate includes an outer circuit layer 401, a solder mask layer 402 and a surface treatment layer 403; wherein, the outer circuit layer 401 and the solder mask layer 402 are located on the surfaces of the first dielectric layer 203 and the third dielectric layer 307; the surface treatment layer 403 is located on the surface of the outer circuit layer 401.
[0054] Here, the first conductive copper pillar 202 is conductively connected to the outer circuit layer 401 located on the surface of the first dielectric layer 203; the third conductive copper pillar 305 is conductively connected to the outer circuit layer located on the surface of the third dielectric layer 307.
[0055] Next, a film is applied to both sides of the substrate, and the end faces of the sacrificial copper pillars 306 are exposed by exposure and development, as shown in Figure 1(l). Here, the film can protect the outer circuit layer 401 and prevent it from being etched in step (b).
[0056] Then, the sacrificial copper pillars 306 are etched to form a cavity—step (b), as shown in Figure 1(m). Here, step (b) involves etching the sacrificial copper strips when the sacrificial copper pillars 306 are joined together to form a sacrificial copper strip.
[0057] Next, a blind via 308 is formed at the location corresponding to the cavity in the second dielectric layer 304; the blind via 308 exposes the bump pad of the first circuit layer 302—step (c), as shown in Figures 1(n), 1(p), and 1(q). Here, Figure 1(q) is an enlarged view of a single package unit in Figure 1(p). A cross-sectional view as shown in Figure 1(n) can be obtained by cutting the package unit along the C-C' wire in Figure 1(q).
[0058] As can be seen from Figure 1(p), along the predetermined direction (e.g.) y The cavities are arranged along the axial direction and their corresponding cavities are interconnected. With this structure, the cavities of adjacent packaging units are interconnected, which can solve the problems of "difficulty in removing flux residue (deflux) from independent closed cavities and difficulty in filling the cavity due to insufficient molding flow".
[0059] Alternatively, the blind hole 308 can be obtained using a laser drilling process.
[0060] It should be noted that the protective outer circuit layer 401 can be removed before step (b).
[0061] Finally, solder the pads and the bumps 404 of the component 405 located in the cavity—step (d), as shown in Figure 1 (o).
[0062] For example, component 405 may be an active component (e.g., transistor, IC chip, logic circuit element, power amplifier) or a passive component (capacitor, inductor, resistor) or a combination thereof.
[0063] In summary, the method for fabricating a packaged substrate with a cavity provided by the present disclosure does not require the design of a metal barrier layer. When etching the sacrificial copper pillar 306 to form the cavity, the second dielectric layer 304 located at the bottom of the sacrificial copper pillar 306 is used to protect the pads on the first circuit layer 302. This not only greatly improves the processing efficiency, but also results in a cavity with high dimensional and depth accuracy and good bottom flatness.
[0064] Based on the same inventive concept, corresponding to any of the above-described embodiments, this disclosure also provides a packaging substrate with a cavity. For example... Figure 2 As shown, the packaging substrate includes: a first circuit layer 302, a cavity, a component 405, and a first dielectric layer 203, a second dielectric layer 304, and a third dielectric layer 307 stacked together; the first circuit layer 302 is located between the first dielectric layer 203 and the second dielectric layer 304; the cavity is located on the surface of the second dielectric layer 304 away from the first dielectric layer 203 and penetrates the third dielectric layer 307; the component 405 is located in the cavity and is electrically connected to the pads located on the first circuit layer 302.
[0065] In some embodiments, as shown in FIG1(p), the packaging substrate includes a plurality of packaging units; some of the packaging units are arranged along a predetermined direction (e.g., y The cavities are arranged along the axial direction and their corresponding cavities are interconnected.
[0066] In some embodiments, the system further includes an outer circuit layer 401, a first conductive copper pillar 202, a second conductive copper pillar 303, and a third conductive copper pillar 305; wherein, the first conductive copper pillar 202 is located in the first dielectric layer 203 and connects the first circuit layer 302 and the outer circuit layer 401 located on the first dielectric layer 203; the second conductive copper pillar 303 is located in the second dielectric layer 304; the third conductive copper pillar 305 is located in the third dielectric layer 307; the second conductive copper pillar 303 and the third conductive copper pillar 305 are interconnected and connect the first circuit layer 302 and the outer circuit layer 401 located on the third dielectric layer 307.
[0067] The packaging substrates of the above embodiments are manufactured by the corresponding methods in any of the foregoing embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.
[0068] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.
[0069] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A method for manufacturing a packaging substrate with a cavity, characterized in that, include: (a) A substrate is provided; wherein the substrate includes a first circuit layer, sacrificial copper pillars, and a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked thereon; the first circuit layer is located between the first dielectric layer and the second dielectric layer; the sacrificial copper pillars are formed on the surface of the second dielectric layer away from the first dielectric layer; and the third dielectric layer exposes the end faces of the sacrificial copper pillars. (b) Etching the sacrificial copper pillar to form a cavity; (c) A blind via is formed in the second dielectric layer at a position corresponding to the cavity; the blind via exposes the pads of the first circuit layer; (d) Installing components in the cavity, wherein the terminal bumps of the components are soldered to the pads.
2. The manufacturing method according to claim 1, characterized in that, Step (a) includes: (a1) Provide a support plate; (a2) A first conductive copper pillar is formed on the bearing plate; (a3) A first dielectric layer is laminated on the carrier plate; wherein the first dielectric layer exposes the end face of the first conductive copper pillar; (a4) The first circuit layer is formed on the first dielectric layer; (a5) A second conductive copper pillar is formed on the first line layer; (a6) The second dielectric layer is laminated on the first dielectric layer, the first circuit layer and the second conductive copper pillar; the second dielectric layer exposes the end face of the second conductive copper pillar; (a7) A third conductive copper pillar and the sacrificial copper pillar are formed on the second dielectric layer; the third conductive copper pillar is connected to the second conductive copper pillar; (a8) A third dielectric layer is laminated on the second dielectric layer; the third dielectric layer exposes the end faces of the third conductive copper pillar and the sacrificial copper pillar; (a9) Remove the support plate.
3. The manufacturing method according to claim 2, characterized in that, Before step (b), the following are also included: A film is laminated on both sides of the substrate, and the end faces of the sacrificial copper pillars are exposed by exposure and development.
4. The manufacturing method according to claim 2, characterized in that, The substrate further includes an outer circuit layer, a solder mask layer, and a surface treatment layer; wherein the outer circuit layer and the solder mask layer are located on the surfaces of the first dielectric layer and the third dielectric layer; and the surface treatment layer is located on the surface of the outer circuit layer.
5. The manufacturing method according to claim 4, characterized in that, Step (a) also includes: (a10) The outer circuit layer and the solder mask layer are formed on the surfaces of the first dielectric layer and the third dielectric layer; (a11) The surface treatment layer is formed on the outer circuit layer.
6. The manufacturing method according to claim 1, characterized in that, The blind hole was obtained using a laser drilling process.
7. The manufacturing method according to claim 2, characterized in that, Step (a2) includes: A first seed layer is formed on the support plate; A first photosensitive layer is formed by attaching a film to the first seed layer, exposing it, and developing it. The first conductive copper pillar is formed by electroplating on the first seed layer exposed by the first photosensitive layer; Remove the first photosensitive layer.
8. The manufacturing method according to claim 2, characterized in that, Step (a3) includes: Press the first dielectric layer; Thinning the first dielectric layer exposes the end face of the first conductive copper pillar.
9. The manufacturing method according to claim 1, characterized in that, The substrate includes multiple packaging units; some of the packaging units are arranged along a predetermined direction and their respective sacrificial copper pillars are connected to each other to form sacrificial copper strips.
10. A packaging substrate having a cavity, characterized in that, include: The first circuit layer, cavity, components, and stacked first dielectric layer, second dielectric layer and third dielectric layer; The first circuit layer is located between the first dielectric layer and the second dielectric layer; the cavity is located on the surface of the second dielectric layer away from the first dielectric layer and penetrates the third dielectric layer; the component is installed in the cavity and the terminal bump of the component is soldered to the pad of the first circuit layer.
11. The packaging substrate according to claim 10, characterized in that, The packaging substrate includes multiple packaging units; some of the packaging units are arranged along a predetermined direction and their corresponding cavities penetrate each other.
12. The packaging substrate according to claim 10, characterized in that, It also includes an outer circuit layer, a first conductive copper pillar, a second conductive copper pillar, and a third conductive copper pillar; wherein, the first conductive copper pillar is located in the first dielectric layer and connects the first circuit layer and the outer circuit layer located on the first dielectric layer; the second conductive copper pillar is located in the second dielectric layer; the third conductive copper pillar is located in the third dielectric layer; the second conductive copper pillar and the third conductive copper pillar are connected to each other and connect the first circuit layer and the outer circuit layer located on the third dielectric layer.