Semiconductor package and stacked package including the same

Abstract

Embodiments of the disclosure provide a semiconductor package and a stacked package including the same, the semiconductor package including: a first interconnection layer; a sub package disposed on the first interconnection layer and including a second interconnection layer, a through-hole interconnection layer disposed on the second interconnection layer and having a through hole, a first semiconductor chip disposed within the through hole, a first encapsulant filling a portion of the through hole and covering a portion of the first semiconductor chip, and a third interconnection layer disposed on the first encapsulant; a second encapsulant covering a portion of the sub package; a second semiconductor chip disposed on the second encapsulant; a third encapsulant covering a portion of the second semiconductor chip; a fourth interconnection layer disposed on the third encapsulant; and a conductive pillar embedded in the third encapsulant and electrically connecting the sub package and the fourth interconnection layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor packages and stacked packages including the thereof. Background Technology

[0002] In the semiconductor industry, a stacked package structure in which an upper semiconductor package is stacked on a lower semiconductor package is known. The lower semiconductor package of the stacked package can be manufactured, for example, by: arranging a semiconductor chip on a front redistribution layer (FRDL); molding it with an encapsulant; and then forming a back redistribution layer (BRDL) electrically connected to the front redistribution layer on the encapsulant. Summary of the Invention

[0003] Embodiments of this disclosure provide semiconductor packages capable of improving product yield and productivity, and stacked packaging apparatuses including the same. Embodiments of this disclosure provide semiconductor packages configured to improve manufacturing yield and stacked packaging apparatus assemblies incorporating the packages.

[0004] Embodiments of this disclosure provide a semiconductor package capable of preventing or reducing defects in conductive pillars and a stacked package assembly including the thereof. Embodiments of this disclosure provide a semiconductor package configured to reduce the occurrence of defects in conductive pillars and a stacked package assembly incorporating the package.

[0005] Embodiments of this disclosure provide a semiconductor package comprising: a first interconnect layer; a sub-package disposed on the first interconnect layer and including a second interconnect layer, a via interconnect layer disposed on the second interconnect layer and having a through-hole, a first semiconductor chip disposed within the through-hole, a first encapsulant filling a portion of the through-hole and covering a portion of the first semiconductor chip, and a third interconnect layer disposed on the first encapsulant; a second encapsulant covering a portion of the sub-package; a second semiconductor chip disposed on the second encapsulant; a third encapsulant covering a portion of the second semiconductor chip; a fourth interconnect layer disposed on the third encapsulant; and conductive pillars embedded in the third encapsulant and electrically connecting the sub-package and the fourth interconnect layer.

[0006] Another embodiment of this disclosure provides a semiconductor package comprising: a first interconnect layer; a sub-package disposed on and electrically connected to the first interconnect layer, and including a second interconnect layer, an intermediate interconnect pattern disposed on and electrically connected to the second interconnect layer and having a through-hole, a first logic chip disposed within the through-hole and electrically connected to the second interconnect layer, a first encapsulant filling a portion of the through-hole and covering a portion of the first logic chip, and a third interconnect layer disposed on the first encapsulant and electrically connected to the intermediate interconnect pattern; a second encapsulant covering a portion of the sub-package; a second logic chip disposed on the second encapsulant and electrically connected to the third interconnect layer; a third encapsulant covering a portion of the second logic chip; a fourth interconnect layer disposed on the third encapsulant; and conductive pillars embedded in the third encapsulant and electrically connecting the third interconnect layer and the fourth interconnect layer.

[0007] Another embodiment of this disclosure provides a stacked package, the stacked package comprising: a first semiconductor package; and a second semiconductor package disposed on the first semiconductor package, wherein the first semiconductor package comprises: a first interconnect layer; a sub-package disposed on the first interconnect layer; a second encapsulant covering a portion of the sub-package; a second semiconductor chip disposed on the second encapsulant; a third encapsulant covering a portion of the second semiconductor chip; a fourth interconnect layer disposed on the third encapsulant; and a conductive post embedded in the third encapsulant and electrically connecting the sub-package and the fourth interconnect layer. The sub-package comprises: a second interconnect layer; an intermediate interconnect pattern disposed on the second interconnect layer and having a through-hole; a first semiconductor chip disposed within the through-hole; a first encapsulant filling a portion of the through-hole and covering a portion of the first semiconductor chip; and a third interconnect layer disposed on the first encapsulant.

[0008] Another embodiment of this disclosure provides a method for manufacturing a semiconductor package, the method comprising: manufacturing a sub-package; arranging the sub-package on a first redistribution structure; molding the sub-package with a first encapsulant; forming conductive pillars on the first encapsulant; arranging a first semiconductor chip on the first encapsulant; molding the conductive pillars and the first semiconductor chip with a second encapsulant; and forming a second redistribution structure on the second encapsulant, wherein manufacturing the sub-package includes: preparing a frame having through-holes; arranging a second semiconductor chip in the through-holes; molding the second semiconductor chip with a third encapsulant; forming a third redistribution structure on the second semiconductor chip and the frame; and forming a fourth redistribution structure on the third encapsulant.

[0009] According to embodiments of this disclosure, a semiconductor package and a stacked packaging apparatus including the thereof can be provided that can improve product yield and productivity.

[0010] According to embodiments of the present disclosure, a semiconductor package and a stacked package device including the present invention can be provided that can prevent or reduce defects in conductive pillars. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view of a semiconductor package according to an embodiment.

[0012] Figure 2 yes Figure 1 An enlarged cross-sectional view of the second semiconductor chip in the semiconductor package shown.

[0013] Figure 3 yes Figure 1 An enlarged cross-sectional view of the first semiconductor chip in the semiconductor package shown.

[0014] Figure 4 This is a cross-sectional view of a semiconductor package according to another embodiment.

[0015] Figure 5 This is a cross-sectional view of a semiconductor package according to another embodiment.

[0016] Figure 6 This is a cross-sectional view of a semiconductor package according to another embodiment.

[0017] Figure 7 This is a cross-sectional view of a semiconductor package according to another embodiment.

[0018] Figure 8 It includes Figure 1 The diagram shows a cross-sectional view of a stacked semiconductor package.

[0019] Figures 9 to 29 It shows the products used in manufacturing in sequence. Figure 1 A cross-sectional view of the method for the semiconductor package shown. Detailed Implementation

[0020] The present disclosure will now be described in detail with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the present disclosure and / or the invention.

[0021] The accompanying drawings and descriptions should be considered illustrative rather than restrictive in nature, and the same reference numerals refer to the same elements throughout the specification.

[0022] Furthermore, since the dimensions and thicknesses of the components shown in the accompanying drawings may be given arbitrarily for ease of understanding and description, this disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions may be exaggerated for ease of understanding and description.

[0023] It will be understood that when an element is referred to as being "connected" or "bonded" to another element or "on" another element, it may be directly connected or bonded to the other element or directly on the other element, or there may be an intermediate element present. In contrast, when an element is referred to as being "directly connected" or "directly bonded" to another element, or as being "in contact" with another element or "in contact" with another element (or using any form of the word "in contact"), there is no intermediate element at the point of contact.

[0024] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. In contrast, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, "on" a reference element means above or below the reference element, and does not necessarily mean being positioned "above" it in a direction opposite to gravity.

[0025] Furthermore, unless explicitly stated otherwise, the word "comprising" and variations such as "including" and "containing" should be understood to mean including the stated elements, but not excluding any other elements. Throughout the specification, when a component is described as "comprising" a particular element or group of elements, it should be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component, unless the context otherwise requires. On the other hand, the term "composed of" indicates that a component is formed solely by the listed elements.

[0026] Additionally, the phrase "in a top view" refers to viewing an object from above, while the phrase "in a cross section" (or "in a cross section view") refers to a vertical cross section of the target portion viewed from the side, unless the context otherwise indicates.

[0027] Furthermore, although the terms "first," "second," etc., are used throughout this specification to describe various components, these components are not limited to such terms, but are only used to distinguish one component from another. Therefore, a construction referred to as a first component in one part of this specification may also be referred to as a second component in other parts of this specification.

[0028] As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise. For example, "insulating layer" can be used to mean not only a single insulating layer (e.g., a single continuous layer formed entirely of the same substrate layer), but also a composite layer comprising multiple insulating layers (e.g., two, three, or more).

[0029] Items described in singular form in this document may be provided in plural form, as can be seen, for example, in the accompanying figures. Therefore, unless the context otherwise indicates, a description of a single item provided in plural form should be understood to apply to the remaining items.

[0030] Furthermore, throughout this specification, references to one surface and another are intended to distinguish different surfaces from one another and are not necessarily intended to limit them to a particular surface. Therefore, a side of a surface referred to in a particular section of this specification may be referred to as another surface in other sections of this specification.

[0031] In addition, throughout the specification, references to directions such as upper surface, upper side, upper part, lower surface, lower side, and lower part are intended to aid in the description and understanding with reference to the accompanying drawings.

[0032] Terms such as “coplanar,” “identical,” “equal,” “constant,” and “flat,” as used herein, are intended to encompass meanings including typical variations resulting from conventional manufacturing processes and / or tolerances acceptable in the manufacturing processes of semiconductor devices, unless the context or other statements indicate otherwise. For example, “identical” and “equal” can cover exactly the same or substantially the same. The term “substantially” may be used herein to emphasize this meaning.

[0033] In the following description, semiconductor packages and stacked packages according to embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0034] Figure 1 This is a cross-sectional view of a semiconductor package according to an embodiment.

[0035] Figure 2 yes Figure 1An enlarged cross-sectional view of the second semiconductor chip in the semiconductor package shown.

[0036] Figure 3 yes Figure 1 An enlarged cross-sectional view of the first semiconductor chip in the semiconductor package shown.

[0037] refer to Figure 1 According to an embodiment, the semiconductor package 10A includes a first redistribution structure 110, a sub-package 200 disposed on the first redistribution structure 110, a second encapsulant 120 covering at least a portion of the sub-package 200, a second semiconductor chip 130 disposed on the second encapsulant 120, a third encapsulant 140 covering at least a portion of the second semiconductor chip 130, a fourth redistribution structure 150 disposed on the third encapsulant 140, and a conductive post 160 embedded in the third encapsulant 140 and electrically connecting the sub-package 200 and the fourth redistribution structure 150. Furthermore, the sub-package 200 includes a second redistribution structure 210, a frame 220 having a through-hole 220h, a first semiconductor chip 230 disposed within the through-hole 220h, a first encapsulant 240 filling at least a portion of the through-hole 220h and covering at least a portion of the first semiconductor chip 230, and a third redistribution structure 250 disposed on the first encapsulant 240. For example, the conductive post 160 may be spaced apart from the first redistribution structure 110.

[0038] For example, throughout the specification, each redistribution structure (or interconnect layer) may be a composite layer including sublayers and / or patterns. For example, throughout the specification, frame 220 (or a via interconnect layer, intermediate interconnect pattern, or intermediate redistribution pattern) may be a composite layer (or composite pattern) including sublayers and / or patterns.

[0039] The first redistribution structure 110 may redistribute the subpackage 200 and the second semiconductor chip 130. For example, throughout the specification, the redistribution structure may be an interconnect layer, each interconnect layer rerouting electrical signals from / to the subpackage and / or the semiconductor chip to redistribute them to designated locations. The first redistribution structure 110 may include an insulating layer 111, a wiring layer 112, and a path 113. For example, the insulating layer 111 may include a first insulating layer 111A, a second insulating layer 111B, and a third insulating layer 111C. For example, the wiring layer 112 may include a first wiring layer 112A, a second wiring layer 112B, a third wiring layer 112C, and a fourth wiring layer 112D. For example, the path 113 may include a first path 113A, a second path 113B, and a third path 113C.

[0040] For example, the first redistribution structure 110 includes a first wiring layer 112A, a first insulating layer 111A covering the first wiring layer 112A, a second wiring layer 112B disposed on the first insulating layer 111A, a first passage 113A penetrating the first insulating layer 111A and electrically connecting the first wiring layer 112A and the second wiring layer 112B, a second insulating layer 111B disposed on the first insulating layer 111A and covering the second wiring layer 112B, a third wiring layer 112C disposed on the second insulating layer 111B, a second passage 113B penetrating the second insulating layer 111B and electrically connecting the second wiring layer 112B and the third wiring layer 112C, a third insulating layer 111C disposed on the second insulating layer 111B and covering the third wiring layer 112C, a fourth wiring layer 112D disposed on the third insulating layer 111C, and a third passage 113C penetrating the third insulating layer 111C and electrically connecting the third wiring layer 112C and the fourth wiring layer 112D. However, the number of layers in the first redistribution structure 110 may be fewer or more than the number shown in the figures. For example, the first redistribution structure 110 may include fewer or more wiring and / or insulation layers than those shown in the figures.

[0041] Insulating materials can be used as the material for insulating layer 111. For example, insulating layer 111 may include thermoplastic resins such as polyimide (PI), thermosetting resins such as epoxy resins, polybenzoxazole (PBO), or benzocyclobutene (BCB), or resins wherein these resins are mixed with inorganic fillers (e.g., Ajinomoto deposited film (ABF)). In some embodiments, insulating layer 111 may include a photoimageable dielectric (PID) capable of being patterned by a photolithography process. For example, insulating layer 111 may include photosensitive polyimide (PSPI). When insulating layer 111 includes a PID, fine pitch can be achieved by forming optical pathways. For example, when insulating layer 111 is formed from a PID, multiple pathways with fine pitch can be formed therein. When insulating layer 111 is multilayered, the material of each insulating layer 111 may be the same or different. For example, when insulating layer 111 includes multiple sublayers (e.g., first insulating layer 111A, second insulating layer 111B, and third insulating layer 111C), the individual sublayers may be formed from the same material or different materials. When the insulating layer 111 is multilayered, the insulating layers 111 may have boundaries with each other, may have indistinct boundaries, or may be integrated and have no boundaries. For example, when the insulating layer 111 comprises multiple sublayers, adjacent sublayers may have clearly defined boundaries, partially distinct (e.g., diffuse, gradient, or hybrid) boundaries, or no boundaries (e.g., integrated into a single continuum).

[0042] Each sublayer of wiring layer 112 (e.g., first wiring layer 112A, second wiring layer 112B, third wiring layer 112C, and fourth wiring layer 112D) may be disposed on a corresponding sublayer (or a corresponding pair of sublayers) of insulating layer 111. Wiring layer 112 may include wiring patterns (e.g., signal patterns, power patterns, ground patterns, etc.), path pads for connecting to path 113, connection pads for electrical connection to other components (e.g., connection pads may be included in the uppermost wiring layer 112D and / or the lowermost wiring layer 112A), etc. Conductive materials may be used as the material of wiring layer 112. For example, wiring layer 112 may include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these.

[0043] Each via 113 penetrates at least one insulating layer 111 and can physically and / or electrically connect wiring layers 112 disposed in different layers (or at different vertical heights). The via 113 can be of various shapes, such as a tapered shape whose width narrows from one side (e.g., top) to the other side (e.g., bottom), or a cylindrical shape. A conductive material can be used as the material for the via 113. For example, the via 113 can include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these. The via 113 can have an interior completely filled with conductive material, or the conductive material can be formed along the walls and bottom surface of the via. For example, the via 113 can be configured as a solid via where the via is substantially completely filled with conductive material. For example, the via 113 can be implemented as a partially filled via with conformal conductive pads on the sidewalls and bottom of the via. The via 113 can be integrally formed with the wiring layer 112 disposed on its upper side. For example, a via 113 and a corresponding one (or a corresponding pair) of wiring layers 112 can be formed of the same material without a boundary interface between them, and can form a single continuous body. For example, the via 113 and the wiring layer 112 can be formed by forming a through-hole penetrating the insulating layer 111 and filling the through-hole with a conductive material to fill the through-hole and extend over the insulating layer 111. The via 113 and the wiring layer 112 may include a first conductive layer serving as a seed layer and a second conductive layer disposed on the first conductive layer. The first conductive layer may extend along the surface of the insulating layer 111, the walls of the through-hole, and the bottom surface.

[0044] A first connection terminal CT1 for physically and / or electrically connecting the semiconductor package 10A to another component (e.g., a motherboard) may be disposed on the lower surface of the first redistribution structure 110. The first connection terminal CT1 may be provided (or configured as) a ball grid array, a planar grid array, or a pin grid array. A conductive material may be used as the material for the first connection terminal CT1. For example, the first connection terminal CT1 may be a solder ball comprising solder formed from Sn-Ag alloys, Sn-Ag-Cu alloys, etc. Alternatively, the first connection terminal CT1 may comprise metal or an alloy of metals. There are no particular limitations on the size, number, spacing, arrangement, etc., of the first connection terminal CT1.

[0045] The subpackage 200 may be disposed on and electrically connected to the first redistribution structure 110. The second semiconductor chip 130 and the conductive pillar 160 are disposed on the subpackage 200, and the width of the subpackage 200 may be wider than the width of the second semiconductor chip 130 in a horizontal direction parallel to the upper surface of the first redistribution structure 110.

[0046] The sub-package 200 may include a second redistribution structure 210, a frame 220 having a through-hole 220h, a first semiconductor chip 230 disposed within the through-hole 220h, a first encapsulant 240 filling at least a portion of the through-hole 220h and covering at least a portion of the first semiconductor chip 230, and a third redistribution structure 250 disposed on the first encapsulant 240. The sub-package 200 may be manufactured, for example, using a panel-level packaging (PLP) process. The sub-package 200 may be a fan-out package, and the second redistribution structure 210 and the third redistribution structure 250 may extend beyond the footprint of the first semiconductor chip 230 in a top view. For example, in a top view, the second redistribution structure 210 and the third redistribution structure 250 may extend horizontally beyond the first semiconductor chip 230.

[0047] The second redistribution structure 210 is electrically connected to the first semiconductor chip 230 and can rewire (or reroute electrical signals from / to the first connection pad 232 of the first semiconductor chip 230) the first connection pad 232 of the first semiconductor chip 230. The second redistribution structure 210 may have a similar or substantially the same construction as the first redistribution structure 110. For example, the second redistribution structure 210 may include an insulating layer 211, a wiring layer 212, and a via 213. For example, the second redistribution structure 210 may include a first insulating layer 211A, a first wiring layer 212A disposed on the lower surface of the first insulating layer 211A, a first passage 213A penetrating the first insulating layer 211A and electrically connecting the first wiring layer 212A and the frame 220, a second insulating layer 211B disposed on the first insulating layer 211A and covering the first wiring layer 212A, a second wiring layer 212B disposed on the lower surface of the second insulating layer 211B, and a second passage 213B penetrating the second insulating layer 211B and electrically connecting the second wiring layer 212B and the first wiring layer 212A. However, the number of layers in the second redistribution structure 210 may be less or more than the number of layers shown in the figures.

[0048] Insulating materials can be used as the material for insulating layer 211. For example, insulating layer 211 may include thermoplastic resins such as polyimide (PI), thermosetting resins such as epoxy resins, polybenzoxazole (PBO), or benzocyclobutene (BCB), or resins wherein these resins are mixed with inorganic fillers (e.g., Ajinomoto deposited film (ABF)). In some embodiments, insulating layer 211 may include a photoimageable dielectric (PID) capable of being patterned by a photolithography process. For example, insulating layer 211 may include photosensitive polyimide (PSPI). When insulating layer 211 includes a PID, fine detail can be achieved by forming optical paths. When insulating layer 211 is multilayered, the material of each insulating layer 211 may be the same or different. When insulating layer 211 is multilayered, insulating layers 211 may have boundaries with each other, may have indistinct boundaries, or may be integral and without boundaries.

[0049] Each wiring layer 212 may be disposed on a corresponding one (or a corresponding pair) of insulating layers 211. Wiring layer 212 may include wiring patterns (e.g., signal patterns, power patterns, ground patterns, etc.), path pads for connection to path 213, connection pads for electrical connection to other components (e.g., may be included in the bottommost second wiring layer 212B), etc. Conductive materials may be used as the material for wiring layer 212. For example, wiring layer 212 may include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these. The pitch of wiring layer 212 may be smaller than, but is not limited to, the pitch of wiring layers 222 and 252 of frame 220 and third redistribution structure 250.

[0050] Each via 213 penetrates at least one insulating layer 211 and can physically and / or electrically connect wiring layers 212 disposed in different layers (or at different vertical heights). Some vias 213 (e.g., the uppermost via 213A) can electrically connect wiring layers 212 to wiring layers 222 of frame 220. Vias 213 can be of various shapes, such as a tapered shape whose width narrows from one side to the other, or a cylindrical shape. Conductive materials can be used as the material for vias 213. For example, vias 213 can include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these. Vias 213 can be formed by completely filling the through-hole with conductive material, or by conformally forming conductive material along the walls and bottom surface of the through-hole. Vias 213 can be integrally formed with the wiring layer 212 disposed below it. For example, the via 213 and the wiring layer 212 can be formed by forming a through-hole penetrating the insulating layer 211 and filling the through-hole with a conductive material to fill the through-hole and extend over the insulating layer 211. The via 213 and the wiring layer 212 may include a first conductive layer serving as a seed layer and a second conductive layer disposed on the first conductive layer. The first conductive layer may extend along the surface of the insulating layer 211, the walls of the through-hole, and the bottom surface. The pitch of the wiring layer 212 may be smaller than the pitch of the vias 223 and 253 of the frame 220 and the third redistribution structure 250, but it is not limited thereto.

[0051] At least one of the passivation layer 214, the under-bump metal layer 215, and the second connection terminal CT2 may be additionally disposed on the lower surface of the second redistribution structure 210.

[0052] A passivation layer 214 is disposed on the lower surface of the second redistribution structure 210 and may have an opening that exposes at least a portion of the lowermost second wiring layer 212B, which serves as a connection pad. The passivation layer 214 may contact the lowermost second insulating layer 211B of the second redistribution structure 210. An insulating material may be used as the material for the passivation layer 214. For example, the passivation layer 214 may include at least one of the materials listed as materials for the insulating layer 211B of the second redistribution structure 210.

[0053] The under-bump metal layer 215 physically and / or electrically connects the second redistribution structure 210 and the second connection terminal CT2, and can prevent or reduce cracks in the second connection terminal CT2 and improve connection reliability. The under-bump metal layer 215 is disposed on the lower surface of the second redistribution structure 210 and can fill at least a portion of the opening of the passivation layer 214. The under-bump metal layer 215 may include under-bump pads disposed on the lower surface of the passivation layer 214 and under-bump pathways penetrating the passivation layer 214 to connect the under-bump pads to the lowermost second wiring layer 212B of the second redistribution structure 210. According to an embodiment, the under-bump pathway may be a plated pathway formed along the wall of the opening of the passivation layer 214 and the surface of the lowermost second wiring layer 212B, but it may also be a filled pathway filling the opening of the passivation layer 214. According to an embodiment, the under-bump pad may be an annular shape with an empty space in the center, but it may also be a circular plate shape with a filled space in the center. A conductive material may be used as the material for the under-bump metal layer 215. For example, the under-bump metal layer 215 may include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these.

[0054] A second connection terminal CT2 may be provided for electrical connection between the sub-package 200 and the first redistribution structure 110. For example, the second connection terminal CT2 may be provided between the under-bump metal layer 215 of the sub-package 200 and the uppermost wiring layer 112D of the first redistribution structure 110 to electrically connect them. A conductive material may be used as the material for the second connection terminal CT2. For example, the second connection terminal CT2 may include solder formed of Sn-Ag alloy, Sn-Ag-Cu alloy, etc. Alternatively, the second connection terminal CT2 may include metal or an alloy of metals. The second connection terminal CT2 may include a single layer (e.g., a single continuous layer formed entirely of the same substrate layer) or multiple layers. In some embodiments, the second connection terminal CT2 may be a C4 bump. In some embodiments, the second connection terminal CT2 may be a columnar bump including a conductive post and a conductive cap disposed on the conductive post. Metals such as copper (Cu) and aluminum (Al) may be used as materials for the conductive posts. Solder may be used as material for the conductive caps. There are no particular limitations on the size, number, spacing, arrangement, etc., of the second connection terminals CT2.

[0055] Frame 220 may be disposed on and electrically connected to the second redistribution structure 210. Frame 220 may be in contact with the second redistribution structure 210. For example, frame 220 may be directly disposed on the uppermost first insulating layer 211A of the second redistribution structure 210 and may be electrically connected to the uppermost first wiring layer 212A through the uppermost passage 213A of the second redistribution structure 210. Frame 220 may include a wiring layer 222, which may increase the freedom of wiring design for the sub-package 200. In addition, frame 220 includes a thick and rigid insulating layer 221, which may increase the rigidity of the sub-package 200. The thickness of frame 220 may be equal to or approximately equal to the thickness of the first semiconductor chip 230. For example, frame 220 may have a thickness greater than that of the second redistribution structure 210 (in the vertical direction).

[0056] The frame 220 may have a through-hole 220h penetrating the frame 220 in the thickness direction (vertical direction). In a top view, the through-hole 220h may have an approximately (or substantially) square shape. The first semiconductor chip 230 may be spaced apart from the wall of the through-hole 220h, and the frame 220 may surround the first semiconductor chip 230. The width of the through-hole 220h may be wider in the horizontal direction than the width of the first semiconductor chip 230. The width of the through-hole 220h may be constant in the thickness direction, or it may narrow from one side to the other. There are no particular limitations on the method of forming the through-hole 220h, and it may be formed by laser processing, mechanical processing, etc.

[0057] Frame 220 may have a similar construction to the second redistribution structure 210 (or the first redistribution structure 110). For example, frame 220 may include an insulating layer 221, a wiring layer 222, and a passage 223. For example, frame 220 may include a first wiring layer 222A, a first insulating layer 221A covering the first wiring layer 222A, a second wiring layer 222B disposed on the first insulating layer 221A, a first passage 223A penetrating the first insulating layer 221A and electrically connecting the first wiring layer 222A and the second wiring layer 222B, a second insulating layer 221B disposed on the first insulating layer 221A and covering the second wiring layer 222B, a third wiring layer 222C disposed on the second insulating layer 221B, and a second passage 223B penetrating the second insulating layer 221B and electrically connecting the second wiring layer 222B and the third wiring layer 222C. However, the number of layers in frame 220 may be fewer or more than the number shown in the figures. The frame 220 may be an embedded trace substrate (ETS) in which the first wiring layer 222A is embedded in the first insulating layer 221A.

[0058] Insulating materials can be used as the material for insulating layer 221. For example, insulating layer 221 may include thermoplastic resins such as polyimide (PI), thermosetting resins such as epoxy resins, resins in which these resins are mixed with inorganic fillers, or resins impregnated into glass fibers together with inorganic fillers (e.g., prepregs, FR-4, bismaleimide triazine (BT), etc.). When insulating layer 221 is multilayered, the material of each insulating layer 221 may be the same or different. When insulating layer 221 is multilayered, insulating layers 221 may have boundaries with each other, may have indistinct boundaries, or may be integral and without boundaries. Each insulating layer 221 may be thicker than insulating layers 111, 211, 251, and 151 of redistribution structures 110, 210, 250, and 150, but is not limited thereto.

[0059] Each wiring layer 222 may be disposed on each insulating layer 221. However, among the wiring layers 222, the lowermost first wiring layer 222A may be covered by the lowermost first insulating layer 221A. For example, the lowermost first insulating layer 221A may cover the upper and side surfaces of the lowermost first wiring layer 222A, and the lower surface of the lowermost first wiring layer 222A may be exposed at the lower surface of the lowermost first insulating layer 221A (or may be exposed beyond the lower surface of the lowermost first insulating layer 221A, or may terminate flush with the lower surface of the lowermost first insulating layer 221A). The lower surface of the lowermost first wiring layer 222A may be coplanar with the lower surface of the lowermost first insulating layer 221A. The wiring layer 222 may include wiring patterns (e.g., signal patterns, power patterns, ground patterns, etc.), path pads for connecting to the path 223, connection pads for electrical connection with other components, etc. Conductive materials may be used as the material of the wiring layer 222. For example, wiring layer 222 may include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these.

[0060] Each via 223 penetrates at least one insulating layer 221 and can physically and / or electrically connect wiring layers 222 disposed in different layers (or at different vertical heights). The via 223 can have various shapes, such as a tapered shape, cylindrical shape, or hourglass shape with a width narrowing from one side to the other. A conductive material can be used as the material for the via 223. For example, the via 223 can include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these. The via 223 can be formed by completely filling the via with conductive material, or by conformally forming conductive material along the walls and bottom surface of the via. The via 223 can be integrally formed with the wiring layer 222 disposed above it. For example, the via 223 and the wiring layer 222 can be formed by forming a through-hole penetrating the insulating layer 221 and filling the through-hole with a conductive material to fill the through-hole and extend over the insulating layer 221. The via 223 and the wiring layer 222 may include a first conductive layer serving as a seed layer and a second conductive layer disposed on the first conductive layer. The first conductive layer may extend along the surface of the insulating layer 221, the walls of the through-hole, and the bottom surface.

[0061] The first semiconductor chip 230 can be disposed within the through-hole 220h and electrically connected to the second redistribution structure 210. The first semiconductor chip 230 can be in contact with the second redistribution structure 210. For example, the first semiconductor chip 230 can be directly disposed on the uppermost first insulating layer 211A of the second redistribution structure 210, and can be electrically connected to the uppermost first wiring layer 212A through the uppermost passage 213A of the second redistribution structure 210.

[0062] The first semiconductor chip 230 may include a semiconductor substrate 231, individual (or unit) elements 233 formed on the surface of the semiconductor substrate 231 (or formed together with the semiconductor substrate 231), a wiring structure 234 disposed on the semiconductor substrate 231 and electrically connected to the individual elements 233, and a first connection pad 232 disposed on the wiring structure 234 and electrically connected to the wiring structure 234. The semiconductor substrate 231 may include semiconductor materials. For example, the semiconductor substrate 231 may include semiconductor elements such as silicon (Si) or germanium (Ge), or compound semiconductors such as gallium arsenide (GaAs), indium arsenide (InAs), or silicon carbide (SiC). The semiconductor substrate 231 may have an approximately quadrilateral shape, such as a square or rectangle, but is not limited thereto. The individual elements 233 may include at least one of, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a fin field-effect transistor (FinFET), a gate-all-around (GAA) transistor, a diode, a capacitor, and a resistor. Wiring structure 234 may include an insulating layer 2341, a wiring layer 2342, and a via 2343. Insulating layer 2341 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon carbonitride (SiCN), and / or an organic insulating material such as polyimide (PI), polybenzoxazole (PBO), or benzocyclobutene (BCB). Although wiring layer 2342 is shown in the figures as including only the first layer M1, wiring layer 2342 may include a greater number of layers. Wiring layer 2342 and via 2343 may include conductive materials such as copper (Cu) or aluminum (Al). First connection pad 232 can electrically connect the first semiconductor chip 230 to the second redistribution structure 210. A conductive material may be used as the material for the first connection pad 232. For example, the first connection pad 232 may include a metal such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or an alloy of two or more of these. The surface of the first semiconductor chip 230 on which the first connection pad 232 is disposed may be referred to as an active surface, while the surface opposite (or back-to-back with) the active surface may be referred to as a passive surface. The first semiconductor chip 230 may be configured with its surface facing down, such that the active surface faces the second redistribution structure 210. However, the first semiconductor chip 230 may be configured with its surface facing up, such that the active surface faces the third redistribution structure 250, and in this embodiment, the first connection pad 232 may be electrically connected to a path 253 of the third redistribution structure 250.

[0063] The first semiconductor chip 230 may include / or a logic chip. The logic chip may include logic circuits and may include / or at least one of the following: application processor (AP), microprocessor, central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), application-specific integrated circuit (ASIC), system-on-a-chip (SoC), physical layer (PHY), modem, power management integrated circuit (PMIC), and display driver IC (DDI).

[0064] The first encapsulant 240 may fill at least a portion of the through-hole 220h and cover at least a portion of the first semiconductor chip 230. For example, the first encapsulant 240 may fill at least a portion of the space between the wall of the through-hole 220h and the side surface of the first semiconductor chip 230, and cover the upper surface and side surface of the first semiconductor chip 230. Additionally, the first encapsulant 240 may extend to the upper surface of the frame 220. An insulating material may be used as the material of the first encapsulant 240. For example, the first encapsulant 240 may include an epoxy molding compound (EMC). Alternatively, the first encapsulant 240 may include a thermoplastic resin such as polyimide (PI), a thermosetting resin such as epoxy resin, or a resin wherein such resins are mixed with an inorganic filler such as SiO2 (e.g., Ajinomoto deposited film (ABF)). Alternatively, the first encapsulant 240 may include a photoimageable dielectric (PID), such as photosensitive polyimide (PSPI).

[0065] The third redistribution structure 250 may be disposed on the first encapsulant 240 and electrically connected to the frame 220. Some regions (e.g., the lower region) or portions of the passage 253 of the third redistribution structure 250 may extend into the first encapsulant 240 covering the upper surface of the frame 220.

[0066] The third redistribution structure 250 may have a similar or substantially identical construction to the first redistribution structure 110 and the second redistribution structure 210. For example, the third redistribution structure 250 may include an insulating layer 251, a wiring layer 252, and a via 253. In some embodiments, the third redistribution structure 250 may be formed as a single layer (e.g., a single continuous layer formed entirely of the same substrate layer) and may include an insulating layer 251 disposed on the first encapsulant 240, a wiring layer 252 disposed on the insulating layer 251, and a via 253 penetrating the insulating layer 251 and extending into the first encapsulant 240 to electrically connect the wiring layer 252 and the frame 220. By introducing (or utilizing) the insulating layer 251 on the first encapsulant 240, the quality of surface planarization processes and other processes can be improved, and the bonding strength with the third connection terminal CT3 can be improved by increasing the planar dimensions of the wiring layer 252, which serves as the via 253 and the connecting pad. Wiring layer 252 can be formed directly on first encapsulant 240, and in this embodiment, third redistribution structure 250 may not include insulating layer 251, and via 253 may be embedded in first encapsulant 240.

[0067] Insulating materials can be used as the material for insulating layer 251. For example, insulating layer 251 may include thermoplastic resins such as polyimide (PI), thermosetting resins such as epoxy resins, polybenzoxazole (PBO) or benzocyclobutene (BCB), or resins wherein these resins are mixed with inorganic fillers (e.g., Ajinomoto deposited film (ABF)). In some embodiments, insulating layer 251 may include a photoimageable dielectric (PID) that can be patterned by a photolithography process.

[0068] Wiring layer 252 is disposed on insulating layer 251 and may be exposed at (or may be exposed beyond, or may terminate flush with, the upper surface of second encapsulant 120) the upper surface of wiring layer 252 and the upper surface of second encapsulant 120. Wiring layer 252 may include wiring patterns (e.g., signal patterns, power patterns, ground patterns, etc.), path pads for connecting to path 253, connection pads for electrical connection to other components, etc. Conductive materials may be used as the material for wiring layer 252. For example, wiring layer 252 may include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these.

[0069] The via 253 penetrates the insulating layer 251 and extends into the first encapsulant 240, and can physically and / or electrically connect the wiring layer 252 to the uppermost third wiring layer 222C of the frame 220. The via 253 can have various shapes, such as a tapered shape with a width narrowing from one side to the other, or a cylindrical shape. A conductive material can be used as the material for the via 253. For example, the via 253 can include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these. The via 253 can be formed by completely filling the through-hole with a conductive material, or by conformally forming a conductive material along the walls and bottom surface of the through-hole. The via 253 can be integrally formed with the wiring layer 252. For example, the via 253 and the wiring layer 252 can be formed by forming a through-hole that penetrates the insulating layer 251 and extends into the first encapsulant 240, and filling the through-hole with a conductive material to fill the through-hole and extend over the insulating layer 251. The via 253 and the wiring layer 252 may include a first conductive layer serving as a seed layer and a second conductive layer disposed on the first conductive layer. The first conductive layer may extend along the surface of the insulating layer 251, the walls of the through-hole, and the bottom surface.

[0070] The second encapsulant 120 may cover at least a portion of the sub-package 200. For example, the second encapsulant 120 may cover the side surface of the sub-package 200 and extend onto the insulating layer 251 of the third redistribution structure 250 to cover the upper surface of the insulating layer 251 and the side surface of the wiring layer 252. The components disposed on the side surface of the sub-package 200 and covered by the second encapsulant 120 may be the frame 220, the second redistribution structure 210, and the third redistribution structure 250. Additionally, the second encapsulant 120 may fill at least a portion of the space between the sub-package 200 and the first redistribution structure 110. An insulating material may be used as the material for the second encapsulant 120. For example, the second encapsulant 120 may include an epoxy molding compound (EMC). Alternatively, the second encapsulant 120 may include a thermoplastic resin such as polyimide (PI), a thermosetting resin such as epoxy resin, or a resin wherein such resins are mixed with an inorganic filler such as SiO2 (e.g., Ajinomoto laminate (ABF)). Alternatively, the second encapsulant 120 may include a photoimageable dielectric (PID), such as a photosensitive polyimide (PSPI).

[0071] A second semiconductor chip 130 is disposed on the second encapsulant 120 and may be electrically connected to the third redistribution structure 250 of the subpackage 200. For example, the second semiconductor chip 130 may be electrically connected to a wiring layer 252, which is exposed at the upper surface of the second encapsulant 120 (or may be exposed beyond the upper surface of the second encapsulant 120, or may terminate flush with the upper surface of the second encapsulant 120). In some embodiments, the upper surface of the second semiconductor chip 130 may be exposed at the upper surface of the third encapsulant 140. The upper surface of the second semiconductor chip 130 may be coplanar with the upper surface of the third encapsulant 140. The upper surface of the second semiconductor chip 130 exposed at the upper surface of the third encapsulant 140 may contact the fourth redistribution structure 150. For example, the second semiconductor chip 130 may contact the lowermost first insulating layer 151A of the fourth redistribution structure 150. However, the upper surface of the second semiconductor chip 130 may be covered by the third encapsulant 140.

[0072] The second semiconductor chip 130 may include a semiconductor substrate 131, individual (or unit) elements 133 formed on the surface of the semiconductor substrate 131 (or formed together with the semiconductor substrate 131), a wiring structure 134 disposed on the semiconductor substrate 131 and electrically connected to the individual elements 133, and connection pads 132 disposed on the wiring structure 134 and electrically connected to the wiring structure 134. The semiconductor substrate 131 may include semiconductor materials. For example, the semiconductor substrate 131 may include semiconductor elements such as silicon (Si) or germanium (Ge), or compound semiconductors such as gallium arsenide (GaAs), indium arsenide (InAs), or silicon carbide (SiC). The semiconductor substrate 131 may have an approximately quadrilateral shape, such as a square or rectangular shape, but is not limited thereto. The individual elements 133 may include, for example, at least one of a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a fin field-effect transistor (FinFET), a gate-all-around (GAA) transistor, a diode, a capacitor, and a resistor. Wiring structure 134 may include an insulating layer 1341, a wiring layer 1342, and a via 1343. Insulating layer 1341 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon carbonitride (SiCN), and / or an organic insulating material such as polyimide (PI), polybenzoxazole (PBO), or benzocyclobutene (BCB). Although wiring layer 1342 is shown in the figures as including only the first layer M1, the second layer M2, and the third layer M3, wiring layer 1342 may include a greater number of layers. Wiring layer 1342 and via 1343 may include conductive materials such as copper (Cu) or aluminum (Al). Connection pads 132 can electrically connect the second semiconductor chip 130 to the third redistribution structure 250. Conductive materials may be used as the material for connection pads 132. For example, the connection pads 132 may include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these. The surface of the second semiconductor chip 130 on which the connection pads 132 are disposed may be referred to as an active surface, while the surface opposite (or back-to-back with) the active surface may be referred to as a passive surface. The second semiconductor chip 130 may be disposed in a face-down configuration such that the active surface faces the third redistribution structure 250.

[0073] The second semiconductor chip 130 may include / or a logic chip. The logic chip may include logic circuits and may include / or at least one of the following: application processor (AP), microprocessor, central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), application-specific integrated circuit (ASIC), system-on-a-chip (SoC), physical layer (PHY), modem, power management integrated circuit (PMIC), and display driver IC (DDI).

[0074] In some embodiments, to improve product yield and / or reduce manufacturing costs, the second semiconductor chip 130 may be fabricated at a leading-edge process node (e.g., a single-digit nanometer node), while the first semiconductor chip 230 may be fabricated at a non-leading-edge node. For example, the process node of the second semiconductor chip 130 may be smaller than that of the first semiconductor chip 230. For example, the second semiconductor chip 130 may include (or) a CPU and / or a GPU, while the first semiconductor chip 230 may include (or) a PHY and / or a modem.

[0075] The size of individual elements 133 of the second semiconductor chip 130 manufactured on a leading-edge process node can be smaller than the size of individual elements 233 of the first semiconductor chip 230. Furthermore, the pitch of the individual elements 133 of the second semiconductor chip 130 can be narrower (or smaller) than the pitch of the individual elements 233 of the first semiconductor chip 230. Here, the pitch of an individual element refers to the center-to-center distance between the centers of adjacent individual elements. Additionally, the integration density of the individual elements 133 of the second semiconductor chip 130 can be higher than the integration density of the individual elements 233 of the first semiconductor chip 230.

[0076] The minimum wiring pitch (or minimum feature size) of the wiring structure 134 of the second semiconductor chip 130 can be smaller than the minimum wiring pitch (or minimum feature size) of the wiring structure 234 of the first semiconductor chip 230. For example, the wiring pitch p1 of the second semiconductor chip 130 can be narrower than the wiring pitch p2 of the first semiconductor chip 230. Here, wiring pitch refers to the distance between the centers of adjacent wiring patterns in each wiring layer. As a representation of the difference between leading-edge nodes and non-leading-edge nodes, the wiring pitch p1 of the second semiconductor chip 130 and the wiring pitch p2 of the first semiconductor chip 230 can be compared using the minimum pitch (e.g., the distance between the centers of the most densely arranged wiring patterns). For example, the minimum wiring pitch can be the distance between the centers of the most densely arranged wiring patterns. As a representation of the difference between leading-edge nodes and non-leading-edge nodes, the wiring pitches (or minimum wiring pitches) p1 and p2 of the second semiconductor chip 130 and the first semiconductor chip 230 can be compared. The first layer M1 with wiring pitch p1 can be the wiring layer in the second semiconductor chip 130 that is closest to the individual element 133, while the first layer M1 with wiring pitch p2 can be the wiring layer in the first semiconductor chip 230 that is closest to the individual element 233. For example, in the figures, wiring pitches p1 and p2 are shown based on the first layer M1 of the wiring layers M1, M2, and M3 of the first semiconductor chip 230 and the second semiconductor chip 130 that are closest to the individual elements 133 and 233. In addition, the number of wiring layers 1342 of the second semiconductor chip 130 can be greater than the number of wiring layers 2342 of the first semiconductor chip 230. In this configuration, the minimum wiring pitch p1 of the first layer M1 of the second semiconductor chip 130 (closest to the individual element 133) can be smaller than the minimum wiring pitch p2 of the first layer M1 of the first semiconductor chip 230 (closest to the individual element 233).

[0077] The width w1 (in the horizontal direction) of the second semiconductor chip 130 can be wider than the width w2 (in the horizontal direction) of the first semiconductor chip 230. The second semiconductor chip 130 has superior performance and various functions, and can be larger than the first semiconductor chip 230 in a top view. The thickness t1 of the second semiconductor chip 130 can be thicker than the thickness t2 of the first semiconductor chip 230. The second semiconductor chip 130 can be a heat-generating chip, and its heat dissipation characteristics can be improved by thickening the second semiconductor chip 130.

[0078] The second semiconductor chip 130 can be physically and / or electrically connected to the third redistribution structure 250 of the subpackage 200 via a third connection terminal CT3. The third connection terminal CT3 can be disposed, for example, between the connection pad 132 of the second semiconductor chip 130 and the wiring layer 252 of the third redistribution structure 250 to electrically connect them. A conductive material can be used as the material for the third connection terminal CT3. For example, the third connection terminal CT3 can include solder formed of Sn-Ag alloys, Sn-Ag-Cu alloys, etc. Alternatively, the third connection terminal CT3 can include metal or an alloy of metals. The third connection terminal CT3 can include a single layer (e.g., a single continuous layer formed entirely of the same substrate layer) or multiple layers. In some embodiments, the third connection terminal CT3 can be a C4 bump. In some embodiments, the third connection terminal CT3 can be a columnar bump including a conductive post and a conductive cap disposed on the conductive post. Metals such as copper (Cu) and aluminum (Al) can be used as materials for the conductive posts. Solder can be used as the material for the conductive caps. There are no particular limitations on the size, number, spacing, arrangement, etc., of the third connection terminals CT3.

[0079] The third connection terminal CT3 may be covered by an underfill material UF, which fills at least a portion of the space between the second encapsulant 120 and the second semiconductor chip 130. The underfill material UF may extend to the lower surface of the second semiconductor chip 130. The underfill material UF may include an insulating material such as epoxy resin, and may also include inorganic fillers such as silicon dioxide or alumina if desired.

[0080] The third encapsulant 140 may cover at least a portion of each of the second semiconductor chip 130 and the conductive pillar 160. For example, the third encapsulant 140 may cover each side surface of the second semiconductor chip 130 and the conductive pillar 160. An insulating material may be used as the material for the third encapsulant 140. For example, the third encapsulant 140 may include an epoxy molding compound (EMC). Alternatively, the third encapsulant 140 may include a thermoplastic resin such as polyimide (PI), a thermosetting resin such as epoxy resin, or a resin wherein such resins are mixed with an inorganic filler such as SiO2 (e.g., Ajinomoto film (ABF)). Alternatively, the third encapsulant 140 may include a photoimageable dielectric (PID), such as photosensitive polyimide (PSPI).

[0081] A fourth redistribution structure 150 is disposed on the third encapsulant 140 and can be electrically connected to the third redistribution structure 250 of the sub-package 200 via conductive posts 160. The fourth redistribution structure 150 may have a similar or substantially identical construction to the first redistribution structure 110, the second redistribution structure 210, and the third redistribution structure 250. For example, the fourth redistribution structure 150 may include an insulating layer 151, a wiring layer 152, and a via 153. For example, the fourth redistribution structure 150 includes a first insulating layer 151A disposed on the third encapsulant 140, a first wiring layer 152A disposed on the first insulating layer 151A, a first passage 153A penetrating the first insulating layer 151A and electrically connecting the first wiring layer 152A and the conductive post 160, a second insulating layer 151B disposed on the first insulating layer 151A and covering the first wiring layer 152A, a second wiring layer 152B disposed on the second insulating layer 151B, a second passage 153B penetrating the second insulating layer 151B and electrically connecting the first wiring layer 152A and the second wiring layer 152B, a third insulating layer 151C disposed on the second insulating layer 151B and covering the second wiring layer 152B, a third wiring layer 152C disposed on the third insulating layer 151C, and a third passage 153C penetrating the third wiring layer 152C and the third insulating layer 151C and electrically connecting the second wiring layer 152B and the third wiring layer 152C. However, the fourth redistribution structure 150 may have fewer or more layers than those shown in the figures.

[0082] Insulating materials can be used as the material for insulating layer 151. For example, insulating layer 151 may include thermoplastic resins such as polyimide (PI), thermosetting resins such as epoxy resins, polybenzoxazole (PBO), or benzocyclobutene (BCB), or resins wherein these resins are mixed with inorganic fillers (e.g., Ajinomoto deposited film (ABF)). In some embodiments, insulating layer 151 may include a photoimageable dielectric (PID) capable of being patterned by a photolithography process. For example, insulating layer 151 may include photosensitive polyimide (PSPI). When insulating layer 151 includes a PID, fine detail can be achieved by forming optical paths. When insulating layer 151 is multilayered, the material of each insulating layer 151 may be the same or different. When insulating layer 151 is multilayered, insulating layers 151 may have boundaries with each other, may have indistinct boundaries, or may be integral and without boundaries.

[0083] Each wiring layer 152 may be disposed on a corresponding one (or a corresponding pair) of insulating layers 151. Wiring layer 152 may include wiring patterns (e.g., signal patterns, power patterns, ground patterns, etc.), path pads for connecting to path 153, connection pads for electrical connection to other components (e.g., which may be included in the uppermost third wiring layer 152C), etc. Conductive materials may be used as the material for wiring layer 152. For example, wiring layer 152 may include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these.

[0084] Each via 153 penetrates at least one insulating layer 151 and can physically and / or electrically connect wiring layers 152 disposed in different layers. Some vias 153 (e.g., the lowermost first via 153A) can electrically connect the wiring layer 152 to the conductive post 160. The vias 153 can have various shapes, such as a tapered shape whose width narrows from one side to the other, or a cylindrical shape. Conductive materials can be used as the material of the vias 153. For example, the vias 153 can include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these metals. The vias 153 can be formed by completely filling the through-hole with conductive material, or by conformally forming conductive material along the walls and bottom surface of the through-hole. The vias 153 can be integrally formed with the wiring layer 152 disposed above them. For example, the via 153 and the wiring layer 152 can be formed by forming a through-hole penetrating the insulating layer 151 and filling the through-hole with a conductive material to fill the through-hole and extend over the insulating layer 151. The via 153 and the wiring layer 152 may include a first conductive layer serving as a seed layer and a second conductive layer disposed on the first conductive layer. The first conductive layer may extend along the surface of the insulating layer 151, the walls of the through-hole, and the bottom surface.

[0085] Conductive post 160 may be embedded in third encapsulant 140 and electrically connect third redistribution structure 250 and fourth redistribution structure 150. Conductive post 160 may contact third redistribution structure 250 and fourth redistribution structure 150. Upper surface of conductive post 160 may be exposed at (or may be exposed beyond) upper surface of third encapsulant 140, or may terminate flush with upper surface of third encapsulant 140. Upper surface of conductive post 160 may be coplanar with upper surface of third encapsulant 140. In some embodiments, conductive post 160 may physically and / or electrically connect wiring layer 252 of third redistribution structure 250 to lowermost passage 153A of fourth redistribution structure 150. In some embodiments, the conductive posts 160 can physically and / or electrically connect the wiring layer 252 of the third redistribution structure 250 to a wiring layer (not shown) disposed on the third encapsulant 140 and embedded in the lowermost first insulating layer 151A of the fourth redistribution structure 150. Conductive materials can be used as the material for the conductive posts 160. For example, the conductive posts 160 may include metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these. The conductive posts 160 may include a first conductive layer serving as a seed layer and a second conductive layer disposed on the first conductive layer. The conductive posts 160 may be arranged to surround the second semiconductor chip 130, but are not limited thereto. The number, spacing, etc., of the conductive posts 160 are not particularly limited.

[0086] The aspect ratio of the conductive pillar 160 can be 10 or less. For example, the aspect ratio of the conductive pillar 160 can be less than 10, less than or equal to 9, less than or equal to 8, less than or equal to 7, less than or equal to 6, less than or equal to 5, or less than 5. For example, the aspect ratio of the conductive pillar can be the vertical height of the pillar (from the bottom surface to the top surface) divided by the horizontal dimension measured at a reference plane (e.g., at a medium height). For example, the horizontal dimension can be the minimum width (or equivalent diameter). In this disclosure, by forming the conductive pillar 160 on the second redistribution structure 210, this disclosure can provide conductive pillars 160 with a low aspect ratio of 10 or less. Therefore, defects that may occur when forming conductive pillars with a high aspect ratio (e.g., defects due to photoresist residue, accidental electrical disconnection due to reduced height consistency of the conductive pillar (e.g., open circuit defects of the conductive pillar), misalignment of the pillar (e.g., path alignment defects), etc.) can be prevented or reduced. It can also prevent or reduce the process steps required to form two-stage conductive pillars (e.g., a combination of a first pillar and a second pillar stacked on the first pillar) as well as other defects (e.g., bubbles, cracks, swelling defects, etc. in the photoresist pattern).

[0087] Semiconductor package 10A (manufactured by packaging a sub-package 200 including a first semiconductor chip 230 and a second semiconductor chip 130 together) can be manufactured using a wafer-level packaging (WLP) process. After being separated into individual semiconductor packages, each side surface of the first redistribution structure 110, the second encapsulant 120, the third encapsulant 140, and the fourth redistribution structure 150 of semiconductor package 10A can be coplanar. For example, the first redistribution structure 110, the second encapsulant 120, the third encapsulant 140, and the fourth redistribution structure 150 are unified in a single operation. Therefore, the sidewalls of the first redistribution structure 110, the second encapsulant 120, the third encapsulant 140, and the fourth redistribution structure 150 can be flush with each other and terminate on substantially the same cutting plane. In the top view, the sidewalls of the first redistribution structure 110, the second encapsulant 120, the third encapsulant 140, and the fourth redistribution structure 150 can be separated from the frame by the second encapsulant 120 at a horizontal distance HD.

[0088] Compared to the disclosed embodiments, when implementing a logic chip as a single chip, there is a potential reduction in product productivity and yield due to differences in process nodes and pitches for each logic unit. Furthermore, when connecting the lower and upper redistribution structures of a semiconductor package with conductive pillars, conductive pillars with high aspect ratios (e.g., greater than 10) are typically required because the diameter and pitch of the conductive pillars decrease as the number of input / output (I / O) terminals increases. For conductive pillars with high aspect ratios, defects may occur due to photoresist residues, open-circuit defects due to reduced height consistency, and path alignment defects. When forming two-stage conductive pillars as an alternative to conductive pillars with high aspect ratios, not only are additional processes required, but defects such as bubbles, cracks, and swelling of the second photoresist may also occur.

[0089] According to this disclosure, by forming the second semiconductor chip 130 of the front-end node separately or independently from the first semiconductor chip 230, product yield can be improved and high-efficiency characteristics of each semiconductor chip can be achieved. For example, this configuration facilitates independent optimization of the characteristics of each chip. Furthermore, as described below, manufacturing the sub-package 200 including the first semiconductor chip 230 using a panel-level packaging (PLP) process can improve product productivity compared to wafer-level packaging. Moreover, by first packaging the first semiconductor chip 230 to form the sub-package 200 and then only secondary packaging the high-quality sub-package 200 with the high-cost second semiconductor chip 130, losses of the second semiconductor chip 130 can be minimized or reduced. For example, each type of chip can be mass-produced, and only known qualified dies (i.e., dies that have passed pre-assembly screening) can be assembled to form the final packaged product. Unlike conventional packaging, this method reduces the scrap of the relatively expensive advanced node chips in both types of chips. Furthermore, by introducing a sub-package 200 between the first redistribution structure 110 and the fourth redistribution structure 150 to form the conductive pillar 160 on the third redistribution structure 250, a conductive pillar 160 with a low aspect ratio of 10 or less can be provided. Therefore, problems that may occur when forming conductive pillars with a high aspect ratio can be prevented or reduced.

[0090] Figure 4 This is a cross-sectional view of a semiconductor package according to another embodiment.

[0091] In the semiconductor package 10B, the first semiconductor chip 230 may further include a second connection pad 236 facing and electrically connected to the third redistribution structure 250, and a through path 235 electrically connecting the first connection pad 232 and the second connection pad 236. By forming the through path 235 and the second connection pad 236 connected thereto in the first semiconductor chip 230, a first semiconductor chip 230 capable of responding to an increase in the number of input / output terminals can be provided.

[0092] The through-path 235 penetrates between the upper and lower surfaces of the semiconductor substrate 231 and electrically connects the wiring structure 234 and the second connection pad 236. The through-path 235 may have a cylindrical shape, but is not limited thereto. A conductive material can be used as the material for the through-path 235. For example, the through-path 235 may include metals or metal alloys such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), or tantalum (Ta). An insulating film can be provided between the through-path 235 and the semiconductor substrate 231 for electrical insulation between them. Insulating materials such as silicon oxide, silicon nitride, and polyimide can be used as the insulating film material. Additionally, a barrier film can be further provided between the through-path 235 and the insulating film to prevent or reduce the diffusion of the material (e.g., copper (Cu)) of the through-path 235. Materials that can be used for the barrier film include tungsten (W), cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), etc. The via 235 can be formed using a via-first, via-middle, or via-last method, and the via 235 can further penetrate at least a portion of the wiring structure 234 depending on the formation method.

[0093] The second connection pad 236 may be disposed on the upper surface of the semiconductor substrate 231 and electrically connected to the through-path 235. Additionally, the second connection pad 236 may be electrically connected to the wiring layer 252 via the path 253 of the third redistribution structure 250. A conductive material may be used as the material for the second connection pad 236. For example, the second connection pad 236 may comprise metals such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), gold (Au), platinum (Pt), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or alloys of two or more of these.

[0094] Furthermore, without contradicting this disclosure, the description of the semiconductor package 10A according to embodiments of this disclosure can also be applied to the description of other components.

[0095] Figure 5 This is a cross-sectional view of a semiconductor package according to another embodiment.

[0096] In the semiconductor package 10C, the third redistribution structure 250 may include a plurality of insulating layers 251 and a plurality of wiring layers 252. For example, the third redistribution structure 250 may include a first insulating layer 251A, a first wiring layer 252A disposed on the first insulating layer 251A, a first passage 253A penetrating the first insulating layer 251A and extending into the first encapsulant 240 to electrically connect the first wiring layer 252A and the frame 220, a second insulating layer 251B disposed on the first insulating layer 251A to cover the first wiring layer 252A, a second wiring layer 252B disposed on the second insulating layer 251B, and a second passage 253B penetrating the second insulating layer 251B to electrically connect the second wiring layer 252B and the third wiring layer 252C. Among the plurality of wiring layers 252, the wiring layer exposed at the upper surface of the second encapsulant 120 may be the uppermost second wiring layer 252B adjacent to the second semiconductor chip 130. By constructing the third redistribution structure 250 as a multilayer structure, the freedom of wiring design can be improved.

[0097] Furthermore, without contradicting this disclosure, the description of the semiconductor package 10A according to embodiments of this disclosure can also be applied to the description of other components.

[0098] Figure 6 This is a cross-sectional view of a semiconductor package according to another embodiment.

[0099] The frame 220 of the semiconductor package 10D may include a first insulating layer 221A, a first wiring layer 222A disposed on the upper surface of the first insulating layer 221A, a second wiring layer 222B disposed on the lower surface of the first insulating layer 221A, a first channel 223A penetrating the first insulating layer 221A and electrically connecting the first wiring layer 222A and the second wiring layer 222B, a second insulating layer 221B disposed on the upper surface of the first insulating layer 221A and covering the first wiring layer 222A, and a second channel 223A disposed on the lower surface of the first insulating layer 221A. The first insulating layer 221B comprises a third wiring layer 222C, a second path 223B that penetrates the second insulating layer 221B and electrically connects the first wiring layer 222A and the third wiring layer 222C, a third insulating layer 221C disposed on the lower surface of the first insulating layer 221A and covering the second wiring layer 222B, a fourth wiring layer 222D disposed on the third insulating layer 221C, and a third path 223C that penetrates the third insulating layer 221C and electrically connects the second wiring layer 222B and the fourth wiring layer 222D. The first insulating layer 221A can be used as a core insulating layer and can be thicker than the second insulating layer 221B and the third insulating layer 221C, but it is not limited thereto. The first insulating layer 221A can be formed of a material with superior rigidity than the second insulating layer 221B and the third insulating layer 221C, but it is not limited thereto. For example, the Young's modulus of the material used to form the first insulating layer 221A may be greater than the Young's modulus of the material used to form the second insulating layer 221B and / or the material used to form the third insulating layer 221C.

[0100] Furthermore, without contradicting this disclosure, the description of the semiconductor package 10A according to embodiments of this disclosure can also be applied to the description of other components.

[0101] Figure 7 This is a cross-sectional view of a semiconductor package according to another embodiment.

[0102] Semiconductor package 10E does not include the second encapsulant 120, and the third encapsulant 140 can be integrally formed to continuously cover the sub-package 200, the second semiconductor chip 130, and the conductive pillars 160. A package such as the one described above can be manufactured by arranging the second semiconductor chip 130 and the conductive pillars 160 on the sub-package 200 and then integrally molding them using the integrally formed third encapsulant 140. Figure 7 The semiconductor package 10E is shown.

[0103] Furthermore, without contradicting this disclosure, the description of the semiconductor package 10A according to embodiments of this disclosure can also be applied to the description of other components.

[0104] Figure 8 It includes Figure 1 A cross-sectional view of a stacked package (or stacked package device) of a semiconductor package shown.

[0105] According to an embodiment, the stacked package 1A includes a first semiconductor package 10A and a second semiconductor package 30 disposed on the first semiconductor package 10A.

[0106] The first semiconductor package 10A is shown as Figure 1 The semiconductor package shown is shown, but it can be replaced with a semiconductor package according to other embodiments of this disclosure (e.g., Figures 4 to 7 Any of the semiconductor packages 10B, 10C, 10D and 10E shown.

[0107] The second semiconductor package 30 may include an interconnect structure 310, a third semiconductor chip 320, and a fourth encapsulant 330. However, the unencapsulated third semiconductor chip 320 may be mounted on the first semiconductor package 10A.

[0108] Interconnect structure 310 can electrically connect the third semiconductor chip 320 and the first semiconductor package 10A. Interconnect structure 310 can be, for example, a package substrate or a redistribution structure. In some embodiments, the third semiconductor chip 320 can be flip-chip bonded to or wire-bonded to interconnect structure 310. For example, the third semiconductor chip 320 can be formed onto interconnect structure 310 using a flip-chip bonding process or a wire bonding process. In some embodiments, the third semiconductor chip 320 can be directly disposed on interconnect structure 310 in a chip-first manner. For example, the third semiconductor chip 320 can be disposed and / or molded before forming interconnect structure 310.

[0109] The third semiconductor chip 320 may include or be a memory chip. The memory chip may include memory circuitry and may include, for example, at least one of high-bandwidth memory (HBM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, read-only memory (ROM), and magnetic random access memory (MRAM).

[0110] The fourth encapsulant 330 may cover at least a portion of the third semiconductor chip 320. An insulating material may be used as the material for the fourth encapsulant 330. For example, the fourth encapsulant 330 may include an epoxy molding compound (EMC). Alternatively, the fourth encapsulant 330 may include a thermoplastic resin such as polyimide (PI), a thermosetting resin such as epoxy resin, or a resin wherein such resins are mixed with an inorganic filler such as SiO2 (e.g., Ajinomoto film (ABF)). Alternatively, the fourth encapsulant 330 may include a photoimageable dielectric (PID), such as photosensitive polyimide (PSPI).

[0111] A fourth connection terminal CT4 can be disposed between the second semiconductor package 30 and the first semiconductor package 10A for electrical connection between them. The fourth connection terminal CT4 can be provided (or configured as) a ball grid array, a planar grid array, or a pin grid array. A conductive material can be used as the material for the fourth connection terminal CT4. For example, the fourth connection terminal CT4 can be a solder ball comprising solder formed of Sn-Ag alloy, Sn-Ag-Cu alloy, etc. Alternatively, the fourth connection terminal CT4 can comprise metal or an alloy of metals. There are no particular limitations on the size, number, spacing, arrangement, etc., of the fourth connection terminal CT4.

[0112] Figures 9 to 29 It shows the products used in manufacturing in sequence. Figure 1 A cross-sectional view of the method for the semiconductor package shown.

[0113] A method for manufacturing a semiconductor package 10A may include the steps (or processes) of packaging a first semiconductor chip 230 to form a sub-package 200 and packaging the sub-package 200 and the second semiconductor chip 130 together. A fan-out panel-level packaging (Fo-PLP) process may be applied in the step of forming the sub-package 200, and a fan-out wafer-level packaging (Fo-WLP) process may be applied in the step of packaging the sub-package 200 and the second semiconductor chip 130 together. For example, the semiconductor package 10A may be manufactured (e.g., the first semiconductor chip 230 may be collectively manufactured in panel form) by dicing a reconstructed panel (including the sub-package 200 formed on the panel) using a process of panel-level packaging of the first semiconductor chip 230. This process may include separating the reconstructed panel into individual sub-packages 200, wafer-level packaging the sub-packages 200 (e.g., the sub-packages 200 may be collectively manufactured in wafer form), and then dicing the reconstructed panel.

[0114] In the following text, the manufacturing process will be described step by step with reference to the accompanying drawings. Figure 1 The accompanying drawings illustrate an exemplary method for creating a semiconductor package. The figures only show some areas included in a single semiconductor package 10A of components packaged at the panel or wafer level. For example, although multiple packages can be formed simultaneously at the wafer or panel level, only one example package 10A is shown in the figures for clarity.

[0115] First, refer to Figure 9A frame 220 with a through hole 220h is prepared. The through hole 220h can be formed by laser processing, mechanical processing, etc. A first adhesive 510 can be attached to the lower surface of the frame 220. The first adhesive 510 can be exposed at the bottom surface of the through hole 220h. The first adhesive 510 can be, for example, a polyimide (PI) tape.

[0116] Next, refer to Figure 10 A first semiconductor chip 230 is disposed within a through-hole 220h, and the first semiconductor chip 230 is molded with a first encapsulating agent 240. The first semiconductor chip 230 disposed within the through-hole 220h can be attached and fixed to a first adhesive 510 exposed at the bottom surface of the through-hole 220h. The process of molding the first semiconductor chip 230 with the first encapsulating agent 240 can be performed, for example, by compression molding or transfer molding.

[0117] Next, refer to Figure 11 The first carrier substrate 520 is attached to the first encapsulant 240. The first carrier substrate 520 may have, for example, a double-sided copper foil (DCF) structure, which includes a substrate layer 521 and copper layers 522 disposed on two surfaces of the substrate layer 521. If necessary, an adhesive may be used to attach the first carrier substrate 520 to the first encapsulant 240.

[0118] Next, refer to Figure 12 A second redistribution structure 210 is formed on the first semiconductor chip 230 and the frame 220, and a passivation layer 214 and a bump under-metal layer 215 are formed on the second redistribution structure 210. The second redistribution structure 210 can be manufactured by sequentially forming an insulating layer 211, a through-path 213 penetrating the insulating layer 211, and a wiring layer 212 disposed on the insulating layer 211, and repeating this sequence as needed. The passivation layer 214 can be formed on the second insulating layer 211B of the second redistribution structure 210. An opening exposing the second wiring layer 212B can be formed in the passivation layer 214. The bump under-metal layer 215 can be formed to fill the opening in the passivation layer 214 and extend onto the passivation layer 214.

[0119] Next, refer to Figure 13 This detaches the first carrier substrate 520 and attaches the second carrier substrate 530 to the under-bump metal layer 215. Similar to the first carrier substrate 520, the second carrier substrate 530 may have a double-sided copper foil (DCF) structure, comprising a substrate layer 531 and copper layers 532 disposed on both surfaces of the substrate layer 531. If desired, an adhesive can be used to attach the second carrier substrate 530 to the under-bump metal layer 215.

[0120] Next, refer to Figures 14 to 16A third redistribution structure 250 is formed on the first encapsulant 240. The third redistribution structure 250 can be manufactured by forming an insulating layer 251 on the first encapsulant 240, processing the insulating layer 251 and the first encapsulant 240 to form through-holes 253h of the wiring layer 222 exposing the frame 220, and then forming a via 253 filling the through-holes 253h and a wiring layer 252 disposed on the insulating layer 251. The through-holes 253h can be formed, for example, by laser processing the insulating layer 251 and the first encapsulant 240.

[0121] Next, refer to Figure 17 and Figure 18 The second adhesive 540 is attached to the third redistribution structure 250, and the second carrier substrate 530 is detached from the under-bump metal layer 215. The second adhesive 540 may be, for example, a polyimide (PI) tape.

[0122] Next, refer to Figure 19 and Figure 20 A second connection terminal CT2 is formed on the under-bump metal layer 215, and the reconstructed panel of the package is cut at the panel level to separate it into individual sub-packages 200. Additionally, a second adhesive 540 is detached from the sub-packages 200.

[0123] Next, refer to Figure 21 The sub-package 200 is disposed on the first redistribution structure 110, which is disposed on the third carrier substrate 550. The third carrier substrate 550 may be, for example, a wafer-level (e.g., having a wafer form) glass carrier substrate. The first redistribution structure 110 may be formed on the third carrier substrate 550. The first redistribution structure 110 may be manufactured, for example, by sequentially forming an insulating layer 111, a through-hole 113 penetrating the insulating layer 111, and a wiring layer 112 disposed on the insulating layer 111 on the third carrier substrate 550, and repeating this sequence as needed. The sub-package 200 may be mounted on the first redistribution structure 110 using a second connection terminal CT2.

[0124] Next, refer to Figure 22 and Figure 23 The sub-package 200 is molded with a second encapsulant 120, and the upper surface of the second encapsulant 120 is ground (or removed) to expose the wiring layer 252 of the third redistribution structure 250. The process of molding the sub-package 200 with the second encapsulant 120 can be performed, for example, by compression molding or transfer molding. By grinding the upper surface of the second encapsulant 120, the upper surface of the sub-package 200, molded together at the wafer level, can be planarized. Therefore, in subsequent processes, a seed layer of conductive pillars 160 (e.g., exposed wiring layer 252) can be uniformly formed on the sub-package 200.

[0125] Next, refer to Figure 24 Conductive pillars 160 are formed on the third redistribution structure 250, and a second semiconductor chip 130 is disposed thereon. In some embodiments, the conductive pillars 160 can be fabricated by forming an additional seed layer on the wiring layer 252 and forming an electroplated layer on the seed layer. The second semiconductor chip 130 can be mounted on the wiring layer 252 using a third connection terminal CT3. If desired, an additional process can be performed to cover the third connection terminal CT3 with an underfill material UF.

[0126] Next, refer to Figure 25 and Figure 26 The conductive pillar 160 and the second semiconductor chip 130 are molded using a third encapsulant 140, and the upper surface of the third encapsulant 140 is ground to expose the upper surface of the conductive pillar 160. The process of molding the conductive pillar 160 and the second semiconductor chip 130 using the third encapsulant 140 can be performed, for example, by compression molding or transfer molding. In the process of grinding the upper surface of the third encapsulant 140, the upper surface of the second semiconductor chip 130 may be exposed along with it, but is not limited thereto.

[0127] Next, refer to Figure 27 A fourth redistribution structure 150 is formed on the third encapsulant 140. The fourth redistribution structure 150 can be manufactured by sequentially forming an insulating layer 151, a passage 153 penetrating the insulating layer 151, and a wiring layer 152 disposed on the insulating layer 151, and repeating this sequence as needed.

[0128] Next, refer to Figure 28 The third adhesive 560 is attached to the fourth redistribution structure 150, causing the third carrier substrate 550 to detach from the first redistribution structure 110, and then the first connection terminal CT1 is formed on the first redistribution structure 110. A known tape (e.g., as described above) can be used as the third adhesive 560.

[0129] Next, refer to Figure 29 The wafer-level semiconductor package is cut and separated into individual semiconductor packages 10A. Additionally, a third adhesive 560 is used to detach the individual semiconductor packages 10A.

[0130] While embodiments of the present disclosure have been described in detail, it should be understood that the invention is not limited to the disclosed embodiments, and various modifications and equivalents will be apparent to those skilled in the art.

[0131] Furthermore, the embodiments of this disclosure are not mutually exclusive and can be combined with each other unless they are particularly contradictory. Therefore, combinations of embodiments of this disclosure should also be considered as included in the embodiments disclosed herein.

Claims

1. A semiconductor package, the semiconductor package comprising: First interconnect layer; A sub-package disposed on a first interconnect layer, the sub-package comprising: a second interconnect layer; a via interconnect layer disposed on the second interconnect layer and having through holes; a first semiconductor chip disposed within the through holes; a first encapsulant filling a portion of the through holes and covering a portion of the first semiconductor chip; and a third interconnect layer disposed on the first encapsulant. A second encapsulating agent covers a portion of the sub-package; A second semiconductor chip, wherein the second semiconductor chip is disposed on the second encapsulating agent; A third encapsulating agent covers a portion of the second semiconductor chip; A fourth interconnect layer, the fourth interconnect layer being disposed on the third encapsulant; and A conductive post is embedded in the third encapsulant and electrically connects the sub-package and the fourth interconnect layer.

2. The semiconductor package according to claim 1, wherein, The first semiconductor chip includes a first connection pad facing the second interconnect layer and electrically connected to the second interconnect layer.

3. The semiconductor package according to claim 2, wherein, The first semiconductor chip also includes: A second connection pad, the second connection pad facing the third interconnect layer and electrically connected to the third interconnect layer; and A through-path electrically connects the first connection pad and the second connection pad.

4. The semiconductor package according to claim 1, wherein, The third interconnect layer includes a wiring layer exposed on the upper surface of the second encapsulant.

5. The semiconductor package according to claim 4, wherein, The upper surface of the wiring layer and the upper surface of the second encapsulant are coplanar.

6. The semiconductor package according to claim 1, wherein, The second encapsulant covers the side surface of the sub-package.

7. The semiconductor package according to claim 6, wherein, The side surfaces of the first interconnect layer, the second encapsulant, the third encapsulant, and the fourth interconnect layer are coplanar.

8. The semiconductor package according to claim 1, wherein, The via interconnect layer includes: First wiring layer; A first insulating layer, the first insulating layer covering the first wiring layer; A second wiring layer is disposed on the first insulating layer and electrically connected to the first wiring layer; A second insulating layer, disposed on the first insulating layer and covering the second wiring layer; and A third wiring layer is disposed on the second insulating layer and electrically connected to the second wiring layer.

9. The semiconductor package according to claim 1, wherein, The via interconnect layer includes: First insulating layer; A first wiring layer is disposed on a first surface of the first insulating layer; A second wiring layer is disposed on a second surface of the first insulating layer and electrically connected to the first wiring layer, wherein the first surface and the second surface of the first insulating layer face away from each other; A second insulating layer is disposed on the first surface of the first insulating layer and covers the first wiring layer; A third wiring layer is disposed on the second insulating layer and electrically connected to the first wiring layer; A third insulating layer, wherein the third insulating layer is disposed on the second surface of the first insulating layer and covers the second wiring layer; and A fourth wiring layer is disposed on the third insulating layer and electrically connected to the second wiring layer.

10. The semiconductor package according to claim 1, wherein, The aspect ratio of the conductive pillar is 10 or less.

11. The semiconductor package according to claim 1, wherein, The second semiconductor chip is in contact with the fourth interconnect layer.

12. The semiconductor package according to claim 1, further comprising: A connection terminal is disposed between the sub-package and the first interconnect layer.

13. The semiconductor package according to claim 1, wherein, The conductive pillars are spaced apart from the first interconnect layer.

14. The semiconductor package of claim 1, wherein: The sidewalls of the first interconnect layer and the fourth interconnect layer terminate on the same plane, and In the top view, the sidewalls of the first interconnect layer and the sidewalls of the fourth interconnect layer are horizontally spaced apart from the perforated interconnect layer.

15. A semiconductor package, the semiconductor package comprising: First interconnect layer; A sub-package disposed on and electrically connected to a first interconnect layer, the sub-package comprising: a second interconnect layer; an intermediate interconnect pattern disposed on and electrically connected to the second interconnect layer, and having a through-hole; a first logic chip disposed within the through-hole and electrically connected to the second interconnect layer; a first encapsulant filling a portion of the through-hole and covering a portion of the first logic chip; and a third interconnect layer disposed on the first encapsulant and electrically connected to the intermediate interconnect pattern; A second encapsulating agent covers a portion of the sub-package; The second logic chip is disposed on the second encapsulant and electrically connected to the third interconnect layer; A third encapsulating agent covers a portion of the second logic chip; A fourth interconnect layer, the fourth interconnect layer being disposed on the third encapsulant; and A conductive post is embedded in the third encapsulant and electrically connects the third interconnect layer and the fourth interconnect layer.

16. The semiconductor package of claim 15, wherein, The wiring pitch of the second logic chip is narrower than that of the first logic chip.

17. The semiconductor package of claim 15, wherein, The second logic chip is thicker than the first logic chip.

18. The semiconductor package of claim 15, wherein, The width of the second logic chip is wider than the width of the first logic chip.

19. The semiconductor package of claim 15, wherein, The aspect ratio of the conductive pillar is 10 or less.

20. A stacked package, the stacked package comprising: First semiconductor package; as well as A second semiconductor package is disposed on the first semiconductor package. The first semiconductor package includes: a first interconnect layer; a sub-package disposed on the first interconnect layer; a second encapsulant covering a portion of the sub-package; a second semiconductor chip disposed on the second encapsulant; a third encapsulant covering a portion of the second semiconductor chip; a fourth interconnect layer disposed on the third encapsulant; and conductive pillars embedded in the third encapsulant and electrically connecting the sub-package and the fourth interconnect layer. The sub-package includes: a second interconnect layer; an intermediate interconnect pattern disposed on the second interconnect layer and having a through-hole; a first semiconductor chip disposed within the through-hole; a first encapsulant filling a portion of the through-hole and covering a portion of the first semiconductor chip; and a third interconnect layer disposed on the first encapsulant.

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