Semiconductor package and method of forming the same

Abstract

A semiconductor package and a method of forming the same are provided. The method includes providing a first semiconductor die having a first active surface and a first inactive surface opposite the first active surface; providing a second semiconductor die having a second active surface and a second inactive surface opposite the second active surface, wherein at least one wire bond pad is formed on the second active surface; attaching the first active surface to the second active surface using hybrid bonding, wherein the at least one wire bond pad is exposed from the first semiconductor die; providing a sub-package including a substrate and a third semiconductor die mounted on the substrate; attaching the second inactive surface of the second semiconductor die to the third semiconductor die; and electrically coupling the at least one wire bond pad to the substrate using wire bonding.

Description

Technical Field

[0001] This application generally relates to semiconductor technology, and more specifically, to a semiconductor package and a method of forming the same. Background Technology

[0002] The semiconductor industry has faced complex integration challenges as consumers demand smaller, faster, and higher-performing electronic devices and pack more and more functionality into a single device. Wire bonding is commonly used to bond upper chips to lower chips or substrates to form stacked chip packages. However, wire bonding can limit performance in high-speed applications and increase the overall package size due to the height of the bonding wires.

[0003] Therefore, there is a need for a method for forming semiconductor packages with higher data transmission speeds and / or reduced height. Summary of the Invention

[0004] The objective of this application is to provide a method for forming a semiconductor package with high data transmission speed and / or reduced height.

[0005] According to one aspect of this application, a method for forming a semiconductor package is provided. The method may include: providing a first semiconductor die having a first active surface and a first non-active surface opposite to the first active surface; providing a second semiconductor die having a second active surface and a second non-active surface opposite to the second active surface, wherein at least one wire bonding pad is formed on the second active surface of the second semiconductor die; attaching the first active surface of the first semiconductor die to the second active surface of the second semiconductor die using hybrid bonding, wherein the at least one wire bonding pad is exposed from the first semiconductor die; providing a subpackage including a substrate and a third semiconductor die mounted on the substrate; attaching the second non-active surface of the second semiconductor die to the third semiconductor die; and electrically coupling the at least one wire bonding pad to the substrate using wire bonding.

[0006] According to another aspect of this application, a semiconductor package is provided. The semiconductor package may include: a first semiconductor die having a first active surface and a first non-active surface opposite the first active surface; a second semiconductor die having a second active surface and a second non-active surface opposite the second active surface, wherein at least one wire bonding pad is formed on the second active surface of the second semiconductor die, and the first active surface of the first semiconductor die is attached to the second active surface of the second semiconductor die using hybrid bonding, such that the at least one wire bonding pad is exposed from the first semiconductor die; and a sub-package including a substrate and a third semiconductor die mounted on the substrate, wherein the second non-active surface of the second semiconductor die is attached to the third semiconductor die, and the at least one wire bonding pad is electrically coupled to the substrate using wire bonding.

[0007] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the invention. Furthermore, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Attached Figure Description

[0008] The accompanying drawings referenced herein form part of this specification. The features shown in the drawings illustrate only some embodiments of this application, and not all embodiments of this application, unless otherwise expressly stated in the detailed description, and the reader of this specification should not draw the contrary inference.

[0009] Figure 1 It is a cross-sectional view of a semiconductor package with semiconductor die stacks.

[0010] Figure 2A This is a cross-sectional view of a semiconductor package according to an embodiment of this application.

[0011] Figure 2B According to one embodiment Figure 2A An enlarged view of a portion of the semiconductor package shown.

[0012] Figure 2C According to another embodiment Figure 2A An enlarged view of a portion of the semiconductor package shown.

[0013] Figure 2D According to another embodiment Figure 2A An enlarged view of a portion of the semiconductor package shown.

[0014] Figure 2E According to another embodiment Figure 2AAn enlarged view of a portion of the semiconductor package shown.

[0015] Figure 3 This is a cross-sectional view of a semiconductor package according to another embodiment of this application.

[0016] Figures 4A to 4H This is a cross-section showing the various steps of a method for forming a semiconductor package according to an embodiment of this application.

[0017] Figures 5A to 5C This is a cross-section showing the various steps of a method for forming a semiconductor die stack according to an embodiment of this application.

[0018] Figures 6A to 6D This is a cross-section showing the various steps of a method for forming a semiconductor die stack according to another embodiment of this application.

[0019] Figures 7A to 7C This is a cross-section showing the various steps of a method for forming a semiconductor die stack according to another embodiment of this application.

[0020] Throughout the accompanying drawings, the same reference numerals will be used to refer to the same or similar parts. Detailed Implementation

[0021] The following detailed description of exemplary embodiments of this application takes into account the accompanying drawings, which form a part of the description. The drawings illustrate specific exemplary embodiments in which this application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice this application. Those skilled in the art can further utilize other embodiments of this application and make logical, mechanical, and other changes without departing from the spirit or scope of this application. Therefore, the reader of the following detailed description should not interpret the description in a limiting sense, and the scope of embodiments of this application is defined only by the appended claims.

[0022] In this application, unless otherwise specified, the use of the singular includes the plural. In this application, unless otherwise specified, the use of “or” means “and / or”. Furthermore, the use of the term “comprising” and other forms such as “including” and “containing” is not restrictive. Additionally, unless otherwise expressly stated, terms such as “element” or “component” cover both elements and components comprising one unit and elements and components comprising more than one sub-unit. Furthermore, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0023] In this document, spatial relative terms such as “below,” “under,” “above,” “on top,” “upper,” “upper part,” “lower part,” “left side,” “right side,” “vertical,” “horizontal,” and “side” are used for ease of description to describe the relationship between one element or feature as shown in the accompanying drawings and one or more other elements or features. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, the element may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0024] Figure 1 This is a cross-sectional view of a semiconductor package 100 with a semiconductor die stack. The semiconductor die stack includes a first semiconductor die 110, a second semiconductor die 120, and a third semiconductor die 130 stacked vertically. Specifically, the third semiconductor die 130 is flip-chip bonded to a substrate 140, and the second semiconductor die 120 is attached to the back side of the third semiconductor die 130 and then wire-bonded to the substrate 140. Furthermore, the first semiconductor die 110 is attached to the back side of the second semiconductor die 120 and then wire-bonded to the substrate 140. However, conventional wire bonding methods face challenges, such as delays in electrical signal transmission. For example, these methods typically only support data transmission speeds of 1-5 Gbps, thus limiting performance in high-speed applications. Additionally, the height of the bonding wires increases the overall package size. For example, the wire height can result in a package thickness of 1-2 mm, posing a significant challenge to the miniaturization of electronic devices.

[0025] To address at least one of the aforementioned problems, this application provides a method for forming a semiconductor package. In this method, an active surface of a first semiconductor die is attached to an active surface of a second semiconductor die using hybrid bonding, while exposing at least one wire bonding pad formed on the active surface of the second semiconductor die from the first semiconductor die. Subsequently, a semiconductor die stack including the first and second semiconductor dies is attached to a third semiconductor die mounted on a substrate. Then, the aforementioned at least one wire bonding pad is electrically coupled to the substrate using wire bonding. In this method, the first semiconductor die is initially electrically coupled to the second semiconductor die using hybrid bonding. It can then be further electrically coupled to the substrate via the second semiconductor die and bonding wires. Therefore, it is not necessary to directly wire bond the first semiconductor die to the substrate. Compared to wire bonding, hybrid bonding technology can significantly enhance signal transmission speed, for example, achieving rates of tens to hundreds of Gbps and reducing latency by approximately 10 times. Because no bonding wires are required, hybrid bonding allows for more compact designs and reduces package thickness by, for example, 50%.

[0026] Figure 2A A cross-sectional view of a semiconductor package 200 according to an embodiment of this application is shown. The semiconductor package 200 includes a first semiconductor die 210 and a second semiconductor die 220 bonded together using hybrid bonding.

[0027] refer to Figure 2B It illustrates one embodiment according to this application. Figure 2A An enlarged view of a portion 201 of the semiconductor package 200 shown. Figure 2B As shown, the first semiconductor die 210 has a first active surface 210a and a first non-active surface 210b opposite to the first active surface 210a, and the second semiconductor die 220 has a second active surface 220a and a second non-active surface 220b opposite to the second active surface 220a.

[0028] In some embodiments, the first semiconductor die 210 and / or the second semiconductor die 220 may include one or more digital chips, analog chips, or mixed-signal chips, such as application-specific integrated circuit (ASIC) chips, sensor chips, wireless and radio frequency (RF) chips, memory chips, logic chips, or voltage regulator chips. The first semiconductor die 210 and the second semiconductor die 220 may be manufactured using surface mount technology (SMT) processes or other similar processes. That is, different types of analog or digital circuits, which can be implemented as active and / or passive devices, may be formed close to the first active surface 210a and the second active surface 220a. In contrast, the first passive surface 210b and the second passive surface 220b may not have any electronic components or conductive patterns exposed therefrom, but the scope of this application is not limited thereto.

[0029] In some embodiments, a first redistribution layer (RDL) 212 may be formed on a first active surface 210a of a first semiconductor die 210, and a second RDL 222 may be formed on a second active surface 210a of a second semiconductor die 220. The first RDL 212 and the second RDL 222 may include one or more dielectric layers and one or more conductive layers between and through the dielectric layers. The conductive layers may be electrically coupled to electronic components formed in the first semiconductor die 210 and the second semiconductor die 220, and may also define pads, traces, and plugs through which electrical signals or voltages may be distributed horizontally and vertically on the redistribution structure.

[0030] Additionally, a first interconnect layer 214 may be formed on a first active surface 210a of the first semiconductor die 210. The first interconnect layer 214 may include a first dielectric layer 215 and a plurality of first conductive structures 216 extending through the first dielectric layer 215. Similarly, a second interconnect layer 224 is formed on a second active surface 220a of the second semiconductor die 220. The second interconnect layer 224 may include a second dielectric layer 225 and a plurality of second conductive structures 226 extending through the second dielectric layer 225. The plurality of first conductive structures 216 and the plurality of second conductive structures 226 may be electrically coupled to the conductive layers of the first RDL 212 and the second RDL 222, respectively. In one example, the first dielectric layer 215 and the second dielectric layer 225 may include silicon oxide, while the plurality of first conductive structures 216 and the plurality of second conductive structures 226 may include copper. However, the scope of this application is not limited to these materials. The first interconnect layer 214 is attached to the second interconnect layer 224 using hybrid bonding, such that the first dielectric layer 215 and the first plurality of conductive structures 216 of the first interconnect layer 214 are vertically aligned and bonded to the second dielectric layer 225 and the second plurality of conductive structures 226 of the second interconnect layer 224, respectively. Hybrid bonding combines dielectric-to-dielectric bonding between the first dielectric layer 215 and the second dielectric layer 225 and metal-to-metal bonding between the first conductive structure 216 and the second plurality of conductive structures 226, and achieves scaling and a much higher interconnect density between the first semiconductor die 210 and the second semiconductor die 220. Compared with wire bonding, hybrid bonding can significantly improve signal transmission speed and reduce package thickness.

[0031] In addition, refer to Figure 2B Multiple wire bonding pads 2501 are formed on the peripheral region of the second active surface 220a of the second semiconductor die 220. The wire bonding pads 2501 may extend through the second dielectric layer 225 of the second interconnect layer 224 to be electrically coupled to the conductive layer of the second RDL 222. The wire bonding pads 2501 may have the same height as the second plurality of conductive structures 226. That is, the upper surface of the wire bonding pads 2501 is coplanar with the upper surface of the second dielectric layer 225. In one example, the wire bonding pads 2501 and the second plurality of conductive structures 226 are formed using the same process and include the same material, such as copper. After the first active surface 210a of the first semiconductor die 210 is attached to the second active surface 220a of the second semiconductor die 220 using hybrid bonding, the wire bonding pads 2501 are exposed from the first semiconductor die 210. In other words, the wire bonding pad 2501 is not covered by the first semiconductor die 210.

[0032] refer to Figure 2C It illustrates another embodiment according to this application. Figure 2A An enlarged view of a portion 201 of the semiconductor package 200 shown. Figure 2C As shown, a plurality of wire bonding pads 2502 are formed on the peripheral region of the second active surface of the second semiconductor die 220 and exposed from the first semiconductor die 210. The wire bonding pads 2502 may extend through the second dielectric layer 225 of the second interconnect layer 224 to be electrically coupled to the conductive layer of the second RDL 222. Unlike Figure 2B Wire bonding pad 2501, Figure 2C Each of the wire bonding pads 2502 may include a lower portion 2502L and an upper portion 2502U. The wire bonding pads 2502 may have the same height as the second plurality of conductive structures 226. That is, the upper surface of the upper portion 2502U of the wire bonding pad 2502 is coplanar with the upper surface of the second dielectric layer 225. In one example, the wire bonding pads 2502 and the second plurality of conductive structures 226 are formed using different processes. For example, the lower portion 2502L of the wire bonding pad 2502 may include the same material as the conductive structure 226, such as copper, but the upper portion 2502U of the wire bonding pad 2502 may include a material different from the conductive structure 226, such as gold. Gold enables strong bonding with bonding wires (e.g., gold wires), thereby enhancing the reliability of subsequent wire bonding processes. Gold-to-gold bonding further allows efficient diffusion, resulting in strong adhesion. In contrast, copper is easily oxidized when exposed to air, which reduces the quality of the bond.

[0033] refer to Figure 2D It illustrates another embodiment according to this application. Figure 2A An enlarged view of a portion 201 of the semiconductor package 200 shown. Figure 2D As shown, a plurality of wire bonding pads 2503 are formed on the peripheral region of the second active surface of the second semiconductor die 220 and exposed from the first semiconductor die 210. The wire bonding pads 2503 may extend through the second dielectric layer 225 of the second interconnect layer 224 to be electrically coupled to the conductive layer of the second RDL 222. Unlike Figure 2B Wire bonding pad 2501, Figure 2D Each of the wire bonding pads 2503 may include a lower portion 2503L and an upper portion 2503U. Additionally, unlike... Figure 2C Wire bonding pad 2502, Figure 2D The wire bonding pad 2503 may be higher than the second plurality of conductive structures 226. That is, the upper surface of the upper portion 2503U of the wire bonding pad 2503 is higher than the upper surface of the second dielectric layer 225. In one example, the lower portion 2503L of the wire bonding pad 2503 may include the same material as the conductive structure 226, such as copper, but the upper portion 2503U of the wire bonding pad 2503 may include a material different from that of the conductive structure 226, such as gold.

[0034] refer to Figure 2E This illustrates another embodiment according to this application. Figure 2A An enlarged view of a portion 201 of the semiconductor package 200 shown. Figure 2E As shown, a plurality of wire bonding pads 2504 are formed on the peripheral region of the second active surface of the second semiconductor die 220 and exposed from the first semiconductor die 210. The wire bonding pads 2504 may extend through the second dielectric layer 225 of the second interconnect layer 224 to be electrically coupled to the conductive layer of the second RDL 222. The wire bonding pads 2504 may have the same height as the second plurality of conductive structures 226. The wire bonding pads 2504 are similar to... Figure 2B The wire bonding pad 2501 shown differs in that the wire bonding pad 2504 is made of a different material than the conductive structure 226. For example, the wire bonding pad 2504 and the conductive structure 226 may be formed using different processes. The wire bonding pad 2504 may include gold, while the conductive structure 226 may include copper.

[0035] Continue to refer to Figure 2A The semiconductor package 200 may further include a substrate 240 and a third semiconductor die 230. The third semiconductor die 230 is mounted on the upper surface of the substrate 240.

[0036] The substrate 240 may support a semiconductor die stack mounted thereon and further electrically connect the semiconductor die stack to other electronic components. As an example, the substrate 240 may be a printed circuit board. However, the substrate 240 is not limited thereto. In other examples, the substrate 240 may be a semiconductor substrate, a laminated interposer, a strip interposer, a lead frame, or other suitable substrate. According to the scope of this application, the substrate 240 may include any structure on or therein on which an integrated circuit system is fabricated. For example, the substrate 240 may include one or more insulating or passivation layers, one or more conductive vias formed through the insulating layers, and one or more conductive layers formed above or between the insulating layers. For example, a redistribution structure may be formed in the substrate 240, the redistribution structure including a plurality of upper conductive patterns on an upper surface of the substrate 240, a plurality of lower conductive patterns on a lower surface of the substrate 240, and a plurality of conductive vias electrically connecting at least one of the upper conductive patterns to at least one of the lower conductive patterns.

[0037] The third semiconductor die 230 may include one or more digital chips, analog chips, or mixed-signal chips, such as application-specific integrated circuit (ASIC) chips, sensor chips, wireless and radio frequency (RF) chips, memory chips, logic chips, or voltage regulator chips. In a particular example, the first semiconductor die 210 and the second semiconductor die 220 are memory chips, and the third semiconductor die 230 is a logic chip. However, this application is not limited to the above examples. In some embodiments, the third semiconductor die 230 is positioned above the substrate 240 with its conductive bumps facing the substrate 230, thereby flip-chip bonding to the substrate 240. Subsequently, a semiconductor die stack including the first semiconductor die 210 and the second semiconductor die 220 is stacked on the third semiconductor die 230. For example, an adhesive layer 235 may be formed on the upper surface of the third semiconductor die 230, and then a second non-active surface of the second semiconductor die 220 is attached to the third semiconductor die 230 via the adhesive layer 235. Furthermore, bonding wires 260 may be used to bond wire bonding pads (e.g., on the second active surface of the second semiconductor die 220) to the third semiconductor die 230. Figure 2B The wire bonding pad 2501 shown is... Figure 2C The wire bonding pad 2502 shown is... Figure 2D The wire bonding pad 2503 shown is... Figure 2E The wire bonding pads 2504 shown are electrically connected to a conductive pattern formed on the upper surface of the substrate 240. Therefore, the first semiconductor die 210 and / or the second semiconductor die 220 can be electrically connected to the third semiconductor die 230 and other electronic components via bonding wires 260 and the substrate 240. In some embodiments, the bonding wires 260 may comprise gold, copper, or aluminum.

[0038] refer to Figure 2A A sealant 270 is formed on substrate 240 to seal the first semiconductor die 210, the second semiconductor die 220, the third semiconductor die 230, and the bonding wire 260. The sealant 270 provides mechanical protection for the first semiconductor die 210, the second semiconductor die 220, the third semiconductor die 230, and the bonding wire 260. The sealant 270 may include, for example, epoxy molding compound (EMC), polyamide compound, or any other suitable dielectric material. Additionally, a plurality of conductive bumps 245 are formed on the lower surface of substrate 240. Figure 2A In the example shown, conductive bump 245 is depicted as a solder bump, but this application is not limited thereto. In some other embodiments, conductive bump 245 may include conductive pillars, copper balls, etc. When the semiconductor package 200 is mounted on an external device or a substrate such as a printed circuit board, the conductive bump 245 can be used to electrically connect the semiconductor package 200 to the external device or the substrate.

[0039] Although reference Figures 2A to 2EThe semiconductor package of this application has been described; however, those skilled in the art will understand that modifications and adjustments can be made to the semiconductor package without departing from the scope of the invention. For example, Figure 3 A cross-sectional view of a semiconductor package 300 according to another embodiment of this application is shown. The semiconductor package 300 may include a first semiconductor die 310, a second semiconductor die 320, and a third semiconductor die 330 vertically stacked on a substrate 340. At least one wire bonding pad 350 is formed on a second active surface of the second semiconductor die 320. The first active surface of the first semiconductor die 310 is attached to the second active surface of the second semiconductor die 320 using hybrid bonding, such that at least one wire bonding pad 350 is exposed from the first semiconductor die 310. Bonding wires 360 are used to electrically connect at least one wire bonding pad 350 to the substrate 340. The semiconductor package 300 is similar to... Figure 2B The semiconductor package 200 shown differs in that the wire bonding pads 350 are formed near the edge of the second active surface of the second semiconductor die 320. Since the bonding wires 360 are disposed on one side of the semiconductor package 300, therefore... Figure 3 The unidirectional stacking architecture shown can further reduce the package size.

[0040] According to another aspect of this application, a method for forming a semiconductor package is provided.

[0041] refer to Figures 4A to 4H This illustrates various steps of a method for forming a semiconductor package according to embodiments of this application. For example, the method can be used to form... Figure 2A The semiconductor package 200 is shown below. Reference will be made to... Figures 4A to 4H The method will be described in more detail below.

[0042] refer to Figure 4A A first semiconductor die 410 is provided. The first semiconductor die 410 has a first active surface 410a and a first non-active surface 410b opposite to the first active surface 410a.

[0043] In some embodiments, surface-mount processes or other similar processes may be used to fabricate the first semiconductor die 410. That is, various types of analog or digital circuitry, which may be implemented as active and / or passive devices, may be formed close to the first active surface 410a. In contrast, the first non-active surface 410b may not have any electronic components or conductive patterns exposed therefrom, but the scope of this application is not limited thereto. A first redistribution layer (RDL) 412 may be formed on the first active surface 410a of the first semiconductor die 410. The first RDL 412 may include one or more dielectric layers and one or more conductive layers between and through the dielectric layers. The conductive layers may be electrically coupled to electronic components formed in the first semiconductor die 410 and may also define pads, traces, and plugs through which electrical signals or voltages may be distributed horizontally and vertically on the redistribution structure. Additionally, a first interconnect layer 414 may be formed on the first RDL 412. The first interconnect layer 414 may include a first dielectric layer 415 and a first plurality of conductive structures 416 extending through the first dielectric layer 415. In one example, the first dielectric layer 415 may include silicon oxide, and the first plurality of conductive structures 416 may include copper.

[0044] refer to Figure 4B A second semiconductor die 420 is provided. The second semiconductor die 420 has a second active surface 420a and a second non-active surface 420b opposite to the second active surface 420a, and at least one wire bonding pad 450 is formed on the second active surface 420a of the second semiconductor die 420.

[0045] In some embodiments, a second redistribution layer (RDL) 422 may be formed on the second active surface 420a of the second semiconductor die 420, and a second interconnect layer 424, including a second dielectric layer 425 and a plurality of conductive structures 426, may be formed on the second RDL 422. The second semiconductor die 420 may have a structure similar to or different from that of the first semiconductor die 410 and will not be described in detail herein. In some embodiments, at least one wire bonding pad 450 may be formed in the same process as the conductive structures 426 of the second interconnect layer 424, and therefore the at least one wire bonding pad 450 may extend through the second dielectric layer 425 of the second interconnect layer 424.

[0046] In some embodiments, the top portion of the second interconnect layer 424 may be polished to form a relatively flat top surface. The polishing process removes oxides to prepare the second semiconductor die 420 for subsequent bonding processes. For example, a chemical mechanical polishing (CMP) process may be performed to polish the second interconnect layer 424. In some cases, a surface treatment process, such as a plasma surface activation process, may be further applied to the upper surface of the second interconnect layer 424. It is understood that a similar surface preparation process may be performed on the first interconnect layer 414 of the first semiconductor die 410.

[0047] refer to Figure 4C Hybrid bonding is used to attach the first interconnect layer 414 of the first semiconductor die 410 to the second interconnect layer 424 of the second semiconductor die 420. After hybrid bonding, the first dielectric layer 415 and the first plurality of conductive structures 416 of the first interconnect layer 414 are vertically aligned and bonded to the second dielectric layer 425 and the second plurality of conductive structures 426 of the second interconnect layer 424, respectively.

[0048] In some embodiments, after the first semiconductor die 410 is placed onto the second semiconductor die 420, the first semiconductor die 410 is pressed against the second semiconductor die 420 by a bonding head 402. During this process, adhesion occurs between the polished surfaces of the first semiconductor die 410 and the second semiconductor die 420. This results in strong surface-to-surface attraction and closes the gap from the center region of the aligned first semiconductor die 410 and the second semiconductor die 420 to the edge. This process can be performed at room temperature to ensure direct and tight contact between the surfaces of the first semiconductor die 410 and the second semiconductor die 420. Next, an annealing process is performed on the first semiconductor die 410 and the second semiconductor die 420. A fusion bond can be established between the first conductive structure 416 and the second conductive structure 426 to form a strong metal-to-metal interconnect. Furthermore, the first dielectric layer 415 and the second dielectric layer 425 can be extended to allow for a tighter contact between them, thereby forming sufficient bonding therebetween. In this manner, a permanent hybrid bond can be formed, which combines the dielectric-to-dielectric bond between the first dielectric layer 415 and the second dielectric layer 425 and the metal-to-metal bond between the first conductive structure 416 and the second conductive structure 426. After the hybrid bond, at least one of the aforementioned wire bond pads 450 should be exposed from the first semiconductor die 410.

[0049] In some implementations, to increase manufacturing yield, multiple second semiconductor dies 420 can be formed on the same wafer in a strip manner, thereby allowing some manufacturing processes to be performed in parallel on all the multiple second semiconductor dies 420 to form multiple semiconductor packages. For example, such as Figure 4CAs shown, hybrid bonding can be used to mount a plurality of first semiconductor dies 410 onto a plurality of second semiconductor dies 420, respectively. Subsequently, refer to... Figure 4C and Figure 4D This allows for a single-cut process, enabling each of a plurality of first semiconductor dies 410 to be bonded to one of a plurality of second semiconductor dies 420. In this manner, multiple double-layer interconnect stacks can be formed simultaneously.

[0050] refer to Figure 4E It provides a subpackage including a substrate 440 and a third semiconductor die 430 mounted on the substrate.

[0051] As an example, substrate 440 may be a printed circuit board. However, substrate 440 is not limited to this. In other examples, substrate 440 may be a semiconductor substrate, a laminated interposer, a strip interposer, a lead frame, or other suitable substrate. According to the scope of this application, substrate 440 may include any structure on or in which an integrated circuit system is fabricated. For example, substrate 440 may include one or more insulating or passivation layers, one or more conductive vias formed through the insulating layers, and one or more conductive layers formed above or between the insulating layers. In some embodiments, third semiconductor die 430 may include one or more digital chips, analog chips, or mixed-signal chips, such as application-specific integrated circuit (ASIC) chips, sensor chips, wireless and radio frequency (RF) chips, memory chips, logic chips, or voltage regulator chips. In a particular example, first semiconductor die 410 and second semiconductor die 420 are memory chips, and third semiconductor die 430 is a logic chip. However, this application is not limited to the examples described above. In some embodiments, third semiconductor die 430 is positioned above substrate 440 such that its conductive bumps face substrate 430, thereby flip-chip bonding to substrate 440.

[0052] refer to Figure 4F An adhesive layer 435 is formed on the upper surface of the third semiconductor die 430. The adhesive layer 435 may be a double-sided adhesive tape. For example, the adhesive layer 435 may be a UV-sensitive tape that can be cured after irradiation with ultraviolet light having a certain wavelength range. In another example, the adhesive layer 435 may include an adhesive material, such as an adhesive polymer, plastic, ceramic, etc. Subsequently, as... Figure 4G As shown, the second non-active surface of the second semiconductor die 420 is attached to the third semiconductor die 430 via an adhesive layer 435.

[0053] Then, refer to Figure 4HAt least one wire bonding pad 450 is electrically coupled to the substrate 440 using wire bonding. For example, a bonding wire 460 can be used to electrically connect at least one wire bonding pad 450 formed on the second active surface of the second semiconductor die 420 to a conductive pattern formed on the upper surface of the substrate 440. Therefore, the first semiconductor die 410 and / or the second semiconductor die 420 can be electrically connected to a third semiconductor die 430 and other electronic components via the bonding wire 460 and the conductive pattern formed in the substrate 440. In some embodiments, the bonding wire 460 may comprise gold, copper, or aluminum.

[0054] Furthermore, a sealant 470 may be formed on the substrate 440 to encapsulate the first semiconductor die 410, the second semiconductor die 420, the third semiconductor die 430, and the bonding wire 460. The sealant 470 provides mechanical protection for the first semiconductor die 410, the second semiconductor die 420, the third semiconductor die 430, and the bonding wire 460. The sealant 470 may include, for example, epoxy molding compound (EMC), polyamide compound, or any other suitable dielectric material. Additionally, a plurality of conductive bumps 445 are formed on the lower surface of the substrate 440. When the semiconductor package is mounted on an external device or a substrate such as a printed circuit board, the conductive bumps 445 can be used to electrically connect the semiconductor package to the external device or the substrate.

[0055] Reference Figures 4A to 4H In the above-described embodiments, the use of and Figure 2B The semiconductor die stack shown is similar to a semiconductor die stack used to describe the manufacturing process of a semiconductor package. However, this application is not limited thereto. In some other embodiments, similar to... Figures 2C to 2E The semiconductor die stack shown is similar to those used to form semiconductor packages. In the following sections, the methods for forming such... Figures 2C to 2E The method for stacking semiconductor dies shown.

[0056] refer to Figures 5A to 5C It provides for forming such Figure 2C The method for stacking semiconductor dies shown.

[0057] like Figure 5A As shown, a second semiconductor die 520 is provided. The second semiconductor die 520 has an active surface and an active surface opposite to the active surface. A second RDL 522 may be formed on the active surface of the second semiconductor die 520, and a second interconnect layer 524 including a second dielectric layer 525 and a plurality of conductive structures 526 may be formed on the second RDL 522. (Reference) Figure 5B It shows Figure 5A An enlarged view of a portion 501 of the second semiconductor die 520 shown. Figure 5B As shown, a wire bonding pad 550 is formed on the active surface of the second semiconductor die 520. The wire bonding pad 550 may extend through the second dielectric layer 525 of the second interconnect layer 524 to be electrically coupled to the conductive layer of the second RDL 522. Figure 5B The wire bonding pad 550 may include a lower portion 550L and an upper portion 550U. The wire bonding pad 550 may have the same height as the second plurality of conductive structures 526. That is, the upper surface of the upper portion 550U is coplanar with the upper surface of the second dielectric layer 525. Unlike Figure 4B The wire bonding pads 450 and 550 shown are formed using different processes than the second plurality of conductive structures 526. For example, the lower portion 550L of the wire bonding pad 550 may include the same material as the conductive structures 526, such as copper, but is lower than the second plurality of conductive structures 526. Subsequently, an electroless immersion of gold may be performed on the lower portion 550L to form the upper portion 550U to match the height. As a result, the total height of the wire bonding pad 550 is the same as the total height of the second plurality of conductive structures 526. Then, as... Figure 5C As shown, a grinding process can be performed on the upper surface of the second semiconductor die 520 for subsequent bonding processes.

[0058] refer to Figures 6A to 6D It provides for forming such Figure 2D The method for stacking semiconductor dies shown.

[0059] like Figure 6A As shown, a second semiconductor die 620 is provided. The second semiconductor die 620 has an active surface and an active surface opposite to the active surface. A second RDL 622 may be formed on the active surface of the second semiconductor die 620, and a second interconnect layer 624 including a second dielectric layer 625 and a plurality of conductive structures 626 may be formed on the second RDL 622. (Reference) Figure 6B and Figure 6C , Figure 6C yes Figure 6B An enlarged view of a portion 601 of the second semiconductor die 620 shown. Wire bonding pads 650 are formed on the active surface of the second semiconductor die 620. The wire bonding pads 650 may extend through the second dielectric layer 625 of the second interconnect layer 624 to be electrically coupled to the conductive layer of the second RDL 622. Figure 6CThe wire bonding pad 650 may include a lower portion 650L and an upper portion 650U. The wire bonding pad 650 may be higher than the second plurality of conductive structures 626. That is, the upper surface of the upper portion 650U of the wire bonding pad 650 is higher than the upper surface of the second dielectric layer 625. In one example, a photoresist layer 603 may be formed on the upper surface of the second semiconductor die 620, and the photoresist layer 603 is patterned to expose the lower portion 650L of the wire bonding pad 650. Subsequently, an additional copper layer is deposited on the lower portion 650L to increase its height, and then a gold layer is deposited on the additional copper layer to form the upper portion 650U. As an example, the additional copper and gold layers can be deposited by electroplating. Subsequently, as Figure 6D As shown, the photoresist layer 603 can be chemically removed. Before performing a chemical mechanical polishing (CMP) process for selectively grinding the conductive structure 626, a hard mask or photoresist can be used to protect the wire bond pads 650. For example, silicon oxide can be deposited to a specific thickness such that only the ends of the wire bond pads 650 are exposed.

[0060] refer to Figures 7A to 7C It provides for forming such Figure 2E The method for stacking semiconductor dies shown.

[0061] like Figure 7A As shown, a second semiconductor die 720 is provided. The second semiconductor die 720 has an active surface and an active surface opposite to the active surface. A second RDL 722 may be formed on the active surface of the second semiconductor die 720, and a second interconnect layer 724 including a second dielectric layer 725 and a plurality of conductive structures 726 may be formed on the second RDL 722. (Reference) Figure 7B It shows Figure 7A An enlarged view of a portion 701 of the second semiconductor die 720 shown. Figure 7B As shown, wire bonding pads 750 are formed on the active surface of the second semiconductor die 720. The wire bonding pads 750 can extend through the second dielectric layer 725 of the second interconnect layer 724 to be electrically coupled to the conductive layer of the second RDL 722. Unlike... Figure 4B The wire bonding pads 450 and 750 shown, and the second plurality of conductive structures 726, are formed using different processes. For example, the wire bonding pads 750 are formed by depositing gold in some vias in the second dielectric layer 725, while the second plurality of conductive structures 726 are formed by depositing copper in other vias in the second dielectric layer 725. Then, as... Figure 7C As shown, a grinding process can be performed on the upper surface of the second semiconductor die 720 for subsequent bonding processes.

[0062] While exemplary semiconductor packages and methods for forming semiconductor packages have been described in conjunction with the accompanying drawings, those skilled in the art will understand that modifications and adjustments can be made to the semiconductor packages and methods without departing from the scope of the invention. The discussion herein includes numerous illustrative drawings illustrating various portions of semiconductor packages and methods for manufacturing semiconductor packages. For clarity, these drawings do not show all aspects of each exemplary semiconductor package. Any example packages and / or methods provided herein may share any or all characteristics with any or all other packages and / or methods provided herein.

[0063] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and alterations can be made thereto, and other embodiments can be implemented, without departing from the broader scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art upon consideration of the practice of one or more embodiments of the invention disclosed herein. Therefore, the examples in this application and herein are intended to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following list of exemplary claims.

Claims

1. A method for forming a semiconductor package, characterized in that, The method includes: A first semiconductor die is provided, the first semiconductor die having a first active surface and a first non-active surface opposite to the first active surface; A second semiconductor die is provided, the second semiconductor die having a second active surface and a second non-active surface opposite to the second active surface, wherein at least one wire bonding pad is formed on the second active surface of the second semiconductor die; Hybrid bonding is used to attach a first active surface of the first semiconductor die to a second active surface of the second semiconductor die, wherein at least one wire bonding pad is exposed from the first semiconductor die; A subpackage is provided, the subpackage including a substrate and a third semiconductor die mounted on the substrate; Attaching the second non-active surface of the second semiconductor die to the third semiconductor die; and The at least one lead bonding pad is electrically coupled to the substrate using wire bonding.

2. The method according to claim 1, characterized in that, Attaching the second non-active surface of the second semiconductor die to the third semiconductor die includes: An adhesive layer is formed on the third semiconductor die; and The second non-active surface of the second semiconductor die is attached to the third semiconductor die via the adhesive layer.

3. The method according to claim 1, characterized in that, The method further includes: A sealant is formed on the substrate to encapsulate the first semiconductor die, the second semiconductor die, and the third semiconductor die.

4. The method according to claim 1, characterized in that, Attaching the first active surface of the first semiconductor die to the second active surface of the second semiconductor die using hybrid bonding includes: A first interconnect layer is formed on a first active surface of the first semiconductor die, wherein the first interconnect layer includes a first dielectric layer and a first plurality of conductive structures extending through the first dielectric layer; A second interconnect layer is formed on a second active surface of the second semiconductor die, wherein the second interconnect layer includes a second dielectric layer and a second plurality of conductive structures extending through the second dielectric layer; and Hybrid bonding is used to attach the first interconnect layer to the second interconnect layer such that the first dielectric layer and the first plurality of conductive structures of the first interconnect layer are vertically aligned and bonded to the second dielectric layer and the second plurality of conductive structures of the second interconnect layer, respectively.

5. The method according to claim 4, characterized in that, The at least one wire bonding pad extends through the second dielectric layer of the second interconnect layer.

6. The method according to claim 5, characterized in that, The at least one wire bonding pad comprises copper or gold.

7. The method according to claim 5, characterized in that, The at least one wire bonding pad includes a lower portion containing copper and an upper portion containing gold.

8. The method according to claim 5, characterized in that, The upper surface of the at least one wire bonding pad is coplanar with the upper surface of the second dielectric layer, or is higher than the upper surface of the second dielectric layer.

9. The method according to claim 1, characterized in that, The at least one wire bonding pad is formed on the peripheral region of the second active surface of the second semiconductor die.

10. The method according to claim 1, characterized in that, The at least one wire bonding pad is formed near the edge of the second active surface of the second semiconductor die.

11. A semiconductor package, characterized in that, The semiconductor package includes: A first semiconductor die has a first active surface and a first non-active surface opposite to the first active surface; A second semiconductor die has a second active surface and a second non-active surface opposite to the second active surface, wherein at least one wire bonding pad is formed on the second active surface of the second semiconductor die, and a first active surface of the first semiconductor die is attached to the second active surface of the second semiconductor die using hybrid bonding, such that the at least one wire bonding pad is exposed from the first semiconductor die; and A sub-package comprising a substrate and a third semiconductor die mounted on the substrate, wherein a second non-active surface of the second semiconductor die is attached to the third semiconductor die, and the at least one wire bonding pad is electrically coupled to the substrate using wire bonding.

12. The semiconductor package according to claim 11, characterized in that, The semiconductor package further includes: An adhesive layer is formed on the third semiconductor die, wherein a second non-active surface of the second semiconductor die is attached to the third semiconductor die via the adhesive layer.

13. The semiconductor package according to claim 11, characterized in that, The semiconductor package further includes: A sealant is formed on the substrate to encapsulate the first semiconductor die, the second semiconductor die, and the third semiconductor die.

14. The semiconductor package according to claim 11, characterized in that, The semiconductor package further includes: A first interconnect layer is formed on a first active surface of the first semiconductor die, wherein the first interconnect layer includes a first dielectric layer and a first plurality of conductive structures extending through the first dielectric layer; and A second interconnect layer is formed on a second active surface of the second semiconductor die, wherein the second interconnect layer includes a second dielectric layer and a second plurality of conductive structures extending through the second dielectric layer. The first interconnect layer is attached to the second interconnect layer using hybrid bonding, such that the first dielectric layer and the first plurality of conductive structures of the first interconnect layer are vertically aligned and bonded to the second dielectric layer and the second plurality of conductive structures of the second interconnect layer, respectively.

15. The semiconductor package according to claim 14, characterized in that, The at least one wire bonding pad extends through the second dielectric layer of the second interconnect layer.

16. The semiconductor package according to claim 15, characterized in that, The at least one wire bonding pad comprises copper or gold.

17. The semiconductor package according to claim 15, characterized in that, The at least one wire bonding pad includes a lower portion containing copper and an upper portion containing gold.

18. The semiconductor package according to claim 15, characterized in that, The upper surface of the at least one wire bonding pad is coplanar with the upper surface of the second dielectric layer, or is higher than the upper surface of the second dielectric layer.

19. The semiconductor package according to claim 11, characterized in that, The at least one wire bonding pad is formed on the peripheral region of the second active surface of the second semiconductor die.

20. The semiconductor package according to claim 11, characterized in that, The at least one wire bonding pad is formed near the edge of the second active surface of the second semiconductor die.

Images