Driving circuit structure, display device and signal transmission method

Abstract

A driving circuit structure, a display device and a signal transmission method. The driving circuit structure comprises a controller (100) and a plurality of source driving chips (200). The controller (100) comprises a plurality of output ports (110), the number of the plurality of output ports (110) is less than the number of the plurality of source driving chips (200), and each of at least part of the output ports (110) is electrically connected with at least two source driving chips (200). The number of the connected output ports (110) in the plurality of source driving chips (200) is different. By increasing the number of the source driving chips (200), the number of the source driving chips (200) is greater than the number of the output ports (110), the exposure blocking of the display panel in the display device can be reduced, and the exposure times are reduced, so that the cost increase caused by the increase of the number of the source driving chips (200) can be balanced, and the overall manufacturing cost of the display panel can be reduced. Moreover, by setting the electrical connection relationship between the output port (110) and the source driving chip (200), the data mapping of the source driving chip (200) and the output port (110) can be realized.

Description

Drive circuit structure, display device and signal transmission method Technical Field

[0001] At least one embodiment of this disclosure relates to a driving circuit structure, a display device, and a signal transmission method. Background Technology

[0002] In a display device, a controller, such as a timing controller, can process each frame of image data, generate a corresponding output signal, and send it to the source driver. The source driver then transmits the corresponding data voltage to the data lines in the display panel to display the image. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a driving circuit structure, a display device, and a signal transmission method.

[0004] At least one embodiment of this disclosure provides a driving circuit structure, including: a controller and a plurality of source driver chips; wherein, the controller includes a plurality of output ports, the number of the plurality of output ports is less than the number of the plurality of source driver chips, and each of at least some of the output ports is electrically connected to at least two source driver chips; the number of output ports connected to at least two of the plurality of source driver chips is different.

[0005] For example, according to at least one embodiment of this disclosure, the plurality of source driver chips include at least one first driver chip and at least one second driver chip, each first driver chip being electrically connected to one of the output ports, and each second driver chip being electrically connected to at least two of the output ports.

[0006] For example, according to at least one embodiment of this disclosure, the number of output channels of different source driver chips is the same.

[0007] For example, according to at least one embodiment of the present disclosure, the driving circuit structure further includes a plurality of transmission elements; each transmission element includes a main body and a branch connected to each other, one end of the main body is provided with at least two branches; the other end of the main body of each transmission element is electrically connected to each output port in a one-to-one correspondence; each branch is electrically connected to one of the source driver chips, and different branches are electrically connected to different source driver chips, so that each output port is electrically connected to the at least two source driver chips through the at least two branches.

[0008] For example, according to at least one embodiment of this disclosure, the number of the plurality of output ports is M, the number of data signals of the output signals of each output port is N, the number of the plurality of source driver chips is A, and the number of output channels of each source driver chip is B; the output ports and the source driver chips satisfy M*N=A*B; where M<A and M, N, A, and B are all positive integers.

[0009] For example, according to at least one embodiment of the present disclosure, the driving circuit structure includes a mapping module configured to determine a mapping relationship between the output signal of the controller's output port and the valid received signal in the received signal of the source driver chip.

[0010] For example, according to at least one embodiment of this disclosure, the controller includes the mapping module, the mapping module includes a segmentation module, the segmentation module is configured to add at least one segmentation identifier signal to the signal received by the controller to obtain the output signal; the output signal of each output port includes at least two signal segments, the segmentation identifier signal is located between two adjacent signal segments in the at least two signal segments, and the at least two signal segments are arranged sequentially in time; each source driver chip is configured to acquire a received signal from at least one of the output ports, and is configured to acquire one signal segment of each received signal as a valid received signal, so as to update the electrical signal transmitted to the output channel of each source driver chip based on the signal segment.

[0011] For example, according to at least one embodiment of this disclosure, each of the signal segments includes a control packet signal and a data packet signal, and the control packet signals of the at least two signal segments correspond one-to-one with the at least two source driver chips; the source driver chip includes an update module, which is configured to obtain the signal segment corresponding to the source driver chip based on the control packet signal, and update the electrical signal transmitted to the output channel of each source driver chip based on the data packet signal in the corresponding signal segment.

[0012] For example, according to at least one embodiment of this disclosure, the control packet signal includes an identification signal corresponding to the source driver chip.

[0013] For example, according to at least one embodiment of this disclosure, the source driver chip includes the mapping module, the mapping module including a data selection module; the data selection module is configured to select the received signal to determine the valid received signal; the source driver chip is configured to update the electrical signals transmitted to the output channels of each source driver chip based on the valid received signal.

[0014] For example, according to at least one embodiment of this disclosure, the data selection module is configured to select the received signals after determining the number and timing information of the valid received signals.

[0015] For example, according to at least one embodiment of this disclosure, the mapping module includes a marking module and a counting module; the marking module is a module in the controller, and the counting module is a module in the source driver chip; the marking module is configured to mark the signal received by the controller to obtain the output signal; the output signal includes at least two counting marking signals, the at least two counting marking signals corresponding one-to-one with the at least two source driver chips; the counting module is configured to determine the valid received signal based on the cumulative counting of data signals in the received signal.

[0016] For example, according to at least one embodiment of this disclosure, the counting marker signal includes a channel marker and a counting threshold, and the counting module is configured to: acquire the counting threshold in the counting marker signal, and in response to the cumulative count value not exceeding the counting threshold, determine a valid received signal corresponding to the output channel of each source driver chip based on the channel marker.

[0017] At least one embodiment of this disclosure provides a display device including the driving circuit structure described in any of the above embodiments.

[0018] At least one embodiment of this disclosure provides a signal transmission method, comprising: mapping the output signals of each output port in at least a portion of the output ports of a controller to valid received signals in the received signals of a source driver chip, and updating the output channels of the source driver chip based on the received signals; wherein each output port of the controller sends the same output signal to at least two source driver chips, and the number of output ports from which the output signals mapped to the valid received signals of the at least two source driver chips originate is different.

[0019] For example, according to at least one embodiment of this disclosure, mapping the output signals of each output port in at least a portion of the output ports of the controller to valid received signals in the received signals of the source driver chip, and updating the output channels of the source driver chip based on the received signals, includes: adding at least one segment identification signal to the signal received by the controller to obtain the output signal; the output signal of each output port includes at least two signal segments, the segment identification signal being located between two adjacent signal segments in the at least two signal segments, and the at least two signal segments being arranged sequentially in time; acquiring received signals from at least one of the output ports, and being configured to acquire one signal segment of each received signal as a valid received signal, so as to update the electrical signals transmitted to the output channels of each source driver chip based on the signal segments.

[0020] For example, according to at least one embodiment of this disclosure, obtaining a signal segment from each received signal includes: obtaining a signal segment corresponding to the source driver chip based on the control packet signal, and updating the electrical signal transmitted to the output channel of each source driver chip based on the data packet signal in the corresponding signal segment; wherein, the control packet signals of the at least two signal segments correspond one-to-one with the at least two source driver chips.

[0021] For example, according to at least one embodiment of this disclosure, the control packet signal includes an identification signal corresponding to the source driver chip.

[0022] For example, according to at least one embodiment of this disclosure, mapping the output signals of each output port in at least a portion of the output ports of the controller to a valid received signal in the received signal of the source driver chip includes: selecting the received signal to determine the valid received signal.

[0023] For example, according to at least one embodiment of this disclosure, selecting the received signal includes: determining the number of valid received signals and timing information, and then selecting the received signal.

[0024] For example, according to at least one embodiment of this disclosure, mapping the output signals of each output port in at least a portion of the controller's output ports to valid received signals in the received signals of the source driver chips includes: marking the signals received by the controller to obtain the output signals; the output signals include at least two counting marker signals, the at least two counting marker signals corresponding one-to-one with the at least two source driver chips; and determining the valid received signals based on the cumulative counting of the data signals in the received signals.

[0025] For example, according to at least one embodiment of this disclosure, the counting marker signal includes a channel marker and a counting threshold; the step of determining the valid received signal based on the cumulative count of the data signals in the received signal includes: obtaining the counting threshold in the counting marker signal, and determining the valid received signal corresponding to the output channel of each source driver chip based on the channel marker in response to the cumulative count value not exceeding the counting threshold. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0027] Figure 1 is a schematic diagram of a driving circuit structure provided in at least one embodiment of the present disclosure.

[0028] Figure 2 is a partial structural schematic diagram of the driving circuit structure shown in Figure 1.

[0029] Figure 3 is a schematic diagram of the data mapping relationship between the controller and the source driver chip in the drive circuit structure shown in Figure 1.

[0030] Figure 4 is a schematic block diagram of a driving circuit structure provided in at least one embodiment of the present disclosure.

[0031] Figure 5 is a schematic diagram of the output signal provided in one example of at least one embodiment of the present disclosure.

[0032] Figure 6 is a schematic diagram of a source driver chip provided in at least one embodiment of this disclosure.

[0033] Figure 7 is a schematic diagram of the output signal provided in one example of at least one embodiment of the present disclosure.

[0034] Figure 8 is a schematic diagram of a source driver chip provided in at least one embodiment of this disclosure.

[0035] Figure 9 is a schematic diagram of the output signal provided in one example of at least one embodiment of the present disclosure.

[0036] Figure 10 is a schematic diagram of a source driver chip provided in at least one embodiment of the present disclosure.

[0037] Figure 11 is a schematic diagram of a source driver chip and data line provided in at least one embodiment of the present disclosure.

[0038] Figure 12 is a schematic flowchart of a signal transmission method provided in at least one embodiment of the present disclosure. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0040] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0041] The controller in the display device can send differential signals to the source driver IC. The source driver IC can receive digital signals (display signals, image signals, etc.) and control signals provided by the controller, and convert the digital signals into corresponding analog grayscale voltage signals through digital-to-analog conversion, which are then input into the data lines of the display panel to drive the pixel units. For example, the controller can be a timing controller (TCON).

[0042] In some display devices, the number of output ports of the controller is the same as the number of source driver chips, with each output port electrically connected to one source driver chip. During their research, the inventors of this application discovered that setting the number of output ports and the number of source driver chips differently can help reduce costs. However, how to achieve data mapping when the number of output ports and the number of source driver chips differs is a problem that urgently needs to be solved.

[0043] At least one embodiment of this disclosure provides a driving circuit structure, a display device, and a signal transmission method. The driving circuit structure includes a controller and a plurality of source driver chips. The controller includes a plurality of output ports, the number of which is less than the number of source driver chips, and each of at least some of the output ports is electrically connected to at least two source driver chips. The number of output ports connected to at least two of the plurality of source driver chips is different.

[0044] The driving circuit structure, display device, and signal transmission method provided in at least one embodiment of this disclosure increase the number of source driver chips, making the number of source driver chips greater than the number of output ports. This reduces the number of exposure blocks in the display panel of the display device, thereby reducing the number of exposures. This balances the cost increase caused by the increased number of source driver chips, resulting in a reduction in the overall manufacturing cost of the display panel. Furthermore, by establishing an electrical connection between the output ports and the source driver chips, data mapping between the source driver chips and the output ports is facilitated.

[0045] The driving circuit structure, display device, and signal transmission method are described below with reference to the accompanying drawings and through some embodiments.

[0046] Figure 1 is a schematic diagram of a driving circuit structure provided in at least one embodiment of the present disclosure.

[0047] Referring to Figure 1, the drive circuit structure includes a controller 100 and multiple source driver chips 200. The controller 100 includes multiple output ports 110, the number of which is less than the number of source driver chips 200. At least some of the output ports 110 are electrically connected to at least two source driver chips 200. For example, each of the at least some output ports may be electrically connected to two source driver chips. For example, each of the at least some output ports may be electrically connected to three or more source driver chips. For example, each of the multiple output ports may be electrically connected to two or more source driver chips. The number of output ports 110 connected to at least two of the multiple source driver chips 200 may differ. For example, two source driver chips may have different numbers of output ports connected to them. For example, three or more source driver chips may have different numbers of output ports connected to them. For example, among the multiple output ports, there may be an output port electrically connected to only one source driver chip. For example, the number of output ports electrically connected to a source driver chip can be one or more, and this disclosure does not limit this.

[0048] Referring to Figure 1, the driving circuit structure provided in this embodiment increases the number of source driver chips 200, making the number of source driver chips 200 greater than the number of output ports 110. This reduces the number of exposure blocks in the display panel of the display device, thereby reducing the number of exposures. This balances the cost increase caused by the increased number of source driver chips 200, thus reducing the overall manufacturing cost of the display panel. Furthermore, by setting the electrical connection between the output ports 110 and the source driver chips 200, it is beneficial to achieve data mapping between the source driver chips 200 and the output ports 110.

[0049] Specifically, this explanation will be based on an example where the controller has 12 output ports and the number of source driver chips is increased from 12 to 16. For instance, referring to Figure 1, the controller 100 with its drive circuit structure includes 12 output ports 110. By setting the electrical connections between the 12 output ports 110 and the 16 source driver chips 200, data transmission between the output ports 110 and the source driver chips 200 can be achieved without changing the structure of the controller 100. For example, without increasing the number of output ports 110 of the controller 100, the model of the controller 100 does not need to be changed, thus effectively controlling the manufacturing cost of the display panel.

[0050] Furthermore, referring to Figure 1, at least some of the output ports 110 are electrically connected to at least two source driver chips 200, and the number of output ports 110 connected to at least two of the multiple source driver chips 200 is different, so that the data output by the controller 100 can be received by the source driver chip 200, which helps to reduce data redundancy.

[0051] During the display process, video and animation are composed of multiple frames displayed sequentially in chronological order (e.g., frame rate of 60Hz or 120Hz). Each frame is a complete image displayed on the display panel. During the display of a frame, the gate driver chip sequentially activates each row of pixel units in the pixel array from the first row to the last row for scanning. During this scanning process, the source driver chip inputs the data signals required by each row of pixel units to the activated pixel units through data lines, thereby completing the scanning and display of one frame.

[0052] For example, each output port of the controller is electrically connected to at least two source driver chips, so that all the data output by the controller can be received by the source driver chips without any redundant data.

[0053] Referring to Figure 1, each output port 110 can output 960 data points. Each of the 12 source driver chips 200 includes 720 output channels, each corresponding one-to-one with a data line in the display panel. The data output from each output port 110 can be received by two source driver chips 200, and each source driver chip 200 can receive data from two output ports 110. Therefore, the total number of data signals output by the controller 100 matches the total number of output channels of all source driver chips 200, thus achieving data mapping between the output ports 110 of the controller 100 and the source driver chips 200.

[0054] For example, referring to Figure 1, controller 100 may include a timing controller (TCON). For example, the controller may include devices such as a system-on-a-chip (SOC), such as the timing controller, which can receive signals from the controller.

[0055] For example, to achieve narrower bezels in display panels, source driver chips can be bonded using a chip-on-film (COF) bonding method.

[0056] Referring to Figure 1, in some examples, the plurality of source driver chips 200 include at least one first driver chip 200A and at least one second driver chip 200B. Each first driver chip 200A is electrically connected to one output port 110, and each second driver chip 200B is electrically connected to at least two output ports 110. The different numbers of output ports 110 connected to the first driver chip 200A and the second driver chip 200B improve the flexibility of the electrical connection between the source driver chip 200 and the controller 100, making the data mapping between the source driver chip 200 and the output ports 110 easier to implement.

[0057] It should be noted that, referring to Figure 1, the only difference between the first driver chip 200A and the second driver chip 200B is the number of output ports 110 connected to them. For example, the structures of the first driver chip 200A and the second driver chip 200B can be completely identical.

[0058] For example, a plurality of source driver chips may include only one first driver chip, or it may include two or more first driver chips. Similarly, a plurality of source driver chips may include only one second driver chip, or it may include two or more second driver chips. Furthermore, a second driver chip may be electrically connected to two output ports, or it may be electrically connected to three or more output ports.

[0059] Figure 2 is a partial structural diagram of the drive circuit structure shown in Figure 1. Figure 3 is a schematic diagram of the data mapping relationship between the controller and the source driver chip in the drive circuit structure shown in Figure 1.

[0060] Referring to Figures 1 and 2, in some examples, the drive circuit structure also includes multiple transmission elements 300. Each transmission element 300 includes a main body 310 and branch portions 320 connected to each other, with at least two branch portions 320 provided at one end of the main body 310. For example, Figures 1 and 2 schematically show that the end of the main body 310 away from the controller 100 has two branch portions 320. However, this disclosure is not limited to this, and one end of the main body may also have three or more branch portions.

[0061] Referring to Figures 1 and 2, the other end of the main body 310 of each transmission element 300 is electrically connected to each output port 110 in a one-to-one correspondence. For example, the end of the main body 310 away from the branch 320 is connected to the output port 110. For example, the number of transmission elements 300 may be the same as the number of output ports 110.

[0062] Referring to Figures 1 and 2, each branch 320 is electrically connected to a source driver chip 200, and different branches 320 are electrically connected to different source driver chips 200, so that each output port 110 is electrically connected to at least two source driver chips 200 through at least two branches 320.

[0063] Referring to Figures 1 and 2, by setting the transmission element 300 to include a main body 310 and a branch 320, the output port 110 can be connected to the main body 310, and data can be transmitted to one or more source driver chips 200 via the branch 320.

[0064] For example, referring to FIG2, output port 1101 is electrically connected to the main body 3101, and transmits data to source driver chip 201 via branch 3201, and transmits data to source driver chip 202 via branch 3202. Output port 1102 is electrically connected to the main body 3102, and transmits data to source driver chip 202 via branch 3203. Thus, source driver chip 201 can receive data transmitted from output port 1101, and source driver chip 202 can receive data transmitted from both output port 1101 and output port 1102.

[0065] For example, referring to Figures 1 and 2, the transmission element 300 can be a set of differential signal lines, such as a pair (two) differential signal line pairs. For example, each connection line shown in Figures 1 and 2 between the output port 110 and the source driver chip 200 can represent a pair of differential signal line pairs, i.e., two differential signal lines. For example, each output port 110 is connected to one or more source driver chips 200 via a pair of differential signal line pairs so that the source driver chip 200 receives differential signals.

[0066] Referring to Figures 1 to 3, in some examples, the number of output channels of different source driver chips 200 is the same, which helps to simplify the electrical connection between the source driver chip 200 and the output port 110. For example, referring to Figure 3, each source driver chip 200 has 720 output channels. For example, the output channels of the source driver chip 200 can be pins (pads) on the source driver chip 200, and multiple output channels on the source driver chip 200 can be connected one-to-one with multiple data lines.

[0067] Referring to Figure 3, each output port 110 outputs 960 data signals. Taking a resolution of 3840×2160 as an example, a row of pixel units needs to receive the three electrical signals required by the red, green, and blue sub-pixels respectively. Therefore, the data signal corresponding to a row of pixel units is 3840×3, and a row of pixel units needs to be provided with data by 3840×3÷960=12 source driver chips.

[0068] Referring to Figures 1 to 3, in some examples, the number of output ports 110 is M, the number of data signals output from each output port 110 is N, the number of source driver chips 200 is A, and the number of output channels of each source driver chip 200 is B. The output ports 110 and source driver chips 200 satisfy M*N = A*B, where M < A and M, N, A, and B are all positive integers. By setting the mathematical relationship between the number of output ports 110 and the number of data signals output, and the number of source driver chips 200 and the number of output channels, the total number of output signals from all output ports 110 can be made the same as the total number of output channels of the source driver chips 200, thus preventing data redundancy.

[0069] For example, in conjunction with the examples described later, the data signal can be the data signal in the data packet signal of the output signal.

[0070] It should be noted that, in this embodiment of the disclosure, the number of multiple output ports 110 shown in FIG1 is 12, the number of data signals of the output signals of each output port 110 is 960, the number of multiple source driver chips 200 is 16, and the number of output channels of each source driver chip 200 is 720, as an example.

[0071] Figure 4 is a schematic block diagram of a driving circuit structure provided in at least one embodiment of the present disclosure.

[0072] Referring to Figure 4, the drive circuit structure includes a mapping module 01. The mapping module 01 is configured to determine the mapping relationship between the output signal of the output port 110 of the controller 100 and the valid received signal in the received signal of the source driver chip 200. By setting the mapping module 01 to determine the mapping relationship, data mapping between a different number of controllers 100 and the source driver chip 200 can be realized.

[0073] For example, the output signal of output port 110 can be the same as the received signal of source driver chip 200. For example, source driver chip 200 can select a portion or all of the received signals as valid received signals, process the valid received signals, and then transmit them outward through the output channel.

[0074] For example, Figure 4 schematically illustrates that the source driver chip 200 may include a mapping module 01, while the controller 100 does not include a mapping module 01. However, this disclosure is not limited to this; for example, the controller may include a mapping module, while the source driver chip may not include a mapping module. For example, the controller may include a mapping module, and the source driver chip may also include a mapping module. For example, the mapping module may also be a module other than the controller and the source driver chip.

[0075] Figure 5 is a schematic diagram of the output signal provided in one example of at least one embodiment of the present disclosure. Figure 6 is a schematic diagram of the source driver chip provided in one example of at least one embodiment of the present disclosure.

[0076] Referring to Figures 5 and 6, the controller 100 includes a mapping module 01, which includes a segmentation module 120. The segmentation module 120 is configured to add at least one segmentation identifier signal K0 to the signal received by the controller 100 to obtain an output signal. The output signal of each output port 110 includes at least two signal segments S, and the segmentation identifier signal K0 is located between at least two adjacent signal segments S, and the at least two signal segments S are arranged sequentially in time.

[0077] Referring to Figures 2, 3, 5, and 6, for example, when each output port 110 is electrically connected to two source driver chips 200, the output signal may include two signal segments S (signal segment S1 and signal segment S2). The two signal segments S correspond one-to-one with the two source driver chips 200. However, this disclosure is not limited to this. For example, when each output port is electrically connected to three or more source driver chips, the output signal may include three or more signal segments to achieve a one-to-one correspondence between the signal segments and the source driver chips.

[0078] Referring to Figures 2, 3, 5, and 6, in some examples, each source driver chip 200 is configured to acquire a received signal from at least one output port 110, and is configured to acquire a signal segment S from each received signal as a valid received signal, so as to update the electrical signal transmitted to the output channel of each source driver chip 200 based on the signal segment S. By segmenting the output signal, after the source driver chip 200 receives the received signal, it can select a signal segment S that matches the source driver chip 200, and update the electrical signal transmitted to the output channel of the source driver chip 200 based on the signal segment S. For example, the source driver chip 200 can process the signal segment S to update the electrical signal of the output channel, such as voltage or current.

[0079] Referring to Figures 2, 3, and 5, for example, source driver chip 201 receives a received signal from output port 1101, and source driver chip 202 receives both the received signal from output port 1101 and the received signal from output port 1102. However, this disclosure is not limited thereto; when the source driver chip is connected to two or more output ports, it can also receive three or more received signals.

[0080] Referring to Figures 2, 3, 5, and 6, for example, source driver chip 201 can select one signal segment (such as signal segment S1) from the received signals from output port 1101 to update the electrical signals transmitted to the output channel of source driver chip 200. For example, source driver chip 202 can select another signal segment (such as signal segment S2) from the received signals from output port 1101, and select one signal segment from the received signals from output port 1102 to update the electrical signals transmitted to the output channel of source driver chip 200. For example, source driver chip 203 can select one signal segment from the received signals from output port 1102 and output port 1103 respectively to update the electrical signals transmitted to the output channel of source driver chip 200. For example, source driver chip 204 can select one signal segment from the received signals from output port 1104 to update the electrical signals transmitted to the output channel of source driver chip 200.

[0081] It is understandable that different source driver chips may select different signal segments from the received signals from the same output port. For example, the signal segment S1 selected by source driver chip 201 from output port 1101 may differ from the signal segment S2 selected by source driver chip 202 from output port 1101, even if the signal segments S1 and S2 are arranged in a timing sequence.

[0082] Referring to Figures 5 and 6, in some examples, each signal segment S includes control packet signals and data packet signals, and the control packet signals of at least two signal segments S correspond one-to-one with at least two source driver chips 200. For example, among the multiple control packet signals of multiple signal segments, at least two control packet signals are different to identify the corresponding source driver chips. For example, when each output port is electrically connected to two source driver chips, the two control packet signals of the two signal segments are different to correspond one-to-one with the two source driver chips.

[0083] For example, a control packet signal can be a line control (Ctrl_L) packet signal. For example, a data packet signal can be a video line signal.

[0084] For example, referring to Figure 5, in signal segment S, the control packet signal and the data packet signal are arranged sequentially in timing, such that the timing of the control packet signal precedes that of the data packet signal. Therefore, after the source driver chip obtains the control packet signal, it can determine whether the signal segment corresponds to the source driver chip, and thus determine whether it is necessary to update the electrical signal transmitted to the output channel of the source driver chip based on the data packet signal in that signal segment.

[0085] Referring to Figures 5 and 6, in some examples, the source driver chip 200 includes an update module 210. The update module 210 is configured to acquire a signal segment S corresponding to the source driver chip 200 based on a control packet signal, and update the electrical signals transmitted to the output channels of each source driver chip 200 based on the data packet signals in the corresponding signal segment S. The update module 210 can acquire configuration information of the control packet signal from the received signal received by the source driver chip 200, thereby selecting the signal segment corresponding to the source driver chip 200 from multiple signal segments of the received signal.

[0086] Referring to Figures 5 and 6, in some examples, the control packet signal includes an identification signal corresponding to the source driver chip 200. For example, the update module 210 can determine the correspondence between the signal segment S containing the control packet signal and the source driver chip 200 based on the identification signal in the control packet signal.

[0087] For example, the controller can send output signals according to a preset communication protocol. For example, a segmentation identifier signal K0 can be added to the output signal based on the Clock-embedded High-speed Point-to-point Interface (CHPI) protocol. For example, in the output signal conforming to the above preset communication protocol, the control packet signal may also include a Multi Drop Mode Enable (MDEN) identifier and a Multi Drop Identification (MDID) identifier.

[0088] For example, MDEN is used to define whether the output signal is sent according to the segmented format including signal segments as described above. For example, MDID is used to indicate the correspondence between the signal segments and the source driver chip 200. For example, when MDEN is a high-level (H) signal, it indicates that the output signal is sent according to the segmented format described above; when MDEN is a low-level (L) signal, it indicates that the output signal is not sent according to the segmented format described above. For example, when MDID is a high-level (H) signal, it indicates that the timing of this signal segment comes first, as shown in signal segment S1 in Figure 5. When MDID is a low-level (L) signal, it indicates that the timing of this signal segment comes later, as shown in signal segment S2 in Figure 5. By identifying the timing sequence of the signal segments, the correspondence between the signal segments and the source driver chip can be achieved.

[0089] Specifically, the example shown in Figure 2, which consists of three output ports and four source driver chips, will be used for illustration. Referring to Figures 2, 3, 5, and 6, the controller 100 includes output ports 1101, 1102, and 1103, and each output port supports outputting 960 data points in a single line of signal. Source driver chips 201, 202, 203, and 204 each include 720 output channels, and each output channel is connected to a corresponding data line in the display panel.

[0090] For example, referring to Figures 2, 3, 5 and 6, for the output signals sent by output ports 1101, 1102 and 1103, MDEN is H and MDID is H in the control packet signal of signal segment S1, and MDEN is H and MDID is L in the control packet signal of signal segment S2.

[0091] Referring to Figures 2, 3, 5, and 6, after the source driver chip 201 receives the received signal from the output port 1101, the update module 210 obtains the configuration of MDEN and MDID in the control packet signals of signal segment S1 and signal segment S2, respectively, thereby determining that the source driver chip 201 selects signal segment S1, and uses the data packet signal in signal segment S1 to update the electrical signals transmitted to the first to the 720th output channels of the source driver chip 201.

[0092] For example, referring to Figures 2, 3, 5 and 6, after the source driver chip 202 receives the received signal from the output port 1101, the update module 210 obtains the configuration of MDEN and MDID in the control packet signals of signal segment S1 and signal segment S2 respectively, thereby determining that the source driver chip 202 selects signal segment S2, and uses the data packet signal in signal segment S2 to update the electrical signals of the first 240 output channels (i.e., the electrical signals of the first to the 240th output channels) transmitted to the source driver chip 201. The source driver chip 202 also receives the received signal from the output port 1102. The update module 210 obtains the configuration of MDEN and MDID in the control packet signals of signal segment S1 and signal segment S2 respectively, thereby determining that the source driver chip 202 selects signal segment S1, and uses the data packet signal in signal segment S1 to update the electrical signals of the last 480 output channels (i.e., the electrical signals of the 241st to 720th output channels) transmitted to the source driver chip 202.

[0093] For example, referring to Figures 2, 3, 5 and 6, after the source driver chip 203 receives the received signal from the output port 1102, the update module 210 obtains the configuration of MDEN and MDID in the control packet signals of signal segment S1 and signal segment S2 respectively, thereby determining that the source driver chip 203 selects signal segment S2, and uses the data packet signal in signal segment S2 to update the electrical signals transmitted to the first 480 output channels (i.e., the first output channel to the 480th output channel) of the source driver chip 203. The source driver chip 203 also receives the received signal from the output port 1103. The update module 210 obtains the configuration of MDEN and MDID in the control packet signals of signal segment S1 and signal segment S2 respectively, thereby determining that the source driver chip 203 selects signal segment S1, and uses the data packet signal in signal segment S1 to update the electrical signals of the last 240 output channels (i.e., the electrical signals of the 481st to 720th output channels) transmitted to the source driver chip 203.

[0094] Referring to Figures 2, 3, 5, and 6, after the source driver chip 204 receives the received signal from the output port 1103, the update module 210 obtains the configuration of MDEN and MDID in the control packet signals of signal segment S1 and signal segment S2, respectively, thereby determining that the source driver chip 204 selects signal segment S2, and uses the data packet signal in signal segment S2 to update the electrical signals transmitted to the first to the 720th output channels of the source driver chip 204.

[0095] Referring to Figures 2, 3, 5, and 6, based on the above, data mapping can be achieved between the three output ports (output port 1101, output port 1102, and output port 1103) of the controller 100 and the four source driver chips 200 (source driver chip 201, source driver chip 202, source driver chip 203, and source driver chip 204). After obtaining the corresponding signal segment and updating the electrical signal (e.g., voltage) transmitted to the output channel, the source driver chip 200 can output the electrical signal to the corresponding data line.

[0096] Referring to Figure 5, the output signals also include a start flag signal K1 and a stop flag signal K2. The start flag signal K1 is used to indicate the start position of each output signal, and the stop flag signal K2 is used to indicate the stop position of each output signal.

[0097] Referring to Figure 5, for example, the segment identification signal K0 can be exactly the same as the start identification signal K1. For example, the segment identification signal K0 can be regarded as the start identification signal of signal segment S2. For example, an empty packet can also be included after the end identification signal K2.

[0098] Referring to Figure 6, for example, the source driver chip 200 may also include other components such as a receive module 21, a buffer 22, a line latch 23, and a channel operational amplifier 24.

[0099] Referring to Figure 6, for example, after the controller 100 receives a signal from an external source (such as a system-on-a-chip), it can encode and process the signal before sending it. Then, the receiving module 21 can receive the output signal sent by the controller 100 and decode the received signal to reconstruct the original signal. For example, the signal received by the receiving module 21 can be exactly the same as the output signal output from the output port 110 of the controller 100.

[0100] Referring to Figure 6, for example, if the control packet signal of the output signal sent by the controller 100 includes MDEN and MDID, the receiving module 21 can obtain MDEN and MDID after decoding, so that the updating module 210 can determine the valid received signal corresponding to the source driver chip according to the configuration of MDEN and MDID.

[0101] Referring to Figure 6, for example, after the update module 210 determines the signal segment corresponding to the source driver chip 200, the data packet signal in the signal segment can be updated to the buffer 22.

[0102] Referring to Figure 6, for example, the data latch 23 can be used to temporarily store a row of data, and the channel operational amplifier 24 can be used to amplify the signal to facilitate the accurate display of information such as the brightness and color of the image.

[0103] For example, the source driver chip may also include an output module, which can control each output channel to synchronously output voltage to the data line based on instructions such as a synchronization signal.

[0104] It is understood that the source driver chip may also include modules such as digital-to-analog conversion modules, logic control modules, and power management modules, and this disclosure does not impose any restrictions on these.

[0105] Figure 7 is a schematic diagram of the output signal provided in one example of at least one embodiment of the present disclosure. Figure 8 is a schematic diagram of the source driver chip provided in one example of at least one embodiment of the present disclosure.

[0106] The difference between the output signal shown in Figure 7 and the output signal shown in Figure 5 is that the output signal shown in Figure 7 does not include an identification signal. The difference between the source driver chip shown in Figure 8 and the source driver chip shown in Figure 6 is that the source driver chip shown in Figure 8 includes a data selection module.

[0107] Referring to Figures 7 and 8, in some examples, the source driver chip 200 includes a mapping module 01, which includes a data selection module 220. The data selection module 220 is configured to select received signals to determine valid received signals. The source driver chip 200 is configured to update the electrical signals transmitted to the output channels of each source driver chip based on the valid received signals. Therefore, by adding the data selection module 220 to the source driver chip 200, the data selection module 220 can automatically allocate received signals, select valid received signals, and thus update the electrical signals transmitted to the output channels of each source driver chip based on the valid received signals. In this case, the output signal output by the controller 100 does not need to carry an additional identification signal, that is, no additional settings are required for the controller 100. For example, no other hardware modules need to be added to the controller 100, nor is it necessary to add identification signals to the interface protocol of the controller 100's output interface.

[0108] Referring to Figures 7 and 8, in some examples, the data selection module 220 is configured to select received signals after determining the number and timing information of valid received signals for the source driver chip 200. For example, the number of valid received signals refers to the number of electrical signals used to update the output channels of each source driver chip. For example, the timing information of valid received signals refers to the update timing of the electrical signals used to update the output channels of each source driver chip.

[0109] Referring to Figures 3, 7, and 8, for example, output port 1101 sends the same output signal to source driver chips 201 and 202. Output port 1102 sends the same output signal to source driver chips 202 and 203. Output port 1103 sends the same output signal to source driver chips 203 and 204. Accordingly, source driver chip 201 can receive the received signal from output port 1101. Source driver chip 202 can receive both the received signal from output port 1101 and the received signal from output port 1102. Source driver chip 203 can receive both the received signal from output port 1102 and the received signal from output port 1103. Source driver chip 204 can receive the received signal from output port 1103.

[0110] Referring to Figures 3, 7, and 8, the data selection module 2201 in the source driver chip 201 can select the first to the 720th data signals in the data packet signal from the received signals received from the output port 1101, and the first to the 720th data signals are used to update the electrical signals transmitted to the first to the 720th output channels of the source driver chip 201, respectively.

[0111] Referring to Figures 3, 7, and 8, the data selection module 2202 in the source driver chip 202 can select the 721st to 960th data signals as valid received signals from the received signals received from the output port 1101. These 721st to 960th data signals are used to update the electrical signals transmitted to the 1st to 240th output channels of the source driver chip 202, respectively. The data selection module 2202 can also select the 1st to 480th data signals as valid received signals from the received signals received from the output port 1102. These 1st to 480th data signals are used to update the electrical signals transmitted to the 241st to 720th output channels of the source driver chip 202, respectively.

[0112] Referring to Figures 3, 7, and 8, for example, since output ports 1101 and 1102 simultaneously output the first data signal in the output signals, the time when the source driver chip 201 receives the first data signal from output port 1101 is the same as the time when the source driver chip 202 receives the first data signal from output port 1102.

[0113] Referring to Figures 3, 7, and 8, the data selection module in the source driver chip 203 can select the 481st to 960th data signals as valid received signals from the received signals received from the output port 1102. These 481st to 960th data signals are used to update the electrical signals transmitted to the 1st to 480th output channels of the source driver chip 203, respectively. The data selection module in the source driver chip 203 can also select the 1st to 240th data signals as valid received signals from the received signals received from the output port 1103. These 1st to 240th data signals are used to update the electrical signals transmitted to the 481st to 720th output channels of the source driver chip 203, respectively.

[0114] Referring to Figures 3, 7, and 8, for example, since output ports 1102 and 1103 simultaneously output the first data signal in the output signals, the time when the source driver chip 201 receives the first data signal from output port 1101 is the same as the time when the source driver chip 203 receives the first data signal from output port 1103.

[0115] Referring to Figures 3, 7, and 8, the data selection module in the source driver chip 204 can select the 241st to 960th data signals as valid received signals from the received signals received from the output port 1103. The 241st to 960th data signals are used to update the electrical signals transmitted to the 1st to 720th output channels of the source driver chip 204, respectively.

[0116] Figure 9 is a schematic diagram of the output signal provided in one example of at least one embodiment of the present disclosure. Figure 10 is a schematic diagram of the source driver chip provided in one example of at least one embodiment of the present disclosure.

[0117] The difference between the output signal shown in Figure 9 and the output signal shown in Figure 7 is that the output signal shown in Figure 9 includes a counting marker signal. The difference between the source driver chip shown in Figure 10 and the source driver chip shown in Figure 8 is that the source driver chip shown in Figure 10 includes a counting module.

[0118] Referring to Figures 9 and 10, in some examples, the mapping module 01 includes a marking module 130 and a counting module 230. The marking module 130 is a module in the controller 100, and the counting module 230 is a module in the source driver chip 200. The marking module 130 is configured to mark the signals received by the controller 100 to obtain an output signal. The output signal includes at least two counting mark signals, each corresponding one-to-one with at least two source driver chips 200, so as to mark the counting rules corresponding to each source driver chip 200 using the counting mark signals.

[0119] Referring to Figures 9 and 10, in some examples, the counting module 230 is configured to cumulatively count the data signal in the received signal based on the counting marker signal to determine the valid received signal. By setting the marker module 130 and the counting module 230, the controller 100 and the source driver chip 200 can cooperate to perform counting by the counting module 230 based on the counting marker signal in the output signal sent by the controller 100, thereby achieving data mapping.

[0120] For example, the controller's output signals may include control packet signals and data packet signals. The control packet signals may include counting marker signals, and the data packet signals may include data signals. For example, the controller can send encoded signals, and the source driver chip can decode the received signals to obtain the decoded control packet signals and data packet signals. The counting module can accumulate and count the data signals in the data packet signals.

[0121] Referring to Figures 2, 3, 9, and 10, for example, when each output port 110 is electrically connected to two source driver chips 200, the output signal may include two counting marker signals. Each of the two counting marker signals corresponds one-to-one with one of the two source driver chips 200. For example, when each output port is electrically connected to three or more source driver chips, the output signal may correspondingly include three or more counting marker signals; this disclosure does not impose any limitations on this.

[0122] Referring to Figures 9 and 10, in some examples, the counting marker signal includes a channel marker and a counting threshold. The counting module 230 is configured to: acquire the counting threshold from the counting marker signal; and, in response to the accumulated count value not exceeding the counting threshold, determine the valid received signal corresponding to the output channel of each source driver chip 200 based on the channel marker. Thus, when the count value does not exceed the counting threshold, the source driver chip 200 can use the received signal as a valid received signal and update the electrical signal transmitted to the corresponding output channel based on the valid received signal. When the count value exceeds the counting threshold, the source driver chip 200 no longer uses the received signal as a valid received signal, i.e., it does not use it to update the electrical signal transmitted to the output channel.

[0123] Referring to Figures 9 and 10, for example, channel markers can be used to mark the correspondence between valid received signals received by the source driver chip 200 and the output channels of the source driver chip 200. For example, the correspondence between valid received signals received by the source driver chip and the output channels of the source driver chip can be determined based on the timing of the output signals.

[0124] For example, cumulative counting refers to counting within each counting threshold.

[0125] For example, referring to Figures 3, 9, and 10, the counting marker signal can use a 10-bit marking method. For example, when output port 1101 simultaneously sends output signals to source driver chip 201 and source driver chip 202, "M_NUM:1011010000" can be used to mark the 720 data signals with the earliest timing sequence that source driver chip 201 needs to receive in the data packet signal, and "S_NUM:0011110000" can be used to mark the 240 data signals with the latest timing sequence that source driver chip 202 needs to receive in the data packet signal.

[0126] Referring to Figures 3, 9, and 10, for example, the count marker signal in the output signal sent by the output port 1101 of the controller 100 can be used to mark that the number of valid received signals to be received by the source driver chip 201 is 720 and the number of valid received signals to be received by the source driver chip 202 is 240. For example, the count marker signal in the output signal sent by the output port 1102 of the controller 100 can be used to mark that the number of valid received signals to be received by the source driver chip 202 is 480 and the number of valid received signals to be received by the source driver chip 203 is 480. For example, the count marker signal in the output signal sent by the output port 1103 of the controller 100 can be used to mark that the number of valid received signals to be received by the source driver chip 203 is 240 and the number of valid received signals to be received by the source driver chip 204 is 720.

[0127] For example, referring to Figures 3, 9, and 10, based on the counting marker signal in the output signal sent by the output port 1101 of the controller 100, it is determined that the source driver chip 201 accumulates counts for the 720 data signals with earlier timings within the counting threshold 720, and the source driver chip 202 accumulates counts for the 240 data signals with later timings within the counting threshold 240. Based on the counting marker signal in the output signal sent by the output port 1102 of the controller 100, it is determined that the source driver chip 202 accumulates counts for the 480 data signals with earlier timings within the counting threshold 480, and the source driver chip 203 accumulates counts for the 480 data signals with later timings within the counting threshold 480. Based on the counting marker signal in the output signal sent by the output port 1103 of the controller 100, it is determined that the source driver chip 203 accumulates the count of the 240 data signals with the earlier timing within the counting threshold 240, and the source driver chip 204 accumulates the count of the 720 data signals with the later timing within the counting threshold 720.

[0128] Referring to Figures 3, 9, and 10, the process of source driver chips 201 and 202 receiving valid received signals from output port 1101 will be described as an example. It is understood that the data transmission process between source driver chips 202, 203, and 204 and output ports 1102 and 1103 will not be described in detail in this disclosure.

[0129] Referring to Figures 3, 9, and 10, the source driver chip 201 accumulates a count of the first received data signal. If the count value accumulated by the counting module 230 in the source driver chip 201 does not reach the counting threshold 720 (i.e., the accumulated count value is not greater than 720), the received data signal is considered a valid received signal. For example, if the accumulated count value is greater than 720 (e.g., 721), the data signal received by the source driver chip 201 is no longer considered a valid received signal.

[0130] For example, referring to Figures 3, 9, and 10, the source driver chip 202 accumulates a count of the 721st received data signal. If the count value accumulated by the counting module 230 in the source driver chip 202 does not reach the counting threshold 240 (i.e., the accumulated count value is not greater than 240), the received data signal is considered a valid received signal. For example, if the accumulated count value is greater than 240 (e.g., 241), the data signal received by the source driver chip 201 is no longer considered a valid received signal.

[0131] Figure 11 is a schematic diagram of a source driver chip and data line provided in at least one embodiment of the present disclosure.

[0132] This disclosure also provides a display device, including a display panel and the driving circuit structure described in any of the above examples. Referring to FIG11, the source driver chip 200 is electrically connected to the data line 400 of the display panel. Since the display device according to the embodiments of this disclosure includes the above-described driving circuit structure, it also has corresponding beneficial technical effects, which will not be elaborated here.

[0133] For example, referring to Figure 11, the output channel 2001 of the source driver chip 200 is electrically connected to the data line 400. For example, the output channel 2001 of the source driver chip and the data line 400 can be electrically connected using anisotropic conductive adhesive (ACA).

[0134] For example, in conjunction with the foregoing examples, FIG11 schematically illustrates that the output channel 2001 of the source driver chip 200 can be a pin on the source driver chip, and one pin is electrically connected to a corresponding data line. For example, FIG11 only schematically illustrates six output channels 2001 and six data lines on a source driver chip 200, but this disclosure is not limited thereto. For example, the ellipsis shown in FIG11 indicates that the source driver chip 200 may include a total of 720 output channels 2001, so that the source driver chip 200 can be electrically connected to 720 data lines 400 through 720 output channels 2001.

[0135] For example, the display device can be a liquid crystal display device, electronic paper, OLED (Organic Light-Emitting Diode) display, or any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator, and this embodiment is not limited thereto.

[0136] Figure 12 is a schematic flowchart of a signal transmission method provided in at least one embodiment of the present disclosure.

[0137] Referring to Figure 12, at least one embodiment of this disclosure provides a signal transmission method, including step S1: mapping the output signals of each output port in at least a portion of the output ports of a controller to the valid received signals in the received signals of a source driver chip, and updating the output channels of the source driver chip based on the received signals. Each output port of the controller sends the same output signal to at least two source driver chips, and the number of output signals mapped to the valid received signals of at least two source driver chips from different output ports.

[0138] For example, step S1 described above can be executed by the mapping module in the aforementioned example. For details, please refer to Figures 1 to 4 for the relevant description of the mapping module; further details are omitted here.

[0139] Referring to Figure 12, in some examples, step S1 includes: adding at least one segment identification signal to the signal received by the controller to obtain an output signal. The output signal of each output port includes at least two signal segments, with the segment identification signal located between two adjacent signal segments, and the at least two signal segments are sequentially arranged in time. Received signals from at least one output port are acquired, and configured to acquire one signal segment from each received signal as a valid received signal to update the electrical signals transmitted to the output channels of each source driver chip based on the signal segments.

[0140] For example, the above steps can be executed jointly by the segmentation module and the source driver chip in the controller, as described in the previous example. For details, please refer to Figures 5 and 6 for the aforementioned description of the segmentation module and the source driver chip; these details will not be repeated here.

[0141] In some examples, acquiring a signal segment from each received signal includes: acquiring the signal segment corresponding to the source driver chip based on the control packet signal, and updating the electrical signals transmitted to the output channels of each source driver chip based on the data packet signals in the corresponding signal segment. The control packet signals of at least two signal segments correspond one-to-one with at least two source driver chips.

[0142] In some examples, the control packet signal includes an identification signal corresponding to the source driver chip.

[0143] For example, the above steps can be executed jointly by the segmentation module in the controller and the update module in the source driver chip in the aforementioned example. For details, please refer to Figures 5 and 6 for the aforementioned description of the segmentation module and the source driver chip; these details will not be repeated here.

[0144] In some examples, mapping the output signals of each output port in at least a portion of the controller's output ports to valid received signals in the received signals of the source driver chip includes: selecting the received signals to determine valid received signals.

[0145] For example, the above steps can be performed by the data selection module in the source driver chip in the aforementioned example. For details, please refer to Figures 7 and 8 for the relevant description of the aforementioned data selection module; further details are omitted here.

[0146] In some examples, selecting the received signal includes: determining the number of valid received signals and timing information, and then selecting the received signal.

[0147] For example, the above steps can be performed by the data selection module in the aforementioned example. For details, please refer to Figures 7 and 8 for the relevant description of the aforementioned data selection module; further details are omitted here.

[0148] In some examples, mapping the output signals of each output port in at least a portion of the controller's output ports to valid received signals in the received signals of the source driver chips includes: marking the signals received by the controller to obtain output signals; the output signals include at least two counting marker signals, each of which corresponds one-to-one with at least two source driver chips; and determining valid received signals based on the cumulative count of data signals in the received received signals.

[0149] For example, the above steps can be performed jointly by the marking module in the controller and the counting module in the source driver chip in the aforementioned example. For details, please refer to Figures 9 and 10 for the relevant descriptions of the marking module in the controller and the counting module in the source driver chip; these will not be repeated here.

[0150] In some examples, the counting marker signal includes a channel marker and a counting threshold; determining a valid received signal based on the cumulative count of data signals in the received received signal includes: acquiring the counting threshold in the counting marker signal; in response to the cumulative count value not exceeding the counting threshold, determining the valid received signal corresponding to the output channel of each source driver chip based on the channel marker.

[0151] For example, the above steps can be performed by the counting module in the aforementioned example. For details, please refer to Figures 9 and 10 for the relevant description of the aforementioned counting module; further details are omitted here.

[0152] It should be noted that, in order to clearly illustrate the working logic of the drive circuit structure, Figures 4, 6, 8 and 10 schematically show the modules that implement signal transmission with rectangular boxes to illustrate the signal transmission process between the controller and the source drive chip.

[0153] In this embodiment of the invention, the module can be implemented in software so that it can be executed by various types of processors. For example, an identified executable code module may include one or more physical or logical blocks of computer instructions, which may be constructed as objects, procedures, or functions. Nevertheless, the executable code of the identified module does not need to be physically located together, but may include different instructions stored on different physical locations. When these instructions are logically combined, they constitute the module and achieve the module's intended purpose.

[0154] In practice, an executable code module can be a single instruction or many instructions, and can even be distributed across multiple different code segments, different programs, and across multiple memory devices. Similarly, operational data can be identified within the module and can be implemented in any suitable form and organized within any suitable type of data structure. This operational data can be collected as a single dataset or distributed across different locations (including different storage devices), and can exist, at least in part, solely as electronic signals within the system or network.

[0155] When a module can be implemented using software, considering the current level of hardware technology, modules that can be implemented in software can be implemented using hardware circuits by those skilled in the art to achieve the corresponding functions, without considering cost. These hardware circuits include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors such as logic chips and transistors, or other discrete components. Modules can also be implemented using programmable hardware devices, such as field-programmable gate arrays, programmable array logic, and programmable logic devices.

[0156] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0157] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0158] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0159] The following points need to be explained:

[0160] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0161] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0162] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A driving circuit structure, comprising: Controller and multiple source driver chips; The controller includes multiple output ports, the number of which is less than the number of multiple source driver chips, and each of the output ports is electrically connected to at least two source driver chips. At least two of the multiple source driver chips have different numbers of connected output ports.

2. The driving circuit structure according to claim 1, wherein, The plurality of source driver chips include at least one first driver chip and at least one second driver chip, each first driver chip being electrically connected to one of the output ports, and each second driver chip being electrically connected to at least two of the output ports.

3. The driving circuit structure according to claim 1 or 2, wherein, The number of output channels is the same for all different source driver chips.

4. The driving circuit structure according to any one of claims 1-3 further includes a plurality of transmission elements; each transmission element includes a main body and a branch connected to each other, and one end of the main body is provided with at least two branches; The other end of the main body of each transmission element is electrically connected to each output port in a corresponding manner; Each of the branches is electrically connected to one of the source driver chips, and different branches are electrically connected to different source driver chips, so that each output port is electrically connected to the at least two source driver chips through the at least two branches.

5. The driving circuit structure according to any one of claims 1-4, wherein, The number of the plurality of output ports is M, the number of data signals of the output signals of each output port is N, the number of the plurality of source driver chips is A, and the number of output channels of each source driver chip is B; The output port and the source driver chip satisfy M*N=A*B; Where M < A and M, N, A, and B are all positive integers.

6. The driving circuit structure according to any one of claims 1-5, wherein, The driving circuit structure includes a mapping module, which is configured to determine the mapping relationship between the output signal of the controller's output port and the valid received signal in the received signal of the source driver chip.

7. The driving circuit structure according to claim 6, wherein, The controller includes the mapping module, which includes a segmentation module. The segmentation module is configured to add at least one segmentation identifier signal to the signal received by the controller to obtain the output signal. The output signal of each output port includes at least two signal segments, the segment identification signal is located between two adjacent signal segments, and the at least two signal segments are arranged sequentially in time. Each source driver chip is configured to acquire a received signal from at least one of the output ports, and is configured to acquire a signal segment of each received signal as a valid received signal, so as to update the electrical signal transmitted to the output channel of each source driver chip based on the signal segment.

8. The driving circuit structure according to claim 7, wherein, Each of the signal segments includes control packet signals and data packet signals, and the control packet signals of the at least two signal segments correspond one-to-one with the at least two source driver chips; The source driver chip includes an update module, which is configured to acquire signal segments corresponding to the source driver chip based on the control packet signal, and update the electrical signals transmitted to the output channels of each source driver chip based on the data packet signals in the corresponding signal segments.

9. The driving circuit structure according to claim 8, wherein, The control packet signal includes an identification signal corresponding to the source driver chip.

10. The driving circuit structure according to claim 6, wherein, The source driver chip includes the mapping module, and the mapping module includes a data selection module; The data selection module is configured to select the received signal to determine the valid received signal; The source driver chip is configured to update the electrical signals transmitted to the output channels of each source driver chip based on the valid received signal.

11. The driving circuit structure according to claim 10, wherein, The data selection module is configured to select the received signals after determining the number and timing information of the valid received signals.

12. The driving circuit structure according to claim 6, wherein, The mapping module includes a marking module and a counting module; The marking module is a module in the controller, and the counting module is a module in the source driver chip; The marking module is configured to mark the signal received by the controller to obtain the output signal; the output signal includes at least two counting mark signals, and the at least two counting mark signals correspond one-to-one with the at least two source driver chips; The counting module is configured to determine the valid received signal based on the cumulative count of data signals in the received signal.

13. The driving circuit structure according to claim 12, wherein, The counting marker signal includes a channel marker and a counting threshold, and the counting module is configured to: Obtain the counting threshold in the counting marker signal, and in response to the cumulative count value not exceeding the counting threshold, determine the valid received signal corresponding to the output channel of each source driver chip based on the channel marker.

14. A display device, comprising: The display panel and the driving circuit structure according to any one of claims 1-13; The source driver chip is electrically connected to the data line of the display panel.

15. A signal transmission method, comprising: The output signals of each output port of the controller are mapped to the valid received signals in the received signals of the source driver chip, and the output channels of the source driver chip are updated based on the received signals. In this controller, each of the output ports in at least a portion of the output ports sends the same output signal to at least two source driver chips, and the number of output signals from which the effective received signals mapped to the at least two source driver chips originate is different.

16. The method according to claim 15, wherein, The step of mapping the output signals of at least some of the output ports of the controller to the valid received signals in the received signals of the source driver chip, and updating the output channels of the source driver chip based on the received signals, includes: At least one segment identification signal is added to the signal received by the controller to obtain the output signal; the output signal of each output port includes at least two signal segments, the segment identification signal is located between two adjacent signal segments in the at least two signal segments, and the at least two signal segments are arranged sequentially in time. Acquire received signals from at least one of the output ports, and be configured to acquire a signal segment from each received signal as a valid received signal, so as to update the electrical signals transmitted to the output channels of each source driver chip based on the signal segment.

17. The method according to claim 16, wherein, The step of acquiring a signal segment from each received signal includes: Based on the control packet signal, obtain the signal segment corresponding to the source driver chip, and update the electrical signal transmitted to the output channel of each source driver chip based on the data packet signal in the corresponding signal segment. The control packet signals of the at least two signal segments correspond one-to-one with the at least two source driver chips.

18. The method according to claim 17, wherein, The control packet signal includes an identification signal corresponding to the source driver chip.

19. The method according to claim 15, wherein, The mapping of the output signals of at least some of the output ports of the controller to the valid received signals in the received signals of the source driver chip includes: The received signals are selected to determine the valid received signals.

20. The method according to claim 19, wherein, The selection of the received signal includes: After determining the number and timing information of the valid received signals, the received signals are selected.

21. The method according to claim 15, wherein, The mapping of the output signals of at least some of the output ports of the controller to the valid received signals in the received signals of the source driver chip includes: The signal received by the controller is marked to obtain the output signal; the output signal includes at least two counting mark signals, and the at least two counting mark signals correspond one-to-one with the at least two source driver chips; The valid received signal is determined by cumulatively counting the data signals in the received signal.

22. The method according to claim 21, wherein, The counting marker signal includes a channel marker and a counting threshold; The step of determining the valid received signal based on the cumulative count of data signals in the received signal includes: Obtain the counting threshold in the counting marker signal, and in response to the cumulative count value not exceeding the counting threshold, determine the valid received signal corresponding to the output channel of each source driver chip based on the channel marker.

Images