Pixel driving circuit, display device, and method of operating pixel driving circuit

Abstract

A pixel drive circuit (PDC) is provided. The pixel drive circuit (PDC) includes a drive transistor (Td), a light emitting element (LE), a node (N3, N4) between the drive transistor (Td) and the light emitting element (LE), a fifth transistor (T5), and a second capacitor (C2). The second capacitor (C2) is connected to the fifth transistor (T5). The fifth transistor (T5) is connected to the node (N3, N4) between the drive transistor (Td) and the light emitting element (LE).

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a pixel driving circuit, a display device, and a method for operating the pixel driving circuit. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] In one aspect, this disclosure provides a pixel driving circuit, comprising: a driving transistor; a light-emitting element; a node located between the driving transistor and the light-emitting element; a fifth transistor; and a second capacitor; wherein the second capacitor is connected to the fifth transistor; and the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

[0004] Optionally, the pixel driving circuit further includes a light-emitting control transistor connected to the driving transistor and connected to the light-emitting element; wherein the fifth transistor is connected to the second electrode of the driving transistor and the first electrode of the light-emitting control transistor.

[0005] Optionally, the pixel driving circuit further includes a light-emitting control transistor connected to the driving transistor and connected to the light-emitting element; wherein the fifth transistor is connected to the second electrode of the light-emitting control transistor and the anode of the light-emitting element.

[0006] Optionally, the gate of the fifth transistor is connected to a corresponding second light emission control signal line among a plurality of second light emission control signal lines.

[0007] Optionally, the gates of the fifth transistor and the light-emitting control transistor are connected to corresponding light-emitting control signal lines among a plurality of light-emitting control signal lines.

[0008] Optionally, the third capacitor electrode of the second capacitor is connected to a corresponding fourth reset signal line among a plurality of fourth reset signal lines; the fourth capacitor electrode of the second capacitor is connected to the first electrode of the fifth transistor; and the second electrode of the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

[0009] Optionally, a corresponding fourth reset signal line among a plurality of fourth reset signal lines is configured to provide a negative voltage signal.

[0010] Optionally, a corresponding fourth reset signal line among a plurality of fourth reset signal lines is configured to provide a positive voltage signal.

[0011] Optionally, a corresponding fourth reset signal line among a plurality of fourth reset signal lines is configured to provide an AC voltage signal.

[0012] Optionally, the third capacitor electrode of the second capacitor is connected to a corresponding second voltage supply line among a plurality of second voltage supply lines; the fourth capacitor electrode of the second capacitor is connected to the first electrode of the fifth transistor; and the second electrode of the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

[0013] Optionally, a corresponding second voltage supply line among a plurality of second voltage supply lines is configured to provide a negative voltage signal to the third capacitor electrode and the cathode of the light-emitting element.

[0014] Optionally, the gate of the fifth transistor is connected to a corresponding second light-emitting control signal line among a plurality of second light-emitting control signal lines; the third capacitor electrode of the second capacitor is connected to a corresponding fourth reset signal line among a plurality of fourth reset signal lines; the fourth capacitor electrode of the second capacitor is connected to the first electrode of the fifth transistor; and the second electrode of the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

[0015] Optionally, the gate of the fifth transistor is connected to a corresponding second light-emitting control signal line among the plurality of second light-emitting control signal lines; the third capacitor electrode of the second capacitor is connected to a corresponding second voltage supply line among the plurality of second voltage supply lines; the fourth capacitor electrode of the second capacitor is connected to the first electrode of the fifth transistor; and the second electrode of the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

[0016] Optionally, the gate of the fifth transistor is connected to a corresponding second light-emitting control signal line among a plurality of second light-emitting control signal lines; the third capacitor electrode of the second capacitor is connected to a corresponding fourth reset signal line among a plurality of fourth reset signal lines; the fourth capacitor electrode of the second capacitor is connected to the first electrode of the fifth transistor; and the second electrode of the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

[0017] Optionally, the gates of the fifth transistor and the light-emitting control transistor are connected to a corresponding light-emitting control signal line among a plurality of light-emitting control signal lines; the third capacitor electrode of the second capacitor is connected to a corresponding fourth reset signal line among a plurality of fourth reset signal lines; the fourth capacitor electrode of the second capacitor is connected to the first electrode of the fifth transistor; and the second electrode of the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

[0018] In another aspect, this disclosure provides a display device including a pixel driving circuit described herein or manufactured by the methods described herein, and a light-emitting element connected to the pixel driving circuit.

[0019] In another aspect, this disclosure provides a method for operating a pixel driving circuit; wherein the pixel driving circuit includes: a driving transistor; a light-emitting element; a node located between the driving transistor and the light-emitting element; a fifth transistor; and a second capacitor; wherein the second capacitor is connected to the fifth transistor; and the fifth transistor is connected to the node located between the driving transistor and the light-emitting element; wherein the method includes: turning on the driving transistor and the fifth transistor during a light-emitting sub-phase of a frame image.

[0020] Optionally, the method further includes determining whether the light-emitting element is configured to display a relatively low grayscale image; wherein, when the light-emitting element is configured to display the relatively low grayscale image, the fifth transistor is turned on during a display light-emitting sub-phase of a frame image.

[0021] Optionally, the method further includes turning off the fifth transistor when it is determined that the light-emitting element is configured to display a relatively high grayscale image.

[0022] Optionally, a relatively low grayscale image is an image with a grayscale value of less than 50.

[0023] Optionally, the method further includes providing a fourth reset signal to the third capacitor electrode of the second capacitor via a corresponding fourth reset signal line among a plurality of fourth reset signal lines.

[0024] Optionally, the method further includes providing a second voltage supply signal to a third capacitor electrode of the second capacitor via a respective second voltage supply line of a plurality of second voltage supply lines. Attached Figure Description

[0025] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0026] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0027] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0028] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0029] Figure 3A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0030] Figure 3B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0031] Figure 4 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0032] Figure 5 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0033] Figure 6 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0034] Figure 7 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0035] Figure 8 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0036] Figure 9 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0037] Figure 10 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0038] Figure 11 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0039] Figure 12 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0040] Figure 13 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. Detailed Implementation

[0041] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0042] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, 8T2C, 9T1C, and 9T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is a 9T2C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0043] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 The array substrate includes an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes multiple first gate lines GL1, multiple second gate lines GL2, multiple data lines DL, and multiple voltage supply lines Vdd. Each subpixel Sp emits light driven by its corresponding pixel driving circuit PDC. In one example, a high-voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via a corresponding high-voltage supply line among the multiple voltage supply lines Vdd; a low-voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via a low-voltage supply line. The voltage difference between the high-voltage signal (e.g., the VDD signal) and the low-voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0044] Figure 2AThis is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A In some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line GL1 among a plurality of second gate lines. The first transistor T1 has a gate, a first electrode connected to the second electrode of the driving transistor Td, and a second electrode connected to the first capacitor electrode Ce1 of the first capacitor C1 and the gate of the driving transistor Td; the third transistor T3 has a gate connected to a corresponding light-emitting control signal line em of a plurality of light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd of a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; the fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line em of a plurality of light-emitting control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the first electrode of the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; and the first reset transistor Tr1 has a gate connected to a corresponding first reset control signal line rst1 of a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 of a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the voltage supply line.

[0045] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0046] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0047] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, a corresponding pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, and S3 represents a corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, and C3 represents a corresponding third sub-pixel of a third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0048] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td.

[0049] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 2A The second transistor T2 is an n-type transistor, such as a metal-oxide-semiconductor (MOS) transistor, while the other transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0050] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A and Figure 2B During one frame of an image, the operation of the pixel driving circuit includes an initial sub-stage t0, a first reset sub-stage t1, a data writing sub-stage t2, a second reset sub-stage t3, and a light-emitting sub-stage t4. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. Cutoff reset control signals are provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. In the initial sub-stage t0, cutoff signals are provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, therefore the first transistor T1 and the second transistor T2 are turned off.

[0051] In the first reset stage t1, a reset control signal is provided to the gate of the second reset transistor Tr2 via the second reset control signal line rst2 to turn on the second reset transistor Tr2; this allows the initialization voltage signal from the corresponding second reset signal line Vint2 to be transmitted from the first electrode of the second reset transistor Tr2 to the second electrode of the second reset transistor Tr2, and then to the first electrode of the second transistor T2 and the second electrode of the driving transistor Td. Node N3 is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding voltage supply line Vdd. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in the first reset stage t1. In the first reset stage t1, a cutoff signal is provided to the corresponding first gate line GL1, thus turning off the first transistor T1. In the first reset stage t1, a turn-on signal is provided to the corresponding second gate line GL2, thus turning on the second transistor T2. A high voltage signal is provided to the corresponding light-emitting control signal line em to turn off the third transistor T3 and the fourth transistor T4.

[0052] During the data write sub-stage t2, a cutoff reset control signal is again provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. The corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with conduction signals, thus turning on the first transistor T1 and the second transistor T2. The second electrode of the driving transistor Td is connected to the first electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the second electrode of the second transistor T2. Since the second transistor T2 is turned on during the data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, making only the PN junction between the gate and the first electrode of the driving transistor Td effective, thus putting the driving transistor Td in diode-connected mode. The first transistor T1 is turned on during the data write sub-stage t2. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. Node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, during the data writing sub-stage t2, the voltage level of node N1 gradually rises to (Vdata + Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. The corresponding light-emitting control signal line em is provided with a high voltage signal to cut off the third transistor T3 and the fourth transistor T4.

[0053] In the second reset stage t3, a turn-on reset control signal is provided to the gate of the first reset transistor Tr1 via the corresponding first reset control signal line rst1 to turn on the first reset transistor Tr1; this allows the initialization voltage signal from the corresponding first reset signal line Vint1 to pass from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and then to node N4. The anode of the light-emitting element LE is initialized. A turn-on reset control signal is provided to the gate of the third reset transistor Tr3 via the corresponding first reset control signal line rst1 to turn on the third reset transistor Tr3; this allows the initialization voltage signal from the corresponding third reset signal line Vint3 to pass from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and then to node N2. Node N2 is initialized.

[0054] In the second reset stage t3, a cutoff reset control signal is again provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. The corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with cutoff signals, and the first transistor T1 and the second transistor T2 are turned off.

[0055] In the light-emitting stage t3, the corresponding light-emitting control signal line em provides a low voltage signal to turn on the third transistor T3 and the fourth transistor T4. In the light-emitting stage t4, the voltage level at node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level, operating in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, the fourth transistor T4, and the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3, connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0056] To achieve low-brightness, low-grayscale display quality in AMOLED display panels, the small current driving the organic light-emitting diodes (OLEDs) must be precisely controlled. However, in existing pixel circuits, the driving transistors, typically employing low-temperature polycrystalline silicon (LTPS) p-type metal-oxide-semiconductor (PMOS) transistors for voltage-to-current conversion, exhibit poor voltage-to-current conversion capability at low grayscale levels. They cannot output values ​​below 10... -12 The current in amperes (similar to the leakage current I in the cutoff state) off Therefore, in theory, it is not feasible to directly adjust the screen brightness by controlling the tiny current flowing through the OLED using LTPS DTFT.

[0057] Display panels typically employ pulse-width modulation (PWM) dimming to adjust brightness at low grayscale levels. However, PWM dimming is widely criticized for its potential harm to the human eye. While increasing the PWM dimming frequency is a common method to mitigate this drawback, the ultimate goal for display panels is to achieve full DC dimming, where brightness across all grayscale levels is directly adjusted by controlling the amplitude of the current.

[0058] Furthermore, circuits using indium gallium zinc oxide (IGZO) or other oxide-based driving transistors (oxide DTFTs) for OLED voltage-to-current conversion and driving have been developed. However, when oxide DTFTs are used as drivers, their voltage-to-current conversion lacks sufficient resolution in the low brightness range, meaning that small voltage changes correspond to large current differences. Compared to low-temperature polycrystalline silicon (LTPS), the current change in oxide DTFTs is twice as large for every 0.2 volt change in gate voltage. Although oxide DTFTs can theoretically control currents as low as 10 volts... -14 Amperes, but for the reasons mentioned above, their practical applications are limited.

[0059] Table 1 shows the brightness level, grayscale, and cutoff leakage current (μ) of LTPS and oxide-based transistors. off (Data).

[0060]

[0061] Referring to Table 1, "Grayscale (at 13 nits)" refers to a specific brightness level of an OLED panel corresponding to a brightness of 13 nits. In the case of displays, grayscale represents the different brightness intensities that a pixel can achieve, typically ranging from 0 (black) to a maximum value (e.g., 255 in an 8-bit system) for white. oled "(G at 13 nits)" refers to the current flowing through the green (G) sub-pixel of the OLED display when the green (G) sub-pixel emits light with a brightness of 13 nits. "LTPS I" off "(At -5.1Vds)" refers to the cutoff-state leakage current (F) of a low-temperature polycrystalline silicon thin-film transistor (LTPS TFT) when the drain-source voltage (Vds) is set to -5.1V. off ).

[0062] As can be observed from Table 1, at an absolute brightness of approximately 1.3 nits, the current flowing through the green (G) pixel OLED is 1 × 10⁻¹² Amperes. At this time, the cutoff-state leakage current (F) of the LTPS TFT is... off The current is also 1 × 10⁻¹² square amperes, which means that for currents below this brightness level, the LTPS TFT cannot output such a small current.

[0063] In comparison, the cutoff-state leakage current (F) of oxide TFTs (e.g., indium gallium zinc oxide-based transistors) off It can be as low as 1×10⁻¹ 4 The ampere, which makes them more suitable for controlling very small currents. However, oxide TFTs exhibit high voltage sensitivity in the low current range. This means that small changes in voltage correspond to large changes in current, making it difficult to distinguish brightness levels (current) by voltage control in the low current region.

[0064] Because the driving current of OLEDs is very small under low grayscale and low brightness conditions, low-temperature polycrystalline silicon (LTPS) driven thin-film transistors (DTFTs) cannot achieve effective low-current driving, and oxide DTFTs lack precision in controlling small currents. This disclosure employs a bypass shunting concept, combined with capacitor design, to increase the current flowing through the DTFT under low grayscale and low brightness conditions. This approach allows LTPS / oxide DTFTs to operate in a controllable and more precise region, achieving better control of large currents. Before the current flows into the OLED branch, a portion of the current is diverted via bypass shunting, thereby reducing the current entering the OLED branch. This allows for effective low-current driving, enabling precise control of low brightness and low brightness levels.

[0065] Therefore, this disclosure particularly provides a pixel driving circuit, a display device, and a method of operating the pixel driving circuit, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a pixel driving circuit. In some embodiments, the pixel driving circuit includes a driving transistor; a light-emitting element; a node located between the driving transistor and the light-emitting element; a fifth transistor; and a second capacitor. Optionally, the second capacitor is connected to the fifth transistor. Optionally, the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

[0066] In relevant display panels, OLEDs have relatively low drive currents, primarily due to the small current flowing through the drive transistors. This is determined by the IV transfer characteristic curve of the drive transistors, where controlling the small current is challenging. Consequently, DC dimming cannot be effectively achieved at low brightness levels and low grayscale. In these display panels, the drive transistors operate in a low-current region, where controlling the small current is difficult, making them unsuitable for DC dimming.

[0067] In some embodiments, the display panel according to this disclosure allows the driving transistors to operate in the high-current region of their IV curves. For p-type metal-oxide-semiconductor (PMOS) driving transistors, this requires setting the Vdata voltage to a lower value (e.g., lower than the voltage in the associated display panel). After the current flows through the main path of the driving transistor, it is then split into two paths. In the display panel according to this disclosure, the driving transistors operate in the high-current region with low brightness levels and low grayscale, while the OLED operates in the low-current region. This is achieved by reducing the gate voltage (Vg) of the driving transistors or by introducing additional shunting through an additional transistor. These adjustments allow for precise control of the OLED current, thereby precisely controlling the brightness.

[0068] The inventors of this disclosure have discovered that the gate-source voltage (Vgs) of the driving transistor can be set differently. For example, in this disclosure, if the driving TFT (DTFT) is a PMOS transistor, the gate-source voltage (Vgs) of the driving transistor can be made more negative compared to the associated display panel. This results in a larger current (I) through the driving transistor in the display panel according to this disclosure, which makes current control easier to manage. The inventors of this disclosure have discovered that operating the driving transistor in a higher current region reduces the sensitivity of the current to voltage changes (i.e., the ratio of voltage to current changes becomes smaller). This helps to better distinguish gray levels. For very low brightness at low gray levels, the current through the OLED branch may drop to the cutoff state leakage current (Io) of the driving transistor. off The following is a description of the process. First, by amplifying the total current R passing through the driving transistor and then splitting it into two paths, precise control can be achieved in the display panel according to this disclosure, even when the current through the OLED branch is extremely small.

[0069] Figure 3A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 3AIn some embodiments, the pixel driving circuit includes a driving transistor Td; a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines and a second electrode connected to the driving transistor Td. The first electrode of the first capacitor C1 and the second electrode of the first capacitor Ce1 connected to the first capacitor C1 and the gate of the driving transistor Td; the third transistor T3 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to a first electrode of the driving transistor Td and a second electrode of the first transistor T1; the fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a second electrode of the driving transistor Td and a first electrode of the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; the first reset transistor Tr1 has a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to a second electrode of the fourth transistor T4 and the anode of the light-emitting element LE; the fifth transistor T5; and the second capacitor C2 has a third capacitor electrode Ce3 and a fourth capacitor electrode Ce4.

[0070] In some embodiments, the third capacitor electrode Ce3 of the second capacitor C2 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the first electrode of the fifth transistor T5.

[0071] In some embodiments, the fourth reset signal provided by the corresponding fourth reset signal line Vint4 is a dynamically adjustable voltage, typically ranging between 4.8V and -3V. This dynamic adjustability allows it to adapt to different operational requirements, such as precharging during specific phases or controlling subpixel behavior. In contrast, the first reset signal provided by the corresponding first reset signal line Vint1 and the second reset signal provided by the corresponding second reset signal line Vint2 are constant negative voltages, typically set around -3V. These constant voltages are used to stabilize certain parts of the circuit, ensuring consistent operation and minimizing fluctuations. In some embodiments, the third reset signal provided by the corresponding third reset signal line Vint3 is a constant positive voltage, typically set to approximately 7V. It provides a stable reference or drive potential for specific parts of the circuit that require a higher positive voltage.

[0072] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding second light-emitting control signal line em2 among a plurality of second light-emitting control signal lines; the first electrode of the fifth transistor T5 is connected to the fourth capacitor electrode Ce4 of the second capacitor C2; and the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td, the second electrode of the second reset transistor Tr2, the first electrode of the second transistor T2, and the first electrode of the fourth transistor T4. In some embodiments, the second light-emitting control signal provided by the corresponding second light-emitting control signal line and the first light-emitting control signal provided by the corresponding first light-emitting control signal line are outputs from different stages of the light-emitting control scanning circuit. Optionally, the corresponding second light-emitting control signal line provides a second light-emitting control signal having the same voltage level as the first light-emitting control signal provided by the corresponding first light-emitting control signal line em. Alternatively, the corresponding second light-emitting control signal line provides a second light-emitting control signal having a different voltage level than the first light-emitting control signal provided by the corresponding first light-emitting control signal line em.

[0073] The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0074] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, the second electrode of the second reset transistor Tr2, and the second electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0075] The pixel driving circuit according to this disclosure includes a fifth transistor T5 and a second capacitor C2, which generate conductive paths at different operating stages. When the fifth transistor T5 is turned on, the second capacitor C2 is connected in parallel with the light-emitting element LE, resulting in an increase in the total capacitance that needs to be charged. This affects the behavior of the circuit by modifying the distribution of current and charge. When the fifth transistor T5 is turned off, the second capacitor C2 is independent of the light-emitting process and does not affect the main light-emitting path.

[0076] The inventors of this disclosure have discovered that adding a fifth transistor T5 and a second capacitor C2 solves two key problems in the prior art. First, the incorporation of a bypass current path improves the accuracy of small current control in the drive transistor Td, which struggles to effectively handle such low current. Second, the pixel drive circuit according to this disclosure accelerates the turn-on speed at low grayscale by allowing a preset voltage to be written to the second capacitor C2 before the light-emitting phase. This reduces the time required for the pixel to reach the turn-on threshold, thereby solving the problem of slow response at low brightness levels. In summary, these improvements significantly enhance the performance of the pixel circuit under challenging low brightness and low grayscale conditions. In some embodiments, the capacitance of the second capacitor C2 is greater than the capacitance of the first capacitor C1.

[0077] exist Figure 3AIn the pixel driving circuit shown, the fifth transistor T5 (and the second capacitor C2 connected to the fifth transistor T5) is connected to the third node N3. During the low-brightness, low-grayscale emission stage, by setting the gate of the fifth transistor T5 to a low level, the current in the emission path is divided into two parts: a first part I1, which flows through the fourth transistor T4 and the light-emitting element LE, and a second part I2, which flows through the fifth transistor T5. The charge corresponding to the second part I2 can be stored in the second capacitor C2. As a result, the total current flowing through the driving transistor Td becomes I1 + I2. Compared to existing pixel driving circuits where only I1 flows through the driving transistor Td, the total current flowing through the driving transistor Td in the pixel driving circuit according to this disclosure is increased. This allows the driving transistor Td to operate in a more precisely controlled region, thereby improving the accuracy of current regulation in the circuit.

[0078] Reference Figure 3A In some embodiments, the pixel driving circuit includes a driving transistor Td, a light-emitting element LE, and a node located between the driving transistor Td and the light-emitting element LE. In some embodiments, the pixel driving circuit further includes a fifth transistor T5 and a second capacitor C2 connected to the fifth transistor T5. The second electrode of the fifth transistor T5 is connected to the node located between the driving transistor Td and the light-emitting element LE.

[0079] exist Figure 3A In the pixel driving circuit shown, the pixel driving circuit also includes a light-emitting control transistor (e.g., a fourth transistor T4), which is connected to the driving transistor Td and to the light-emitting element LE. In some embodiments, the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td and the first electrode of the light-emitting control transistor. For example, the second electrode of the fifth transistor T5 is connected to the third node N3.

[0080] In some embodiments, the third capacitor electrode Ce3 of the second capacitor C2 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the first electrode of the fifth transistor T5.

[0081] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, the first electrode of the fifth transistor T5 is connected to the fourth capacitor electrode Ce4 of the second capacitor C2, and the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td and the first electrode of the light emission control transistor (e.g., the fourth transistor T4).

[0082] The inventors of this disclosure have discovered that several advantages can be achieved by configuring a second capacitor C2 and a fifth transistor T5. First, the problem of insufficient black-state performance arises, primarily because the black-state Vdata is already quite high (typically set to VGMP), yet the current is still insufficient to achieve a truly black state. Vdata refers to the data voltage applied to the pixel during the data writing phase of an AMOLED display's operation. It represents the voltage that determines the pixel's brightness level. VGMP refers to the gate modulation potential voltage, which is typically used in AMOLED driving circuits as a reference voltage to control the transistor gate, especially under low brightness or black-state conditions.

[0083] Increasing the capacitance between the fourth node N4 and the cathode (Vss) reduces the charging of the light-emitting element (LE), thereby improving the black state. Theoretically, increasing VGMP could also achieve a black state, but this method would result in excessive power consumption due to the higher voltage. In this disclosure, the black state is optimized by turning on the fifth transistor T5, which adds a second capacitor C2 in parallel with the capacitor between the fourth node N4 and the cathode. This increases the total capacitance and improves black state performance. In related pixel driving circuits, a common approach is to increase the anode area to improve the capacitance between the fourth node N4 and the cathode, especially for red and green pixels, where achieving a complete black state is more challenging. However, increasing the capacitance between the fourth node N4 and the cathode in this way introduces problems such as slow low-grayscale turn-on and ghosting.

[0084] Second, because the potential of the fourth node N4 cannot reach the turn-on voltage Vop of the light-emitting element LE, a problem of not lighting up at low grayscale occurs. In this case, turning on the fifth transistor T5 and adjusting the voltage at the second capacitor C2 (which requires integrated circuit support for AC Vint4, for example, an AC signal applied to the third capacitor electrode Ce3 of the second capacitor C2) allows a voltage jump variable to be written to the fourth node N4. This enables the pre-charging of the potential of the fourth node N4, allowing the fourth node N4 to quickly reach the turn-on voltage Vop at low grayscale. By configuring different capacitors for different RGB light-emitting devices, this disclosure enables synchronous lighting up at low grayscale across all colors.

[0085] Figure 3B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 3A and Figure 3BDuring one frame of an image, the operation of the pixel driving circuit includes the following time periods: first time period p1, second time period p2, third time period p3, fourth time period p4, fifth time period p5, sixth time period p6, seventh time period p7, eighth time period p8, ninth time period p9, tenth time period p10, eleventh time period p11, twelfth time period p12, thirteenth time period p13, fourteenth time period p14, fifteenth time period p15, and sixteenth time period p16. In the first time period p1, the corresponding light emission control signal line em is set with an invalid voltage (cutoff voltage) to cut off the third transistor T3 and the fourth transistor T4.

[0086] During the second time period p2, the second gate line GL2 is supplied with an effective voltage (turn-on voltage) to turn on the second transistor T2.

[0087] During the third time period p3, the voltage signal from the corresponding second reset signal line Vint2 initializes the third node N3 through the second reset transistor Tr2. Subsequently, the first node N1 is initialized through the second transistor T2.

[0088] In the fourth time period p4, the initialization of the third node N3 and the first node N1 is completed.

[0089] In the fifth time period p5, the first transistor T1 is turned on, and the data writing process begins.

[0090] In the sixth time period p6, the first transistor T1 is turned off, and the data writing process ends.

[0091] In the seventh time period p7, the corresponding second gate line GL2 is provided with an invalid voltage (cutoff voltage) to turn off the second transistor T2.

[0092] In the eighth time period p8, the first reset transistor Tr1 is turned on, allowing the voltage signal from the corresponding first reset signal line Vint1 to initialize the fourth node N4. Simultaneously, the third reset transistor Tr3 is turned on, allowing the voltage signal from the corresponding third reset signal line Vint3 to initialize the second node N2. During this phase, bias stress is applied to the drive transistor Td to improve hysteresis performance.

[0093] In the ninth time period p9, the first reset transistor Tr1 and the third reset transistor Tr3 are turned off, marking the end of the initialization and bias stress process.

[0094] In the tenth period p10, the fifth transistor T5 is turned on to prepare the circuit for bypass current.

[0095] During the eleventh time period p11, the voltage at the corresponding fourth reset signal line Vint4 changes from a low voltage level to a high voltage level, pre-charging the fourth node N4 to facilitate subsequent rapid power-on.

[0096] During the twelfth and thirteenth time periods (p12 and p13), the pre-charging process continues until the light emission control signal em transitions to an effective voltage (turn-on voltage), thus initiating light emission. The pre-charging voltage of the corresponding fourth reset signal line Vint4 is set to be greater than the voltage of the corresponding first reset signal line Vint1. In some configurations, the durations of p12 and p13 can be ignored.

[0097] In the fourteenth period p14, the light-emitting period occurs. During this period, the fifth transistor T5 remains on, achieving a current bypass effect due to the lower voltage at the corresponding fourth reset signal line Vint4.

[0098] During the fifteenth time period p15, the corresponding second light-emitting control signal line em2 is supplied with an invalid voltage (cutoff voltage), ending the light-emitting period. The current bypass effect also ends during this time period.

[0099] In the sixteenth time period p16, after the light emission control signal em2 is turned off, the voltage of the corresponding fourth reset signal line Vint4 is adjusted to a state that neither precharges nor bypasses the current in order to reduce power consumption.

[0100] Figure 4 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 4In some embodiments, the pixel driving circuit includes a driving transistor Td; a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines and a second electrode connected to the driving transistor Td. The first electrode of the first capacitor C1 and the second electrode of the first capacitor Ce1 connected to the first capacitor C1 and the gate of the driving transistor Td; the third transistor T3 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to a first electrode of the driving transistor Td and a second electrode of the first transistor T1; the fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a second electrode of the driving transistor Td and a first electrode of the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; the first reset transistor Tr1 has a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to a second electrode of the fourth transistor T4 and the anode of the light-emitting element LE; the fifth transistor T5; and the second capacitor C2 has a third capacitor electrode Ce3 and a fourth capacitor electrode Ce4.

[0101] In some embodiments, the third capacitor electrode Ce3 of the second capacitor C2 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the first electrode of the fifth transistor T5.

[0102] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding second light-emitting control signal line em2 among a plurality of second light-emitting control signal lines, the first electrode of the fifth transistor T5 is connected to the fourth capacitor electrode Ce4 of the second capacitor C2, and the second electrode of the fifth transistor T5 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0103] The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0104] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, the second electrode of the fifth transistor T5, and the anode of the light-emitting element LE.

[0105] The pixel driving circuit according to this disclosure includes a fifth transistor T5 and a second capacitor C2, which generate conductive paths at different operating stages. When the fifth transistor T5 is turned on, the second capacitor C2 is connected in parallel with the light-emitting element LE, resulting in an increase in the total capacitance that needs to be charged. This affects the behavior of the circuit by modifying the distribution of current and charge. When the fifth transistor T5 is turned off, the second capacitor C2 is independent of the light-emitting process and does not affect the main light-emitting path.

[0106] The inventors of this disclosure have discovered that adding a fifth transistor T5 and a second capacitor C2 solves two key problems in the prior art. First, the incorporation of a bypass current path improves the accuracy of small current control in the drive transistor Td, which struggles to effectively handle such low current. Second, the pixel drive circuit according to this disclosure accelerates the turn-on speed at low grayscale by allowing a preset voltage to be written to the second capacitor C2 before the light-emitting phase. This reduces the time required for the pixel to reach the turn-on threshold, thereby solving the problem of slow response at low brightness levels. In summary, these improvements significantly enhance the performance of the pixel circuit under challenging low brightness and low grayscale conditions.

[0107] exist Figure 4In the pixel driving circuit shown, the fifth transistor T5 (and the second capacitor C2 connected to the fifth transistor T5) is connected to the fourth node N4. During the low-brightness, low-grayscale emission stage, by setting the gate of the fifth transistor T5 to a low level, the current in the emission path is divided into two parts: a first part I1, which flows through the light-emitting element LE, and a second part I2, which flows through the fifth transistor T5. The charge corresponding to the second part I2 can be stored in the second capacitor C2. As a result, the total current flowing through the driving transistor Td becomes I1 + I2. Compared to existing pixel driving circuits where only I1 flows through the driving transistor Td, the total current flowing through the driving transistor Td in the pixel driving circuit according to this disclosure is increased. This allows the driving transistor Td to operate in a more precisely controlled region, thereby improving the accuracy of current regulation in the circuit.

[0108] Furthermore, prior to the low grayscale emission stage, the fifth transistor T5 can be turned on, and the voltage of Vint4 can be adjusted to pre-charge the N4 node voltage and the OLED capacitor. Subsequently, the third transistor T3 and the fourth transistor T4 are turned on to enable emission. This method solves the delayed start-up problem in the low grayscale case, improves the response time, and ensures better performance.

[0109] Reference Figure 4 In some embodiments, the pixel driving circuit includes a driving transistor Td, a light-emitting element LE, and a node located between the driving transistor Td and the light-emitting element LE. In some embodiments, the pixel driving circuit further includes a fifth transistor T5 and a second capacitor C2 connected to the fifth transistor T5. The second electrode of the fifth transistor T5 is connected to the node located between the driving transistor Td and the light-emitting element LE.

[0110] exist Figure 4 In the pixel driving circuit shown, the pixel driving circuit also includes a light-emitting control transistor (e.g., a fourth transistor T4), which is connected to the driving transistor Td and to the light-emitting element LE. In some embodiments, the second electrode of the fifth transistor T5 is connected to the second electrode of the light-emitting control transistor and the anode of the light-emitting element LE. For example, the second electrode of the fifth transistor T5 is connected to the fourth node N4.

[0111] In some embodiments, the third capacitor electrode Ce3 of the second capacitor C2 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the first electrode of the fifth transistor T5.

[0112] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding second light-emitting control signal line em2 among a plurality of second light-emitting control signal lines, the first electrode of the fifth transistor T5 is connected to the fourth capacitor electrode Ce4 of the second capacitor C2, and the second electrode of the fifth transistor T5 is connected to the second electrode of the light-emitting control transistor (e.g., the fourth transistor T4) and the anode of the light-emitting element LE.

[0113] The inventors of this disclosure have discovered that several advantages can be achieved by configuring a second capacitor C2 and a fifth transistor T5. First, the problem of insufficient black-state performance arises, primarily because the black-state Vdata is already quite high (typically set to VGMP), yet the current is still insufficient to achieve a truly black state. Vdata refers to the data voltage applied to the pixel during the data writing phase of an AMOLED display's operation. It represents the voltage that determines the pixel's brightness level. VGMP refers to the gate modulation potential voltage, which is typically used in AMOLED driving circuits as a reference voltage to control the transistor gate, especially under low brightness or black-state conditions.

[0114] Increasing the capacitance between the fourth node N4 and the cathode (Vss) reduces the charging of the light-emitting element (LE), thereby improving the black state. Theoretically, increasing VGMP could also achieve a black state, but this method would result in excessive power consumption due to the higher voltage. In this disclosure, the black state is optimized by turning on the fifth transistor T5, which adds a second capacitor C2 in parallel with the capacitor between the fourth node N4 and the cathode. This increases the total capacitance and improves black state performance. In related pixel driving circuits, a common approach is to increase the anode area to improve the capacitance between the fourth node N4 and the cathode, especially for red and green pixels, where achieving a complete black state is more challenging. However, increasing the capacitance between the fourth node N4 and the cathode in this way introduces problems such as slow low-grayscale turn-on and ghosting.

[0115] Second, because the potential of the fourth node N4 cannot reach the turn-on voltage Vop of the light-emitting element LE, a problem of not lighting up at low grayscale occurs. In this case, turning on the fifth transistor T5 and adjusting the voltage at the second capacitor C2 (which requires integrated circuit support for AC Vint4, for example, an AC signal applied to the third capacitor electrode Ce3 of the second capacitor C2) allows a voltage jump variable to be written to the fourth node N4. This enables the pre-charging of the potential of the fourth node N4, allowing the fourth node N4 to quickly reach the turn-on voltage Vop at low grayscale. By configuring different capacitors for different RGB light-emitting devices, this disclosure enables synchronous lighting up at low grayscale across all colors.

[0116] exist Figure 3A and Figure 3BIn the illustrated embodiment, current bypass occurs during the light-emitting phase. During this phase, a conductive path is established between the corresponding first voltage supply line Vdd and the corresponding second voltage supply line Vss through the fully conducting third transistor T3, driving transistor Td, and fourth transistor T4. Simultaneously, the fifth transistor T5 is also turned on. The current at the third node N3 is split into two branches: one branch flows through the fourth transistor T4, and the other branch flows through the fifth transistor T5. This also charges the second capacitor C2 and the light-emitting element LE, achieving the purpose of current bypass.

[0117] exist Figure 4 In the illustrated embodiment, current bypass occurs during the light-emitting phase. During this phase, a conductive path is established between the corresponding first voltage supply line Vdd and the corresponding second voltage supply line Vss through the fully turned-on third transistor T3, driving transistor Td, and fourth transistor T4. Simultaneously, the fifth transistor T5 is also turned on. The current at the fourth node N4 is split into two branches. This also charges the second capacitor C2 and the light-emitting element LE, achieving the purpose of current bypass.

[0118] In an alternative embodiment, during the light-emitting phase, an operating mode similar to a pulse-width modulation (PWM) dimming process is used. In this mode, the third transistor T3 and the fourth transistor T4 switch at a high frequency to modulate the brightness. When the PWM pulse turns on the fourth transistor T4, current bypass occurs in the same manner as described above. However, if the PWM pulse turns off the fourth transistor T4 and the fifth transistor T5 turns on, even in this configuration, the capacitor can store charge to achieve current bypass.

[0119] Figure 5 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 5In some embodiments, the pixel driving circuit includes a driving transistor Td; a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines and a second electrode connected to the driving transistor Td. The first electrode of the first capacitor C1 and the second electrode of the first capacitor Ce1 connected to the first capacitor C1 and the gate of the driving transistor Td; the third transistor T3 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to a first electrode of the driving transistor Td and a second electrode of the first transistor T1; the fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a second electrode of the driving transistor Td and a first electrode of the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; the first reset transistor Tr1 has a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to a second electrode of the fourth transistor T4 and the anode of the light-emitting element LE; the fifth transistor T5; and the second capacitor C2 has a third capacitor electrode Ce3 and a fourth capacitor electrode Ce4.

[0120] In some embodiments, the third capacitor electrode Ce3 of the second capacitor C2 is connected to a corresponding second voltage supply line Vss among a plurality of second voltage supply lines, and the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the first electrode of the fifth transistor T5.

[0121] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, the first electrode of the fifth transistor T5 is connected to the fourth capacitor electrode Ce4 of the second capacitor C2, and the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td, the second electrode of the second reset transistor Tr2, the first electrode of the second transistor T2, and the first electrode of the fourth transistor T4.

[0122] The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0123] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, the second electrode of the second reset transistor Tr2, and the second electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0124] The pixel driving circuit according to this disclosure includes a fifth transistor T5 and a second capacitor C2, which generate conductive paths at different operating stages. When the fifth transistor T5 is turned on, the second capacitor C2 is connected in parallel with the light-emitting element LE, resulting in an increase in the total capacitance that needs to be charged. This affects the behavior of the circuit by modifying the distribution of current and charge. When the fifth transistor T5 is turned off, the second capacitor C2 is independent of the light-emitting process and does not affect the main light-emitting path.

[0125] The inventors of this disclosure have discovered that adding a fifth transistor T5 and a second capacitor C2 solves two key problems in the prior art. First, the incorporation of a bypass current path improves the accuracy of small current control in the drive transistor Td, which struggles to effectively handle such low current. Second, the pixel drive circuit according to this disclosure accelerates the turn-on speed at low grayscale by allowing a preset voltage to be written to the second capacitor C2 before the light-emitting phase. This reduces the time required for the pixel to reach the turn-on threshold, thereby solving the problem of slow response at low brightness levels. In summary, these improvements significantly enhance the performance of the pixel circuit under challenging low brightness and low grayscale conditions.

[0126] exist Figure 5In the pixel driving circuit shown, the fifth transistor T5 (and the second capacitor C2 connected to the fifth transistor T5) is connected to the third node N3. During the low-brightness, low-grayscale emission stage, by setting the gate of the fifth transistor T5 to a low level, the current in the emission path is divided into two parts: a first part I1, which flows through the fourth transistor T4 and the light-emitting element LE, and a second part I2, which flows through the fifth transistor T5. The charge corresponding to the second part I2 can be stored in the second capacitor C2. As a result, the total current flowing through the driving transistor Td becomes I1 + I2. Compared to existing pixel driving circuits where only I1 flows through the driving transistor Td, the total current flowing through the driving transistor Td in the pixel driving circuit according to this disclosure is increased. This allows the driving transistor Td to operate in a more precisely controlled region, thereby improving the accuracy of current regulation in the circuit.

[0127] Reference Figure 5 In some embodiments, the pixel driving circuit includes a driving transistor Td, a light-emitting element LE, and a node located between the driving transistor Td and the light-emitting element LE. In some embodiments, the pixel driving circuit further includes a fifth transistor T5 and a second capacitor C2 connected to the fifth transistor T5. The second electrode of the fifth transistor T5 is connected to the node located between the driving transistor Td and the light-emitting element LE.

[0128] exist Figure 5 In the pixel driving circuit shown, the pixel driving circuit also includes a light-emitting control transistor (e.g., a fourth transistor T4), which is connected to the driving transistor Td and to the light-emitting element LE. In some embodiments, the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td and the first electrode of the light-emitting control transistor. For example, the second electrode of the fifth transistor T5 is connected to the third node N3.

[0129] In some embodiments, the third capacitor electrode Ce3 of the second capacitor C2 is connected to a corresponding second voltage supply line Vss among a plurality of second voltage supply lines, and the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the first electrode of the fifth transistor T5.

[0130] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, the first electrode of the fifth transistor T5 is connected to the fourth capacitor electrode Ce4 of the second capacitor C2, and the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td and the first electrode of the light emission control transistor (e.g., the fourth transistor T4).

[0131] The inventors of this disclosure have discovered that several advantages can be achieved by configuring a second capacitor C2 and a fifth transistor T5. First, the problem of insufficient black-state performance arises, primarily because the black-state Vdata is already quite high (typically set to VGMP), yet the current is still insufficient to achieve a truly black state. Vdata refers to the data voltage applied to the pixel during the data writing phase of an AMOLED display's operation. It represents the voltage that determines the pixel's brightness level. VGMP refers to the gate modulation potential voltage, which is typically used in AMOLED driving circuits as a reference voltage to control the transistor gate, especially under low brightness or black-state conditions.

[0132] Increasing the capacitance between the fourth node N4 and the cathode (Vss) reduces the charging of the light-emitting element (LE), thereby improving the black state. Theoretically, increasing VGMP could also achieve a black state, but this method would result in excessive power consumption due to the higher voltage. In this disclosure, the black state is optimized by turning on the fifth transistor T5, which adds a second capacitor C2 in parallel with the capacitor between the fourth node N4 and the cathode. This increases the total capacitance and improves black state performance. In related pixel driving circuits, a common approach is to increase the anode area to improve the capacitance between the fourth node N4 and the cathode, especially for red and green pixels, where achieving a complete black state is more challenging. However, increasing the capacitance between the fourth node N4 and the cathode in this way introduces problems such as slow low-grayscale turn-on and ghosting.

[0133] Second, because the potential of the fourth node N4 cannot reach the turn-on voltage Vop of the light-emitting element LE, a problem of not lighting up at low grayscale occurs. In this case, turning on the fifth transistor T5 and adjusting the voltage at the second capacitor C2 (which requires integrated circuit support for AC Vss, for example, an AC signal applied to the third capacitor electrode Ce3 of the second capacitor C2) allows a voltage jump variable to be written to the fourth node N4. This makes it possible to precharge the potential of the fourth node N4, allowing the fourth node N4 to quickly reach the turn-on voltage Vop at low grayscale. By configuring different capacitors for different RGB light-emitting devices, this disclosure enables synchronous lighting up at low grayscale for all colors. In one example, the capacitance of the second capacitor C2 in the blue sub-pixel is greater than the capacitance of the second capacitor C2 in the green sub-pixel and the capacitance of the second capacitor C2 in the red sub-pixel.

[0134] Figure 6 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 6In some embodiments, the pixel driving circuit includes a driving transistor Td; a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines and a second electrode connected to the driving transistor Td. The first electrode of the first capacitor C1 and the second electrode of the first capacitor Ce1 connected to the first capacitor C1 and the gate of the driving transistor Td; the third transistor T3 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to a first electrode of the driving transistor Td and a second electrode of the first transistor T1; the fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a second electrode of the driving transistor Td and a first electrode of the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; the first reset transistor Tr1 has a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to a second electrode of the fourth transistor T4 and the anode of the light-emitting element LE; the fifth transistor T5; and the second capacitor C2 has a third capacitor electrode Ce3 and a fourth capacitor electrode Ce4.

[0135] In some embodiments, the third capacitor electrode Ce3 of the second capacitor C2 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the first electrode of the fifth transistor T5.

[0136] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, the first electrode of the fifth transistor T5 is connected to the fourth capacitor electrode Ce4 of the second capacitor C2, and the second electrode of the fifth transistor T5 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0137] The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0138] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, the second electrode of the fifth transistor T5, and the anode of the light-emitting element LE.

[0139] The pixel driving circuit according to this disclosure includes a fifth transistor T5 and a second capacitor C2, which generate conductive paths at different operating stages. When the fifth transistor T5 is turned on, the second capacitor C2 is connected in parallel with the light-emitting element LE, resulting in an increase in the total capacitance that needs to be charged. This affects the behavior of the circuit by modifying the distribution of current and charge. When the fifth transistor T5 is turned off, the second capacitor C2 is independent of the light-emitting process and does not affect the main light-emitting path.

[0140] The inventors of this disclosure have discovered that adding a fifth transistor T5 and a second capacitor C2 solves two key problems in the prior art. First, the incorporation of a bypass current path improves the accuracy of small current control in the drive transistor Td, which struggles to effectively handle such low current. Second, the pixel drive circuit according to this disclosure accelerates the turn-on speed at low grayscale by allowing a preset voltage to be written to the second capacitor C2 before the light-emitting phase. This reduces the time required for the pixel to reach the turn-on threshold, thereby solving the problem of slow response at low brightness levels. In summary, these improvements significantly enhance the performance of the pixel circuit under challenging low brightness and low grayscale conditions.

[0141] exist Figure 6In the pixel driving circuit shown, the fifth transistor T5 (and the second capacitor C2 connected to the fifth transistor T5) is connected to the fourth node N4. During the low-brightness, low-grayscale emission stage, by setting the gate of the fifth transistor T5 to a low level, the current in the emission path is divided into two parts: a first part I1, which flows through the light-emitting element LE, and a second part I2, which flows through the fifth transistor T5. The charge corresponding to the second part I2 can be stored in the second capacitor C2. As a result, the total current flowing through the driving transistor Td becomes I1 + I2. Compared to existing pixel driving circuits where only I1 flows through the driving transistor Td, the total current flowing through the driving transistor Td in the pixel driving circuit according to this disclosure is increased. This allows the driving transistor Td to operate in a more precisely controlled region, thereby improving the accuracy of current regulation in the circuit.

[0142] Furthermore, prior to the low grayscale emission stage, the fifth transistor T5 can be turned on, and the voltage of Vint4 can be adjusted to pre-charge the N4 node voltage and the OLED capacitor. Subsequently, the third transistor T3 and the fourth transistor T4 are turned on to enable emission. This method solves the delayed start-up problem in the low grayscale case, improves the response time, and ensures better performance.

[0143] Reference Figure 6 In some embodiments, the pixel driving circuit includes a driving transistor Td, a light-emitting element LE, and a node located between the driving transistor Td and the light-emitting element LE. In some embodiments, the pixel driving circuit further includes a fifth transistor T5 and a second capacitor C2 connected to the fifth transistor T5. The second electrode of the fifth transistor T5 is connected to the node located between the driving transistor Td and the light-emitting element LE.

[0144] exist Figure 6 In the pixel driving circuit shown, the pixel driving circuit further includes a light-emitting control transistor (e.g., a fourth transistor T4), which is connected to the driving transistor Td and to the light-emitting element LE. In some embodiments, the second electrode of the fifth transistor T5 is connected to the second electrode of the light-emitting control transistor and the anode of the light-emitting element LE. For example, the second electrode of the fifth transistor T5 is connected to the fourth node N4.

[0145] In some embodiments, the third capacitor electrode Ce3 of the second capacitor C2 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the first electrode of the fifth transistor T5.

[0146] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, the first electrode of the fifth transistor T5 is connected to the fourth capacitor electrode Ce4 of the second capacitor C2, and the second electrode of the fifth transistor T5 is connected to the second electrode of the light-emitting control transistor (e.g., the fourth transistor T4) and the anode of the light-emitting element LE.

[0147] The inventors of this disclosure have discovered that several advantages can be achieved by configuring a second capacitor C2 and a fifth transistor T5. First, the problem of insufficient black-state performance arises, primarily because the black-state Vdata is already quite high (typically set to VGMP), yet the current is still insufficient to achieve a truly black state. Vdata refers to the data voltage applied to the pixel during the data writing phase of an AMOLED display's operation. It represents the voltage that determines the pixel's brightness level. VGMP refers to the gate modulation potential voltage, which is typically used in AMOLED driving circuits as a reference voltage to control the transistor gate, especially under low brightness or black-state conditions.

[0148] Increasing the capacitance between the fourth node N4 and the cathode (Vss) reduces the charging of the light-emitting element (LE), thereby improving the black state. Theoretically, increasing VGMP could also achieve a black state, but this method would result in excessive power consumption due to the higher voltage. In this disclosure, the black state is optimized by turning on the fifth transistor T5, which adds a second capacitor C2 in parallel with the capacitor between the fourth node N4 and the cathode. This increases the total capacitance and improves black state performance. In related pixel driving circuits, a common approach is to increase the anode area to improve the capacitance between the fourth node N4 and the cathode, especially for red and green pixels, where achieving a complete black state is more challenging. However, increasing the capacitance between the fourth node N4 and the cathode in this way introduces problems such as slow low-grayscale turn-on and ghosting.

[0149] Second, because the potential of the fourth node N4 cannot reach the turn-on voltage Vop of the light-emitting element LE, a problem of not lighting up at low grayscale occurs. In this case, turning on the fifth transistor T5 and adjusting the voltage at the second capacitor C2 (which requires integrated circuit support for AC Vint4, for example, an AC signal applied to the third capacitor electrode Ce3 of the second capacitor C2) allows a voltage jump variable to be written to the fourth node N4. This enables the pre-charging of the potential of the fourth node N4, allowing the fourth node N4 to quickly reach the turn-on voltage Vop at low grayscale. By configuring different capacitors for different RGB light-emitting devices, this disclosure enables synchronous lighting up at low grayscale across all colors.

[0150] exist Figure 4In the pixel driving circuit shown, adding a fifth transistor T5 requires its gate to be controlled by a corresponding second light emission control signal line em2 among multiple second light emission control signal lines. This necessitates an additional gate-on-array (GOA) driver, which affects the bezel size of the display. Furthermore, including multiple second light emission control signal lines for controlling the fifth transistor T5 in the active area reduces the available wiring space in high pixel density (high PPI) displays, increases crosstalk between signal lines, and reduces light transmittance.

[0151] exist Figure 6 In the pixel driving circuit shown, the fifth transistor T5 (along with the third transistor T3 and the fourth transistor T4) is controlled by a corresponding light emission control signal line em among multiple light emission control signal lines. The fifth transistor T5 is simultaneously turned on or off along with the third transistor T3 and the fourth transistor T4. With this modification, the second capacitor C2 will be included in the circuitry used for both high and low grayscale levels, which may affect performance. Additionally, the ability to independently control the on / off state of the fifth transistor T5 is reduced.

[0152] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figures 3A to 6 The second transistor T2 is an n-type transistor, such as a metal-oxide-semiconductor (MOS) transistor, while the other transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0153] In some embodiments, a respective second voltage supply line Vss among a plurality of second voltage supply lines is configured to provide a negative voltage signal.

[0154] In some embodiments, a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines is configured to provide a negative voltage signal. In an alternative embodiment, a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines is configured to provide a positive voltage signal. In an alternative embodiment, a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines is configured to provide an AC voltage. The inventors of this disclosure have found that negative voltages can be used to reduce unwanted current or leakage at certain stages. Positive voltages can facilitate the pre-charging or activation of certain components in a circuit. Dynamic AC voltages enable precise control and modulation, addressing specific challenges such as synchronization, pre-charging, or improving performance at low grayscale levels.

[0155] In addition, Figure 3A , Figure 4 and Figure 6 In the pixel driving circuit shown, by simply introducing the fifth transistor T5, the purpose of current shunting and rapid brightening at low gray levels can be achieved even without adding the second capacitor C2. In this case, the current flowing through the fifth transistor T5 will enter the fourth reset signal line circuit network, which operates in a constant voltage state.

[0156] exist Figure 4 In the pixel driving circuit shown, the gate of the fifth transistor T5 is controlled by the corresponding second light-emitting control signal line em2, which is different from the corresponding light-emitting control signal line em that controls the gate of the fourth transistor T4. Figure 6 In the pixel driving circuit shown, the fourth transistor T4 and the fifth transistor T5 are simultaneously turned on and off.

[0157] Figure 4 The pixel driving circuit shown allows the corresponding second light-emitting control signal line em2 to be independently turned on when the corresponding light-emitting control signal line em is turned off, enabling pre-charging of the fourth node N4 before light emission. This improves the turn-on speed of the light-emitting element LE. Furthermore, since the current bypass function is only required at low brightness and low grayscale, separating the gate control of the fourth transistor T4 and the fifth transistor T5 allows the current bypass function to be disabled at high brightness and high grayscale, thereby reducing screen power consumption.

[0158] On the contrary, Figure 6 In the pixel driving circuit shown, the fourth transistor T4 and the fifth transistor T5 share a common GOA control and are simultaneously turned on and off. This configuration reduces the display bezel size by eliminating the need for additional control lines.

[0159] Figure 7 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 7In some embodiments, the pixel driving circuit includes a driving transistor Td; a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines. The transistor comprises: a first electrode connected to the second electrode of the driving transistor Td; a second electrode connected to the first capacitor electrode Ce1 of the first capacitor C1 and the gate of the driving transistor Td; a third transistor T3 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the first electrode of the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE; and a fifth transistor T5.

[0160] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, the first electrode of the fifth transistor T5 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td, the second electrode of the second reset transistor Tr2, the first electrode of the second transistor T2, and the first electrode of the fourth transistor T4.

[0161] The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0162] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, the second electrode of the second reset transistor Tr2, and the second electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0163] The inventors of this disclosure have discovered that adding a fifth transistor T5 solves two key problems in the prior art. First, the incorporation of a bypass current path improves the accuracy of small current control in the drive transistor Td, which struggles to effectively handle such low current. Second, the pixel drive circuit according to this disclosure accelerates the turn-on speed at low grayscale by allowing a preset voltage to be written to the fourth reset signal network before the light-emitting phase. This reduces the time required for the pixel to reach the turn-on threshold, thereby solving the problem of slow response at low brightness levels. In summary, these improvements significantly enhance the performance of the pixel circuit under challenging low brightness and low grayscale conditions.

[0164] exist Figure 7 In the pixel driving circuit shown, the fifth transistor T5 is connected to the third node N3. During the low-brightness, low-grayscale emission stage, by setting the gate of the fifth transistor T5 to a low level, the current in the emission path is divided into two parts: a first part I1, which flows through the fourth transistor T4 and the light-emitting element LE, and a second part I2, which flows through the fifth transistor T5. The charge corresponding to the second part I2 can be stored in the fourth reset signal network. As a result, the total current flowing through the driving transistor Td becomes I1 + I2. Compared to existing pixel driving circuits where only I1 flows through the driving transistor Td, the total current flowing through the driving transistor Td in the pixel driving circuit according to this disclosure is increased. This allows the driving transistor Td to operate in a more precisely controlled region, thereby improving the accuracy of current regulation in the circuit.

[0165] Reference Figure 7In some embodiments, the pixel driving circuit includes a driving transistor Td, a light-emitting element LE, and a node located between the driving transistor Td and the light-emitting element LE. In some embodiments, the pixel driving circuit further includes a fifth transistor T5. The second electrode of the fifth transistor T5 is connected to the node located between the driving transistor Td and the light-emitting element LE.

[0166] exist Figure 7 In the pixel driving circuit shown, the pixel driving circuit also includes a light-emitting control transistor (e.g., a fourth transistor T4), which is connected to the driving transistor Td and to the light-emitting element LE. In some embodiments, the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td and the first electrode of the light-emitting control transistor. For example, the second electrode of the fifth transistor T5 is connected to the third node N3.

[0167] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, the first electrode of the fifth transistor T5 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td and the first electrode of the light emission control transistor (e.g., the fourth transistor T4).

[0168] The inventors of this disclosure have discovered that several advantages can be achieved by configuring a fifth transistor T5. For example, the problem of insufficient black-state performance arises primarily because the black-state Vdata is already quite high (typically set to VGMP), yet the current is still insufficient to achieve a complete black state. Vdata refers to the data voltage applied to the pixel during the data writing phase of AMOLED display operation. It represents the voltage that determines the pixel's brightness level. VGMP refers to the gate modulation potential voltage, which is typically used as a reference voltage for controlling the gate of transistors in AMOLED driving circuits, especially under low brightness or black-state conditions.

[0169] Increasing the capacitance between the fourth node N4 and the cathode (Vss) reduces the charging of the light-emitting element (LE), thereby improving the black state. Theoretically, increasing VGMP could also achieve a black state, but this method would result in excessive power consumption due to the higher voltage. In this disclosure, the black state is optimized by turning on the fifth transistor T5, which adds a fourth reset signal network in parallel with the capacitor between the fourth node N4 and the cathode. This increases the total capacitance and improves black state performance. In related pixel driving circuits, a common approach is to increase the anode area to increase the capacitance between the fourth node N4 and the cathode, especially for red and green pixels, where achieving a complete black state is more challenging. However, increasing the capacitance between the fourth node N4 and the cathode in this way introduces problems such as slow low-grayscale turn-on and ghosting.

[0170] In the pixel driving circuit shown in Figure 3, the gate of the fifth transistor T5 is controlled separately from the gates of the third transistor T3 and the fourth transistor T4. This allows the fifth transistor T5 to conduct when the second transistor T2, the third transistor T3, the fourth transistor T4, and the second reset transistor Tr2 are all off (i.e., before the light-emitting stage). By turning on the fifth transistor T5, the voltage at the third node N3 can be reset. The reset voltage is closer to the voltage of the corresponding voltage supply line Vdd, which allows the voltages at the third node N3 and the fourth node N4 to reach the light-emitting element turn-on voltage more quickly in the subsequent light-emitting stage, thus achieving faster turn-on.

[0171] Figure 8 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 8In some embodiments, the pixel driving circuit includes a driving transistor Td; a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines. The transistor comprises: a first electrode connected to the second electrode of the driving transistor Td; a second electrode connected to the first capacitor electrode Ce1 of the first capacitor C1 and the gate of the driving transistor Td; a third transistor T3 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the first electrode of the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE; and a fifth transistor T5.

[0172] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, the first electrode of the fifth transistor T5 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the second electrode of the fifth transistor T5 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0173] The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0174] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, the second electrode of the fifth transistor T5, and the anode of the light-emitting element LE.

[0175] The pixel driving circuit according to this disclosure includes a fifth transistor T5, which generates a conductive path at different operating stages. When the fifth transistor T5 is turned on, a fourth reset signal network is connected in parallel with the light-emitting element LE, resulting in an increase in the total capacitance requiring charging. This affects the behavior of the circuit by modifying the distribution of current and charge. When the fifth transistor T5 is turned off, the fourth reset signal network is independent of the light-emitting process and does not affect the main light-emitting path.

[0176] The inventors of this disclosure have discovered that adding a fifth transistor T5 solves two key problems in the prior art. First, the incorporation of a bypass current path improves the accuracy of small current control in the drive transistor Td, which struggles to effectively handle such low current. Second, the pixel drive circuit according to this disclosure accelerates the turn-on speed at low grayscale by allowing a preset voltage to be written to the fourth reset signal network before the light-emitting phase. This reduces the time required for the pixel to reach the turn-on threshold, thereby solving the problem of slow response at low brightness levels. In summary, these improvements significantly enhance the performance of the pixel circuit under challenging low brightness and low grayscale conditions.

[0177] exist Figure 8In the pixel driving circuit shown, the fifth transistor T5 is connected to the fourth node N4. During the low-brightness, low-grayscale emission stage, by setting the gate of the fifth transistor T5 to a low level, the current in the emission path is divided into two parts: a first part I1, which flows through the light-emitting element LE, and a second part I2, which flows through the fifth transistor T5. The charge corresponding to the second part I2 can be stored in the fourth reset signal network. As a result, the total current flowing through the driving transistor Td becomes I1 + I2. Compared to existing pixel driving circuits where only I1 flows through the driving transistor Td, the total current flowing through the driving transistor Td in the pixel driving circuit according to this disclosure is increased. This allows the driving transistor Td to operate in a more precisely controlled region, thereby improving the accuracy of current regulation in the circuit.

[0178] Furthermore, prior to the low grayscale emission stage, the fifth transistor T5 can be turned on, and the voltage of Vint4 can be adjusted to pre-charge the N4 node voltage and the OLED capacitor. Subsequently, the third transistor T3 and the fourth transistor T4 are turned on to enable emission. This method solves the delayed start-up problem in the low grayscale case, improves the response time, and ensures better performance.

[0179] Reference Figure 8 In some embodiments, the pixel driving circuit includes a driving transistor Td, a light-emitting element LE, and a node located between the driving transistor Td and the light-emitting element LE. In some embodiments, the pixel driving circuit further includes a fifth transistor T5. The second electrode of the fifth transistor T5 is connected to the node located between the driving transistor Td and the light-emitting element LE.

[0180] exist Figure 8 In the pixel driving circuit shown, the pixel driving circuit further includes a light-emitting control transistor (e.g., a fourth transistor T4), which is connected to the driving transistor Td and to the light-emitting element LE. In some embodiments, the second electrode of the fifth transistor T5 is connected to the second electrode of the light-emitting control transistor and the anode of the light-emitting element LE. For example, the second electrode of the fifth transistor T5 is connected to the fourth node N4.

[0181] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding second light-emitting control signal line em2 among a plurality of second light-emitting control signal lines, the first electrode of the fifth transistor T5 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the second electrode of the fifth transistor T5 is connected to the second electrode of the light-emitting control transistor (e.g., the fourth transistor T4) and the anode of the light-emitting element LE.

[0182] The inventors of this disclosure have discovered that several advantages can be achieved by configuring a fifth transistor T5. For example, the problem of insufficient black-state performance arises primarily because the black-state Vdata is already quite high (typically set to VGMP), yet the current is still insufficient to achieve a complete black state. Vdata refers to the data voltage applied to the pixel during the data writing phase of AMOLED display operation. It represents the voltage that determines the pixel's brightness level. VGMP refers to the gate modulation potential voltage, which is typically used as a reference voltage for controlling the gate of transistors in AMOLED driving circuits, especially under low brightness or black-state conditions.

[0183] Increasing the capacitance between the fourth node N4 and the cathode (Vss) reduces the charging of the light-emitting element (LE), thereby improving the black state. Theoretically, increasing VGMP could also achieve a black state, but this method would result in excessive power consumption due to the higher voltage. In this disclosure, the black state is optimized by turning on the fifth transistor T5, which adds a fourth reset signal network in parallel with the capacitor between the fourth node N4 and the cathode. This increases the total capacitance and improves black state performance. In related pixel driving circuits, a common approach is to increase the anode area to increase the capacitance between the fourth node N4 and the cathode, especially for red and green pixels, where achieving a complete black state is more challenging. However, increasing the capacitance between the fourth node N4 and the cathode in this way introduces problems such as slow low-grayscale turn-on and ghosting.

[0184] Figure 9 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 9In some embodiments, the pixel driving circuit includes a driving transistor Td; a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines. The transistor comprises: a first electrode connected to the second electrode of the driving transistor Td; a second electrode connected to the first capacitor electrode Ce1 of the first capacitor C1 and the gate of the driving transistor Td; a third transistor T3 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the first electrode of the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE; and a fifth transistor T5.

[0185] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, the first electrode of the fifth transistor T5 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the second electrode of the fifth transistor T5 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0186] The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0187] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, the second electrode of the fifth transistor T5, and the anode of the light-emitting element LE.

[0188] The pixel driving circuit according to this disclosure includes a fifth transistor T5, which generates a conductive path at different operating stages. When the fifth transistor T5 is turned on, a fourth reset signal network is connected in parallel with the light-emitting element LE, resulting in an increase in the total capacitance requiring charging. This affects the behavior of the circuit by modifying the distribution of current and charge. When the fifth transistor T5 is turned off, the fourth reset signal network is independent of the light-emitting process and does not affect the main light-emitting path.

[0189] The inventors of this disclosure have discovered that adding a fifth transistor T5 solves two key problems in the prior art. First, the incorporation of a bypass current path improves the accuracy of small current control in the drive transistor Td, which struggles to effectively handle such low current. Second, the pixel drive circuit according to this disclosure accelerates the turn-on speed at low grayscale by allowing a preset voltage to be written to the fourth reset signal network before the light-emitting phase. This reduces the time required for the pixel to reach the turn-on threshold, thereby solving the problem of slow response at low brightness levels. In summary, these improvements significantly enhance the performance of the pixel circuit under challenging low brightness and low grayscale conditions.

[0190] exist Figure 9In the pixel driving circuit shown, the fifth transistor T5 is connected to the fourth node N4. During the low-brightness, low-grayscale emission stage, by setting the gate of the fifth transistor T5 to a low level, the current in the emission path is divided into two parts: a first part I1, which flows through the light-emitting element LE, and a second part I2, which flows through the fifth transistor T5. The charge corresponding to the second part I2 can be stored in the fourth reset signal network. As a result, the total current flowing through the driving transistor Td becomes I1 + I2. Compared to existing pixel driving circuits where only I1 flows through the driving transistor Td, the total current flowing through the driving transistor Td in the pixel driving circuit according to this disclosure is increased. This allows the driving transistor Td to operate in a more precisely controlled region, thereby improving the accuracy of current regulation in the circuit.

[0191] Furthermore, prior to the low grayscale emission stage, the fifth transistor T5 can be turned on, and the voltage of Vint4 can be adjusted to pre-charge the N4 node voltage and the OLED capacitor. Subsequently, the third transistor T3 and the fourth transistor T4 are turned on to enable emission. This method solves the delayed start-up problem in the low grayscale case, improves the response time, and ensures better performance.

[0192] Reference Figure 9 In some embodiments, the pixel driving circuit includes a driving transistor Td, a light-emitting element LE, and a node located between the driving transistor Td and the light-emitting element LE. In some embodiments, the pixel driving circuit further includes a fifth transistor T5. The second electrode of the fifth transistor T5 is connected to the node located between the driving transistor Td and the light-emitting element LE.

[0193] exist Figure 9 In the pixel driving circuit shown, the pixel driving circuit further includes a light-emitting control transistor (e.g., a fourth transistor T4), which is connected to the driving transistor Td and to the light-emitting element LE. In some embodiments, the second electrode of the fifth transistor T5 is connected to the second electrode of the light-emitting control transistor and the anode of the light-emitting element LE. For example, the second electrode of the fifth transistor T5 is connected to the fourth node N4.

[0194] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, the first electrode of the fifth transistor T5 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the second electrode of the fifth transistor T5 is connected to the second electrode of the light-emitting control transistor (e.g., the fourth transistor T4) and the anode of the light-emitting element LE.

[0195] The inventors of this disclosure have discovered that several advantages can be achieved by configuring a fifth transistor T5. For example, the problem of insufficient black-state performance arises primarily because the black-state Vdata is already quite high (typically set to VGMP), yet the current is still insufficient to achieve a complete black state. Vdata refers to the data voltage applied to the pixel during the data writing phase of AMOLED display operation. It represents the voltage that determines the pixel's brightness level. VGMP refers to the gate modulation potential voltage, which is typically used as a reference voltage for controlling the gate of transistors in AMOLED driving circuits, especially under low brightness or black-state conditions.

[0196] Increasing the capacitance between the fourth node N4 and the cathode (Vss) reduces the charging of the light-emitting element (LE), thereby improving the black state. Theoretically, increasing VGMP could also achieve a black state, but this method would result in excessive power consumption due to the higher voltage. In this disclosure, the black state is optimized by turning on the fifth transistor T5, which adds a fourth reset signal network in parallel with the capacitor between the fourth node N4 and the cathode. This increases the total capacitance and improves black state performance. In related pixel driving circuits, a common approach is to increase the anode area to increase the capacitance between the fourth node N4 and the cathode, especially for red and green pixels, where achieving a complete black state is more challenging. However, increasing the capacitance between the fourth node N4 and the cathode in this way introduces problems such as slow low-grayscale turn-on and ghosting.

[0197] Various suitable implementations can be practiced in this disclosure. In some embodiments, the fifth transistor may be implemented as a driving thin-film transistor, and the shunt magnitude may be directly controlled by the conduction state conditions of the fifth transistor T5 in its linear region, thereby eliminating the need for a separately adjustable fourth reset signal.

[0198] Figure 10 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. Figure 10 The pixel driving circuit shown is Figure 7 The difference in the pixel driving circuit shown is that the first electrode of the fifth transistor T5 is not connected to the corresponding fourth reset signal line. Alternatively, the fifth transistor T5 can be implemented as a driving thin-film transistor. When a transistor is implemented as a driving transistor, it makes full use of its current characteristics. For example, the implemented driving transistor typically operates in the linear region, where the drain current is controlled by the gate voltage. This type of transistor has a relatively large gate voltage range (data range) between the on and off states, and its characteristic curve is relatively flat. Conversely, other transistors are typically used as switching transistors. They rely on voltage characteristics and operate in an "on" or "off" state controlled by the gate voltage. These transistors have a smaller gate voltage range between the on and off states, and their characteristic curves are steeper.

[0199] Furthermore, the implemented driving transistors typically have a large aspect ratio, for example, a width-to-length (W / L) ratio of 3.5 / 20. In contrast, switching transistors have a smaller aspect ratio, such as 3.5 / 4. Therefore, the implemented driving transistors occupy a larger layout area in the pixel driving circuitry.

[0200] The current bypass concept according to this disclosure allows for adjustment of the current bypass amplitude based on grayscale, similar to the concept of a sliding resistor. One embodiment provided in the examples involves charging a capacitor for current bypass, wherein the current bypass amplitude is controlled by adjusting the voltage of the corresponding fourth reset signal line Vint4 at the other terminal. Another embodiment allows a fifth transistor T5 to operate in the linear region, wherein the bypass current is adjustable. In this case, the fifth transistor T5 can be implemented as a drive transistor, thereby eliminating the need for the corresponding fourth reset signal line Vint4.

[0201] Figure 11 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. Figure 11 The pixel driving circuit shown is Figure 8 The difference in the pixel driving circuit shown is that the first electrode of the fifth transistor T5 is not connected to the corresponding fourth reset signal line. Alternatively, the fifth transistor T5 can be implemented as a driving thin-film transistor.

[0202] Figure 12 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. Figure 12 The pixel driving circuit shown is Figure 9 The difference in the pixel driving circuit shown is that the first electrode of the fifth transistor T5 is not connected to the corresponding fourth reset signal line. Alternatively, the fifth transistor T5 can be implemented as a driving thin-film transistor.

[0203] Figure 13 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 13In some embodiments, the pixel driving circuit includes a driving transistor Td; a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines, a first electrode connected to a second electrode of the driving transistor Td, and a second electrode connected to a first capacitor C1. A capacitor electrode Ce1 and a second electrode of the gate of a driving transistor Td; a third transistor T3 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the first electrode of the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE; a fifth transistor T5; a second capacitor C2 having a third capacitor electrode Ce3 and a fourth capacitor electrode Ce4; a sixth transistor T6; and a third capacitor C3 having a fifth capacitor electrode Ce5 and a sixth capacitor electrode Ce6.

[0204] In some embodiments, the third capacitor electrode Ce3 of the second capacitor C2 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the first electrode of the fifth transistor T5.

[0205] In some embodiments, the fifth capacitor electrode Ce5 of the third capacitor C3 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the sixth capacitor electrode Ce6 of the third capacitor C3 is connected to the first electrode of the sixth transistor T6.

[0206] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, the first electrode of the fifth transistor T5 is connected to the fourth capacitor electrode Ce4 of the second capacitor C2, and the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td, the second electrode of the second reset transistor Tr2, the first electrode of the second transistor T2, and the first electrode of the fourth transistor T4.

[0207] In some embodiments, the gate of the sixth transistor T6 is connected to a corresponding second light-emitting control signal line em2 among a plurality of second light-emitting control signal lines, the first electrode of the sixth transistor T6 is connected to the sixth capacitor electrode Ce6 of the third capacitor C3, and the second electrode of the sixth transistor T6 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0208] The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0209] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the first electrode of the second transistor T2, the first electrode of the fourth transistor T4, the second electrode of the second reset transistor Tr2, and the second electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, the second electrode of the sixth transistor T6, and the anode of the light-emitting element LE.

[0210] The pixel driving circuit according to this disclosure includes a fifth transistor T5 and a second capacitor C2, which generate conductive paths at different operating stages. When the fifth transistor T5 is turned on, the second capacitor C2 is connected in parallel with the light-emitting element LE, resulting in an increase in the total capacitance that needs to be charged. This affects the behavior of the circuit by modifying the distribution of current and charge. When the fifth transistor T5 is turned off, the second capacitor C2 is independent of the light-emitting process and does not affect the main light-emitting path.

[0211] The pixel driving circuit according to this disclosure also includes a sixth transistor T6 and a third capacitor C3, which generate conductive paths at different operating stages. When the sixth transistor T6 is turned on, the third capacitor C3 is connected in parallel with the light-emitting element LE, resulting in an increase in the total capacitance that needs to be charged. This affects the behavior of the circuit by modifying the distribution of current and charge. When the sixth transistor T6 is turned off, the third capacitor C3 is independent of the light-emitting process and does not affect the main light-emitting path.

[0212] The inventors of this disclosure have discovered that adding a fifth transistor T5, a second capacitor C2, a sixth transistor T6, and a third capacitor C3 solves two key problems in the prior art. First, the incorporation of a bypass current path improves the accuracy of small current control in the drive transistor Td, which struggles to effectively handle such low current. Second, the pixel drive circuit according to this disclosure accelerates the turn-on speed at low grayscale by allowing a preset voltage to be written to the second capacitor C2 and the third capacitor C3 before the light-emitting phase. This reduces the time required for the pixel to reach the turn-on threshold, thereby solving the problem of slow response at low brightness levels. In summary, these improvements significantly enhance the performance of the pixel circuit under challenging low-brightness, low-grayscale conditions.

[0213] exist Figure 13 In the pixel driving circuit shown, the fifth transistor T5 (and the second capacitor C2 connected to the fifth transistor T5) is connected to the third node N3. During the low-brightness, low-grayscale emission stage, by setting the gate of the fifth transistor T5 to a low level, the current in the emission path is divided into two parts: a first part I1, which flows through the fourth transistor T4 and the light-emitting element LE, and a second part I2, which flows through the fifth transistor T5. The charge corresponding to the second part I2 can be stored in the second capacitor C2. As a result, the total current flowing through the driving transistor Td becomes I1 + I2. Compared to existing pixel driving circuits where only I1 flows through the driving transistor Td, the total current flowing through the driving transistor Td in the pixel driving circuit according to this disclosure is increased. This allows the driving transistor Td to operate in a more precisely controlled region, thereby improving the accuracy of current regulation in the circuit.

[0214] exist Figure 13In the pixel driving circuit shown, the sixth transistor T6 (and the third capacitor C3 connected to the sixth transistor T6) is connected to the fourth node N4. During the low-brightness, low-grayscale emission stage, by setting the gate of the sixth transistor T6 to a low level, the current in the emission path is divided into two parts: a first part I1, which flows through the light-emitting element LE, and a second part I2, which flows through the sixth transistor T6. The charge corresponding to the second part I2 can be stored in the third capacitor C3. As a result, the total current flowing through the driving transistor Td becomes I1 + I2. Compared to existing pixel driving circuits where only I1 flows through the driving transistor Td, the total current flowing through the driving transistor Td in the pixel driving circuit according to this disclosure is increased. This allows the driving transistor Td to operate in a more precisely controlled region, thereby improving the accuracy of current regulation in the circuit.

[0215] Furthermore, prior to the low grayscale emission stage, the sixth transistor T6 can be turned on, and the voltage of Vint4 can be adjusted to pre-charge the N4 node voltage and the OLED capacitor. Subsequently, the third transistor T3 and the fourth transistor T4 are turned on to enable emission. This method solves the delayed start-up problem in the low grayscale case, improves the response time, and ensures better performance.

[0216] Reference Figure 13 In some embodiments, the pixel driving circuit includes a driving transistor Td, a light-emitting element LE, and a node located between the driving transistor Td and the light-emitting element LE. In some embodiments, the pixel driving circuit further includes a fifth transistor T5, a second capacitor C2 connected to the fifth transistor T5, a sixth transistor T6, and a third capacitor C3 connected to the sixth transistor T6. The second electrode of the fifth transistor T5 is connected to the node located between the driving transistor Td and the light-emitting element LE (e.g., a third node N3). The second electrode of the sixth transistor T6 is connected to the node located between the driving transistor Td and the light-emitting element LE (e.g., a fourth node N4).

[0217] exist Figure 13 In the pixel driving circuit shown, the pixel driving circuit also includes a light-emitting control transistor (e.g., a fourth transistor T4), which is connected to the driving transistor Td and to the light-emitting element LE. In some embodiments, the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td and the first electrode of the light-emitting control transistor. For example, the second electrode of the fifth transistor T5 is connected to the third node N3.

[0218] exist Figure 13In the pixel driving circuit shown, the pixel driving circuit also includes a light-emitting control transistor (e.g., a fourth transistor T4), which is connected to the driving transistor Td and to the light-emitting element LE. In some embodiments, the second electrode of the sixth transistor T6 is connected to the second electrode of the light-emitting control transistor and the anode of the light-emitting element LE. For example, the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0219] In some embodiments, the third capacitor electrode Ce3 of the second capacitor C2 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the first electrode of the fifth transistor T5.

[0220] In some embodiments, the fifth capacitor electrode Ce5 of the third capacitor C3 is connected to a corresponding fourth reset signal line Vint4 among a plurality of fourth reset signal lines, and the sixth capacitor electrode Ce6 of the third capacitor C3 is connected to the first electrode of the sixth transistor T6.

[0221] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, the first electrode of the fifth transistor T5 is connected to the fourth capacitor electrode Ce4 of the second capacitor C2, and the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor Td and the first electrode of the light emission control transistor (e.g., the fourth transistor T4).

[0222] In some embodiments, the gate of the sixth transistor T6 is connected to a corresponding second light emission control signal line em2 among a plurality of second light emission control signal lines, the first electrode of the sixth transistor T6 is connected to the sixth capacitor electrode Ce6 of the third capacitor C3, and the second electrode of the sixth transistor T6 is connected to the second electrode of the light emission control transistor (e.g., the fourth transistor T4) and the anode of the light emission element LE.

[0223] The inventors of this disclosure have discovered that several advantages can be achieved by configuring a second capacitor C2, a third capacitor C3, a fifth transistor T5, and a sixth transistor T6. First, the problem of insufficient black-state performance arises, primarily because the black-state Vdata is already quite high (typically set to VGMP), yet the current is still insufficient to achieve a truly black state. Vdata refers to the data voltage applied to the pixel during the data writing phase of an AMOLED display's operation. It represents the voltage that determines the pixel's brightness level. VGMP refers to the gate modulation potential voltage, which is typically used as a reference voltage for controlling the transistor gate in AMOLED driving circuits, especially under low brightness or black-state conditions.

[0224] Increasing the capacitance between the fourth node N4 and the cathode (Vss) reduces the charging of the light-emitting element (LE), thereby improving the black state. Theoretically, increasing VGMP could also achieve a black state, but this method would result in excessive power consumption due to the higher voltage. In this disclosure, the black state is optimized by turning on the fifth transistor T5, which adds a second capacitor C2 in parallel with the capacitor between the fourth node N4 and the cathode. This increases the total capacitance and improves black state performance. In related pixel driving circuits, a common approach is to increase the anode area to improve the capacitance between the fourth node N4 and the cathode, especially for red and green pixels, where achieving a complete black state is more challenging. However, increasing the capacitance between the fourth node N4 and the cathode in this way introduces problems such as slow low-grayscale turn-on and ghosting.

[0225] Second, because the potential of the fourth node N4 cannot reach the turn-on voltage Vop of the light-emitting element LE, a problem of not lighting up at low grayscale occurs. In this case, turning on the fifth transistor T5 and adjusting the voltage at the second capacitor C2 (which requires integrated circuit support for AC Vint4, for example, an AC signal applied to the third capacitor electrode Ce3 of the second capacitor C2) allows a voltage jump variable to be written to the fourth node N4. This enables the pre-charging of the potential of the fourth node N4, allowing the fourth node N4 to quickly reach the turn-on voltage Vop at low grayscale. By configuring different capacitors for different RGB light-emitting devices, this disclosure enables synchronous lighting up at low grayscale across all colors.

[0226] In another aspect, the present invention provides a display device including a pixel driving circuit described herein or manufactured by the methods described herein, and a light-emitting element connected to the pixel driving circuit. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS devices, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0227] In another aspect, this disclosure provides a method of operating a pixel driving circuit. In some embodiments, the pixel driving circuit includes a driving transistor; a light-emitting element; a node located between the driving transistor and the light-emitting element; a fifth transistor; and a second capacitor. Optionally, the second capacitor is connected to the fifth transistor. Optionally, the fifth transistor is connected to the node located between the driving transistor and the light-emitting element. In some embodiments, the method includes turning on the driving transistor and the fifth transistor during a light-emitting sub-phase of a frame image.

[0228] In some embodiments, the method further includes determining whether the light-emitting element is configured to display a relatively low grayscale image. Optionally, when the light-emitting element is configured to display the relatively low grayscale image, the fifth transistor is turned on during a light-emitting sub-phase of a frame image.

[0229] In some embodiments, the method further includes turning off the fifth transistor when it is determined that the light-emitting element is configured to display a relatively high grayscale image.

[0230] In some embodiments, a relatively low grayscale image is an image having a grayscale value less than 50, such as less than 45, less than 40, less than 35, less than 30, less than 25, less than 20, less than 15, less than 10, or less than 5.

[0231] In some embodiments, a relatively high grayscale image is an image with a grayscale value greater than or equal to 50, such as greater than or equal to 55, greater than or equal to 60, greater than or equal to 65, greater than or equal to 70, greater than or equal to 75, greater than or equal to 80, greater than or equal to 85, greater than or equal to 90, greater than or equal to 95, or greater than or equal to 100.

[0232] In some embodiments, the method further includes providing a fourth reset signal to the third capacitor electrode of the second capacitor via a respective fourth reset signal line among a plurality of fourth reset signal lines.

[0233] In some embodiments, the method further includes providing a second voltage supply signal to a third capacitor electrode of a second capacitor via a respective second voltage supply line of a plurality of second voltage supply lines.

[0234] In another aspect, this disclosure provides a method for manufacturing a pixel driving circuit. In some embodiments, the method includes forming a driving transistor; forming a light-emitting element; forming a node located between the driving transistor and the light-emitting element; forming a fifth transistor; and forming a second capacitor. Optionally, the second capacitor is connected to the fifth transistor. Optionally, the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

[0235] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A pixel driving circuit, comprising: Drive transistors; Light-emitting elements; The node located between the driving transistor and the light-emitting element; The fifth transistor; as well as Second capacitor; The second capacitor is connected to the fifth transistor; as well as The fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

2. The pixel driving circuit according to claim 1 further includes a light-emitting control transistor, the light-emitting control transistor being connected to the driving transistor and connected to the light-emitting element; in, The fifth transistor is connected to the second electrode of the driving transistor and the first electrode of the light-emitting control transistor.

3. The pixel driving circuit according to claim 1 further includes a light-emitting control transistor, the light-emitting control transistor being connected to the driving transistor and connected to the light-emitting element; in, The fifth transistor is connected to the second electrode of the light-emitting control transistor and the anode of the light-emitting element.

4. The pixel driving circuit according to any one of claims 1 to 3, wherein, The gate of the fifth transistor is connected to a corresponding second light emission control signal line among a plurality of second light emission control signal lines.

5. The pixel driving circuit according to any one of claims 1 to 3, wherein, The gates of the fifth transistor and the light-emitting control transistor are connected to the corresponding light-emitting control signal lines among the plurality of light-emitting control signal lines.

6. The pixel driving circuit according to any one of claims 1 to 5, wherein, The third capacitor electrode of the second capacitor is connected to a corresponding fourth reset signal line among a plurality of fourth reset signal lines; The fourth capacitor electrode of the second capacitor is connected to the first electrode of the fifth transistor; as well as The second electrode of the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

7. The pixel driving circuit according to any one of claims 1 to 6 further includes a first capacitor, the first capacitor including a first capacitor electrode and a second capacitor electrode; in, The first capacitor electrode is connected to the gate of the driving transistor; The second capacitor electrode is connected to the voltage supply line; as well as The capacitance of the second capacitor is greater than that of the first capacitor.

8. The pixel driving circuit according to any one of claims 1 to 7, wherein, The capacitance of the second capacitor in the blue sub-pixel is greater than the capacitance of the second capacitor in the green sub-pixel. as well as The capacitance of the second capacitor in the green sub-pixel is greater than the capacitance of the second capacitor in the red sub-pixel.

9. The pixel driving circuit according to any one of claims 1 to 8, wherein, The corresponding fourth reset signal line among the multiple fourth reset signal lines is configured to provide a dynamically adjustable voltage.

10. The pixel driving circuit according to any one of claims 1 to 5, wherein, The third capacitor electrode of the second capacitor is connected to a corresponding second voltage supply line among a plurality of second voltage supply lines; The fourth capacitor electrode of the second capacitor is connected to the first electrode of the fifth transistor; as well as The second electrode of the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

11. The pixel driving circuit according to claim 10, wherein, A corresponding second voltage supply line among a plurality of second voltage supply lines is configured to provide a negative voltage signal to the third capacitor electrode and the cathode of the light-emitting element.

12. The pixel driving circuit according to claim 2, wherein, The gate of the fifth transistor is connected to a corresponding second light emission control signal line among a plurality of second light emission control signal lines; The third capacitor electrode of the second capacitor is connected to a corresponding fourth reset signal line among a plurality of fourth reset signal lines; The fourth capacitor electrode of the second capacitor is connected to the first electrode of the fifth transistor; as well as The second electrode of the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

13. The pixel driving circuit according to claim 2, wherein, The gate of the fifth transistor is connected to a corresponding second light emission control signal line among a plurality of second light emission control signal lines; The third capacitor electrode of the second capacitor is connected to a corresponding second voltage supply line among a plurality of second voltage supply lines; The fourth capacitor electrode of the second capacitor is connected to the first electrode of the fifth transistor; as well as The second electrode of the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

14. The pixel driving circuit according to claim 3, wherein, The gate of the fifth transistor is connected to a corresponding second light emission control signal line among a plurality of second light emission control signal lines; The third capacitor electrode of the second capacitor is connected to a corresponding fourth reset signal line among a plurality of fourth reset signal lines; The fourth capacitor electrode of the second capacitor is connected to the first electrode of the fifth transistor; as well as The second electrode of the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

15. The pixel driving circuit according to claim 3, wherein, The gates of the fifth transistor and the light-emitting control transistor are connected to the corresponding light-emitting control signal lines among the plurality of light-emitting control signal lines; The third capacitor electrode of the second capacitor is connected to a corresponding fourth reset signal line among a plurality of fourth reset signal lines; The fourth capacitor electrode of the second capacitor is connected to the first electrode of the fifth transistor; as well as The second electrode of the fifth transistor is connected to the node located between the driving transistor and the light-emitting element.

16. A display device comprising a pixel driving circuit according to any one of claims 1 to 15, and a light-emitting element connected to the pixel driving circuit.

17. A method for operating a pixel driving circuit; in, The pixel driving circuit includes: Drive transistors; Light-emitting elements; The node located between the driving transistor and the light-emitting element; The fifth transistor; and Second capacitor; Wherein, the second capacitor is connected to the fifth transistor; and The fifth transistor is connected to the node located between the driving transistor and the light-emitting element; The method includes: The driving transistor and the fifth transistor are turned on during the photonic phase of a frame of an image.

18. The method of claim 17, further comprising determining whether the light-emitting element is configured to display a relatively low grayscale image; in, When the light-emitting element is configured to display the relatively low grayscale image, the fifth transistor is turned on during the display light-emitting sub-phase of a frame of image.

19. The method of claim 18, further comprising turning off the fifth transistor when it is determined that the light-emitting element is configured to display a relatively high grayscale image.

20. The method according to claim 18, wherein, The relatively low grayscale image is an image with a grayscale value of less than 50.

21. The method according to any one of claims 17 to 20, further comprising providing a fourth reset signal to a third capacitor electrode of the second capacitor via a respective fourth reset signal line of a plurality of fourth reset signal lines.

22. The method according to any one of claims 17 to 20, further comprising providing a second voltage supply signal to a third capacitor electrode of the second capacitor via a respective second voltage supply line of a plurality of second voltage supply lines.

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