Systematic duty cycle corrector offset reduction

Abstract

A charge pump includes a first transistor, a first switch coupled between the first transistor and an output of the charge pump, a second transistor, and a second switch coupled between the output of the charge pump and the second transistor. The charge pump further includes a third transistor, wherein a gate of the third transistor is coupled to a gate of the first transistor, a fourth transistor, wherein a drain of the fourth transistor is coupled to a drain of the third transistor, and a biasing circuit configured to bias a gate of the fourth transistor and a gate of the second transistor. The charge pump further includes an amplifier having a first input coupled to the output of the charge pump, a second input coupled to the drain of the third transistor, and an output coupled to the gate of the third transistor.

Description

Cross-references to related applications

[0001] This application claims priority and benefit to non-provisional patent application serial number 18 / 626,770, filed April 4, 2024, with the United States Patent and Trademark Office, the entire contents of which are as fully set forth herein and incorporated herein for all applicable purposes. Technical Field

[0002] All aspects of this disclosure relate to charge pumps in general, and more specifically to charge pumps with systematic offset reduction. Background Technology

[0003] A charge pump can be configured to tune (i.e., adjust) a control voltage across a capacitor by controlling the current flowing into and out of a capacitor (e.g., a capacitor in a duty cycle corrector) based on one or more input signals. For example, in a duty cycle corrector, the control voltage controls the duty cycle of a clock signal. In this example, the charge pump can be coupled in a feedback loop that causes the charge pump to tune the control voltage in a direction that reduces the error between the clock signal's duty cycle and a target duty cycle. Summary of the Invention

[0004] The following is a simplified overview of one or more embodiments to provide a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that follow.

[0005] A first aspect relates to a system. The system includes a charge pump comprising: a first transistor; a first switch coupled between the drain of the first transistor and an output of the charge pump; a second transistor; and a second switch coupled between the output of the charge pump and the drain of the second transistor. The charge pump further includes: a third transistor, wherein the gate of the third transistor is coupled to the gate of the first transistor; a fourth transistor, wherein the drain of the fourth transistor is coupled to the drain of the third transistor; and a bias circuit configured to bias the gate of the fourth transistor and the gate of the second transistor. The charge pump further includes a first amplifier having a first input, a second input, and an output, wherein the first input of the first amplifier is coupled to the output of the charge pump, the second input of the first amplifier is coupled to the drain of the third transistor, and the output of the first amplifier is coupled to the gate of the third transistor. The system also includes a first capacitor coupled to the output of the charge pump.

[0006] A second aspect relates to a method for operating a charge pump. The charge pump includes a first transistor providing a first current, a second transistor providing a second current, a third transistor, a fourth transistor, and a biasing circuit biasing the gate of the second transistor and the gate of the fourth transistor, wherein the gate of the third transistor is coupled to the gate of the first transistor, and the drain of the third transistor is coupled to the drain of the fourth transistor. The method includes: sensing a first voltage at an output terminal of the charge pump; sensing a second voltage at the drain of the third transistor; and driving the gate of the third transistor in a direction that reduces the difference between the second voltage and the first voltage. Attached Figure Description

[0007] Figure 1 An example of a charge pump according to certain aspects of this disclosure is shown.

[0008] Figure 2 An exemplary embodiment of a current source in a charge pump according to certain aspects of this disclosure is shown.

[0009] Figure 3 This illustrates configuration for setting certain aspects according to this disclosure. Figure 2 An exemplary specific implementation of a current control circuit for a current source.

[0010] Figure 4 An example is shown in which a charge pump, according to certain aspects of this disclosure, includes a feedback loop for reducing drain voltage mismatch.

[0011] Figure 5 An example is shown in which a charge pump, according to certain aspects of this disclosure, includes circuitry for reducing charge sharing errors.

[0012] Figure 6 An exemplary specific implementation of a switch in a charge pump according to certain aspects of this disclosure is shown.

[0013] Figure 7 An example of a duty cycle corrector including a charge pump, according to certain aspects of this disclosure, is shown.

[0014] Figure 8 This is a timing diagram illustrating an exemplary waveform of a ramp voltage according to certain aspects of this disclosure.

[0015] Figure 9 This is a timing diagram showing an exemplary waveform of the control voltage according to certain aspects of this disclosure.

[0016] Figure 10 This is a flowchart illustrating a method for operating a charge pump according to certain aspects of this disclosure. Detailed Implementation

[0017] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0018] Figure 1 An example of a charge pump 110 according to certain aspects is shown. The charge pump 110 is configured to tune (i.e. adjust) a control voltage V on capacitor 170 by controlling the current flowing into and out of capacitor 170 based on one or more input signals. ctl For example, charge pump 110 can be used in a duty cycle corrector to regulate the control voltage V. ctl The control voltage controls the duty cycle of the clock signal, as discussed further below. In this example, the charge pump 110 may be coupled in a feedback loop that causes the charge pump 110 to tune the control voltage V in a direction that reduces the error between the clock signal's duty cycle and a target duty cycle (e.g., 50 percent duty cycle). ctl However, it should be understood that the charge pump 110 is not limited to a duty cycle corrector, and the charge pump 110 can be used to tune the control voltage in other types of circuits such as a phase-locked loop (PLL). For the example of a PLL, the charge pump 110 can tune the control voltage based on a phase error signal from a phase detector, which controls the output frequency of the PLL.

[0019] exist Figure 1 In the example, charge pump 110 includes a first current source 115, a second current source 120, a first switch 130, and a second switch 140. The first current source 115 and the first switch 130 are coupled in series between a power rail having a supply voltage Vdd and the output terminal 155 of charge pump 110. The first switch 130 has a control input 132 configured to control the on / off state of the first switch 130 based on an input signal (e.g., input voltage) at the control input 132. For example, the first switch 130 may be configured to be on when the input voltage is low (e.g., ground potential) and off when the input voltage is high (e.g., Vdd), and vice versa.

[0020] A second current source 120 and a second switch 140 are coupled in series between the output terminal 155 of the charge pump 110 and ground. The second switch 140 has a control input terminal 142 configured to control the on / off state of the second switch 140 based on an input signal (e.g., input voltage) at the control input terminal 142. For example, the second switch 140 may be configured to be on when the input voltage is high (e.g., Vdd) and off when the input voltage is low (e.g., ground potential), and vice versa.

[0021] Each of switches 130 and 140 may be implemented using a transistor, a transmit gate, or another type of switch. For example, in some implementations, the first switch 130 may be implemented using a p-type field-effect transistor (PFET), and the second switch 140 may be implemented using an n-type field-effect transistor (NFET), as discussed further below.

[0022] In this example, the output 155 of charge pump 110 is coupled to capacitor 170. Capacitor 170 integrates the current from charge pump 110 to generate the control voltage V discussed above. ctl .exist Figure 1 In the example shown, capacitor 170 is coupled between the output terminal 155 of charge pump 110 and the power rail. However, it should be understood that this disclosure is not limited to this example, and in other specific embodiments, capacitor 170 may be coupled between the output terminal 155 of charge pump 110 and ground.

[0023] In this example, the first current source 115 is configured to supply a current I_up to the capacitor 170 when the first switch 130 is turned on (i.e., closed). In this case, the current I_up flows into the capacitor 170, causing the control voltage V across the capacitor 170 to... ctl Increase (e.g., ascend).

[0024] The second current source 120 is configured to draw current I_dn from capacitor 170 when the second switch 140 is turned on (i.e., closed). In this case, current I_dn flows out of capacitor 170, which causes the control voltage V on capacitor 170 to... ctl Decrease (e.g., by sloping down). In some respects, the currents I_up and I_dn are approximately equal.

[0025] exist Figure 1 In the example shown, the on / off states of switches 130 and 140 are controlled by clock signals clk_pump, which are input to control inputs 132 and 142 of switches 130 and 140, respectively. As used herein, a “clock signal” is a periodic signal that alternates between high levels (e.g., Vdd) and low levels (e.g., ground potential).

[0026] In this example, the first switch 130 is configured to turn on when the clock signal clk_pump is low (e.g., ground) and turn off when the clock signal clk_pump is high (e.g., Vdd), and the second switch 140 is configured to turn on when the clock signal clk_pump is high and turn off when the clock signal is low. Therefore, in this example, the first switch 130 and the second switch 140 are alternately turned on, with the first switch 130 turning on when the clock signal clk_pump is low and the second switch 140 turning on when the clock signal clk_pump is high. Thus, when the clock signal clk_pump is low, the first current source 115 supplies current I_up to the capacitor 170 through the first switch 130, and when the clock signal clk_pump is high, the second current source 120 draws current I_dn from the capacitor 170 through the second switch 140. In this example, the first switch 130 can be implemented using a PFET, and the second switch 140 can be implemented using an NFET. However, it should be understood that the first switch 130 and the second switch 140 are not limited to this example.

[0027] In this example, charge pump 110 can tune (i.e. adjust) the control voltage V on capacitor 170 based on the duty cycle of clock signal clk_pump. ctl As used herein, the "duty cycle" of a clock signal is the proportion of the clock signal's period during which the clock signal is at a high level. This proportion can be expressed as a percentage or ratio. In this example, when the duty cycle of the clock signal clk_pump is greater than 50 percent, charge pump 110 reduces the control voltage V. ctl This is because during each clock cycle with a duty cycle greater than 50%, the second switch 140 is on for a longer duration than the first switch 130. Therefore, during each clock cycle, the amount of charge drawn by the second current source 120 from the capacitor 170 is greater than the amount of charge supplied to the capacitor 170 by the first current source 115, which reduces the control voltage V. ctl .

[0028] In this example, when the duty cycle of the clock signal clk_pump is less than 50%, charge pump 110 increases the control voltage V. ctl This is because during each clock cycle with a duty cycle less than 50%, the first switch 130 is on for a longer duration than the second switch 140. Therefore, during each clock cycle, the amount of charge supplied to the capacitor 170 by the first current source 115 is greater than the amount of charge drawn from the capacitor 170 by the second current source 120, which increases the control voltage V. ctl .

[0029] In this example, when the duty cycle of the clock signal clk_pump is approximately 50%, the control voltage V ctl A stable state can be achieved. This is because when the duty cycle is 50%, the first switch 130 and the second switch 140 are on for approximately the same duration (i.e., half a clock cycle) during each clock cycle. Therefore, during each clock cycle, the amount of charge supplied to the capacitor 170 by the first current source 115 is approximately equal to the amount of charge drawn from the capacitor 170 by the second current source 120 (assuming currents I_up and I_dn are equal).

[0030] It should be understood that the charge pump 110 is not limited to the clock signal clk_pump, and other types of signals can be input to the control inputs 132 and 142 of switches 130 and 140, respectively. For example, in a PLL, up pulses and down pulses can be input from a phase detector to the control inputs 132 and 142, respectively.

[0031] Figure 2 An exemplary specific implementation of a first current source 115 and a second current source 120 according to certain aspects is shown. In this example, the first current source 115 includes a first transistor 210 (e.g., a PFET), and the second current source 120 includes a second transistor 215 (e.g., an NFET). The source of the first transistor 210 is coupled to a power rail, and a first switch 130 is coupled between the drain of the first transistor 210 and the output terminal 155 of the charge pump 110. The source of the second transistor 215 is coupled to ground, and a second switch 140 is coupled between the output terminal 155 of the charge pump 110 and the drain of the second transistor 215.

[0032] In this example, charge pump 110 includes current control circuitry 220 coupled to the gate of first transistor 210 and the gate of second transistor 215. Current control circuitry 220 is configured to bias the gate of first transistor 210 with a gate voltage vg_p and the gate of second transistor 215 with a gate voltage vg_n. In this example, current control circuitry 220 sets the current I_up of first current source 115 by setting the gate voltage vg_p of first transistor 210. For an example where first transistor 210 is a PFET, current control circuitry 220 can set current I_up to a higher current by decreasing the gate voltage vg_p. Current control circuitry 220 also sets the current I_dn of second current source 120 by setting the gate voltage vg_n of second transistor 215. For an example where second transistor 215 is an NFET, current control circuitry 220 can set current I_dn to a higher current by increasing the gate voltage vg_n.

[0033] Figure 3An exemplary embodiment of the current control circuit 220 is shown, wherein the current control circuit 220 generates gate voltages vg_p and vg_n for the first transistor 210 and the second transistor 215, respectively, based on a reference current Iref. In this example, the current control circuit 220 includes a third transistor 310 (e.g., a PFET), a fourth transistor 320 (e.g., an NFET), and a gate bias circuit 330.

[0034] exist Figure 3 In this example, the source of the third transistor 310 is coupled to the power rail, and the gate of the third transistor 310 is coupled to the drain of the third transistor 310. The gate of the third transistor 310 is also coupled to the gate of the first transistor 210. In this example, the third transistor 310 and the first transistor 210 are coupled in a current mirror configuration, wherein the first transistor 210 mirrors the current flowing through the third transistor 310, as discussed further below.

[0035] The drain of the fourth transistor 320 is coupled to the drain of the third transistor 310, so that the current Ic flowing through the fourth transistor 320 flows through the third transistor 310. The source of the fourth transistor 320 is coupled to ground.

[0036] Gate biasing circuit 330 is coupled to the gate of fourth transistor 320 and the gate of second transistor 215. Gate biasing circuit 330 is configured to generate gate voltage vg_n based on reference current Iref and output gate voltage vg_n to the gate of fourth transistor 320 and the gate of second transistor 215. Figure 3 In the example, the gate bias circuit 330 includes a fifth transistor 340 and a reference current source 345 configured to generate a reference current Iref. The reference current source 345 is coupled to the drain of the fifth transistor 340. The gate of the fifth transistor 340 is coupled to the drain of the fifth transistor 340. The gate of the fifth transistor 340 is also coupled to the gate of the fourth transistor 320 and the gate of the second transistor 215.

[0037] In operation, a reference current Iref from reference current source 345 flows through the fifth transistor 340. The reference current Iref flowing through the fifth transistor 340 generates a gate voltage vg_n at the gate of the fifth transistor 340. The gate voltage vg_n biases the gate of the second transistor 215, causing the current I_dn of the second current source 120 to mirror the reference current Iref. The gate voltage vg_n also biases the gate of the fourth transistor 320, causing the current Ic of the fourth transistor 320 to mirror the reference current Iref.

[0038] The current Ic flowing through the fourth transistor 320 flows through the third transistor 310, as discussed above. The current Ic flowing through the third transistor 310 generates a gate voltage vg_p at its gate. This gate voltage vg_p biases the gate of the first transistor 210, causing the current I_up from the first current source 115 to mirror the current Ic, which in turn mirrors the reference current Iref. Therefore, the current I_up from the first current source 115 mirrors the reference current Iref.

[0039] Therefore, in this example, the current I_up of the first current source 115 and the current I_dn of the second current source 120 mirror the reference current Iref. For an example where transistors 210, 215, 310, and 320 have the same channel width, the current I_up of the first current source 115 and the current I_dn of the second current source 120 are approximately equal. However, in reality, the mismatch between transistors 210, 215, 310, and 320 results in a mismatch between the current I_up of the first current source 115 and the current I_dn of the second current source 120. When the charge pump 110 is used in a duty cycle corrector, this current mismatch can cause a duty cycle shift. When the charge pump 110 is used in a PLL, the current mismatch can also cause a phase shift.

[0040] Mismatches among transistors 210, 215, 310, and 320 can include random mismatches (e.g., caused by process variations) and systematic mismatches caused by the design of charge pump 110. For example, drain voltage mismatches of transistors 210, 215, 310, and 320 caused by the design of charge pump 110 may result in a systematic current mismatch between the first current source 115 and the second current source 120. When charge pump 110 is used in a duty cycle corrector, the systematic current mismatch causes a systematic duty cycle offset.

[0041] Figure 3 An example of the drain voltages of transistors 210, 215, 310, and 320 is shown. In this example, when the corresponding switches 130 and 140 are closed, the drain voltage vd1 of the first transistor 210 and the drain voltage vd2 of the second transistor 215 are each approximately equal to the control voltage V. ctl This assumes that charge-sharing errors are negligible. Exemplary techniques for reducing charge-sharing errors are discussed further below.

[0042] The drain voltage vd3 of the third transistor 310 is approximately equal to the gate voltage vg_p at the gate of the third transistor 310, which is equal to Vdd - Vsg3, where Vsg3 is the source-to-gate voltage of the third transistor 310. This is because the drain of the third transistor 310 is coupled to its gate. The drain voltage vd4 of the fourth transistor 320 is also approximately equal to Vdd - Vsg3, because the drain of the fourth transistor 320 is coupled to the drain of the third transistor 310.

[0043] Therefore, in this example, the drain voltage vd1 of the first transistor 210 and the drain voltage vd2 of the second transistor 215 are each approximately equal to the control voltage V. ctl The drain voltages vd3 of the third transistor 310 and vd4 of the fourth transistor 320 are each approximately equal to Vdd - Vsg3, which is different from the control voltage V. ctl In other words, the drain voltages vd1 and vd2 of the first transistor 210 and the second transistor 215 are mismatched with the drain voltages vd3 and vd4 of the third transistor 310 and the fourth transistor 320. Due to the channel length modulation of transistors 210, 215, 310, and 320 (which is a function of the drain voltage), this drain voltage mismatch results in a systematic current mismatch between the first current source 115 and the second current source 120. When the charge pump 110 is used in a duty cycle corrector, this systematic current mismatch causes a systematic duty cycle shift.

[0044] To address the aforementioned problems, aspects of this disclosure provide a feedback loop that forces the drain voltages vd3 and vd4 of the third transistor 310 and the fourth transistor 320 to be approximately equal to the drain voltages vd1 and vd2 of the first transistor 210 and the second transistor 215 in current sources 115 and 120. This reduces the systematic current mismatch between the first current source 115 and the second current source 120 caused by drain voltage mismatch. The above-mentioned and other features of this disclosure are further discussed below.

[0045] Figure 4 An example in which the charge pump 110 includes an amplifier 420 (e.g., an operational amplifier) ​​is shown. The amplifier 420 is coupled in a feedback loop that forces the drain voltages vd3 and vd4 of the third transistor 310 and the fourth transistor 320 to be approximately equal to the drain voltages vd1 and vd2 of the first transistor 210 and the second transistor 215 in the current sources 115 and 120, as discussed further below.

[0046] In this example, amplifier 420 has a first input terminal 422 (e.g., a negative input terminal), a second input terminal 424 (e.g., a positive input terminal), and an output terminal 426. The first input terminal 422 is coupled to the output terminal 155 of charge pump 110, the second input terminal 424 is coupled between the drain of third transistor 310 and the drain of fourth transistor 320, and the output terminal 426 is coupled to the gates of third transistor 310 and first transistor 210. Therefore, output terminal 426 drives the gate of third transistor 310. In this example, amplifier 420 and third transistor 310 are coupled in a negative feedback loop 428 with two gain stages, where these two gain stages include the gain of amplifier 410 and the gain of third transistor 310 (which acts as a common-source amplifier).

[0047] During operation, since the first input terminal 422 is coupled to the output terminal 155 of the charge pump 110, the amplifier 420 senses the control voltage V at the first input terminal 422. ctl And since the second input terminal 424 is coupled to the drain of the third transistor 310, the amplifier senses the drain voltage vd3 of the third transistor 310 at the second input terminal 424. Feedback loop 428 causes amplifier 420 to adjust the gate voltage vg_p at the gate of the third transistor 310, such that the drain voltage vd3 at the second input terminal 424 of amplifier 420 is approximately equal to the control voltage V at the first input terminal 422 of amplifier 420. ctl Therefore, feedback loop 428 forces the drain voltage vd3 of the third transistor 310 to be approximately equal to the control voltage V. ctl Since the drain of the fourth transistor 320 is coupled to the drain of the third transistor 310, the feedback loop 428 also forces the drain voltage Vd4 of the fourth transistor 320 to be approximately equal to the control voltage V. ctl .

[0048] Therefore, the feedback loop 428 forces the drain voltage vd3 of the third transistor 310 and the drain voltage vd4 of the fourth transistor 320 to be approximately equal to the control voltage V. ctl Since the drain voltage vd1 of the first transistor 210 and the drain voltage vd2 of the second transistor 215 are each approximately equal to the control voltage V... ctl Therefore, feedback loop 428 forces the drain voltages vd3 and vd4 of the third transistor 310 and the fourth transistor 320 to approximately match the drain voltages vd1 and vd2 of the first transistor 210 and the second transistor 215. This reduces the systematic current mismatch between the first current source 115 and the second current source 120 caused by drain voltage mismatch. In the example where the charge pump 110 is used in a duty cycle corrector, the reduction in systematic current mismatch reduces the systematic duty cycle offset, thereby improving the performance of the duty cycle corrector.

[0049] exist Figure 4 In the example shown, charge pump 110 includes a compensation capacitor 430 and a resistor 440, which are coupled in series between the drain and gate of third transistor 310. In this example, third transistor 310 acts as a common-source amplifier, with compensation capacitor 430 coupled between the input and output of the common-source amplifier. In this example, compensation capacitor 430 provides Miller compensation to feedback loop 428, which helps stabilize feedback loop 428 (e.g., improves the phase margin of feedback loop 428). Compensation capacitor 430 may also be referred to as a second capacitor.

[0050] In the above discussion, it is assumed that charge sharing error is negligible. Due to the drain capacitance of the first transistor 210 and the drain capacitance of the second transistor 215, charge sharing error may occur.

[0051] When the first switch 130 is turned on (i.e., closed), the drain voltage vd1 of the first transistor 210 is approximately equal to the control voltage V. ctl However, when the first switch 130 is turned off, the drain of the first transistor 210 is decoupled from the output terminal 155 of the charge pump 110, and the drain voltage vd1 of the first transistor 210 is pulled up to Vdd. When the first switch 130 is turned back on, charge is transferred between the drain capacitance of the first transistor 210 and the capacitor 170 to pull the drain voltage vd1 back to the control voltage Vdd. ctl Charge transfer leads to charge sharing error, where the control voltage V ctl Interference occurred.

[0052] When the second switch 140 is turned on (i.e., closed), the drain voltage vd2 of the second transistor 215 is approximately equal to the control voltage V. ctl However, when the second switch 140 is turned off, the drain of the second transistor 215 is decoupled from the output terminal 155 of the charge pump 110, and the drain voltage vd2 of the second transistor 215 is pulled down to ground potential. When the second switch 140 is turned back on, charge is transferred between the drain capacitance of the second transistor 215 and the capacitor 170 to pull the drain voltage vd2 back to the control voltage V. ctl Charge transfer leads to charge sharing error, where the control voltage V ctl Interference occurred.

[0053] Figure 5 An example is shown in which the charge pump 110 includes circuitry for reducing charge sharing errors. In this example, the charge pump 110 includes a third switch 530, a fourth switch 540, and a second amplifier 550.

[0054] A third switch 530 is coupled between the drain of the first transistor 210 and node 560, and a fourth switch 540 is coupled between node 560 and the drain of the second transistor 215. The second amplifier 550 has a first input terminal 552 (positive input), a second input terminal 554 (e.g., negative input), and an output terminal 556. The first input terminal 552 of the second amplifier 550 is coupled to the output terminal 155 of the charge pump 110, and the output terminal 556 of the second amplifier 550 is coupled to node 560 between switches 530 and 540. Furthermore, the second input terminal 554 of the second amplifier 550 is coupled to the output terminal 556, which provides unity gain, forcing the voltage at the output terminal 556 of the second amplifier 550 (and therefore the voltage at node 560) to be approximately equal to the voltage V at the first input terminal 552 of the second amplifier 550. ctl Therefore, the second amplifier 550 forces the voltage at node 560 between switches 530 and 540 to be approximately equal to the control voltage V. ctl .exist Figure 5 In the example shown, charge pump 110 includes capacitor 570 coupled between node 560 and power rail.

[0055] The third switch 530 has a control input 532, and the fourth switch 540 has a control input 542. In this example, the third switch 530 (e.g., a PFET) can be configured to turn on when the input voltage at the control input 532 is low (e.g., ground) and turn off when the input voltage at the control input 532 is high (e.g., Vdd). The fourth switch 540 (e.g., an NFET) can be configured to turn on when the input voltage at the control input 542 is high (e.g., Vdd) and turn off when the input voltage at the control input 542 is low (e.g., ground).

[0056] exist Figure 5 In the example shown, the control inputs 532 of the third switch 530 and 542 of the fourth switch 540 are driven by an inverted clock signal clk_pump_b, which is the inverse (i.e., complementary) of the clock signal clk_pump that drives the control inputs 132 of the first switch 130 and 142 of the second switch 140. Therefore, when the first switch 130 is off, the third switch 530 is on, and when the second switch 140 is off, the fourth switch 540 is on.

[0057] In this example, when the first switch 130 is turned off by the clock signal clk_pump, the third switch 530 is turned on by the inverted clock signal clk_pump_b. The third switch 530 couples the drain of the first transistor 210 to node 560, which, due to the second amplifier 550, has a voltage approximately equal to the control voltage V. ctl Therefore, while the first switch 130 is turned off, the drain voltage vd1 of the first transistor 210 remains at the control voltage V. ctl This reduces charge sharing error when the first switch 130 is re-energized.

[0058] When the second switch 140 is turned off by the clock signal clk_pump, the fourth switch 540 is turned on by the inverted clock signal clk_pump_b. The fourth switch 540 couples the drain of the second transistor 215 to node 560, which, due to the second amplifier 550, has a voltage approximately equal to the control voltage V. ctl Therefore, while the second switch 140 is turned off, the drain voltage vd2 of the second transistor 215 remains at the control voltage V. ctl This reduces charge sharing error when the second switch 140 is re-energized.

[0059] Figure 6 An example is shown in which a first switch 130 includes a first PFET 610, a second switch 140 includes a first NFET 620, a third switch 530 includes a second PFET 630, and a fourth switch 540 includes a second NFET 640. In this example, the source of the first PFET 610 is coupled to the drain of the first transistor 210, the gate of the first PFET 610 is coupled to the control input 132, and the drain of the first PFET 610 is coupled to the output 155. The source of the second PFET 630 is coupled to the drain of the first transistor 210, the gate of the second PFET 630 is coupled to the control input 532, and the drain of the second PFET 630 is coupled to node 560. The drain of the first NFET 620 is coupled to the output 155, the gate of the first NFET 620 is coupled to the control input 142, and the source of the first NFET 620 is coupled to the drain of the second transistor 215. The drain of the second NFET 640 is coupled to node 560, the gate of the second NFET 640 is coupled to control input 542, and the source of the second NFET 640 is coupled to the drain of the second transistor 215. It should be understood that switches 130, 140, 530, and 540 are not limited to... Figure 6 The exemplary implementation is shown.

[0060] As discussed above, the charge pump 110 can be used in duty cycle correctors. In this respect, Figure 7An example of a duty cycle corrector 710 including a charge pump 110 is shown according to certain aspects. The duty cycle corrector 710 has an input terminal 712 and an output terminal 714. The duty cycle corrector 710 is configured to receive an input clock signal clkin at input terminal 712, adjust the duty cycle of the input clock signal clkin to obtain an output clock signal clkout, and output the output clock signal clkout at output terminal 714. For example, the input clock signal clkin may have a large duty cycle distortion, causing the input clock signal clkin to deviate from a target duty cycle (e.g., 50 percent). Large duty cycle distortion may be caused by long wiring distances, low supply voltages, low-performance clock generators (e.g., PLLs), and / or any combination thereof. In this example, the duty cycle corrector 710 adjusts the duty cycle of the input clock signal clkin to a duty cycle closer to the target duty cycle (e.g., 50 percent).

[0061] In this example, the duty cycle corrector 710 includes a feedback circuit 718 configured to operate based on a control voltage V. ctl This is used to adjust the duty cycle of the clock signal clk_pump. The feedback circuit 718 includes a flip-flop 720, a clock path 725, a first transistor 730 (e.g., a PFET), a second transistor 740 (e.g., an NFET), and a second capacitor 735. In the discussion below, capacitor 170 is referred to as the first capacitor 170.

[0062] Flip-flop 720 has a clock input coupled to input 712 to receive the clock signal clkin. Flip-flop 720 also has an input D coupled to the power rail to receive the power supply voltage Vdd (i.e., logic one). Flip-flop 720 also has an output Q and a reset input rst. The reset input rst is configured to reset the output Q to a low level when the reset input rst receives a rising edge (i.e., a transition from low to high).

[0063] Clock path 725 is coupled between the output Q of flip-flop 720 and the gate of second transistor 740. In this example, clock path 725 includes a first inverter 722, a second inverter 724, and a third inverter 726 coupled in series between the output Q of flip-flop 720 and the gate of second transistor 740. In this example, the clock signal clk_pump input to charge pump 110 is taken from the output of second inverter 724, and the inverted clock signal clk_pump_b input to charge pump 110 is taken from the output of first inverter 722. Clock signal clk_pump and inverted clock signal clk_pump_b are complementary because second inverter 724 is located between clock signals clk_pump and clk_pump_b. Output 714 of duty cycle corrector 710 is coupled to the output of second inverter 724. Therefore, in this example, after propagation through inverters 722 and 724, the output clock signal clkout is provided at output 714 by the output Q of flip-flop 720. However, it should be understood that this disclosure is not limited to this example. In this example, the clock signal clk_pump and the output clock signal clkout are the same because they are both derived from the output of the second inverter 724. However, it should be understood that this disclosure is not limited to this example.

[0064] The source of the first transistor 730 is coupled to the power rail, and the gate of the first transistor 730 is coupled between the first capacitor 170 and the output terminal 155 of the charge pump 110 to receive the control voltage V. ctl As discussed further below, the first transistor 730 is based on the control voltage V. ctl This provides a charging current Irmp to the second capacitor 735. In the example where the first transistor 730 is implemented using a PFET, when the control voltage V... ctl When the voltage decreases, the charging current Irmp increases, and when the control voltage V... ctl As the current increases, the charging current Irmp decreases.

[0065] The second capacitor 735 is coupled between the drain of the first transistor 730 and ground. The second transistor 740 is coupled in parallel with the second capacitor 735, with the drain of the second transistor 740 coupled between the drain of the first transistor 730 and the second capacitor 735, and the source of the second capacitor 735 coupled to ground. As mentioned above, the clock path 725 is coupled between the output Q of the flip-flop 720 and the gate of the second transistor 740. In this example, the second transistor 740 is configured to turn on when its gate is high and turn off when its gate is low. When the second transistor 740 is on, it provides a short circuit to discharge the second capacitor 735, thus grounding the voltage Vrmp on the second capacitor 735. When the second transistor 740 is off, the charging current Irmp charges the second capacitor 735, causing the voltage Vrmp on the second capacitor 735 to ramp up.

[0066] The reset input terminal rst of flip-flop 720 is coupled to capacitor 735 through reset path 746. Figure 7 In the example shown, reset path 746 includes inverters 742 and 744 coupled in series. In this example, the reset input rst of flip-flop 720 is configured to reset the output Q of flip-flop 720 to a low level when the voltage Vrmp across the second capacitor 735 reaches the threshold voltage of inverter 742. As used herein, the “threshold voltage” of an inverter is the voltage at the input of the inverter that transitions the output of the inverter from a high level to a low level. For example, the threshold voltage of inverter 742 may be approximately equal to Vdd / 2. In this example, when the voltage Vrmp across the second capacitor 735 reaches the threshold voltage (e.g., Vdd / 2) of inverter 742, inverters 742 and 744 cause the reset input rst of flip-flop 720 to reset the output Q of flip-flop 720 to a low level. It should be understood that reset path 746 is not limited to... Figure 7 As shown in the example, and in some specific implementations, the reset path 746 may include a different number of inverters or may not include inverters.

[0067] Exemplary operation of the duty cycle corrector 710 will now be described in some respects. When flip-flop 720 receives the rising edge of the clock signal clkin, flip-flop 720 is configured to latch logic one at input D and output the latched logic one at output Q. Assuming output Q is initially reset to low, this causes a rising edge to be generated at output Q of flip-flop 720. After propagation through inverters 722 and 744, the rising edge at output Q of flip-flop 720 is output at output 714 of duty cycle corrector 710. The rising edge at output 714 provides the rising edge of the output clock signal clkout.

[0068] An inverted clock signal clk_pump_b is input to charge pump 110 from the output of the first inverter 722, and a clock signal clk_pump is input to charge pump 110 from the output of the second inverter 724. Charge pump 110 tunes (i.e., adjusts) the control voltage V based on the duty cycle of the clock signal clk_pump. ctl As discussed above.

[0069] The rising edge at the output Q of flip-flop 720 causes the voltage at the gate of second transistor 740 to go low. This is because the gate of second transistor 740 is coupled to output Q through an odd number of inverters (i.e., inverters 722, 724, and 725). When the voltage at the gate of second transistor 740 goes low, second transistor 740 is turned off, which allows the charging current Irmp from first transistor 730 to charge second capacitor 735. As discussed above, the charging current Irmp is the control voltage V input to the gate of first transistor 730. ctl The charging current Irmp causes the voltage Vrmp at the second capacitor 735 to ramp up. When the voltage Vrmp reaches the threshold voltage of inverter 742 (e.g., Vdd / 2), the output of inverter 742 goes low, which causes the output of inverter 744 to go high. The high output of inverter 744 is input to the reset input rst of flip-flop 720, resetting the output Q of flip-flop 720 to logic zero and outputting a falling edge. The falling edge propagates through inverters 722 and 724 to the output 714 of duty cycle corrector 710 to provide the falling edge of the output clock signal clkout.

[0070] In this example, the delay of the falling edge of the output clock signal clkout relative to its rising edge depends on how quickly flip-flop 720 is reset to zero after the rising edge. The time taken to reset flip-flop 720 depends on the time it takes for the voltage Vrmp on the second capacitor 735 to ramp up to the threshold voltage (e.g., Vdd / 2) of inverter 742, which in turn depends on the charging current Irmp. The charging current Irmp then depends on the control voltage V ctl Therefore, the delay of the falling edge of the output clock signal clkout relative to the rising edge of the output clock signal clkout depends on the control voltage V. ctl The control voltage is tuned by charge pump 110 based on the duty cycle of clock signal clk_pump. In this example, the control voltage V ctl The duty cycle of the output clock signal clkout is controlled by adjusting the delay between the falling edge and the rising edge of clkout. Increasing the delay increases the duty cycle, while decreasing the delay decreases it. The control voltage V...ctl The duty cycle of the clock signal clk_pump is controlled in a similar manner.

[0071] Figure 8 This is a timing diagram showing an exemplary waveform of the voltage Vrmp across the second capacitor 735 over multiple clock cycles. (See diagram for example.) Figure 8 As shown, during each clock cycle, the voltage Vrmp ramps up to the threshold voltage of inverter 742 (e.g., Vdd / 2). Each time the voltage Vrmp reaches the threshold voltage, flip-flop 720 is reset to zero and the second transistor 740 is turned on, which discharges the second capacitor 735 and causes the voltage Vrmp to drop to ground potential.

[0072] Figure 9 This shows the control voltage V. ctl Timing diagram of exemplary waveforms over multiple clock cycles. In this example, the control voltage V... ctl In a stable state, the control voltage V ctl Oscillates around the average value. For example... Figure 9 As shown, the control voltage V ctl A sawtooth waveform is generated by slightly sloping the peak when the clock signal clkout is low and slightly sloping the peak when clkout is high. The sawtooth waveform may cause a small duty cycle error. The impact of the sawtooth waveform on the duty cycle error can be reduced by decreasing the amplitude of the sawtooth waveform. This amplitude can be reduced by increasing the capacitance of the first capacitor 170, which in turn reduces the control voltage V. ctl The waveform is smooth. However, increasing the capacitance will increase the area of ​​the first capacitor 170.

[0073] In some respects, amplifier 420 (such as Figures 4 to 6 The bandwidth (as shown) may be high enough to track the control voltage V. ctl The sawtooth waveform. In these respects, the drain voltages Vd3 and Vd4 of transistors 310 and 320 track the control voltage V. ctl The sawtooth waveform. This tracking reduces the impact of the sawtooth waveform on the duty cycle error without increasing the size of the first capacitor 170, which improves area efficiency compared to increasing the size of the first capacitor 170.

[0074] Figure 10An exemplary method for operating a charge pump is shown according to certain aspects. The charge pump (e.g., charge pump 110) includes a first transistor (e.g., first transistor 210) providing a first current (e.g., I_up), a second transistor (e.g., second transistor 215) providing a second current (e.g., I_dn), a third transistor (e.g., third transistor 310), a fourth transistor (e.g., fourth transistor 320), and a biasing circuit (e.g., biasing circuit 330) biasing the gates of the second transistor and the fourth transistor, wherein the gate of the third transistor is coupled to the gate of the first transistor, and the drain of the third transistor is coupled to the drain of the fourth transistor.

[0075] At box 1010, a first voltage is sensed at the output of the charge pump. For example, the first voltage may correspond to a control voltage V. ctl The first voltage can be sensed at the first input terminal 422 of the first amplifier 420.

[0076] At block 1020, a second voltage is sensed at the drain of the third transistor. For example, the second voltage may correspond to the drain voltage vd3. The second voltage may be sensed at the second input terminal 424 of the first amplifier 420.

[0077] At block 1030, the gate of the third transistor is driven in a direction that reduces the difference between the second voltage and the first voltage. For example, the gate of the third transistor may be driven by the output terminal 426 of the first amplifier 420.

[0078] In some aspects, the charge pump also includes a first switch (e.g., first switch 130) coupled between the first transistor and the output of the charge pump, and a second switch (e.g., second switch 140) coupled between the output of the charge pump and the second transistor. In these aspects, method 1000 may also include receiving a clock signal (e.g., clk_pump) and driving the first and second switches based on the clock signal.

[0079] In some respects, driving the first switch and the second switch based on a clock signal includes turning on the first switch and turning off the second switch when the clock signal is low, and turning off the first switch and turning on the second switch when the clock signal is high.

[0080] In some respects, method 1000 also includes adjusting the duty cycle of the clock signal based on a first voltage at the output of the charge pump. For example, the duty cycle of the clock signal may be adjusted by feedback circuit 718.

[0081] Specific implementation examples are described in the following numbered clauses:

[0082] 1. A system comprising:

[0083] A charge pump, the charge pump comprising:

[0084] First transistor;

[0085] A first switch is coupled between the drain of the first transistor and the output of the charge pump.

[0086] Second transistor;

[0087] A second switch is coupled between the output terminal of the charge pump and the drain of the second transistor;

[0088] A third transistor, wherein the gate of the third transistor is coupled to the gate of the first transistor;

[0089] A fourth transistor, wherein the drain of the fourth transistor is coupled to the drain of the third transistor;

[0090] A biasing circuit configured to bias the gate of the fourth transistor and the gate of the second transistor; and

[0091] A first amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first amplifier is coupled to the output terminal of the charge pump, the second input terminal of the first amplifier is coupled to the drain of the third transistor, and the output terminal of the first amplifier is coupled to the gate of the third transistor and the gate of the first transistor; and

[0092] A first capacitor is coupled to the output terminal of the charge pump.

[0093] 2. The system according to Clause 1, wherein the charge pump further comprises a second capacitor coupled between the drain of the third transistor and the gate of the third transistor.

[0094] 3. The system according to Clause 1 or 2, wherein the first capacitor is coupled between the output terminal of the charge pump and the power rail.

[0095] 4. The system according to any one of clauses 1 to 3, wherein the source of the first transistor and the source of the third transistor are coupled to a power supply voltage, and the source of the second transistor and the source of the fourth transistor are coupled to ground.

[0096] 5. The system according to Clause 4, wherein the first transistor includes a first p-type field-effect transistor (PFET), the second transistor includes a first n-type field-effect transistor (NFET), the third transistor includes a second PFET, and the fourth transistor includes a second NFET.

[0097] 6. The system according to any one of clauses 1 to 5, wherein the bias circuit comprises:

[0098] Reference current source; and

[0099] A fifth transistor, wherein the drain of the fifth transistor is coupled to the reference current source, and the gate of the fifth transistor is coupled to the drain of the fifth transistor, the gate of the fourth transistor, and the gate of the second transistor.

[0100] 7. The system according to Clause 6, wherein the source of the first transistor and the source of the third transistor are coupled to a power supply voltage, and the source of the second transistor, the source of the fourth transistor, and the source of the fifth transistor are coupled to ground.

[0101] 8. The system according to any one of clauses 1 to 7, wherein the first switch and the second switch are driven by a clock signal.

[0102] 9. The system according to Clause 8, wherein:

[0103] The first switch is configured to turn on when the clock signal is low and turn off when the clock signal is high; and

[0104] The second switch is configured to turn on when the clock signal is high and turn off when the clock signal is low.

[0105] 10. The system according to Clause 8 or 9, wherein the first switch comprises a p-type field-effect transistor (PFET) and the second switch comprises an n-type field-effect transistor (NFET).

[0106] 11. The system according to any one of clauses 8 to 10, the system further comprising a feedback circuit configured to adjust the duty cycle of the clock signal based on a control voltage on the first capacitor.

[0107] 12. The system according to any one of clauses 1 to 11, wherein the charge pump further comprises:

[0108] A third switch is coupled between the drain and the node of the first transistor;

[0109] A fourth switch, coupled between the node and the drain of the second transistor; and

[0110] A second amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second amplifier is coupled to the output terminal of the charge pump, the second input terminal of the second amplifier is coupled to the output terminal of the second amplifier, and the output terminal of the second amplifier is coupled to the node.

[0111] 13. The system according to Clause 12, wherein:

[0112] The first switch and the second switch are driven by a clock signal: and

[0113] The third switch and the fourth switch are driven by the inverted phase of the clock signal.

[0114] 14. The system according to Clause 13, wherein:

[0115] The first switch is configured to turn on when the clock signal is low and turn off when the clock signal is high;

[0116] The second switch is configured to turn on when the clock signal is high and turn off when the clock signal is low;

[0117] The third switch is configured to turn on when the inverted phase of the clock signal is low and turn off when the inverted phase of the clock signal is high; and

[0118] The fourth switch is configured to turn on when the inverted phase of the clock signal is high and turn off when the inverted phase of the clock signal is low.

[0119] 15. The system according to Clause 13 or 14, wherein the first switch includes a first p-type field-effect transistor (PFET), the second switch includes a first n-type field-effect transistor (NFET), the third switch includes a second PFET, and the fourth switch includes a second NFET.

[0120] 16. The system according to any one of clauses 13 to 15, the system further comprising a feedback circuit configured to adjust the duty cycle of the clock signal based on a control voltage on the first capacitor.

[0121] 17. A method for operating a charge pump, the charge pump comprising a first transistor providing a first current, a second transistor providing a second current, a third transistor, a fourth transistor, and a bias circuit biasing the gate of the second transistor and the gate of the fourth transistor, wherein the gate of the third transistor is coupled to the gate of the first transistor, and the drain of the third transistor is coupled to the drain of the fourth transistor, the method comprising:

[0122] Sensing a first voltage at the output terminal of the charge pump;

[0123] Sensing a second voltage at the drain of the third transistor; and

[0124] The gate of the third transistor is driven in a direction that reduces the difference between the second voltage and the first voltage.

[0125] 18. The method of claim 17, wherein the charge pump further comprises a first switch coupled between the first transistor and the output terminal of the charge pump, and a second switch coupled between the output terminal of the charge pump and the second transistor, and wherein the method further comprises:

[0126] Receive clock signal; and

[0127] The first switch and the second switch are driven based on the clock signal.

[0128] 19. The method according to Clause 18, wherein driving the first switch and the second switch based on the clock signal comprises:

[0129] When the clock signal is low, the first switch is turned on and the second switch is turned off; and

[0130] When the clock signal is high, the first switch is turned off and the second switch is turned on.

[0131] 20. The method according to Clause 18 or 19, the method further comprising adjusting the duty cycle of the clock signal based on the first voltage at the output of the charge pump.

[0132] Within this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect electrical coupling between two structures. It should also be understood that the term "ground" can refer to DC ground or AC ground, and therefore the term "ground" covers both possibilities. As used herein, "approximately" means within 90 percent to 110 percent of the stated values.

[0133] The use of designations such as "first" and "second" to refer to elements in this document generally does not limit the number or order of those elements. Rather, these designations are used here as a convenient way to distinguish two or more elements or instances of elements. Therefore, a reference to the first element and the second element does not imply that only two elements can be used, or that the first element must precede the second element.

[0134] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Thus, this disclosure is not intended to be limited to the examples described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: A charge pump, the charge pump comprising: First transistor; A first switch is coupled between the drain of the first transistor and the output of the charge pump. Second transistor; A second switch is coupled between the output terminal of the charge pump and the drain of the second transistor; A third transistor, wherein the gate of the third transistor is coupled to the gate of the first transistor; A fourth transistor, wherein the drain of the fourth transistor is coupled to the drain of the third transistor; A biasing circuit configured to bias the gate of the fourth transistor and the gate of the second transistor; and A first amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first amplifier is coupled to the output terminal of the charge pump, the second input terminal of the first amplifier is coupled to the drain of the third transistor, and the output terminal of the first amplifier is coupled to the gate of the third transistor; and A first capacitor is coupled to the output terminal of the charge pump.

2. The system of claim 1, wherein the charge pump further comprises a second capacitor coupled between the drain of the third transistor and the gate of the third transistor.

3. The system of claim 1, wherein the first capacitor is coupled between the output terminal of the charge pump and the power rail.

4. The system of claim 1, wherein the source of the first transistor and the source of the third transistor are coupled to a power supply voltage, and the source of the second transistor and the source of the fourth transistor are coupled to ground.

5. The system of claim 4, wherein the first transistor comprises a first p-type field-effect transistor (PFET), the second transistor comprises a first n-type field-effect transistor (NFET), the third transistor comprises a second PFET, and the fourth transistor comprises a second NFET.

6. The system of claim 1, wherein the bias circuit comprises: Reference current source; and A fifth transistor, wherein the drain of the fifth transistor is coupled to the reference current source, and the gate of the fifth transistor is coupled to the drain of the fifth transistor, the gate of the fourth transistor, and the gate of the second transistor.

7. The system of claim 6, wherein the source of the first transistor and the source of the third transistor are coupled to a power supply voltage, and the source of the second transistor, the source of the fourth transistor, and the source of the fifth transistor are coupled to ground.

8. The system according to claim 1, wherein the first switch and the second switch are driven by a clock signal.

9. The system according to claim 8, wherein: The first switch is configured to turn on when the clock signal is low and turn off when the clock signal is high; and The second switch is configured to turn on when the clock signal is high and turn off when the clock signal is low.

10. The system of claim 8, wherein the first switch comprises a p-type field effect transistor (PFET) and the second switch comprises an n-type field effect transistor (NFET).

11. The system of claim 8, further comprising a feedback circuit configured to adjust a duty cycle of the clock signal based on a control voltage on the first capacitor.

12. The system of claim 1, wherein the charge pump further comprises: a third switch coupled between the drain of the first transistor and a node; a fourth switch coupled between the node and the drain of the second transistor; and a second amplifier having a first input, a second input, and an output, wherein the first input of the second amplifier is coupled to the output of the charge pump, the second input of the second amplifier is coupled to the output of the second amplifier, and the output of the second amplifier is coupled to the node.

13. The system of claim 12, wherein: the first switch and the second switch are driven by a clock signal; and the third switch and the fourth switch are driven by an inverse of the clock signal.

14. The system of claim 13, wherein: the first switch is configured to turn on when the clock signal is low and turn off when the clock signal is high; the second switch is configured to turn on when the clock signal is high and turn off when the clock signal is low; the third switch is configured to turn on when the inverse of the clock signal is low and turn off when the inverse of the clock signal is high; and the fourth switch is configured to turn on when the inverse of the clock signal is high and turn off when the inverse of the clock signal is low.

15. The system of claim 13, wherein the first switch comprises a first p-type field effect transistor (PFET), the second switch comprises a first n-type field effect transistor (NFET), the third switch comprises a second PFET, and the fourth switch comprises a second NFET.

16. The system of claim 13, further comprising a feedback circuit configured to adjust a duty cycle of the clock signal based on a control voltage on the first capacitor.

17. A method for operating a charge pump, the charge pump comprising a first transistor providing a first current, a second transistor providing a second current, a third transistor, a fourth transistor, and a biasing circuit biasing a gate of the second transistor and a gate of the fourth transistor, wherein a gate of the third transistor is coupled to a gate of the first transistor and a drain of the third transistor is coupled to a drain of the fourth transistor, the method comprising: sensing a first voltage at an output of the charge pump; ​ sensing a second voltage at the drain of the third transistor; and driving the gate of the third transistor in a direction that reduces a difference between the second voltage and the first voltage.

18. The method of claim 17, wherein the charge pump further comprises a first switch coupled between the first transistor and the output of the charge pump, and a second switch coupled between the output of the charge pump and the second transistor, and wherein the method further comprises: receiving a clock signal; and driving the first switch and the second switch based on the clock signal.

19. The method of claim 18, wherein driving the first switch and the second switch based on the clock signal comprises: turning on the first switch and turning off the second switch when the clock signal is low; and turning off the first switch and turning on the second switch when the clock signal is high.

20. The method of claim 18, further comprising adjusting a duty cycle of the clock signal based on the first voltage at the output of the charge pump.

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