Adiabatic flip-flop and memory design

Abstract

Provided herein are circuits for generating energy recovery Benett clocks using resonators.

Description

Cross-referencing of related applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 626,904, filed January 30, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This invention relates to resonators and methods for reducing heat dissipation (referred to as adiabatic logic). Specifically, this invention relates to supplying power to digital circuits using Bennett timing. Background Technology

[0003] In Bennett timing, a series of ramp clocks supply power to the circuit. The system starts up in a low, empty state in all phases. Each phase lasts for a period t. o The phases are sequentially raised to the active state, transferring energy to the reversible logic. When all phases are raised, the system is in its active state. Next, each phase raises to the active state within period t. o The internal phase decreases, and the reversible logic recovers energy. When all phases have decreased, the system returns to its empty state. Information regarding the adiabatic logic can be found in U.S. Patent No. 11,488,660 and International Publication No. WO 2023 / 250007, the contents of which are incorporated herein by reference.

[0004] To achieve significant overall system power savings in computing systems, the power dissipation of the Bennett clock circuit must also be considered. Reversible logic offers the possibility of reusing energy used in computation, but the Bennett power clock circuit must supply energy to the logic circuit during the rising edge of the clock and then reclaim it at the falling edge. In this way, energy is stored in the clock generator until it is supplied to the logic circuit again in the next clock cycle, thus allowing energy to be reused multiple times, rather than being dissipated as heat in only one clock cycle as is the case with conventional complementary MOSFET logic (CMOS).

[0005] One way to implement a system that performs a sequence of absorbing, storing, and then releasing energy is to use a resonant circuit or resonator. In this document, the terms "resonant circuit" and "resonator" may be used interchangeably. A resonator can be considered as a system that moves energy between two storage elements in a periodic manner. The most common electrical resonator is the LC resonator, in which energy is alternately stored as a magnetic field in an inductor and as an electric field in a capacitor. In an ideal parallel resonator, at the resonant frequency, the impedance of the combination of inductor and capacitor tends to infinity, and in a steady state, no energy is drawn from the AC power supply. In practice, there are resistors or resistances associated with the circuit that cause some of the energy moving through the elements of the LC resonator to dissipate as heat. A simple set of parasitic resistances includes: the output resistance R1 of the power supply, which dissipates some of the energy leaving the supply; and the parasitic resistance R2 of the inductor, which dissipates some of the energy stored in the inductor.

[0006] At resonance, as energy moves between the inductor and capacitor, R2 dissipates some energy as heat. To quantify the effect of this dissipation, a figure of merit is introduced: the quality factor Q = E. L / E d It is the total energy E stored in the inductor. L With the energy E dissipated in each cycle d The ratio. In an ideal resonator with R2 = 0 Ω, the quality factor Q is infinite. For a practical resonator, it will still draw some energy from the power supply at steady-state resonance because the impedance of the resonator will not tend to infinity due to losses in R2.

[0007] In an adiabatic reversible computing system using a resonant clock, the logic circuitry becomes part of the resonator. The logic circuitry forms a capacitive load, containing the gate capacitances of the transistors that constitute the logic gates. The combined capacitance of all these gates can be represented by the capacitor C of the resonator, and the parasitic resistances of the interconnects on the logic chip can be pooled together and represented by resistor R2. In this model of the logic circuitry, the Q of the resonator includes not only the losses in the inductor but also the losses in the logic chip. At resonance, the resonator exhibits high impedance as energy moves between the logic circuitry represented by capacitor C and inductor L. The only energy drawn from the power supply is the energy necessary to constitute the energy lost in the resonator at each cycle due to the resistive losses that impart an infinite Q. In this way, the overall system energy dissipation is reduced compared to conventional CMOS systems. Summary of the Invention

[0008] This paper presents a circuit that uses four orthogonal resonators Res 1 to Res 4, each delayed by a phase of π / 2 = 90°, to produce a set of nested positive and negative ramps.

[0009] This paper also provides a circuit that uses a resonator array to construct arbitrary waveforms using the Fourier series principle.

[0010] Further non-limiting implementation methods are described in the following numbered clauses:

[0011] 1. A method comprising:

[0012] (a) In a circuit having at least four quadrature resonators with a phase delay of π / 2 = 90°, wherein at least four quadrature resonators generate a set of positive and negative ramps that initially hold the output clock line at zero;

[0013] (b) When the output clock line intersects zero, connect the output clock line to at least one of at least four quadrature resonators;

[0014] (c) After at least one resonator has risen to its maximum voltage, disconnect the output clock line from at least one resonator;

[0015] (d) Maintaining a constant output clock line over several resonator cycles; and

[0016] (e) When at least one resonator degrades, reconnect the output clock line to at least one resonator.

[0017] 2. A method comprising: forming a Bennett phase based on Fourier components, wherein approximately ten harmonics are used to construct an arbitrary waveform, and wherein the ten harmonics comprise:

[0018] At least one resonator for each of the ten harmonics; and

[0019] The control circuit that generates the main waveform to drive the resonator. Attached Figure Description

[0020] Figure 1 This demonstrates the output of a resonator with a single positive phase and the required Bennett clock waveform.

[0021] Figure 2 A block diagram showing a resonator-based clock system.

[0022] Figure 3 A block diagram showing the delayed locking ring.

[0023] Figure 4 An implementation of a distribution circuit system for a Bennett clock phase is shown, the distribution circuit system comprising a transmission gate and two transistors.

[0024] Figure 5 Show the timing diagram of the signals required for the operation control logic.

[0025] Figure 6 A block diagram showing the control logic used for the distribution circuit.

[0026] Figure 7 A diagram showing the phase control circuit system used to generate the signals required by the distribution circuit.

[0027] Figure 8a The 10th harmonic waveform suitable for use as the positive Benznet phase 1 is shown.

[0028] Figure 8b An example of a 12-phase Bennett clock formed by 10 harmonics is shown.

[0029] Figure 9a The Bennett clock generator with 10 harmonics is shown, which includes 10 resonators and 10 master oscillators.

[0030] Figure 9b A simplified circuit with 10 resonators but only one master waveform generator is shown.

[0031] Figure 10a A top view of a multispectral piezoelectric profile mode resonator.

[0032] Figure 10b The cross-section of a multispectral piezoelectric profile mode resonator is shown.

[0033] Figure 10c A schematic diagram showing the energy reflector placed at the end of each anchor point.

[0034] Figure 11a Demonstrating the phase control circuit.

[0035] Figure 11b Display the output waveform. Detailed Implementation

[0036] This disclosure describes in detail two embodiments of a circuit that uses resonators to generate an energy-recovery Bennett clock. In the first embodiment, four orthogonal resonators Res 1 to Res 4, each delayed by a phase of π / 2 = 90°, are used to generate a set of nested positive and negative ramps. The basic principle is to use portions of a sine wave as the rising and falling ramps of the Bennett clock. Figure 1The sinusoidal output of the resonator is shown (dashed line). To form the Bennett clock phase shown, the output clock line is initially held at zero, and then connected to the resonator when the resonator's output intersects zero on its rising edge. As the resonator rises to its maximum voltage, the Bennett clock line remains connected to the resonator, and then disconnected. The Bennett clock line remains constant for a certain number of resonator cycles, then reconnects to the resonator as it falls, and then disconnects at zero and remains at zero when the resonator output intersects zero. Using this sequence, the resonator provides energy as it rises and receives energy as it falls. Figure 2 A schematic block diagram of a system with eight bipolar Bennett phases Ф1 to Ф8 is shown. (Using...) Figure 1 The method described above can use four resonators to generate eight positive phases and eight negative phases.

[0037] The master digital clock sets the timing sequence of the timing system. The period of the master digital clock (TMC) is equal to the ramp phase time t0 and / or t1. Equation 1 gives the complete period of the Bennett clock:

[0038] TBennett=(2NPhase+NActive+NNull) TMC (1)

[0039] Where TBennett is the total period, NPhase is the number of Bennett phases, NActive is the number of clock cycles in which the system remains active, and NNull is the number of clock cycles in which the system remains idle. The master digital clock period (TMC) sets the time step of the timing system and is the rise and fall time of each Bennett clock phase, and is ¼ of the resonator period Tosc.

[0040] Tosc=4 TMC (2)

[0041] A delay-locked loop (DLL) is used to generate four master clock phases MФ1 to MФ4, each phase offset by 90°. The outputs of the DLL are digital signals, but by simply filtering the fundamental frequency, they can be used to drive resonators Res1 to Res4. The control logic block contains a counter and decoder circuitry system that includes a simple state machine that generates signals to step through the sequence using distribution circuitry, thereby connecting each Bennett clock phase to the appropriate resonator at the appropriate time. Details of each block are given below.

[0042] Delay-locked loops (DLLs) are well-known circuits, most commonly used for synchronizing clock signals and generating multiphase clocks. Figure 3The diagram illustrates a schematic block diagram of a DLL, where a four-stage voltage-controlled delay line is used to introduce a delay into the signal from the input, which in this disclosure is the Master Digital Clock (MDC). A phase detector (PD) then measures the phase difference between the input and the delayed signal and generates a signal to adjust the delay of the delay line. Simply put, the DLL locks when the phase difference between the input and output is 0°, meaning the delay is set to exactly one clock cycle (360°). To generate a multiphase clock, the delay line is implemented using several series-connected delay elements or amplifiers D, each introducing a delay Di. In one example, four or multiples of four delay elements or amplifiers D are used to implement the delay line. Under locked conditions, the delay line repeats the total delay of 360°, thus, by sampling the line at four equidistant points, clock replicas with 90° phase intervals can be produced. These are the four clock phases required to drive four resonators.

[0043] Continue to refer to Figures 1 to 2 To specify the control logic and distribution circuitry, consider a single Bennett phase, where each Bennett phase comprises four parts: 1. Clock line remains at 0V, empty state. 2. Clock rises to active state. 3. Clock remains active state. 4. Clock falls to empty state, in which it returns to 0V.

[0044] Figure 4 The diagram shows a detailed schematic of an example distribution circuit system for a Bennett clock phase (e.g., Ф1+ and Ф1-), where, when the Bennett phase is in a ramp state, a transmission gate T1 formed by a p-channel transistor M1 and an n-channel transistor M2 connected in parallel will connect the resonator (e.g., ...). Figure 2 The resonator Res1 shown is connected to the Ф1+ line, and transmission gate T2 connects the resonator Res3 to Ф1-. When the Bennett phase is not in the ramp state, T1 and T2 isolate Ф1+ and Ф1- from the resonators Res1 and Res3. When the Bennett phase is in the active state, transistor M1 connects Ф1+ to VDD and the transistor...

[0045] M8 connects Ф1- to VSS. In the no-state, transistors M4 and M7 connect Ф1+ and Ф1- to ground (0V). Figure 5 exhibit Figure 4 The timing of the control signals for the distribution circuit system. In order to generate... Figure 5 The top trace shows the Bennett clock signal, and the control logic block is configured for each Bennett clock phase (in...). Figure 2In this example, there are a total of 16 clock phases, from Ф1+ to Ф8-) generating three control signals: Ramp, Stay Up, and Stay Down, along with their logical inversions. The distribution circuitry may include signals for other Bennett clock phases. Figure 4 Other examples of the distribution circuit system shown include, for instance, a distribution circuit system for each Bennett clock phase. The timing of the transition of the Ramp signal output by the control logic to the distribution circuit for the Bennett clock phase is preferably synchronized with the oscillations in resonators Res1 through Res4. This is possible because the phases of resonators Res1 through Res4 are set by the master oscillators MФ1 through MФ4 for resonators Res1 through Res4, which are set by a DLL, which is in turn set by a master digital clock input to the DLL, and this master digital clock also sets the timing of the Ramp signal output by the control logic.

[0046] Continue to refer to Figures 1 to 5 During the ramp state, the ramp control signal is established (Ramp is set to logic 1 and ( The Ф1+ and Ф1- are set to logic 0, which turns on transmission gates T1 and T2, thereby connecting Ф1+ and Ф1- to resonators Res1 and Res3.

[0047] Consider the example of the Bennett phase Ф1+. When the output of resonator 1 (Res1) intersects zero volts with a rising slope, the ramp is activated. This connects the Bennett phase Ф1+ to Res1, and the resonator voltage rises from 0V to VDD, thus supplying energy to the adiabatic logic to drive its calculations. When Res1 reaches VDD, the ramp signal is deactivated, and Res1 is disconnected from the Bennett phase. Simultaneously, transmission gate T2 and transistors M7 and M8 connect Ф1- to resonator R3, which rises from 0V to VSS.

[0048] When transmission gates T1 and T2 are closed at the end of the ramp state. Figure 5 The clock outputs Ф1+ and Ф1-, and the adiabatic logic driven by these outputs, are in a floating state. If the leakage current in the adiabatic logic is small, the voltage will remain at VDD and VSS because the adiabatic logic represents a capacitive load. However, if there is significant leakage, then... Figure 5 The voltages on the Ф1+ and Ф1- lines will drop, which will cause undesirable power spikes when the clock lines are reconnected to the resonator (e.g., Res1 in the downstate). To avoid or eliminate this voltage drop, a Stay-Up signal can be established when the Ramp signal is deactivated. This will turn on the p-channel transistor M3 and the n-channel transistor M8 and connect the Bennett clock lines Ф1+ and Ф1- to VDD and VSS, respectively.

[0049] When the Bennett clock phase is reduced, Stay Up is deactivated and Ramp is re-established, turning on T1 and T2 and reconnecting Ф1+ and Ф1- to the resonators (e.g., Res1 and Res3). This occurs when resonator Res1 is at VDD and about to drop back to 0V. As the resonator voltage drops, energy is drawn back from the adiabatic logic to the resonator and stored for reuse. When the resonator voltage reaches 0V, the Ramp signal is deactivated, disconnecting Ф1+ and Ф1-, and thus the adiabatic logic, from the resonator, and the Stay Down line is established. This turns on transistors M4 and M7, which connect Ф1+ and Ф1- to 0V, keeping them in an unconnected state.

[0050] To generate the necessary control signals (i.e., Ramp, Stay Up, Stay Down, and their inverses) for each Bennett phase, the control logic implements a simple state machine. The sequence of control signals is determined by the properties of the Bennett clock timing: Ф1 rises to the active state (Ф1+ and Ф1-), then Ф2 rises, and so on, until the last phase ФN rises. When all phases have risen, the system is in the active state, remaining in this state for NActive clock cycles. Then, the Bennett clock phases decrease to 0V in reverse order.

[0051] Figure 6 The block diagram showing the control logic is shown below. The required bit length for the counter is:

[0052] NBits=1+int(log2(2Nphase+NActive+NNull-1)) (3)

[0053] for Figure 2 For an example, with Nphase=8 and NActive=NNull=1 selected, a 5-bit counter is required. The counter is a standard incrementing counter that counts repeatedly from zero and is reset at NReset=2NPhase+NActive+NNull-1. The counter's output is fed into a decoder, whose outputs are equal to the number of steps NReset+1. As the counter counts, each decoder output is sequentially set to logic 1 from Out0 to OutNReset. The decoder outputs are routed to phase control blocks Phase Ctl 1 through Phase Ctl N, one for each Bennett phase.

[0054] Figure 7 China Showcase Figure 6 A circuit system with a single-phase control block (e.g., Phase Ctl1) having two inputs, Up and Down. For Figure 2The eight Bennett phase instances in the code, where NActive=1, have the decoder output Out0 connected as the Up input of Phase Ctl1, and Out9 connected as the Down input, as shown below. Figure 6 As shown. Other phase control circuits are connected in a similar manner, where Phase Ctl8 has decoder output Out7 as its Up input and Out16 as its Down input. All flip-flops F1 through F4 have reset inputs (omitted for clarity), which are established when power is applied, so all flip-flops F1 through F4 are activated when Q=0. The Up and Down inputs are from the decoder outputs and are set to logic 1 when the power is increased and decreased, respectively. Note that in Figure 7 For clarity, the logic inversion of the output signal is not shown, but it is provided... Figure 4 Distribution circuit system.

[0055] When the Up signal is timed to flip-flop F1, there is a delay of one MCLK cycle, after which the Ramp signal is established. In the next MCLK cycle, Ramp (from logic 1) changes to logic 0, and then flip-flop F3 changes state, thus establishing Stay Up to keep the Bennett clock line active. Flip-flop F3 keeps Stay Up established until the decoder sends the Down signal. In the next MCLK cycle, Stay Up is de-established, and then flip-flop F2 establishes Ramp to keep the Bennett clock line active and thus connect the adiabatic logic to the resonator (e.g., Res1) to recover energy. After all the Bennett phases have de-decreased, the counter ( Figure 6 Reset to zero and restart the loop. Figure 6 The circuit system of other phase control blocks and Figure 7 The circuit system shown is similar. Figure 6 The phase control block operates in a manner that generates the Bennett clock signal required to drive the adiabatic logic.

[0056] The Bennett clock can also be generated using a resonator array based on the well-known Fourier series principle to construct arbitrary waveforms. Simulations show that approximately 10 harmonics are sufficient to produce a trapezoidal waveform that closely approximates the desired waveform, as shown in Figure 8. Figure 8a The waveform of Bennett phase 1, consisting of 10 harmonics, is shown. Figure 8b It displays 12 Bennett phases, each containing 10 harmonics. Figure 9a This section illustrates a simplified implementation of a Bennett clock generator. As before, resonators Res1 through Res10 drive adiabatic logic, but no switches are required (e.g., ...). Figure 4The transmission gate T1 in the circuit is used to connect and disconnect the adiabatic logic and the resonator, because the composite waveform of the resonator has the correct shape for the Bennett phase, such as... Figure 8a As shown. To construct the Bennett phase based on the Fourier components, each harmonic requires a resonator, where the resonator required for each harmonic can be driven by a dedicated oscillator, such as... Figure 9a Osc1 drives Res1, and its frequency and amplitude are set by the desired Fourier components. The outputs of the resonators (e.g., Res1 to Res10) are combined by parallel connection and applied to adiabatic logic. If ten harmonics are needed to construct the desired waveform, ten resonators and ten master oscillators are required, as shown in Figure 9(a).

[0057] However, simplification is possible by combining the master oscillator and resonators. Specifically, if the oscillator array is driven by a waveform with the desired Bennett clock waveform shape, then according to the Fourier series theorem, this Bennett clock waveform contains all Fourier components at the appropriate harmonics and amplitudes. Piezoelectric resonators can also be used as frequency selectors, so when this waveform is applied to the resonator array, each resonator responds only to its own resonant frequency, ignoring all other frequency components. Therefore, Figure 9a The oscillators Osc1 to Osc10 in the circuit can be replaced by the main waveform generation circuit, such as... Figure 9b As shown.

[0058] To simplify the resonator array, instead of implementing a piezoelectric resonator for each desired component, multiple harmonics can be implemented in a single piezoelectric resonator structure, essentially a piezoelectric profile mode resonator. Referring to Figure 10, in a typical piezoelectric profile mode resonator, a rectangular suspended piezoelectric material plate held in place by anchor points is used to form the resonator. Metal electrodes are fabricated on the top surface of the material, and an optional metal ground plane (as shown) can be formed on the back side of the material, and a sinusoidal voltage is applied. The electric field formed by the electrodes excites mechanical oscillations in the piezoelectric material, and resonance occurs when the mechanical oscillations from each electrode are in phase and conform to the boundary conditions provided by the shape of the piezoelectric material plate. In this way, the resonant frequency of the oscillation is set by the spacing of the electrodes and the properties of the material. By fabricating electrodes with multiple spacings on the piezoelectric material, a multispectral resonator can be formed, thereby exciting oscillations at multiple frequencies. For example, Figure 10a The resonator shown in the top view has electrode fingers spaced A, A / 2, and A / 4, which will resonate at fo, 2fo, and 4fo. Note that all electrode fingers are connected together and driven by a common voltage, and there is a ground plane on the back of the piezoelectric material. A key feature of this multispectral resonator is the distance between the electrodes and the edge of the piezoelectric material. Due to mechanical oscillations... Figure 10aIn the horizontal direction, the edges of the material thus set boundary conditions, as energy is reflected at the edges, which selects the frequency modes that can be excited by the electrodes. A set of electrodes at a distance of π / 2 (half the wavelength) from the edge will be selected as the resonant mode. The number of frequency components that can be excited in the resonator is limited by the electrode spacing, which in turn is limited by the lithography method used to manufacture the electrodes. To relax the lithography requirements, the desired harmonics of the waveform can be decomposed among multiple resonators by manufacturing some harmonic electrodes on one resonator plate and other harmonic electrodes on another resonator plate. The outputs of the resonators can then be combined by connecting the resonators in parallel. The signal from the master waveform generator driving these resonators keeps the resonators in phase.

[0059] exist Figure 10a In the contour-mode resonator shown, a suspended piezoelectric plate is held in place by anchor points. These anchor points provide a path for some of the vibrational energy in the resonator plate to escape. This energy loss adversely affects the resonator's performance and should be minimized. This is particularly challenging in multispectral resonators, as multiple vibrational wavelengths must be prevented from escaping through the anchor points. This can be achieved by placing an energy reflector at each anchor point, such as... Figure 10a As shown. Figure 10c The energy reflector schematically shown is constructed based on the principle of a Bragg reflector using an array of holes etched in a piezoelectric material. By placing the holes with a spatial period of π / 4, the reflection of vibrational waves at these holes creates destructive interference, thereby preventing energy escape. Similar to electrodes, in... Figure 10a In this process, multiple periodicities of holes can be created to reflect the desired harmonics of the resonator.

[0060] To implement a full Bennett clock array with N phases, N resonators for the positive phase, N resonators for the negative phase, and control circuitry to generate a total of 2N main waveforms to drive the resonators are required. The main waveform generator can use... Figure 6 It is implemented using the same counter and decoder circuitry as in [the original text], but with a modified phase control circuit, such as [the original text]. Figure 11a As shown, the Up or Down signal is used to trigger the dual-state flip-flop F1, and the RC filter is used to expand the output step size to approximate the Bennett clock ramp. See [link to relevant documentation]. Figure 11b The output main waveform can be applied to a multispectral resonator (e.g., Figure 9b To generate the Bennett phase applied to the adiabatic logic by exciting the required harmonics.

Claims

1. A method comprising: (a) In a circuit having at least four quadrature resonators with a phase delay of π / 2 = 90°, wherein the at least four quadrature resonators generate a set of positive and negative ramps that initially hold the output clock line at zero; (b) When the output clock line intersects zero, connect the output clock line to at least one of the at least four quadrature resonators; (c) After the at least one resonator has risen to its maximum voltage, disconnect the output clock line from the at least one resonator; (d) Keep the output clock line constant for several resonator cycles; and (e) When the at least one resonator degrades, the output clock line is reconnected to the at least one resonator.

2. A method comprising: forming a Bennett phase based on Fourier components, wherein approximately ten harmonics are used to construct an arbitrary waveform, and wherein said ten harmonics comprise: At least one resonator, said at least one resonator being used for each of the ten harmonics; and A control circuit that generates a main waveform to drive the resonator.

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