Circuit board and semiconductor package comprising a circuit board

Abstract

An embodiment of the present application provides a circuit board, including: a first insulating layer; a second insulating layer, the second insulating layer being disposed on the first insulating layer; a dielectric layer, the dielectric layer being disposed between the first insulating layer and the second insulating layer; and a first via electrode, the first via electrode passing through the first insulating layer and the dielectric layer, wherein the dielectric layer includes a first through hole, the first via electrode is disposed inside the first through hole of the dielectric layer, a side surface of the first via electrode has a first inclination angle with a width narrowing towards an upper surface of the first insulating layer, a first inner side surface forming the first through hole of the dielectric layer has an inclined surface with a second inclination angle narrowing towards the upper surface of the first insulating layer, the first inclination angle and the second inclination angle are different from each other, and the side surface of the first via electrode and the first inner side surface overlap with each other along a horizontal direction.

Description

Technical Field

[0001] The present invention relates to circuit boards and semiconductor packages. Background Technology

[0002] As the performance of electrical / electronic products continues to improve, technologies are being proposed and researched for attaching a greater number of packages to substrates with limited dimensions. However, since conventional packages are essentially designed to mount a single semiconductor chip, there are limitations in achieving the desired performance.

[0003] A typical circuit board or packaging substrate has a processor package containing a processor chip and a memory package containing a memory chip interconnected. This type of packaging substrate has the advantages of reducing chip mounting area by manufacturing the processor chip and memory chip into a single integrated package, and enabling high-speed signal transmission through shorter signal paths. Due to these advantages, the aforementioned packaging substrate is widely used in mobile devices and the like.

[0004] Meanwhile, in recent years, package sizes have increased due to factors such as higher specifications in electronic devices like mobile devices and the adoption of High-Bandwidth Memory (HBM). Furthermore, as the number of functions required in application processors increases, there is a need for circuit boards that house these application processor chips, each configured as a separate processor chip based on its function. In this case, even when the application processor is divided into two processor chips based on function, the number of input / output terminals on each processor chip also increases.

[0005] Furthermore, due to advancements such as 5G, the Internet of Things (IoT), higher image quality, and increased communication speeds, the number of power and signal lines has increased, leading to a gradual increase in the number of terminals on processor chips. Consequently, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, issues arise such as difficulties in product miniaturization, reduced reliability due to board warping, and increased product costs. Therefore, increasing the density of circuit patterns, rather than increasing the area and thickness of the circuit board, is more advantageous in terms of product cost, reliability due to warping, and product miniaturization. Thus, miniaturization of circuit patterns or through electrodes is necessary.

[0006] Specifically, in order to eliminate power transmission noise and voltage drop, a capacitor layer needs to be formed in the substrate. Summary of the Invention

[0007] Technical issues

[0008] Embodiments of the present invention provide a circuit board in which a capacitor layer is formed in a desired insulating layer to reduce the electrical connection path of the capacitor layer and suppress the occurrence of voltage drop and power transmission noise, as well as a semiconductor package including the circuit board.

[0009] Furthermore, the implementation can realize a circuit board that improves integration density and increases input / output count through an embedded capacitor layer, as well as a semiconductor package including the circuit board.

[0010] Furthermore, the embodiments can realize a circuit board and a semiconductor package including the circuit board, in which, since a through-layer of dielectric layer is provided and a via electrode having an inclination angle different from the inclination angle of the through-layer is provided in the through-layer, cracks at the interface between the insulating layer and the dielectric layer, which are different insulating layers, are prevented, thereby improving structural reliability.

[0011] The objectives to be addressed in the implementation are not limited to this, and the implementation may also include objectives or effects that can be understood from the solutions to the problems described below or from the implementation.

[0012] Technical solution

[0013] A circuit board according to an embodiment of the present invention includes: a first insulating layer; a second insulating layer disposed on the first insulating layer; a dielectric layer disposed between the first insulating layer and the second insulating layer; and a first via electrode passing through the first insulating layer and the dielectric layer, wherein the dielectric layer includes a first through-hole, the first via electrode is disposed inside the first through-hole of the dielectric layer, a side surface of the first via electrode has a first tilt angle such that the width of the side surface of the first via electrode decreases toward the upper surface of the first insulating layer, a first inner surface of the first through-hole forming the dielectric layer has a tilted surface having a second tilt angle such that the width of the first inner surface decreases toward the upper surface of the first insulating layer, the first tilt angle and the second tilt angle are different from each other, and the side surface of the first via electrode overlaps with the first inner surface in the horizontal direction.

[0014] The side surface of the first via electrode may be spaced apart from the first inner surface in the horizontal direction.

[0015] The circuit board may include a second via electrode that passes through the second insulating layer and the dielectric layer.

[0016] The first via electrode can pass through the first through hole, and the dielectric layer may include a second through hole, wherein the second via electrode is disposed in the second through hole.

[0017] The side surface of the second via electrode may have a third tilt angle, such that the width of the side surface of the second via electrode increases toward the upper surface of the second insulating layer.

[0018] The second inner surface of the second via forming the dielectric layer may have an inclined surface with a fourth tilt angle, such that the width of the second inner surface increases from the first insulating layer toward the second insulating layer, the fourth tilt angle and the third tilt angle may be different from each other, and the side surface of the second via electrode may overlap with the second inner surface in the horizontal direction.

[0019] The first via electrode, the second via electrode, the first through hole, and the second through hole may overlap each other in the horizontal direction.

[0020] A portion of the first insulating layer may be disposed between the first through hole and the first via electrode, and a portion of the second insulating layer may be disposed between the second through hole and the second via electrode.

[0021] A portion of the first via electrode, the dielectric layer, and a portion of the second via electrode may overlap each other in the horizontal direction.

[0022] The width of the upper surface of the first via electrode may be less than the minimum width of the first through hole, and the width of the lower surface of the second via electrode may be less than the minimum width of the second through hole.

[0023] The length of the dielectric layer in the vertical direction may be less than the length of at least one of the first via pad and the second via pad in the vertical direction.

[0024] A portion of the first insulating layer may be disposed in the first through-hole and may overlap with a portion of the second through-hole electrode in the horizontal direction.

[0025] The second insulating layer may be disposed in the second through hole and may overlap with a portion of the first through hole electrode in the horizontal direction.

[0026] The distance from the lower surface of the dielectric layer to the lower surface of the first insulating layer may be less than the length of the first via electrode in the vertical direction.

[0027] The distance from the upper surface of the dielectric layer to the upper surface of the second insulating layer may be less than the length of the second via electrode in the vertical direction.

[0028] The length of the first via electrode in the vertical direction may be greater than the length of the first via pad in the vertical direction, and the length of the second via electrode in the vertical direction may be greater than the length of the second via pad in the vertical direction.

[0029] The circuit board may include a capacitor structure, the capacitor structure comprising: a first via pad disposed between a first insulating layer and a second insulating layer; a second via pad disposed between the first via pad and the upper surface of the second insulating layer; and a dielectric layer disposed between the first via pad and the second via pad.

[0030] According to an embodiment, a circuit board includes: a first insulating layer; a second insulating layer disposed on the first insulating layer; a dielectric layer disposed between the first insulating layer and the second insulating layer; and a first via electrode passing through the first insulating layer and the dielectric layer, wherein the dielectric layer includes a first through-hole, the first via electrode is disposed in the first through-hole of the dielectric layer, the side surface of the first via electrode is spaced apart from the inner side of the first through-hole of the dielectric layer, and the first inner surface of the first through-hole forming the dielectric layer overlaps with the side surface of the first via electrode in the horizontal direction.

[0031] The circuit board may further include a second via electrode passing through the second insulating layer and the dielectric layer, wherein the dielectric layer may include a second through hole, the second via electrode is disposed in the second through hole, a portion of the first insulating layer may be disposed between the first through hole and the first via electrode, and a portion of the second insulating layer may be disposed between the second through hole and the second via electrode.

[0032] A portion of the first insulating layer, a portion of the second insulating layer, the first through-hole, and the second through-hole may overlap each other in the horizontal direction.

[0033] Beneficial effects

[0034] Embodiments of the present invention provide a circuit board in which a capacitor layer is formed in a desired insulating layer to reduce the electrical connection path of the capacitor layer and suppress the occurrence of voltage drop and power transmission noise, as well as a semiconductor package including the circuit board.

[0035] Furthermore, embodiments may provide a circuit board that improves integration density and increases input / output count through an embedded capacitor layer, as well as a semiconductor package including the circuit board.

[0036] Furthermore, the embodiments may provide a circuit board and a semiconductor package including the circuit board, in which a through-layer of dielectric layer is provided and a via electrode having an inclination angle different from the inclination angle of the through-layer is provided in the through-layer, thereby preventing the occurrence of cracks at the interface between the insulating layer and the dielectric layer, which are different insulating layers, thereby improving structural reliability.

[0037] The various advantages and effects of the present invention are not limited to those described above, and will be more readily understood in the process of describing specific embodiments of the invention. Attached Figure Description

[0038] Figure 1 This is a plan view of a circuit board according to an embodiment of the present invention.

[0039] Figure 2 This is a perspective view of a circuit board according to an embodiment of the present invention.

[0040] Figure 3 This is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0041] Figure 4 This is a perspective view of the dielectric layer, the first via electrode, and the second via electrode in a circuit board according to a first embodiment of the present invention.

[0042] Figure 5 yes Figure 3 A magnified view of K1 in the image.

[0043] Figure 6 yes Figure 3 A magnified view of K2 in the image.

[0044] Figure 7 yes Figure 3 A magnified view of K3 in the image.

[0045] Figure 8 yes Figure 5 Examples.

[0046] Figure 9 yes Figure 5 Another example.

[0047] Figures 10a to 10x This is a view used to describe a method of manufacturing a circuit board according to a first embodiment.

[0048] Figure 11 This is a cross-sectional view of the circuit board according to the second embodiment.

[0049] Figure 12 yes Figure 11 A magnified view of K4 in the image.

[0050] Figures 13a to 13jThis is a view used to describe a method for manufacturing a circuit board according to a second embodiment.

[0051] Figure 14 This is a cross-sectional view of the circuit board according to the third embodiment.

[0052] Figure 15 yes Figure 14 A magnified view of the K5.

[0053] Figure 16 yes Figure 14 A magnified view of K6.

[0054] Figure 17 It is a cross-sectional view of the circuit board based on the modified example. Detailed Implementation

[0055] This invention can be modified in various ways and has various embodiments, therefore specific embodiments thereof will be described and illustrated in the accompanying drawings. However, it should be understood that:

[0056] This is not intended to limit the invention to specific embodiments, but rather to include all variations, equivalents, and substitutions that are contained within the spirit and scope of the invention.

[0057] Terms including ordinal numbers such as second and first may be used to describe various components, but the meaning of a component is not limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of the invention, a second component may be referred to as a first component, and similarly, a first component may be referred to as a second component. The term "and / or" includes a combination of or any one of the related listed items.

[0058] When a component is mentioned as "connected" or "linked" to another component, it should be understood that a component can be directly connected or linked to another component, but another component may exist in between. On the other hand, when a component is mentioned as "directly connected" or "directly linked" to another component, it should be understood that no other component exists in between.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. Unless it has a clearly different meaning in the context, the singular usage encompasses the plural usage. In this application, the words “comprising” or “having” are used to describe the presence of features, quantities, processes, operations, constituent elements, components, or combinations thereof, and it will be understood that the possibility of the presence or addition of one or more other features or quantities, processes, operations, constituent elements, components, or combinations thereof is not excluded in advance.

[0060] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms such as those defined in general dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0061] In the following description, embodiments will be described in detail with reference to the accompanying drawings, wherein similar reference numerals refer to the same or corresponding components, and redundant descriptions will be omitted.

[0062] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package according to the embodiments are applied will be briefly described. The electronic device includes a motherboard (not shown). The motherboard may be physically and / or electrically connected to various components. For example, the motherboard may be connected to the semiconductor package of the embodiments. The semiconductor package may also include a circuit board, a plurality of semiconductor elements disposed on the circuit board, and connecting members that electrically connect the plurality of semiconductor elements.

[0063] The circuit board may include multiple stacked insulating layers, circuit patterns disposed in the multiple stacked insulating layers, and via electrodes for connecting the circuit patterns disposed in the insulating layers.

[0064] Semiconductor components can be mounted on a circuit board and can be semiconductor chips in the form of integrated circuits (ICs) that integrate hundreds to millions or more active and / or passive components on a single chip. For example, semiconductor components can be logic chips or memory chips. Logic chips can be central processing units (CPUs) or graphics processing units (GPUs). For example, a logic chip can be: an application processor (AP) chip that includes at least one of a CPU, GPU, digital signal processor (DSP), cryptographic processor, microprocessor, and microcontroller; an analog-to-digital converter, an application-specific IC (ASIC), or a field-programmable gate array (FPGA); or a chipset that includes a specific combination of those listed above. Furthermore, semiconductor components can be memory components such as high-bandwidth memory (HBM).

[0065] A connection member is used to electrically connect multiple semiconductor elements and can be disposed between the semiconductor elements and a circuit board. For example, the connection member can be embedded in the circuit board or disposed on the circuit board. When the connection member is embedded in the circuit board, it is advantageous to reduce the thickness of the semiconductor package. The connection member can be formed of silicon, but the invention is not limited thereto. The connection member can be formed of organic materials. The connection member can be referred to as a bridge because it is used to electrically connect multiple semiconductor elements to each other.

[0066] Furthermore, the connecting member can be disposed on the circuit board. When the connecting member is disposed on the circuit board, the connecting member is covered by the molding member, and the circuit board, semiconductor element, and connecting member can be electrically interconnected through a through-mold via (TMV) through the molding member. Additionally, a redistribution layer can be separately disposed between the molding member and the semiconductor element.

[0067] Meanwhile, the product group of semiconductor packaging in the application implementation method can be any of, but not limited to, Chip Scale Package (CSP), Flip Chip-Chip Scale Package (FC-CSP), Flip Chip Ball Grid Array (FC-BGA), Package On Package (POP), and System In Package (SiP).

[0068] Furthermore, the electronic device can be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television set (TV), a video game device, a smartwatch, or an automotive device, etc. However, the present invention is not limited to these, and in addition to those mentioned above, the electronic device can also be any other electronic device that processes data.

[0069] A circuit board according to an embodiment of the present invention may include a first stacked layer and a second stacked layer disposed on the first stacked layer. Furthermore, the first and second stacked layers may each include multiple stacked insulating layers. That is, the circuit board may include insulating layers of the first and second stacked layers (or the first and / or the second stacked layers). The upper and lower stacked layers can be distinguished from each other by a structure in which the diameters of the vias in the layers increase in a direction opposite to each other. For example, in the upper stacked layer, the width or area of ​​the vias may increase upwards. Furthermore, in the lower stacked layer, the width or area of ​​the vias may decrease upwards. Additionally, each stacked layer may correspond to an insulating layer other than the core layer. The first and second insulating layers, described below, may correspond to the first and second stacked layers. Furthermore, the stacked layers may be layers different from the protective layer. This will be described in detail below.

[0070] Figure 1 This is a plan view of a circuit board according to an embodiment of the present invention. Figure 2 This is a perspective view of a circuit board according to an embodiment of the present invention, and Figure 3 This is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0071] Reference Figures 1 to 3 According to the embodiment, the circuit board 100 may include an insulating layer 110, an electrode portion 120, and a capacitor layer CAL. Furthermore, the circuit board 100 may include a protective layer SR disposed on the electrode portion 120. Additionally, a semiconductor chip connected to a via electrode may be further disposed on the circuit board 100.

[0072] First, the insulating layer 110 may include multiple insulating layers. As an embodiment, the insulating layer 110 may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113.

[0073] The second insulating layer 112 can be positioned on the first insulating layer 111. The lower surface BS2 of the second insulating layer 112 is in contact with the upper surface US1 of the first insulating layer 111 and can be coplanar with each other.

[0074] The third insulating layer 113 may be positioned on the first insulating layer 111. The upper surface of the third insulating layer 113 may contact the lower surface BS1 of the first insulating layer 111 and may be coplanar with the lower surface BS1.

[0075] For example, the third insulating layer 113, the first insulating layer 111, and the second insulating layer 112 may be arranged sequentially along the stacking direction or the vertical direction (X-axis direction).

[0076] Each stacked layer includes an insulating layer. For example, when a core layer is present on a circuit board, an upper stacked layer can be disposed on the core layer, and a lower stacked layer can be disposed below the core layer. In this case, each of the upper and lower stacked layers includes multiple insulating layers.

[0077] Furthermore, as mentioned above, the stacked layer is a layer different from the aforementioned protective layer SR, and the uppermost / lowest surface of the stacked layer (or insulating layer) corresponds to the uppermost / lowest surface of the stacked layer (insulating layer) disposed on the uppermost side, and does not refer to the uppermost / lowest surface of the protective layer SR. In other words, the uppermost surface of the insulating layer of the circuit board refers to the uppermost / lowest surface of the stacked layer, not the uppermost / lowest surface of the protective layer.

[0078] Furthermore, the insulation layer 110 may comprise a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. Additionally, the insulation layer 110 may also comprise a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcement or an inorganic filler. The fabric reinforcement may be glass fiber, and the glass fiber may be impregnated with resin to form a prepreg (PPG).

[0079] For example, the insulating layer 110 may be formed of any insulating resin such as a thermosetting resin and / or a photocurable resin. As a thermosetting resin, Ajinomoto Build-up Film (ABF), a product commercially available from Ajinomoto Co., Ltd., may be used, or a material such as PPG (Prepreg) including glass fibers may be used. As a photocurable resin, any insulating resin such as a Photo Imageable Dielectric (PID) resin may be used. The aforementioned insulating resin may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin, and may include inorganic fillers such as silica. When the insulating resin is used as a core, the core may include reinforcing materials including glass fibers or aramid fibers. For example, insulating layer 110 may exemplarily use ABF (Ajinomoto Build-up Film), a product commercially available from Ajinomoto Co., Ltd., and may also use FR-4, bismalleimide triazine (BT), PID resin (Photo Imageable Dielectric resin), or BT, etc. For example, insulating layer 110 may comprise multiple layers formed of ABF.

[0080] The insulating layers can be formed of the same material or different materials. For example, the first to third insulating layers can be formed of the same material or different materials.

[0081] Furthermore, the electrode portion 120 may include circuit patterns (or circuit pattern layers), pads, and via electrodes. The interconnect portion may correspond to "electrode pattern," "pattern," or "line," etc.

[0082] In one embodiment, electrode portion 120 may include interconnect electrodes and via electrodes. The interconnect electrodes may include interconnect portions (circuit patterns or designs) and pads disposed on an insulating layer. The via electrodes may be positioned in through-holes or vertical interconnect access holes (vias) formed in the insulating layer. Electrical connections can be achieved by the via electrodes within, on, or beneath the insulating layer.

[0083] Furthermore, the pads provided on the outside of the electrode portion 120 can be bonded to semiconductor components, substrates, or boards using solder, wiring, or conductive adhesive, and can be configured to have a width larger than the width of the circuit pattern to address the issue of ensuring yield. However, the present invention is not limited to this, and depending on the technical limitations of the bonding process, the pads can have a width equal to the width of the circuit pattern. Additionally, the pads provided on the inside are used to connect the via electrode and the circuit pattern. When the via electrode is configured to have a width larger than the width of the circuit pattern, pads with a width larger than the width of the circuit pattern are provided to ensure positional matching accuracy in the process of manufacturing the via electrode to be provided on each circuit pattern. Therefore, each via electrode can have an upper surface positioned coplanar with the lower surface of the upper pad that directly contacts the via electrode, and a lower surface positioned coplanar with the upper surface of the lower pad that directly contacts the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily refer to flat surfaces, and should be understood to include even recessed or raised surfaces that may appear depending on various processes.

[0084] In one embodiment, the electrode portion 120 may include a first electrode portion 121, a second electrode portion 122, and a third electrode portion 123. The electrode portion may include an interconnect portion and a via electrode.

[0085] The first electrode portion 121 may include a first via electrode 121a, a first interconnect portion 121b, and a first connection via electrode 121c. Furthermore, the second electrode portion 122 may include a second via electrode 122a, a second interconnect portion 122b, and a second connection via electrode 122c. Additionally, the third electrode portion 123 may include a third via electrode 123a and a third interconnect portion 123b.

[0086] The first electrode portion 121 may be positioned within the first insulating layer 111. Furthermore, the first via electrode 121a, the first interconnect portion 121b, and the first connecting via electrode 121c may be positioned within the first insulating layer 111. The first via electrode 121a may pass through the first insulating layer 111. The first via electrode 121a may be disposed between the second layer L2 and the first interconnect portion 121b. The first via electrode 121a may contact the second layer L2 and the first interconnect portion 121b. The first via electrode 121a may electrically connect the second layer L2 and the first interconnect portion 121b. The first connecting via electrode 121c may pass through at least a portion of the first insulating layer 111. The first via electrode 121a may contact the second layer L2 and the first interconnect portion 121b. Therefore, the first via electrode 121a may be electrically connected to the second layer L2 and the first interconnect portion 121b.

[0087] The second electrode portion 122 may include a second via electrode 122a and may be positioned on the dielectric layer DLL. The second via electrode 122a may pass through the dielectric layer DLL and the second insulating layer 112. The second via electrode 122a may be disposed between the first layer L1 and the second interconnect portion 122b. The second via electrode 122a may contact the first layer L1 and the second interconnect portion 122b. The second via electrode 122a may electrically connect the first layer L1 and the second interconnect portion 122b. The second connecting via electrode 122c of the second electrode portion 122 may pass through at least a portion of the second insulating layer 112. The second connecting via electrode 122c may contact the second layer L2 and the second interconnect portion 122b between the second layer L2 and the second interconnect portion 122b. The second connecting via electrode 122c may electrically connect the second layer L2 and the second interconnect portion 122b.

[0088] The third electrode portion 123 can be positioned in the third insulating layer 113. The third via electrode 123a can be positioned between the first interconnect portion 121b and the third interconnect portion 123b and can electrically connect the first interconnect portion 121b and the third interconnect portion 123b.

[0089] As an implementation, the first via electrode 121a may pass through the dielectric layer DLL and an insulating layer (e.g., a first insulating layer) in contact with the dielectric layer DLL. For example, the first via electrode 121a may pass through the dielectric layer DLL and the first insulating layer 111. The dielectric layer DLL may include a first via TH1. Furthermore, the first via electrode 121a may be located inside the first via TH1. For example, the first via electrode 121a may be accommodated in the first via TH1 and may pass through the first via TH1. For example, the first via electrode 121a may pass through the first insulating layer 111 in the first via TH1.

[0090] Furthermore, the second via electrode 122a may pass through the dielectric layer DLL and an insulating layer (e.g., a second insulating layer) in contact with the dielectric layer DLL. For example, the second via electrode 122a may pass through the dielectric layer DLL and the second insulating layer 112. The dielectric layer DLL may include a second via TH2. Furthermore, the second via electrode 122a may be located inside the second via TH2. For example, the second via electrode 122a may be accommodated in and pass through the second via TH2. For example, the second via electrode 122a may pass through the second insulating layer 112 in the second via TH2.

[0091] Here, the dielectric layer DLL can be located between the first insulating layer 111 and the second insulating layer 112. For example, the dielectric layer DLL can be located between the lower surface BS1 of the first insulating layer 111 and the upper surface US2 of the second insulating layer 112.

[0092] Furthermore, the first via electrode 121a can be positioned between the upper surface of the dielectric layer DLL and the lower surface BS1 of the first insulating layer 111. Additionally, the first via electrode 121a can pass through both the upper surface BS1 and the lower surface BS1 of the first insulating layer 111.

[0093] Furthermore, the second via electrode 122a can be positioned between the lower surface of the dielectric layer DLL and the upper surface US2 of the second insulating layer 112. Additionally, the second via electrode 122a can pass through the upper surface US2 and the lower surface BS2 of the second insulating layer 112.

[0094] The third via electrode 123a may be disposed between the lower surface of the third insulating layer 113 and the lower surface BS1 of the first insulating layer 111. Furthermore, the third via electrode 123a may pass through at least a portion of the third insulating layer 113.

[0095] Furthermore, in this specification, the via electrode may be positioned within a via formed in each insulating layer, etc. This corresponds to the via electrode passing through at least a portion of each insulating layer, etc. This specification will be described based on such a configuration.

[0096] The capacitor layer CAL can be positioned on, below, or in the middle of the insulating layer 110. For example, as described above, the capacitor layer CAL can be positioned between the first insulating layer 111 and the second insulating layer 112.

[0097] According to an embodiment, a capacitor layer CAL may include a first layer L1, a dielectric layer DLL, and a second layer L2. In the capacitor layer CAL, the first layer L1, the dielectric layer DLL, and the second layer L2 may be sequentially stacked or positioned in the vertical direction (X-axis direction). Therefore, the dielectric layer DLL may be positioned between the first layer L1 and the second layer L2. A capacitor may be formed by the dielectric layer DLL located between the first layer L1 and the second layer L2. The first layer L1 may be disposed between a first insulating layer 111 and a second insulating layer 112. For example, the first layer L1 may be positioned within the second insulating layer 112. The first layer L1 may be positioned between the first insulating layer 111 and the second insulating layer 112. The second layer L2 may be positioned on the dielectric layer DLL. The second layer L2 may be positioned between the upper surfaces of the first layer L1 and the second insulating layer 112. Therefore, the dielectric layer DLL may be positioned between the first layer L1 and the second layer L2.

[0098] The first layer L1 and the second layer L2 can be in direct contact with the via electrode. The first layer L1 and the second layer L2 enable functions such as ensuring the positional matching accuracy of the via electrode and providing electrical connection to the circuitry of the via electrode. Furthermore, the first and second layers can be used as electrodes for a capacitor. Additionally, the first and second layers can also serve as interconnects located on the upper and lower surfaces of the dielectric layer DLL.

[0099] The second layer L2 can be positioned on the upper surface US1 of the first insulating layer 111. Furthermore, the second layer L2 can be positioned between the second protective layer and the first layer (or dielectric layer).

[0100] In addition, at least a portion of the capacitor layer CAL may be embedded in the first insulating layer 111 or the second insulating layer 112.

[0101] Furthermore, in this embodiment, the capacitor layer CAL can be a continuous or connected layer or structure located on the second insulating layer 112. However, the invention is not limited to this, and the dielectric layer DLL of the capacitor layer CAL can be discontinuously disposed between the first insulating layer 111 and the second insulating layer 112. For example, the capacitor layers can be discontinuously disposed, multiple capacitor layers can be spaced apart from each other, or the capacitor layers can be disposed in a portion of the insulating layer.

[0102] Furthermore, the first layer and the second layer may correspond to the first via pad and the second via pad, which will be described below. The first layer may be used interchangeably with "first via pad," "first via pad layer," "first electrode layer," or "first electrode," etc. The second layer may be used interchangeably with "second via pad," "second via pad layer," "second electrode layer," or "second electrode," etc. Additionally, the capacitor layer may correspond to "capacitor," "capacitor structure," or "capacitor region," etc.

[0103] Furthermore, the first and second layers can be one electrode (layer) and another electrode (layer) of a capacitor layer used as a capacitor. Additionally, although a via electrode is shown as being connected to one of the first and second layers of the capacitor, one or more via electrodes may be connected according to circuit connections (e.g., series connection or parallel connection, etc.).

[0104] According to the embodiments, a capacitor layer is embedded in the circuit board to suppress the occurrence of voltage drop and power transmission noise. More specifically, when the processor of an electronic device or package substrate continuously draws more power, the first voltage drop and power transmission noise can become obstacles. Specifically, the first voltage drop may occur when the circuit inside the die or semiconductor element draws power. To mitigate the first voltage drop, as in the embodiments, capacitors can be added to the circuit board on which the die or semiconductor element is disposed. Specifically, it is preferable to add capacitors near the die or semiconductor element that is the source of the voltage drop. In this case, when capacitors are disposed on the die side or sideland of the substrate, the electrical path between the die and the capacitor on the sideland (or die side) becomes longer, and therefore the additional effect of the capacitors due to the increase in parasitic inductance, etc., can be reduced. Furthermore, capacitors on the via or sideland may cause interference to the interface of the circuit board or package substrate. Therefore, the above problems can be easily solved by a capacitor layer.

[0105] Furthermore, a dielectric layer with a high dielectric constant can be applied to form a large capacitor. In addition, in embodiments, the capacitor layer can have any suitable shape and size. For example, the capacitor layer can have a rectangular or circular shape in a plan view. Furthermore, the capacitor layer can be disposed anywhere on the circuit board. For example, to shorten electrical paths, the capacitor layer can be positioned in a layer adjacent to the upper die on the circuit board. That is, the capacitor layer can be positioned in a region of the insulating layer adjacent to the die, thus suppressing degradation of electrical performance.

[0106] The protective layer SR may further include a protective layer located on the uppermost or lowermost portion of the insulating layer 110. The protective layer SR may include a first protective layer SR1 and a second protective layer SR2. The first protective layer SR1 may be located below the first insulating layer 111. Furthermore, the second protective layer SR2 may be located on the second insulating layer 112 or below the third insulating layer 113. As a modified example, the second protective layer SR2 may be disposed on the capacitor layer CAL to cover the capacitor layer CAL. Therefore, as a modified example, the protective layer may pass through a via pad to contact the dielectric layer. For example, the second protective layer SR2 may pass through the second layer L2, which serves as a second via pad. Furthermore, the second protective layer SR2 may contact the dielectric layer DLL. The dielectric layer DLL may be located in the insulating layer 110 of the circuit board 100 or at the outermost edge of the insulating layer. Therefore, when the protective layer SR is formed, a portion of the second layer L2 may be open to expose the outermost dielectric layer DLL.

[0107] The protective layer SR can be used to protect the pads from external moisture or contaminants, and to prevent short circuits during the bonding process between semiconductor components and / or the motherboard and the circuit board, the protective layer SR can, exemplarily, be formed of solder resist. Specifically, the semiconductor components and / or the motherboard include multiple terminals for connection to the circuit board. Furthermore, the multiple terminals can be arranged in a high density. Solder can be used as an example when the multiple terminals and the pads of the circuit board are bonded. When using solder, solder short circuits between the high-density terminals can occur. Therefore, to address the short circuit problem, a solder resist with poor solder wetting properties can be provided. Furthermore, the protective layer SR can be formed of an insulating material for electrical connection. The protective layer SR can include resins, curing agents, photoinitiators, pigments, solvents, fillers, additives, or acrylic monomers, etc. Additionally, a third insulating layer (not shown) can include any of a photoresist layer, a cover-lay, and a polymer material. Furthermore, the insulating layer or protective layer SR positioned in the outer stacked area of ​​the circuit board can have openings. Through these openings, the circuit board can be electrically connected to another semiconductor component or circuit board, etc.

[0108] Furthermore, the protective layer SR may include connection trenches for electrically connecting each electrode portion to a chip or die, etc. For example, multiple connection trenches CG1, CG2, and CG3 may exist. Connection trench CG1 may include a first connection trench CG1, a second connection trench CG2, and a third connection trench CG3.

[0109] The first connection trench CG1 may include a first connection terminal PP1 and a second connection terminal PP2. Each of the first connection terminal PP1 and the second connection terminal PP2 can be connected to a first layer L1 and a second layer L2. Furthermore, a chip can be mounted in the first connection trench CG1. Therefore, each of the first connection terminal PP1 and the second connection terminal PP2 can be electrically connected to one terminal and the other terminal of the chip. Thus, due to the formation of a capacitor between the first layer L1 and the second layer L2, the chip can be electrically connected to a capacitor.

[0110] The second connecting groove CG2 may include a third connecting terminal PP3 and a fourth connecting terminal PP4. The third connecting terminal PP3 and the fourth connecting terminal PP4 may perform the same function as the first connecting terminal and the second connecting terminal described above.

[0111] Furthermore, as mentioned above, when the dielectric layer DLL is disposed on the outermost side of the insulating layer or stacked layer, the electrical connection distance between the semiconductor chip and the capacitor layer can be reduced. Therefore, improved electrical performance can be provided.

[0112] Furthermore, as described below, even when the dielectric layer DLL is disposed between stacked insulating layers, the dielectric layer DLL is also configured to be adjacent to the outermost insulating layer to reduce the electrical connection path with the capacitor, thereby improving electrical performance.

[0113] Furthermore, the third connecting trench CG3 can be used for capacitor connection, and can also be a trench in which various components are disposed.

[0114] The outermost surface of the protective layer may be located inside the outermost surface of the dielectric layer DLL or the insulating layers 111, 112 and 113. However, the invention is not limited thereto, and the outermost surface of the protective layer may be formed to be coplanar with the outermost surfaces of the insulating layers 111, 112 and 113 or the outermost surface of the dielectric layer DLL.

[0115] Furthermore, the first layer L1 may be exposed at the outermost surface of the circuit board 100. When the first layer L1 is exposed at the outermost surface of the circuit board 100, the first layer L1 exposed at the outermost surface may be a dummy layer. Alternatively, the first layer L1 may be covered by the second insulating layer 112. Therefore, the first layer L1 may not be exposed at the circuit board 100.

[0116] Furthermore, the first interconnect portion 121b may be exposed at the outermost surface of the circuit board 100. When the first interconnect portion 121b is exposed at the outermost surface of the circuit board 100, the first interconnect portion 121b exposed at the outermost surface may be a dummy layer. Alternatively, the first interconnect portion 121b may be covered by the first insulating layer 111. Therefore, the first interconnect portion 121b may not be exposed at the circuit board 100. This can be equally applied to other interconnect portions.

[0117] Figure 4 This is a perspective view of the dielectric layer, the first via electrode, and the second via electrode in a circuit board according to a first embodiment of the present invention. Figure 5 yes Figure 3 A magnified view of K1 in the image.

[0118] Reference Figure 4 and Figure 5 The side surface S1 of the first via electrode 121a may have a width that decreases toward the upper surface of the first insulating layer 111, and may have a first tilt angle θ1. The width of the first via electrode 121a may decrease in the vertical direction. The first tilt angle θ1 may correspond to the angle formed between the upper (or lower) surface of the first via electrode 121a and the side surface S1.

[0119] Furthermore, the dielectric layer DLL may have a first inner surface IS1 forming the first via TH1. Additionally, the first insulating layer 111 may be positioned on the first inner surface IS1. Therefore, the first inner surface IS1 may contact the first insulating layer 111. Furthermore, the first inner surface IS1 may have a second tilt angle θ2, such that the width of the first inner surface IS1 decreases towards the upper surface of the first insulating layer 111. Accordingly, the width (or diameter) of the first via TH1 may be reduced (or decreased) in the vertical direction. In an embodiment, the first tilt angle θ1 may be different from the second tilt angle θ2. Furthermore, the side surface S1 of the first via electrode 121a and the first inner surface IS1 may overlap each other in the horizontal direction (Y-axis direction).

[0120] In this configuration, the side surface S1 of the first via electrode 121a is spaced apart from the first inner surface IS1 in the horizontal direction (Y-axis direction). The side surface S1 of the first via electrode 121a has a first separation distance gap1 from the first inner surface IS1 in the horizontal direction (Y-axis direction). Due to this configuration, the side surface S1 of the first via electrode 121a does not contact either the dielectric layer DLL or the first insulating layer 111. That is, the first via electrode 121a does not contact the interface between the dielectric layer DLL and the first insulating layer 111, which are different insulating layers. Therefore, during processes such as decontamination processes, the formation of trenches at the interface between the dielectric layer DLL and the first insulating layer 111 can be suppressed. Therefore, the bonding strength of the first via electrode 121a can be improved, and cracks such as trenches at the interface between the dielectric layer DLL and the first insulating layer 111 can be suppressed, thereby improving the reliability of the circuit board 100.

[0121] Furthermore, the side surface S2 of the second via electrode 122a may have a width (or diameter) that increases toward the upper surface of the second insulating layer 112. For example, the width (or diameter) of the second via electrode 122a may increase in the vertical direction. The side surface S2 of the second via electrode 122a may increase toward the upper surface of the second insulating layer 112 and may have a third tilt angle θ3. The third tilt angle θ3 may correspond to the angle formed between the lower (or upper) surface of the second via electrode 122a and the side surface S2.

[0122] Furthermore, the dielectric layer DLL may have a second inner surface IS2 forming the second via TH2. Additionally, the second insulating layer 112 may be positioned on the second inner surface IS2. Therefore, the second inner surface IS2 may contact the second insulating layer 112. Furthermore, the second inner surface IS2 may have a fourth tilt angle θ4, such that the width of the second inner surface IS2 increases towards the upper surface of the second insulating layer 112. Therefore, the width (or diameter) of the second via TH2 may become larger (or increase) in the vertical direction. In an embodiment, the third tilt angle θ3 may be different from the fourth tilt angle θ4. Furthermore, the side surface S2 of the second via electrode 122a and the second inner surface IS2 may overlap each other in the horizontal direction (Y-axis direction).

[0123] In this configuration, the side surface S2 of the second via electrode 122a can be spaced apart from the second inner surface IS2 in the horizontal direction (Y-axis direction). The side surface S2 of the second via electrode 122a can also have a second separation distance gap2 from the second inner surface IS2 in the horizontal direction (Y-axis direction). This configuration suppresses the formation of trenches at the interface between the dielectric layer DLL and the second insulating layer 112. Therefore, the reliability of the circuit board 100 can be improved.

[0124] The first via electrode 121a can be disposed in the first via TH1 of the dielectric layer DLL, and the second via electrode 121b can be disposed in the second via TH2. Therefore, the first via electrode 121a, the second via electrode 122a, the first via TH1, and the second via TH2 can overlap each other in the horizontal direction (Y-axis direction). Furthermore, the first via TH1 and the second via TH2 can overlap with the side surface S1 of the first via electrode 121a and the side surface S2 of the second via electrode 122a in the horizontal direction (Y-axis direction).

[0125] Furthermore, as described above, a portion of the first insulating layer 111 may be disposed between the first through hole TH1 and the first via electrode 121a. Specifically, a portion of the first insulating layer 111 may be positioned between the first through hole TH1 and the side surface S1 of the first via electrode 121a.

[0126] Furthermore, a portion of the second insulating layer 112 may be disposed between the second through hole TH2 and the second via electrode 122a. Specifically, a portion of the second insulating layer 112 may be positioned between the side surface S2 of the second through hole TH2 and the second via electrode 122a.

[0127] Therefore, a portion of the first via electrode 121a, the dielectric layer DLL, and a portion of the second via electrode 122a can overlap each other in the horizontal direction (Y-axis direction). Specifically, a portion of the first insulating layer 111 can be disposed in the first via TH1, and a portion of the second via electrode 122a can be disposed in the second via TH2. Therefore, a portion of the first insulating layer 111 can overlap with a portion of the second via electrode 122a in the horizontal direction.

[0128] In addition, a portion of the first via electrode 121a, the dielectric layer DLL, and a portion of the second via electrode 122a may also overlap with the first via TH1 and the second via TH2 in the horizontal direction.

[0129] Therefore, the first via electrode 121a can pass through the first via TH1 and a portion of the first insulating layer 111 in the first via TH1. The second via electrode 122a can pass through a portion of the second insulating layer 112 in the second via TH2 and the second via TH2. The first via electrode 121a and the second via electrode 122a can pass through the dielectric layer DLL. Furthermore, the first via electrode 121a can pass through the first via TH1 of the dielectric layer DLL. Furthermore, the second via electrode 122a can pass through the dielectric layer DLL. Furthermore, the second via electrode 122a can pass through the second via TH2 of the dielectric layer DLL.

[0130] Accordingly, in the first through hole TH1, the width W1 of the first through hole TH1 can be greater than the width W2 of the first via electrode 121a. Furthermore, in the second through hole TH2, the width W3 of the second through hole TH2 can be greater than the width W4 of the second via electrode 122a.

[0131] Furthermore, the width (or diameter) of the first via electrode 121a can gradually increase from the upper surface of the second insulating layer 112 toward the lower surface of the second insulating layer 112. Conversely, the width (or diameter) of the second via electrode 122a can gradually decrease from the upper surface of the second insulating layer 112 toward the lower surface of the second insulating layer 112. Therefore, the directions in which the diameters of the first via electrode 121a and the second via electrode 122a increase can be opposite to each other. In other words, the directions in which the widths of the first via electrode 121a and the second via electrode 122a increase can be opposite to each other. In this embodiment, the width of the second via electrode 122a can gradually decrease from the upper surface of the second insulating layer 112 toward the lower surface of the second insulating layer 112. On the other hand, the width of the first via electrode 121a can gradually increase from the upper surface of the second insulating layer 112 toward the lower surface of the second insulating layer 112.

[0132] Furthermore, the width (or diameter) of the first through-hole TH1 can increase from the upper surface of the second insulating layer 112 toward the lower surface of the second insulating layer 112. Correspondingly, the width (or diameter) of the second through-hole TH2 can decrease from the upper surface of the second insulating layer 112 toward the lower surface of the second insulating layer 112.

[0133] Furthermore, in this embodiment, the first via electrode 121a and the second via electrode 122a may at least partially not overlap with each other in the vertical direction (X-axis direction). Furthermore, the third via electrode may not overlap with the first via electrode 121a and the second via electrode 122a in the horizontal direction (Y-axis direction). Furthermore, the third via electrode 123a may not overlap with the capacitor layer CAL in the horizontal direction (Y-axis direction).

[0134] Simultaneously, the first via electrode 121a may overlap with at least a portion of the capacitor layer CAL in the horizontal direction (Y-axis direction). The first via electrode 121a may overlap with the first layer L1 of the dielectric layer DLL and the capacitor layer CAL in the horizontal direction (Y-axis direction).

[0135] Furthermore, the second via electrode 122a and the first via electrode 121a may overlap with the dielectric layer DLL in the horizontal direction (Y-axis direction).

[0136] The outer surfaces of the first via electrode 121a and the second via electrode 122a, which overlap with the dielectric layer DLL in the horizontal direction, can be set at different angles to each other. For example, the angle (first tilt angle) formed between the first via electrode 121a and the upper surface of the dielectric layer DLL can be different from the angle (second tilt angle) formed between the via electrode 122a and the upper surface of the dielectric layer DLL.

[0137] Furthermore, a storage capacitor or capacitor may be formed between the first layer L1 and the second layer L2, with the dielectric layer DLL interposed therebetween. In other words, as described above, the capacitor of the dielectric layer DLL may be formed between the second via pad L2 and the first via pad L1. Additionally, the capacitor layer CAL may be used as a “capacitor.” This capacitor layer or capacitor needs to be further miniaturized to meet the increased integration density required by the substrate and semiconductor components.

[0138] As a method to improve the storage capacitance of a capacitor, one could consider increasing the effective area of ​​the first and second layers (via pads or electrodes), reducing the thickness of the dielectric film, and using a high-dielectric-constant material as the dielectric film. Specifically, when using a high-dielectric-constant material as the dielectric film, leakage current frequently occurring between the first layer (used as the lower electrode) and the second layer (used as the upper electrode) can be sufficiently reduced while maintaining a thin equivalent oxide thickness. In embodiments, the high-dielectric-constant material can be used as the dielectric film. For example, the high-dielectric-constant material may include, for example, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, or titanium oxide.

[0139] Furthermore, as described above, when a high-capacitance capacitor is mounted on the circuit board according to the embodiment, problems such as reduced circuit board integration density and input / output count due to capacitor size can be solved. In other words, the capacitor layer according to the embodiment increases circuit board integration density and input / output count while providing improved storage capacitance.

[0140] A capacitor can be formed in the region where the first via pad L1, the dielectric layer DLL, and the second via pad L2 overlap each other in the vertical direction (X-axis direction). Furthermore, the size of the capacitor can correspond to the size of the region where the first via pad L1, the dielectric layer DLL, and the second via pad L2 overlap each other in the vertical direction (X-axis direction).

[0141] Furthermore, the areas of the first layer L1 and the second layer L2 can be the same or different. For example, the area of ​​the first layer L1 can be smaller than the area of ​​the second layer L2. After forming the first layer (or the second layer) and the dielectric layer DLL, the second layer (or the first layer) can be formed by etching. For example, the area of ​​the upper surface of the first layer L1 can be smaller than the area of ​​the upper surface of the second layer L2. Furthermore, the area of ​​the lower surface of the first layer L1 can be smaller than the area of ​​the lower surface of the second layer L2. Furthermore, the planar area of ​​the dielectric layer DLL can be larger than the area of ​​either the first layer L1 or the second layer L2. Therefore, a capacitor can be formed by adjusting the formation area of ​​the second layer L2. Furthermore, it is easy to prevent a decrease in the capacitance value due to the dielectric layer. Therefore, capacitance deviations and errors caused by differences in the overlapping area can be suppressed.

[0142] Figure 6 yes Figure 3 A magnified view of K2 in the image, and Figure 7 yes Figure 3 A magnified view of K3 in the image.

[0143] Reference Figure 6 and Figure 7 The first via electrode 121a may at least partially overlap with the second connecting via electrode 122c in the vertical direction (X-axis direction).

[0144] Furthermore, the first through-hole TH1 may have a minimum width W1a at its upper surface. The second through-hole TH2 may have a minimum width W3a at its lower surface. Furthermore, the first via electrode 121a may have a minimum width W2a at its upper surface. Furthermore, the second via electrode 122a may have a minimum width W4a at its lower surface.

[0145] In this embodiment, the minimum width W2a of the upper surface of the first via electrode 121a can be smaller than the minimum width W1a of the first via TH1. Therefore, the first via electrode 121a can be spaced apart from the inner surface of the first via TH1. Furthermore, the minimum width W4a of the lower surface of the second via electrode 122a can be smaller than the minimum width W3a of the second via TH2. Therefore, the second via electrode 122a can be spaced apart from the inner surface of the second via TH2. Thus, cracks or separations occurring at the interface between the dielectric layer DLL and the first insulating layer (or the second insulating layer), which are different insulating layers, can be suppressed.

[0146] Furthermore, the vertical length H1 of the first via electrode 121a can be greater than the length H2 from the lower surface of the dielectric layer DLL to the lower surface of the first insulating layer 111. In other words, the length H2 from the lower surface of the dielectric layer DLL to the lower surface of the first insulating layer 111 can be less than the vertical length H1 of the first via electrode 121a. Alternatively, the maximum vertical length of the first insulating layer 111 can be greater than the length H2 from the lower surface of the dielectric layer DLL to the lower surface of the first insulating layer 111.

[0147] Furthermore, the length H3 from the upper surface of the dielectric layer DLL to the upper surface of the second insulating layer 112 in the vertical direction can be less than the length H4 of the second via electrode 122a in the vertical direction. In other words, the length H4 of the second via electrode 122a in the vertical direction can be greater than the length H3 from the upper surface of the dielectric layer DLL to the upper surface of the second insulating layer 112. Alternatively, the maximum length of the second insulating layer 112 in the vertical direction can be greater than the length H3 from the upper surface of the dielectric layer DLL to the upper surface of the second insulating layer 112.

[0148] Furthermore, the length of the dielectric layer DLL in the vertical direction may be less than the length of at least one of the first via pad L1, the second via pad L2, the first via electrode 121a, and the second via electrode 122b in the vertical direction. For example, the length of the dielectric layer DLL in the vertical direction (X-axis direction) may be less than the length of the first via pad L1 or the second via pad L2 in the vertical direction. Therefore, even when a capacitor layer is embedded in the circuit board, a compact or thin circuit board can be provided.

[0149] Furthermore, the length of the first via electrode 121a or the second via pad 122a in the vertical direction may be greater than the length of the first via pad L1 or the second via pad L2 in the vertical direction.

[0150] Furthermore, in the circuit board 100, among the multiple via electrodes, the first via electrode 121a, the second via electrode 122a, and the third via electrode 123a can be disposed at different positions in the vertical direction. The first via electrode 121a and the second via electrode 122a can be non-overlapping with the third via electrode 123a in the horizontal direction (Y-axis direction).

[0151] Furthermore, the first connecting via electrode 121c may partially overlap with the first via electrode 121a in the vertical direction, but may not overlap with the second via electrode 122a in the vertical direction. Similarly, the second connecting via electrode 122c may partially overlap with the second via electrode 122a in the vertical direction, but may not overlap with the first via electrode 121a in the vertical direction.

[0152] Furthermore, the vertical length of the first connecting via electrode 121c may be less than the vertical length of the first insulating layer 111 or the vertical length of the second via electrode 122a. Similarly, the vertical length of the second connecting via electrode 122c may be less than the vertical length of the second insulating layer 112 or the vertical length of the first via electrode 121a.

[0153] In this embodiment, the thicknesses of the first via electrode 121a, the second via electrode 122a, and the third via electrode 123a may be equal to or different from each other. For example, the thickness of the first via electrode 121a may be greater than the thickness of the second via electrode 122a. Furthermore, the thickness of the third via electrode 123a may be greater than the thickness of at least one of the first via electrode 121a and the second via electrode 122a. For example, the thickness of the third via electrode 123a may be greater than the thickness of the second via electrode 122a. Due to this configuration, at least one die (or semiconductor element) disposed on the circuit board 100 can be easily connected to a capacitor.

[0154] Even when the first via electrode 121a and the first connecting via electrode 121c have the same minimum width (or area), they can have different maximum areas based on the same height. Similarly, even when the second via electrode 122a and the second connecting via electrode 122c have the same minimum width (or area), they can have different maximum areas based on the same height.

[0155] Furthermore, the length of each of the first insulating layer 111 and the second insulating layer 112 in the vertical direction may be greater than the length of the dielectric layer DLL. For example, the length of the first insulating layer 111 in the vertical direction may be greater than the length of the dielectric layer DLL in the vertical direction. Similarly, the length of the second insulating layer 112 in the vertical direction may be greater than the length of the dielectric layer DLL in the vertical direction.

[0156] Figure 8 yes Figure 5 Examples, and Figure 9 yes Figure 5 Another example.

[0157] In an implementation, the first tilt angle θ1 may be different from the second tilt angle θ2. Furthermore, the third tilt angle θ3 may be different from the fourth tilt angle θ4.

[0158] Reference Figure 8 The first tilt angle θ1 can be smaller than the second tilt angle θ2. They can be different. Furthermore, the third tilt angle θ3 can be smaller than the fourth tilt angle θ4.

[0159] Therefore, the first separation distance gap1 between the first inner surface IS1 of the first through hole TH1 and the side surface S1 of the first through hole electrode 121a can decrease from the upper surface of the first insulating layer 111 toward the lower surface.

[0160] Furthermore, the second separation distance gap2 between the second inner surface IS2 of the second through hole TH2 and the side surface S2 of the second through hole electrode 122a can increase from the upper surface of the first insulating layer 111 toward the lower surface.

[0161] Therefore, when the first layer L1 or the second layer L2 is adjacent to the first via electrode 121a or the second via electrode 122a, the capacitance reduction caused by the capacitor layer can be reduced.

[0162] Reference Figure 9 In this example, the first tilt angle θ1 can be greater than the second tilt angle θ2. They can be different. Furthermore, the third tilt angle θ3 can be greater than the fourth tilt angle θ4.

[0163] Therefore, the first separation distance gap1 between the first inner surface IS1 of the first through hole TH1 and the side surface S1 of the first through hole electrode 121a can increase from the upper surface of the first insulating layer 111 toward the lower surface.

[0164] Furthermore, the second separation distance gap2 between the second inner surface IS2 of the second through hole TH2 and the side surface S2 of the second through hole electrode 122a can decrease from the upper surface of the first insulating layer 111 toward the lower surface.

[0165] Figures 10a to 10x This is a view used to describe a method of manufacturing a circuit board according to a first embodiment.

[0166] Reference Figure 10a A carrier substrate 310 can be fabricated. The carrier substrate 310 can be a copper clad laminate (CCL). Therefore, the carrier substrate 310 can include a carrier insulating layer 311 and copper foil layers 312 disposed on both surfaces of the carrier insulating layer 311. The carrier insulating layer 311 can be formed of PPG.

[0167] Furthermore, an additional insulating layer 320 may be provided on one or both side surfaces of the carrier plate 310. The structure of providing each layer on the two side surfaces will be described below.

[0168] Furthermore, dielectric layer DLL', first base layer LL1, and second base layer LL2, which are separated and disposed on both sides or one side of the carrier board 310 for use as capacitor layers as described below, may be provided. Dielectric layer DLL' may correspond to the aforementioned "dielectric layer". First base layer LL1 may correspond to the aforementioned "first layer" or "first via pad". Second base layer LL2 may correspond to the aforementioned "second layer" or "second via pad".

[0169] Furthermore, a separation layer 330 for separation can be disposed on the first substrate layer LL1 and the second substrate layer LL2. The separation layer 330 can be a copper foil. Therefore, in the first substrate layer LL1 and the second substrate layer LL2, the bonding force with the dielectric layer can be greater than the bonding force with the separation layer 330.

[0170] Reference Figure 10b The carrier plate 310, the additional insulating layer 320, the release layer 330, the second base layer LL2, the dielectric layer DLL', and the first base layer LL1 can be stacked and pressed. In this case, pressing can be performed with the outermost release layer 330 removed. Therefore, the additional insulating layer 320, the release layer 330, the second base layer LL2, the dielectric layer DLL', and the first base layer LL1 can be sequentially stacked on both side surfaces of the carrier plate 310.

[0171] Reference Figure 10cA mask 350 can be formed on the first substrate layer LL1. For example, the mask 350 can be a dry film. Furthermore, exposure and development can be performed on the mask 350.

[0172] Reference Figure 10d An opening region OP can be formed in the mask 350 on the first substrate layer LL1 by exposure and development performed on the mask 350. In other words, patterning can be performed on the dry film. The mask 350 can be disposed in areas other than where the first via pad is formed. Furthermore, a mask curing process can be performed after the opening region is formed by exposure or the like. This mask formation can be applied to the formation of other masks in the same manner.

[0173] Reference Figure 10e The plating can be performed in the opening area of ​​the mask 350. That is, the plating layer EE1 can be formed to correspond to the position of the first via pad. For example, various processes, including chemical plating, can be applied to the plating layer.

[0174] Reference Figure 10f The mask 350 can be removed. The mask 350 can be removed using various etching methods. Furthermore, etching can be performed on the plating layer and the first base layer. Etching can be performed on a partial area or the entire area to correspond to the first via pad. Partial etching can be performed by adding a mask, etc. Furthermore, when etching the entire area, both the plating layer and the first base layer can be etched. Through etching, the plating layer and the first base layer can be held in the desired position to correspond to the mask of FIG. 10C. That is, the first via pad L1 can be formed.

[0175] Reference Figure 10g Etching can be performed on the dielectric layer DLL. Therefore, a first via TH1 can be formed in the dielectric layer DLL.

[0176] Reference Figure 10h A first insulating layer 111 may be formed. The first insulating layer 111 may be formed on the first via pad and the dielectric layer. In addition, a plating layer EE2 for the third electrode portion may be formed on the first insulating layer 111.

[0177] Reference Figure 10i A first via V1 can be formed to house the first via electrode. The first via V1 can be formed within the aforementioned first through-hole TH1. That is, the first via V1 can pass through the first through-hole TH1. Furthermore, a second via V2 can be formed through the first insulating layer 111 to expose the first via pad L1. The first via V1 can pass through the dielectric layer DLL and the first insulating layer 111. Additionally, the first via V1 can also pass through the plating layer on the first insulating layer 111.

[0178] In this case, the first via V1 and the second via V2 can be formed by various methods. For example, the via can be formed by a laser. For example, the first via V1 and the second via V2 can be formed by a carbon dioxide (CO2) laser drill.

[0179] Reference Figure 10j The de-smear method can be performed on the formed first and second vias. For example, since the boundary between the first insulating layer and the dielectric layer DLL is eliminated by de-smearing, cracks and gaps at the interface between the stacked insulating layers can be suppressed by the de-smearing method.

[0180] Furthermore, a plating layer EE3 can be formed in the first via and the second via. The plating layer EE3 formed in the first via V1 and the second via V2 can be connected to the plating layer located on the upper surface of the first insulating layer 111 and the second base layer LL2. In this case, the plating layer can be located outside the first via electrode as a seed layer. In addition, the seed layer can be disposed outside the aforementioned extension portion (first extension portion), or it can be located over the entire extension portion. That is, the aforementioned seed layer can be located at the outermost part of the first via electrode, and the plating layer described below can be located inside the first via electrode or inside the seed layer. In this case, the seed layer and the plating layer can be formed from different metallic materials, such as the aforementioned first metal and second metal. Therefore, by using a more flexible metal as the seed layer, the reliability against the brittle properties of the dielectric layer can be improved more effectively.

[0181] Reference Figure 10k and Figure 10l A mask 350' can be formed on the first insulating layer 111 and the aforementioned plating layer. For example, the mask 350' can be a dry film. Furthermore, the opening region can be formed by performing exposure and development on the mask 350'. In other words, patterning can be performed on the dry film. The mask 350' can be disposed in a region other than the location where the first electrode portion is formed. Furthermore, a mask curing process can be performed after the opening region OP1 is formed by exposure or the like.

[0182] Reference Figure 10m The plating can be performed in the opening region OP1 of the mask 350'. That is, the plating layer EE4 can be formed to correspond to the position of the first electrode portion. For example, various processes, including chemical plating, can be applied to the plating layer EE4.

[0183] Reference Figure 10n It can remove the mask by 350'.

[0184] In addition, refer to Figure 10oThe plating layer can be etched. Therefore, the plating layers EE3 and EE4 formed on the first insulating layer 111 can be electrically separated corresponding to the position of the first electrode portion 121. Therefore, the first via electrode 121a, the first interconnect portion 121b, and the first connecting via electrode 121 can be formed in the first electrode portion 121.

[0185] Reference Figure 10p A third insulating layer 113 may be formed on the first electrode portion 121. Furthermore, a plating layer EE5 may be formed on the third insulating layer 113. Here, the third electrode portion may be formed in the third insulating layer 113 as the first electrode portion. However, as described below, the third electrode portion may also be formed simultaneously with the formation of the second electrode portion in the second insulating layer. The description will be based on this configuration.

[0186] Reference Figure 10q The second base layer LL2 and the layer located on the second base layer LL2 can be separated from the aforementioned carrier plate and additional insulating layer.

[0187] Reference Figure 10r A plating layer can be formed on the second substrate layer LL2. Furthermore, a mask 350'' can be formed on the plating layer formed on the second substrate layer LL2. Additionally, the mask 350'' can be formed below the third via and the third insulating layer 113. For example, the mask 350'' can be a dry film. Furthermore, an opening region can be formed by performing exposure and development on the mask 350''. In other words, patterning can be performed on the dry film. The mask 350'' can be disposed in an area other than where the second electrode portion is formed. Furthermore, a mask curing process can be performed after the opening region is formed by exposure and development.

[0188] Reference Figure 10s A plating layer can be applied to the opening area of ​​the mask 350''. Therefore, a plating layer can be formed. Furthermore, the mask 350'' can be removed. The mask 350 can be removed by various etching methods. Furthermore, etching can be performed on the plating layer and the second base layer. Etching can be performed on a partial area or the entire area to correspond to the second via pad. Partial etching can be performed by adding a mask, etc. Furthermore, when etching the entire area, both the plating layer and the second base layer can be etched. Through etching, the plating layer and the first base layer can be held in the desired position to correspond to the mask. That is, the second via pad L2 can be formed.

[0189] Reference Figure 10t Etching can be performed on the dielectric layer DLL. Therefore, a second via TH2 can be formed in the dielectric layer DLL.

[0190] Reference Figure 10uA second insulating layer 112 may be formed on the dielectric layer DLL. The second insulating layer 112 may be formed on the second via pad and the dielectric layer. In addition, a portion of the second insulating layer 112 may be positioned in the second via TH2.

[0191] Reference Figure 10v A third via V3 can be formed to house the second via electrode. The third via V3 can be formed within the aforementioned second via TH2. That is, the third via V3 can pass through the second via TH2. Furthermore, a fourth via V4 can be formed through the second insulating layer 112 to expose the second via pad. The third via V3 can pass through the dielectric layer DLL and the second insulating layer 112. Additionally, the third and fourth vias can also pass through the plating layer located on the second insulating layer 112.

[0192] In this case, the third via V3 and the fourth via V4 can be formed by various methods. For example, the vias can be formed by a laser.

[0193] In addition, a via corresponding to the third via electrode of the third electrode section can also be formed.

[0194] Furthermore, methods such as the aforementioned decontamination method can be applied to the third through-hole V3 and the fourth through-hole V4.

[0195] Reference Figure 10w Similar to the formation of the first and second vias described above, plating layers can be formed in the third via V3 and the fourth via V4. The plating layers formed in the third via V3 and the fourth via V4 can be connected to the plating layer positioned on the upper surface of the second insulating layer and the first via pad (or the second via pad). Furthermore, a mask can be formed on the second insulating layer 112 and the aforementioned plating layers. For example, the mask can be a dry film. Furthermore, opening regions can be formed by performing exposure and development on the mask. In other words, patterning can be performed on the dry film. The mask can be disposed in areas other than where the second electrode portion is formed. Furthermore, a curing process of the mask can be performed after forming the opening regions by exposure, etc. Furthermore, plating can be performed in the opening regions of the mask. That is, the plating layer can be formed to correspond to the position of the second electrode portion. For example, various processes including chemical plating can be applied to the plating layer. Next, the mask can be removed. Furthermore, similarly, the third electrode portion 123 can also be formed by a process including the aforementioned plating.

[0196] Reference Figure 10x A protective layer SR can be formed on the second electrode portion and the third electrode portion. In addition, an opening region for electrical connection with the chip or substrate can be formed in the protective layer SR.

[0197] Figure 11 This is a cross-sectional view of the circuit board according to the second embodiment, and Figure 12yes Figure 11 A magnified view of K4 in the image.

[0198] Reference Figure 11 and Figure 12 The circuit board 100A according to the second embodiment may include an insulating layer 110, an electrode portion 120, and a capacitor layer CAL. Furthermore, the circuit board 100A may also include a protective layer SR disposed on the electrode portion 120. In addition, the configurations described in the embodiments of the present invention, except as described below, can be applied equivalently.

[0199] In this embodiment, in the circuit board 100A, the insulating layer 110 may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113. Furthermore, the electrode portion 120 may include a first electrode portion 121, a second electrode portion 122, and a third electrode portion 123.

[0200] In this case, the second electrode section 122 may not include the second via electrode 122a.

[0201] That is to say, there may only be a first via TH1 relative to the dielectric layer DLL, and the aforementioned second via TH2 may not exist.

[0202] Therefore, the second electrode portion 122 may include a second interconnect portion and a second connecting via electrode. Thus, the first via electrode 121a may overlap with the dielectric layer DLL (first via TH1) and a portion of the first insulating layer 111 in the horizontal direction. Furthermore, the first via electrode 121a may not overlap with the second insulating layer 112 in the horizontal direction. Additionally, a portion of the first insulating layer 111 may also not overlap with the second insulating layer 112 in the horizontal direction.

[0203] Furthermore, in a circuit board, the number of insulating layers located below the dielectric layer DLL may be the same as or different from the number of insulating layers located on the dielectric layer DL.

[0204] As an example, the number of insulating layers below the dielectric layer DLL can be 2n (n is a natural number). Furthermore, the number of insulating layers above the dielectric layer DLL can be 2m-1 (m is a natural number). That is, the number of upper insulating layers relative to the dielectric layer DLL can differ from the number of lower insulating layers, and when either the upper or lower insulating layer is set to an even number, the other can be set to an odd number.

[0205] Furthermore, the number of insulating layers below the dielectric layer DLL can be 2^n (n is a natural number). Additionally, the number of insulating layers above the dielectric layer DLL can be 2^m (m is a natural number). That is, with respect to the dielectric layer DLL, the number of upper insulating layers can be the same as or different from the number of lower insulating layers, and when either the upper or lower insulating layer is set to an even (odd) number, the other can be set to an even (odd) number. Therefore, the number of insulating layers above and above the dielectric layer DLL can be easily set to a desired number relative to the dielectric layer DLL.

[0206] Figures 13a to 13j This is a view used to describe a method for manufacturing a circuit board according to a second embodiment.

[0207] In addition to the content described below, the above-described method for manufacturing a circuit board can be applied to the method for manufacturing a circuit board according to this embodiment.

[0208] Reference Figure 13a A carrier plate 310 can be prepared. The carrier plate 310 can be a CCL (Copper Clad Laminate). Therefore, the carrier plate can include a carrier insulating layer and copper foil layers disposed on two surfaces of the carrier insulating layer. The carrier insulating layer can be formed of PPG. The carrier plate may be omitted in the accompanying drawings.

[0209] Furthermore, additional insulating layers may be provided on either of the two side surfaces or one side surface of the carrier plate 310. The structure of providing each layer on the two side surfaces will be described below.

[0210] Furthermore, dielectric layer DLL', first base layer LL1, and second base layer LL2, which are separated and disposed on both sides or one side of the carrier board 310 for use as capacitor layers as described below, may be provided. Dielectric layer DLL' may correspond to the aforementioned "dielectric layer". First base layer LL1 may correspond to the aforementioned "first layer" or "first via pad". Second base layer LL2 may correspond to the aforementioned "second layer" or "second via pad".

[0211] Furthermore, a separation layer for separation can be disposed on the first substrate layer LL1 and the second substrate layer LL2. The separation layer can be copper foil. Therefore, in the first substrate layer LL1 and the second substrate layer LL2, the bonding force with the dielectric layer can be greater than the bonding force with the separation layer.

[0212] The carrier board, additional insulating layer, release layer, second base layer LL2, dielectric layer DLL', and first base layer LL1 can be stacked and pressed. In this case, pressing can be performed with the outermost release layer removed. Therefore, the additional insulating layer, release layer, second base layer LL2, dielectric layer DLL', and first base layer LL1 can be sequentially stacked on both side surfaces of the carrier board.

[0213] Reference Figure 13b A mask can be formed on the first substrate layer LL1. For example, the mask can be a dry film. Furthermore, exposure and development can be performed on the mask. The exposure and development performed on the mask can form an opening region in the mask on the first substrate layer. In other words, patterning can be performed on the dry film. The mask can be positioned in areas other than where the first via pad is formed. Furthermore, a curing process for the mask can be performed after the opening region is formed by exposure, etc. This mask formation can be applied to the formation of other masks in the same manner. Furthermore, plating can be performed in the opening region of the mask. That is, the plating layer can be formed to correspond to the position of the first via pad. For example, various processes, including chemical plating, can be applied to the plating layer. Next, the mask can be removed. The mask can be removed by various etching methods. Furthermore, etching can be performed on the plating layer and the first substrate layer. Etching can be performed on a partial area or the entire area to correspond to the first via pad. Partial etching can be performed by adding a mask, etc. Furthermore, when etching is performed on the entire area, both the plating layer and the first substrate layer LL1 can be etched. Through etching, the plating layer and the first base layer can be held in the desired positions, corresponding to the mask. That is, the first via pad L1 can be formed.

[0214] Reference Figure 13c Etching can be performed on the dielectric layer DLL. Therefore, a first via TH1 can be formed in the dielectric layer DLL.

[0215] Reference Figure 13d A first insulating layer 111 can be formed. The first insulating layer 111 can be formed on the first via pad and the dielectric layer. In addition, a plating layer for the third electrode portion can be formed on the first insulating layer 111.

[0216] Reference Figure 13e A first via V1 can be formed to house the first via electrode. The first via V1 can be formed within the aforementioned first through-hole TH1. That is, the first via can pass through the first through-hole TH1. Furthermore, a second via can be formed through the first insulating layer 111 to expose the first via pad. The first via V1 can pass through the dielectric layer DLL and the first insulating layer 111. Additionally, the first via can also pass through a plating layer on the first insulating layer 111.

[0217] In this case, the first via V1 and the second via can be formed by various methods. For example, the via can be formed by a laser. For example, the first and second vias can be formed by a carbon dioxide (CO2) laser drill.

[0218] Reference Figure 13f A mask can be formed on the first insulating layer 111 and the plating layer. Similarly, an opening region can be formed by performing exposure and development on the mask. In other words, patterning can be performed on the dry film. The mask can be disposed in a region other than the location where the first electrode portion is formed. Furthermore, a curing process of the mask can be performed after the opening region is formed by exposure or the like. Furthermore, plating can be performed in the opening region of the mask. That is, the plating layer can be formed to correspond to the location of the first electrode portion. For example, various processes including chemical plating can be applied to the plating layer. Next, the mask can be removed, and etching can be performed on the plating layer. Therefore, the plating layer formed on the first insulating layer 111 can be electrically separated corresponding to the location of the first electrode portion. Therefore, the first via electrode 121a, the first interconnect portion 121b, and the first connecting via electrode of the first electrode portion can be formed.

[0219] Reference Figure 13g A third insulating layer 113 may be formed on the first electrode portion. Furthermore, a plating layer EE6 may be formed on the third insulating layer 113. As described above, the third electrode portion may be formed simultaneously with the formation of the second electrode portion in the second insulating layer.

[0220] Reference Figure 13h The second substrate layer LL2 and the layers located on the second substrate layer LL2 can be separated from the carrier plate and the additional insulating layer.

[0221] Reference Figure 13i The second via pad L2 can be formed by performing exposure, development, and stripping on the mask. A via corresponding to the third via electrode can be formed in the third insulating layer 113. The via can be formed by etching or etching. Furthermore, after forming the via, the third electrode portion can be formed by plating or the like. As described above, the third electrode portion can be formed by mask formation, exposure, development, curing, stripping, and plating.

[0222] Reference Figure 13j A protective layer SR can be formed on the second electrode portion and the third electrode portion. In addition, an opening region for electrical connection with the chip or substrate can be formed in the protective layer SR.

[0223] Figure 14 This is a cross-sectional view of the circuit board according to the third embodiment. Figure 15 yes Figure 14 A magnified view of the K5, and Figure 16 yes Figure 14 A magnified view of K6.

[0224] The circuit board 100B according to the third embodiment may include an insulating layer 110, an electrode portion 120, and a capacitor layer CAL. Furthermore, the circuit board 100A may also include a protective layer SR disposed on the electrode portion 120. In addition, the configurations described in the embodiments of the present invention, except as described below, can be applied equivalently.

[0225] According to this embodiment, as described above, the first via electrode 121a can pass through the dielectric layer DLL and the insulating layer (e.g., the first insulating layer) in contact with the dielectric layer DLL. Furthermore, the first via electrode 121a can pass through a first additional insulating layer 111' disposed in a through-hole of the first insulating layer. For example, the first via electrode 121a can pass through the first additional insulating layer 111'. Furthermore, the first additional insulating layer 111' can pass through the first insulating layer 111. Therefore, the first additional insulating layer 111' and the first insulating layer 111 can be sequentially disposed outwards relative to the center of the first via electrode 121a.

[0226] Furthermore, the dielectric layer DLL may include a first via TH1. Furthermore, a first via electrode 121a may be located inside the first via TH1. Furthermore, a first additional insulating layer 111' may also be located inside the first via TH1. Furthermore, the first insulating layer 111 may also be disposed inside the first via TH1. For example, the first via electrode 121a, the first additional insulating layer 111', and the first insulating layer 111 may be accommodated in the first via TH1 and sequentially positioned outwards relative to the center. That is, the first via electrode 121a, the first additional insulating layer 111', and the first insulating layer 111 may overlap with the first via TH1 or the dielectric layer DLL in the horizontal direction. Furthermore, as another example, the first insulating layer 111 may be disposed parallel to the inclined surface of the dielectric layer DLL. Therefore, the first via electrode 121a, the first additional insulating layer 111', and the first insulating layer 111 may be sequentially positioned outwards from the first via electrode 121a.

[0227] However, the first additional insulating layer 111' and the first via electrode 121a may be positioned in the first via TH1 passing through the dielectric layer DLL. Accordingly, the first insulating layer 111 may not overlap with the dielectric layer DLL in the horizontal direction.

[0228] The first additional insulating layer 111' can suppress cracks such as trenches at the boundary between the dielectric layer DLL and the first insulating layer 111, thus improving the reliability of the circuit board.

[0229] Furthermore, an additional insulating layer (a second additional insulating layer) may also be positioned within the second via electrode 122a and the second insulating layer 112. First, the second via electrode 122a may pass through the dielectric layer DLL and an insulating layer (e.g., a first insulating layer) in contact with the dielectric layer DLL. Furthermore, the second via electrode 122a may pass through the second additional insulating layer 112' disposed in a through-hole in the first insulating layer. For example, the second via electrode 122a may pass through the second additional insulating layer 112'. Furthermore, the second additional insulating layer 112' may pass through the second insulating layer 112. Therefore, the second additional insulating layer 112' and the second insulating layer 112 may be sequentially disposed outwards relative to the center of the second via electrode 122a.

[0230] Furthermore, the dielectric layer DLL may include a second via TH2. Furthermore, a second via electrode 122a may be positioned inside the second via TH2. Furthermore, a second additional insulating layer 112' may also be positioned inside the second via TH2. Furthermore, the second insulating layer 112 may also be disposed inside the second via TH2. For example, the second via electrode 122a, the second additional insulating layer 112', and the second insulating layer 112 may be accommodated in the second via TH2 and sequentially positioned outwards relative to the center. That is, the second via electrode 122a, the second additional insulating layer 112', and the second insulating layer 112 may overlap with the second via TH2 or the dielectric layer DLL in the horizontal direction. Furthermore, as another example, the second insulating layer 112 may be disposed parallel to the inclined surface of the dielectric layer DLL. Therefore, the second via electrode 122a, the second additional insulating layer 112', and the second insulating layer 112 may be sequentially positioned in the outward direction of the second via electrode 122a.

[0231] However, the second additional insulating layer 112' and the second via electrode 122a may be positioned in the second via TH2 passing through the dielectric layer DLL. Accordingly, the second insulating layer 112 may not overlap with the dielectric layer DLL in the horizontal direction.

[0232] The second additional insulating layer 112' can suppress cracks such as trenches at the boundary between the dielectric layer DLL and the second insulating layer 112, thus improving the reliability of the circuit board.

[0233] Figure 17 It is a cross-sectional view of the circuit board based on the modified example.

[0234] Reference Figure 17 The circuit board according to the modified example may include an insulating layer 110, an electrode portion 120, and a capacitor layer CAL. Furthermore, the circuit board may also include a protective layer SR disposed on the electrode portion 120. In addition, the configurations described in the embodiments of the present invention, except as described below, can be applied equivalently.

[0235] According to this example, as described above, the first via electrode 121a may pass through the dielectric layer DLL and the insulating layer (e.g., the first insulating layer) in contact with the dielectric layer DLL. A portion of the first via electrode 121a may be coupled to the third via electrode. That is, the first via electrode 121a may pass through both the first insulating layer 111 and the third insulating layer 113. Furthermore, the first via electrode 121a may also pass through the dielectric layer DLL.

[0236] Specifically, the third insulating layer 113 can pass through the first insulating layer 111. Correspondingly, the first insulating layer 111 can pass through the first via TH1 of the dielectric layer DLL. Furthermore, the third insulating layer 113 can pass through the first via TH1 of the dielectric layer DLL. The first via electrode 121a can pass through the third insulating layer 113. Furthermore, the third insulating layer 113 can be disposed in the first via TH1. Therefore, the first via TH1 can overlap with the first insulating layer 111 and the third insulating layer 113 in the horizontal direction. Therefore, the third insulating layer 113 and the first insulating layer 111 can be sequentially disposed outward relative to the center of the first via electrode 121a or the first via TH1. Due to this configuration, even when the via electrode passes through all the sequentially stacked insulating layers, the via electrode can pass through multiple insulating layers while contacting one insulating layer. Therefore, the via electrode can be formed without exposing the interface between the stacked insulating layers. Therefore, reliability problems occurring at the stacked interface can be solved.

[0237] In addition to the first and third insulating layers, via electrodes can also be similarly applied to an additional insulating layer disposed below the third insulating layer. That is, the additional insulating layer disposed below the third insulating layer can be positioned in the first via TH1 of the dielectric layer DLL.

[0238] Furthermore, this configuration of dielectric layer DLL, first insulating layer 111, third insulating layer 113, and via electrodes passing through the first and third insulating layers can be similarly applied to other stacked insulating layers, dielectric layers, and via electrodes on the circuit board.

[0239] For example, when the additional insulating layer is disposed on the second insulating layer 112, the via electrode passing through the additional insulating layer and the second insulating layer 112 (including the dielectric layer) can contact the via of the additional insulating layer. That is, the additional insulating layer can pass through both the second insulating layer 112 and the dielectric layer, and can be specifically positioned in the via of the second insulating layer 112.

[0240] Furthermore, the semiconductor package may include interconnect components. Interconnect components may be referred to as bridging substrates. For example, interconnect components may include redistribution layers. Interconnect components can be used to horizontally electrically connect multiple semiconductor elements to each other. Exemplarily, because the area required for semiconductor elements is typically too large, the interconnect components may include redistribution layers. Because semiconductor packages and semiconductor elements differ significantly in aspects such as the width or area of ​​their circuit patterns, buffering of the circuit patterns used for electrical connections is required. Buffering may mean providing an intermediate dimension between the dimensions, such as the width or area, of the circuit pattern of the semiconductor package and the dimensions, such as the width or area, of the circuit pattern of the semiconductor element, and the redistribution layer may include functionality to perform this buffering.

[0241] In this embodiment, the connecting member can be an organic bridge. For example, the connecting member may include an organic material. For instance, the connecting member may include an organic substrate comprising an organic material instead of a silicon substrate. The connecting member may be embedded in a circuit board.

[0242] For this purpose, the circuit board may include a cavity, and connecting members may be disposed within the cavity of the circuit board. The connecting members can horizontally connect multiple semiconductor elements disposed on the circuit board.

[0243] Furthermore, the circuit board according to the embodiment can be classified into a packaging substrate and an interposer corresponding to the lower substrate, and can be applied therein, based on the function of the circuit board. The packaging substrate is used to mount semiconductor components and / or the interposer. Due to the increase in data, as the area of ​​the circuit board increases or the number of stacked insulating layers increases, the yield of the circuit board may decrease significantly. Therefore, the circuit board can be separated into an interposer and a packaging substrate to improve the yield of circuit boards with a large number of stacked layers, thereby improving the overall yield of the circuit board. In addition, as the density of semiconductor component terminals increases, it may be difficult to realize a pad on the packaging substrate having an area corresponding to the terminal of the semiconductor component. Therefore, a buffer can be implemented between the pad size of the packaging substrate and the fine terminal pattern size of the semiconductor component.

[0244] The aforementioned packaging substrate and interposer can each be classified as core-based substrates and coreless substrates based on the configuration of the insulating layers. In the case of a core-based substrate, the insulating layer may include a core layer, and the core layer may be a layer that includes reinforcing members within the stacked insulating layers. The reinforcing members may be glass fiber. The core layer may be configured to be thicker than other insulating layers, thus providing functionality such as preventing circuit board warping during processing. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, coreless substrates where the circuit board's insulating layer does not include a core layer may be used.

[0245] In various semiconductor packages, the circuit board according to the various embodiments described above can be positioned in a partial area or can correspond to a substrate.

[0246] Furthermore, when a circuit board with the above-described features of this invention is used in IT devices or home appliances such as smartphones, server computers, or TVs, functions such as signal transmission or power supply can be performed stably. For example, when a circuit board with the features of this invention performs a semiconductor packaging function, the circuit board can be used to safely protect the semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current or electrical short circuits between terminals, or electrical open circuits at terminals supplying power or signals to the semiconductor chip. In addition, when the circuit board performs a signal transmission function, noise problems can be solved. Therefore, a circuit board with the above-described features of this invention allows IT devices or home appliances to maintain stable functionality, enabling functional integration or technical interoperability between the entire product and the circuit board to which this invention is applied.

[0247] When a circuit board with the above-described features of this invention is used in a transportation device such as a vehicle, the problem of signal distortion transmitted to the transportation device can be solved, the semiconductor chip controlling the transportation device can be safely protected from external influences, and the problems of leakage current, electrical short circuits between terminals, or electrical open circuits at terminals supplying power or signals to the semiconductor chip can be solved, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which this invention is applied can achieve functional integration or technical interoperability.

[0248] The features, structures, and effects described in the above embodiments are included in at least one embodiment, and are not necessarily limited to one embodiment. Furthermore, the features, structures, and effects illustrated in each embodiment can be combined, modified, and implemented in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, content related to these combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0249] Although the invention has been described with reference to embodiments, these are merely examples and are not intended to limit the embodiments, and those skilled in the art will understand that various modifications and applications not illustrated above are possible without departing from the essential characteristics of these embodiments. For example, each component specifically shown in the embodiments may be implemented with modifications. Furthermore, differences related to modifications and applications should be interpreted as including within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: First insulating layer; A second insulating layer is disposed on the first insulating layer; A dielectric layer is disposed between the first insulating layer and the second insulating layer; as well as The first via electrode passes through the first insulating layer and the dielectric layer. The dielectric layer includes a first via. The first via electrode is disposed inside the first via in the dielectric layer. The side surface of the first via electrode has a first tilt angle, such that the width of the side surface of the first via electrode decreases towards the upper surface of the first insulating layer. The first inner surface of the first via forming the dielectric layer has an inclined surface with a second tilt angle, such that the width of the first inner surface decreases towards the upper surface of the first insulating layer. The first tilt angle and the second tilt angle are different from each other, and The side surface of the first via electrode overlaps with the first inner surface in the horizontal direction.

2. The circuit board according to claim 1, wherein, The side surface of the first via electrode is spaced apart from the first inner surface in the horizontal direction.

3. The circuit board according to claim 1, comprising a second via electrode passing through the second insulating layer and the dielectric layer.

4. The circuit board according to claim 3, wherein, The first via electrode passes through the first through hole, and The dielectric layer includes a second via, and the second via electrode is disposed in the second via.

5. The circuit board according to claim 4, wherein, The side surface of the second via electrode has a third tilt angle, such that the width of the side surface of the second via electrode increases toward the upper surface of the second insulating layer.

6. The circuit board according to claim 5, wherein, The second inner surface of the second via forming the dielectric layer has an inclined surface with a fourth tilt angle, such that the width of the second inner surface increases from the first insulating layer toward the second insulating layer. The fourth tilt angle and the third tilt angle are different from each other, and The side surface of the second via electrode overlaps with the second inner surface in the horizontal direction.

7. The circuit board according to claim 4, wherein, The first via electrode, the second via electrode, the first through hole, and the second through hole overlap each other in the horizontal direction.

8. The circuit board according to claim 4, wherein, A portion of the first insulating layer is disposed between the first through hole and the first via electrode, and A portion of the second insulating layer is disposed between the second through hole and the second via electrode.

9. The circuit board according to claim 3, wherein, A portion of the first via electrode, the dielectric layer, and a portion of the second via electrode overlap each other in the horizontal direction.

10. The circuit board according to claim 4, wherein, The width of the upper surface of the first via electrode is less than the minimum width of the first through hole, and The width of the lower surface of the second via electrode is less than the minimum width of the second through hole.

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