Server mainboard and server

Abstract

The embodiment of the utility model discloses a server mainboard and a server, relates to the technical field of computers, and aims to provide data processing capability. The server main board comprises a main board body; the four processor slots are arranged on the mainboard body; each processor slot is provided with a group of interfaces used for being connected with pins of a processor, each group of interfaces comprises a plurality of interfaces, and at least two groups of interfaces are correspondingly connected through at least one interface; the interfaces correspondingly connected among the different groups of interfaces are interfaces supporting an interconnection protocol among the processors. The method is suitable for occasions with high data processing capability requirements.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a server mainboard and a server. Background Art

[0002] A server is a type of computer that runs faster and has a higher load than an ordinary computer. A server has high-speed CPU computing power, long-term reliable operation, powerful I / O external data throughput capacity, and better scalability.

[0003] The most important component of a server is the server motherboard. The server motherboard is equipped with a processor. Currently, only one processor is installed on the server motherboard, which has limited data processing capabilities and is difficult to meet more application scenarios. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a server motherboard and a server to improve data processing capability.

[0005] In a first aspect, an embodiment of the present invention provides a server motherboard, comprising: a motherboard body; a first processor slot, a second processor slot, a third processor slot and a fourth processor slot arranged on the motherboard body; wherein the first processor slot is used to install a first processor, the second processor slot is used to install a second processor, the third processor slot is used to install a third processor, and the fourth processor slot is used to install a fourth processor; a plurality of memory slots arranged on the motherboard body, the first processor slot, the second processor slot, the third processor slot and the fourth processor slot are respectively connected to different memory slots; wherein the first processor slot has a first group of interfaces for connecting to the pins of the first processor, the second processor slot has a second group of interfaces for connecting to the pins of the second processor, the third processor slot has a third group of interfaces for connecting to the pins of the third processor, and the fourth processor slot has a fourth group of interfaces for connecting to the pins of the fourth processor; among the four groups of interfaces consisting of the first group of interfaces, the second group of interfaces, the third group of interfaces and the fourth group of interfaces, each group of interfaces includes a plurality of interfaces, and at least two groups of interfaces are correspondingly connected through at least one interface; the interfaces correspondingly connected between different groups of interfaces are interfaces supporting an inter-processor interconnection protocol.

[0006] According to an implementable method of a specific embodiment of the present invention, the first interface in the first group of interfaces is correspondingly connected to the first interface in the second group of interfaces, the second interface in the first group of interfaces is correspondingly connected to the first interface in the third group of interfaces, and the third interface in the first group of interfaces is correspondingly connected to the first interface in the fourth group of interfaces; the second interface in the second group of interfaces is correspondingly connected to the second interface in the third group of interfaces, and the third interface in the second group of interfaces is correspondingly connected to the second interface in the fourth group of interfaces; and the third interface in the third group of interfaces is correspondingly connected to the third interface in the fourth group of interfaces.

[0007] According to an implementable manner of a specific embodiment of the present invention, the first interface in the first group of interfaces is connected correspondingly to the first interface in the second group of interfaces; the second interface in the first group of interfaces is connected correspondingly to the second interface in the second group of interfaces; the third interface in the first group of interfaces is connected correspondingly to the first interface in the third group of interfaces; the fourth interface in the first group of interfaces is connected correspondingly to the second interface in the third group of interfaces; the fifth interface in the first group of interfaces is connected correspondingly to the first interface in the fourth group of interfaces; the sixth interface in the first group of interfaces is connected correspondingly to the second interface in the fourth group of interfaces; the third interface in the second group of interfaces is connected correspondingly to the third interface in the third group of interfaces; the fourth interface in the second group of interfaces is connected correspondingly to the fourth interface in the third group of interfaces; the fifth interface in the second group of interfaces is connected correspondingly to the third interface in the fourth group of interfaces; the sixth interface in the second group of interfaces is connected correspondingly to the fourth interface in the fourth group of interfaces; the fifth interface in the third group of interfaces is connected correspondingly to the fifth interface in the fourth group of interfaces; the sixth interface in the third group of interfaces is connected correspondingly to the sixth interface in the fourth group of interfaces.

[0008] According to an implementable method of a specific embodiment of the present invention, there are eight groups of memory slots arranged on the main board body, each group of memory slots includes 6 memory slots; the first processor slot, the second processor slot, the third processor slot and the fourth processor slot are each connected to two groups of memory slots.

[0009] According to an implementable manner of a specific embodiment of the present invention, between each processor slot and the two connected groups of memory slots, each memory channel is connected to one dual in-line storage module slot; or, between each processor slot and the two connected groups of memory slots, four memory channels are each connected to two dual in-line storage module slots, and the other four memory channels are each connected to one dual in-line storage module slot.

[0010] According to an implementable manner of a specific embodiment of the present invention, the first processor socket and the second processor socket are arranged at intervals along a first direction of the main board body; the third processor socket and the fourth processor socket are also arranged at intervals along the first direction of the main board body; and the fourth processor socket and the first processor socket are arranged at intervals along a second direction of the main board body, and the third processor socket and the second processor socket are also arranged at intervals along the second direction of the main board body;

[0011] The first group of memory slots and the second group of memory slots are arranged in parallel on two opposite sides of the first processor slot; wherein the second directions of the first group of memory slots and the second group of memory slots are consistent with the second direction of the main board body; the third group of memory slots and the fourth group of memory slots are arranged in parallel on two opposite sides of the second processor slot; the third group of memory slots and the second group of memory slots are arranged in parallel and adjacent to each other; the fifth group of memory slots and the sixth group of memory slots are arranged in parallel on two opposite sides of the third processor slot; wherein the second directions of the fifth group of memory slots and the sixth group of memory slots are also consistent with the second direction of the main board body; the seventh group of memory slots and the eighth group of memory slots are arranged in parallel on two opposite sides of the fourth processor slot; the seventh group of memory slots and the sixth group of memory slots are arranged in parallel and adjacent to each other.

[0012] According to an implementable manner of a specific embodiment of the present invention, the server motherboard further includes: a cable connector arranged on the motherboard body, the cable connector correspondingly connected to an interface of at least one processor slot; the cable connector includes: an internal cable interconnection system MCIO connector and / or a slimline Slimline connector.

[0013] According to an implementable manner of a specific embodiment of the present invention, the cable connector includes a front cable connector arranged at the front end of the mainboard body, and / or a rear cable connector arranged at the rear end of the mainboard body.

[0014] According to an implementable manner of a specific embodiment of the present invention, the server motherboard further includes: at least one PCIe 5.0 slot arranged on the motherboard body, and the at least one PCIe 5.0 slot is correspondingly connected to an interface of at least one processor slot.

[0015] According to an implementable manner of a specific embodiment of the present invention, the server motherboard further includes: an Open Compute Project Specification OCP 3.0 connector disposed at the rear end of the motherboard body and an internal cable interconnection system MCIO connector connected to the OCP3.0 connector.

[0016] According to an implementable method of a specific embodiment of the present invention, the server motherboard further includes: a baseboard management controller arranged on the motherboard body, a graphics card is integrated in the baseboard management controller, and a PCIe signal of the baseboard management controller is connected to an interface of the first processor slot.

[0017] In a second aspect, an embodiment of the present invention further provides a server, including a housing, in which a server mainboard as described in any of the above embodiments is arranged. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 This is a schematic structural diagram of a first embodiment of a server motherboard of the present invention;

[0020] Figure 2 for Figure 1 Schematic diagram of the interconnection structure between the four processor sockets;

[0021] Figure 3a A schematic diagram of a connection structure between a CPU installed in a first processor slot and a memory slot using a first 1DPC mode;

[0022] Figure 3b A schematic diagram of a connection structure between a CPU installed in a first processor slot and a memory slot using a second 1DPC mode;

[0023] Figure 4a A schematic diagram of a connection structure between a CPU installed in a first processor slot and a memory slot using a first 1DPC and 2DPC combination mode;

[0024] Figure 4b A schematic diagram of a connection structure between a CPU installed in a first processor slot and a memory slot using a second 1DPC and 2DPC combination mode;

[0025] Figure 5 The figure is a schematic diagram of the interconnection structure between four processor slots in the second embodiment of the server motherboard of the present invention. DETAILED DESCRIPTION

[0026] The embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In order to improve the data processing capability of a server motherboard, some embodiments of the present invention disclose a server motherboard, comprising: a motherboard body; a first processor slot, a second processor slot, a third processor slot and a fourth processor slot arranged on the motherboard body; wherein the first processor slot is used to install a first processor, the second processor slot is used to install a second processor, the third processor slot is used to install a third processor, and the fourth processor slot is used to install a fourth processor; a plurality of memory slots arranged on the motherboard body, the first processor slot, the second processor slot, the third processor slot and the fourth processor slot are respectively connected to different memory slots; wherein the first processor slot has a first group of interfaces for connecting to pins of the first processor, the second processor slot has a second group of interfaces for connecting to pins of the second processor, the third processor slot has a third group of interfaces for connecting to pins of the third processor, and the fourth processor slot has a fourth group of interfaces for connecting to pins of the fourth processor; among the four groups of interfaces consisting of the first group of interfaces, the second group of interfaces, the third group of interfaces and the fourth group of interfaces, each group of interfaces includes a plurality of interfaces, and at least two groups of interfaces are correspondingly connected through at least one interface; the interfaces correspondingly connected between different groups of interfaces are interfaces supporting an inter-processor interconnection protocol.

[0028] In some embodiments of the present invention, a server motherboard is disclosed, which has four processor slots, and a processor can be placed in each processor slot, so that the entire service motherboard can simultaneously place four processors so that the four processors can work simultaneously, thereby improving data processing capabilities; further, at least two processor slots are interconnected so that the processors placed in the at least two processor slots can work in coordination, which can further improve the data processing capability to adapt to more application scenarios.

[0029] The embodiments of the present invention and examples thereof are described in detail below with reference to the accompanying drawings.

[0030] First Implementation Method

[0031] Figure 1 FIG. 1 is a structural block diagram of a first embodiment of a server motherboard of the present invention. Figure 1As shown, the server motherboard of this embodiment includes: a motherboard body 1, a processor slot 2 and a memory slot 3 arranged on the motherboard body 1.

[0032] There are four processor slots 2, namely, the first processor slot 21, the second processor slot 22, the third processor slot 23 and the fourth processor slot 24; wherein, the first processor slot 21 is used to install the first processor CPU1, the second processor slot 22 is used to install the second processor CPU2, the third processor slot 23 is used to install the third processor CPU3, and the fourth processor slot 24 is used to install the fourth processor CPU4. The processors installed in the four processor slots can be processors of the same series, such as processors of the Haiguang 7400 series, etc. In order to provide the best coordination performance between different processors, the processors installed in the four processor slots are preferably processors of the same model.

[0033] Figure 2 for Figure 1 Schematic diagram of the interconnection structure between the four processor sockets, see Figure 2 , the first processor socket 21 has a first group of interfaces 210 for connecting to the pins of the first processor CPU1. The first group of interfaces 210 may include: a first interface 2101 (e.g., the G0 interface of the first processor socket), a second interface 2102 (e.g., the G2 interface of the first processor socket), a third interface 2103 (e.g., the G3 interface of the first processor socket), a fourth interface 2104 (e.g., the G1 interface of the first processor socket), a fifth interface 2105 (e.g., the G4 interface of the first processor socket), and a sixth interface 2106 (e.g., the G5 interface of the first processor socket). In addition to being connected to the corresponding pins of the first processor CPU1, the six interfaces also support an inter-processor interconnection protocol, which can be used for interconnection between different processor sockets (i.e., different processors). The inter-processor interconnection protocol may be, for example, the Hygon chip interconnection bus xHCL (External Hygon Chip Link) protocol, the Hygon external storage interface (eXternal Hygon memory interface) protocol, etc.

[0034] The second processor socket 22 has a second group of interfaces 220 for connecting to the pins of the second processor CPU2. The second group of interfaces 220 may include: a first interface 2201 (e.g., a G2 interface of the second processor socket), a second interface 2202 (e.g., a G0 interface of the second processor socket), a third interface 2203 (e.g., a G5 interface of the second processor socket), a fourth interface 2204 (e.g., a G4 interface of the second processor socket), a fifth interface 2205 (e.g., a G1 interface of the second processor socket), and a sixth interface 2206 (e.g., a G3 interface of the second processor socket). In addition to being connected to the corresponding pins of the second processor CPU2, the six interfaces also support an inter-processor interconnection protocol and can be used for interconnection between different processor sockets (i.e., different processors).

[0035] The third processor socket 23 has a third group of interfaces 230 for connecting to the pins of the third processor CPU3. The third group of interfaces 230 may include: a first interface 2301 (e.g., a G1 interface of the third processor socket), a second interface 2302 (e.g., a G3 interface of the third processor socket), a third interface 2303 (e.g., a G4 interface of the third processor socket), a fourth interface 2304 (e.g., a G5 interface of the third processor socket), a fifth interface 2305 (e.g., a G2 interface of the third processor socket), and a sixth interface 2306 (e.g., a G0 interface of the third processor socket). In addition to being connected to the corresponding pins of the third processor CPU3, the six interfaces also support an inter-processor interconnection protocol and can be used for interconnection between different processor sockets (i.e., different processors).

[0036] The fourth processor socket 24 has a fourth group of interfaces 240 for connecting to the pins of the fourth processor. The fourth group of interfaces 240 may include: a first interface 2401 (e.g., a G5 interface of the fourth processor socket), a second interface 2402 (e.g., a G4 interface of the fourth processor socket), a third interface 2403 (e.g., a G3 interface of the fourth processor socket), a fourth interface 2404 (e.g., a G1 interface of the fourth processor socket), a fifth interface 2405 (e.g., a G0 interface of the fourth processor socket), and a sixth interface 2406 (e.g., a G2 interface of the fourth processor socket). In addition to being connected to the corresponding pins of the fourth processor CPU4, the six interfaces also support an inter-processor interconnection protocol and can be used for interconnection between different processor sockets (i.e., different processors).

[0037] The different processor slots on the main board body 1 are interconnected by dual interfaces. Dual interface interconnection means that in two interconnected processor slots, one processor slot is connected to the two interfaces of the other processor slot in a one-to-one correspondence through two interfaces. In other words, in two interconnected processor slots, each processor slot is interconnected through two interfaces, which can provide bandwidth for two interconnected processors and further improve the data processing speed. For example, a single interface used for interconnection can transmit 16 signals in parallel. When dual interface interconnection is used, 32 signals can be transmitted in parallel between two interconnected processors.

[0038] See also Figure 2 In the server motherboard of this embodiment, the dual-interface interconnection between different processor slots on the motherboard body 1 can be implemented in the following exemplary manner:

[0039] The first interface 2101 in the first interface group 210 and the first interface 2201 in the second interface group 220 are connected correspondingly via a connection line L12A arranged on the mainboard body 1;

[0040] The second interface 2102 in the first group of interfaces 210 and the second interface 2202 in the second group of interfaces 220 are connected correspondingly via a connection line L12B arranged on the mainboard body 1;

[0041] The third interface 2103 in the first interface group 210 and the first interface 2301 in the third interface group 230 are connected correspondingly via a connection line L13A arranged on the mainboard body 1;

[0042] The fourth interface 2104 in the first interface group 210 and the second interface 2302 in the third interface group 230 are connected correspondingly via a connection line L13B arranged on the mainboard body 1;

[0043] The fifth interface 2105 in the first interface group 210 and the first interface 2401 in the fourth interface group 240 are connected correspondingly via a connection line L14A arranged on the mainboard body 1;

[0044] The sixth interface 2106 in the first interface group 210 and the second interface 2402 in the fourth interface group 240 are connected correspondingly via a connection line L14B arranged on the mainboard body 1;

[0045] The third interface 2203 in the second interface group 220 and the third interface 2303 in the third interface group 230 are connected correspondingly via a connection line L23A arranged on the mainboard body 1;

[0046] The fourth interface 2204 in the second group of interfaces 220 and the fourth interface 2304 in the third group of interfaces 230 are connected correspondingly via a connection line L23B arranged on the mainboard body 1;

[0047] The fifth interface 2205 in the second interface group 220 and the third interface 2403 in the fourth interface group 240 are connected correspondingly via a connection line L24A arranged on the mainboard body 1;

[0048] The sixth interface 2206 in the second interface group 220 and the fourth interface 2404 in the fourth interface group 240 are connected correspondingly via a connection line L24B arranged on the mainboard body 1;

[0049] The fifth interface 2305 in the third interface group 230 and the fifth interface 2405 in the fourth interface group 240 are connected correspondingly via a connection line L34A arranged on the mainboard body 1;

[0050] The sixth interface 2306 in the third interface group 230 and the sixth interface 2406 in the fourth interface group 240 are connected correspondingly via a connection line L34B arranged on the mainboard body 1 .

[0051] It should be understood that each group of interfaces may also include one or more other interfaces that support the inter-processor interconnection protocol. Figure 2 In addition to the interconnection methods illustrated, the interconnection can also be implemented through or in conjunction with other interfaces that support the inter-processor interconnection protocol.

[0052] Figure 2 The G0 interface, G1 interface, G2 interface, G3 interface, G4 interface and G5 interface of each processor slot shown in the figure, in addition to supporting the inter-processor interconnection protocol, can also support the PCIe (Peripheral Component Interconnect Express) protocol and the SATA (Serial Advanced Technology Attachment) protocol.

[0053] See also Figure 2 In addition to the interface supporting the inter-processor interconnection protocol, each processor slot also has an interface supporting the PCIe protocol and the SATA protocol, such as the P6 interface and the P7 interface.

[0054] See also Figure 1 The memory slots 3 provided on the mainboard body 1 can be divided into eight groups, namely, the first group of memory slots 31, the second group of memory slots 32, the third group of memory slots 33, the fourth group of memory slots 34, the fifth group of memory slots 35, the sixth group of memory slots 36, the seventh group of memory slots 37, and the eighth group of memory slots 38. In the above eight groups of memory slots, each group of memory slots includes 6 memory slots, so that the mainboard body 1 can be provided with 48 memory slots.

[0055] The first processor socket 21 , the second processor socket 22 , the third processor socket 23 and the fourth processor socket 24 are respectively connected to two groups of memory sockets.

[0056] See also Figure 1 As shown, the first processor slot 21 is respectively connected to the first group of memory slots 31 and the second group of memory slots 32, the second processor slot 22 is respectively connected to the third group of memory slots 33 and the fourth group of memory slots 34, the third processor slot 23 is respectively connected to the fifth group of memory slots 35 and the sixth group of memory slots 36, and the fourth processor slot 24 is respectively connected to the seventh group of memory slots 37 and the eighth group of memory slots 38.

[0057] The processors installed in the first processor slot 21, the second processor slot 22, the third processor slot 23, and the fourth processor slot 24 may be processors supporting 12 memory channels respectively. The processor supporting 12 memory channels has 12 memory controllers, and each memory controller can control the read and write operations of the physical memory inserted in one or two memory slots.

[0058] In some embodiments, each processor socket may have 12 memory interfaces (also referred to as memory channel interfaces), each memory interface corresponds to a memory channel, the 12 memory interfaces are connected one-to-one with the 12 memory sockets through wiring on the motherboard body, and the 12 memory interfaces can be connected correspondingly to the interfaces of the 12 memory controllers in the processor installed in the processor socket.

[0059] In some embodiments, each processor slot and the two connected memory slots can be connected in 1DPC (1DIMMPerChannel, 1 DIMM slot per channel) mode, that is, each memory interface is connected to a dual inline memory module slot. This is conducive to improving the read and write speed of the CPU installed in each processor slot and the physical memory inserted in the memory slot. Among them, DIMM stands for Dual-Inline-Memory-Modules, and its Chinese name is Dual-Inline Memory Module.

[0060] See also Figure 3a and Figure 3b The first processor slot 21 (that is, the first processor CPU1 installed in the first processor slot 21) and the first group of memory slots 31 and the second group of memory slots 32 are connected in 1DPC mode, which is beneficial to improving the reading and writing speed of the first processor CPU1 on the physical memory inserted in the first group of memory slots 31 and the second group of memory slots 32.

[0061] See also Figure 3aIn some examples, the first processor CPU1 installed in the first processor socket 21 is connected to the first group of memory sockets 31 and the second group of memory sockets 32 using the first 1DPC mode. Specifically, the 12 memory sockets connected to the first processor socket 21, namely, memory sockets A0 to L0, are connected to the first ports (such as port 0) of the 12 memory controllers in the first processor CPU1 installed in the first processor socket 21 in a one-to-one correspondence.

[0062] See also Figure 3b In other examples, the first processor CPU1 installed in the first processor socket 21 and the first group of memory sockets 31 and the second group of memory sockets 32 may be connected in a second 1DPC mode. Specifically, the 12 memory sockets connected to the first processor socket 21, namely the memory sockets A1 to L1, are connected one-to-one with the second ports (such as port 1) of the 12 memory controllers in the first processor CPU1 installed in the first processor socket 21.

[0063] The second processor socket 22 (ie, the first processor CPU2 installed in the second processor socket 22) and the third group of memory sockets 33 and the fourth group of memory sockets 34 may also be connected in the first 1DPC mode or the second 1DPC mode.

[0064] The third processor slot 23 (ie the third processor CPU3 installed in the third processor slot 23) and the fifth group of memory slots 35 and the sixth group of memory slots 36 may also be connected using the first 1DPC mode or the second 1DPC mode.

[0065] The fourth processor slot 24 (ie the fourth processor CPU4 installed in the fourth processor slot 24) and the seventh and eighth memory slots 37 and 38 can also be connected using the first 1DPC mode or the second 1DPC mode.

[0066] In other embodiments, at least one processor slot may have 8 memory interfaces, each memory interface corresponds to a memory channel, the 8 memory interfaces are connected to the 12 memory slots through wiring on the motherboard body, and the 8 memory interfaces can be connected to the interfaces of 8 memory controllers in the processor installed in the processor slot.

[0067] Specifically, in some embodiments, each processor slot and the two connected groups of memory slots can be connected in a mode combining 1DPC and 2DPC (2DIMM Per Channel, 2 DIMM slots per channel), that is, the four memory interfaces in each processor slot are each connected to 2 DIMM slots, and the other four memory interfaces are each connected to 1 DIMM slot, so that each processor slot is compatible with processors supporting 12 memory channels and processors supporting 8 memory channels. There are 8 memory controllers in the processor supporting 8 memory channels, and each memory controller can control the read and write operations of the physical memory inserted in 1 or 2 memory slots.

[0068] See also Figure 4a and Figure 4b The first processor socket 21 (ie, the first processor CPU1 installed in the first processor socket 21) and the first group of memory sockets 31 and the second group of memory sockets 32 are connected in a mode combining 1DPC and 2DPC.

[0069] See also Figure 4a In some examples, the first processor CPU1 installed in the first processor socket 21 is connected to the first group of memory sockets 31 and the second group of memory sockets 32 using a first mode combining 1DPC and 2DPC.

[0070] Specifically, among the 12 memory slots connected to the first processor slot 21, the memory slots corresponding to channel A, channel B, channel G, and channel H are connected using a 2DPC mode; the memory slots corresponding to channel E, channel F, channel K, and channel L are connected using a 1DPC mode, and can be connected one-to-one with the second ports (such as port 1) of the four memory controllers in the first processor CPU1 installed in the first processor slot 21.

[0071] See also Figure 4b In some examples, the first processor CPU1 installed in the first processor socket 21 and the first group of memory sockets 31 and the second group of memory sockets 32 can be connected using a second mode combining 1DPC and 2DPC.

[0072] Specifically, among the 12 memory slots connected to the first processor slot 21, the memory slots corresponding to channel A, channel B, channel G, and channel H are connected using a 2DPC mode; the memory slots corresponding to channel E, channel F, channel K, and channel L are connected using a 1DPC mode, and can be connected one-to-one with the first ports (such as port 0) of the four memory controllers in the first processor CPU1 installed in the first processor slot 21.

[0073] The second processor slot 22 (that is, the first processor CPU2 installed in the second processor slot 22) and the third group of memory slots 33 and the fourth group of memory slots 34 can also be connected using the above-mentioned first mode of combining 1DPC and 2DPC or the second mode of combining 1DPC and 2DPC.

[0074] The third processor slot 23 (that is, the third processor CPU3 installed in the third processor slot 23) and the fifth group of memory slots 35 and the sixth group of memory slots 36 can also be connected using the above-mentioned first mode of combining 1DPC and 2DPC or the second mode of combining 1DPC and 2DPC.

[0075] The fourth processor slot 24 (that is, the fourth processor CPU4 installed in the fourth processor slot 24) and the seventh group of memory slots 37 and the eighth group of memory slots 38 can also be connected using the above-mentioned first mode of combining 1DPC and 2DPC or the second mode of combining 1DPC and 2DPC.

[0076] In order to realize the reasonable arrangement of each processor slot and memory slot on the mainboard body 1, see Figure 1 As shown, in some embodiments, the first processor slot 21 and the second processor slot 22 are arranged at intervals along the first direction of the main board body 1; the third processor slot 23 and the fourth processor slot 24 are also arranged at intervals along the first direction of the main board body 1; and the fourth processor slot 24 and the first processor slot 21 are arranged parallel and at intervals along the second direction of the main board body 1, and the third processor slot 23 and the second processor slot 22 are also arranged parallel and at intervals along the second direction of the main board body 1; the first group of memory slots 31 and the second group of memory slots 32 are arranged in parallel on opposite sides of the first processor slot; wherein the second direction of the first group of memory slots 31 and the second group of memory slots 32 The second direction of the motherboard body 1 is consistent with the second direction of the motherboard body 1; the third group of memory slots 33 and the fourth group of memory slots 34 are arranged in parallel on the opposite sides of the second processor slot 22; the third group of memory slots 33 and the second group of memory slots 32 are arranged in parallel and adjacent to each other; the fifth group of memory slots 35 and the sixth group of memory slots 36 are arranged in parallel on the opposite sides of the third processor slot 23; wherein the second direction of the fifth group of memory slots 35 and the sixth group of memory slots 36 is also consistent with the second direction of the motherboard body 1; the seventh group of memory slots 37 and the eighth group of memory slots 38 are arranged in parallel on the opposite sides of the fourth processor slot 24; the seventh group of memory slots 37 and the sixth group of memory slots 36 are arranged in parallel and adjacent to each other. The second direction of the motherboard body is a direction perpendicular to the first direction.

[0077] In order to enable the server motherboard of this embodiment to support the insertion of PCIe boards to expand the functions of the server motherboard, see Figure 1In some embodiments, a PCIe slot 4 may be provided on the mainboard body 1, and the PCIe slot 4 is connected to the interface of the processor slot. The PCIe slot may be provided at the rear end of the mainboard body 1. The rear end of the mainboard body refers to the end at the rear of the chassis when the server mainboard is installed in the chassis of the server, and correspondingly, the front end of the mainboard body refers to the end at the front of the chassis when the server mainboard is installed in the chassis of the server. The front of the chassis is usually provided with a power switch, and the rear of the chassis is used to plug in power, network and other cables.

[0078] The number of the PCIe slots 4 can be multiple. Figure 1 6 PCIe slots are exemplarily shown, namely PCIe slot 41, PCIe slot 42, PCIe slot 43, PCIe slot 44, PCIe slot 45 and PCIe slot 46. Among them, PCIe slot 41 and PCIe slot 46 are PCIe 5.0×16 slots, and PCIe slot 42 to PCIe slot 45 are PCIe 5.0×8 slots.

[0079] In some examples, Figure 1 The PCIe slot 41 to the PCIe slot 46 shown are connected to the interfaces of the processor slots in the following manner: PCIe slot 41 is connected to the P6 [15:0] interface of the second processor slot 22, PCIe slot 42 is connected to the P7 [15:8] interface of the second processor slot 22, and PCIe slot 43 is connected to the P7 [7:0] interface of the second processor slot 22; PCIe slot 44 is connected to the P6 [15:8] interface of the first processor slot 21, PCIe slot 45 is connected to the P6 [7:0] interface of the first processor slot 21, and PCIe slot 46 is connected to the P7 [15:0] interface of the first processor slot 21.

[0080] In order to enable the server motherboard of this embodiment to support cross-board connection of PCIe 5.0 signals through a connecting cable, in some embodiments, an internal cable interconnection system MCIO (Mini Cool Edge IO) connector corresponding to the interface of the processor slot may be provided on the motherboard body 1, and the connector may support cross-board connection of PCIe 5.0 signals through a connecting cable. The MCIO connector is a thin-line cable that can support PCIe5.0 and SAS (Serial Attached SCSI) / SATA standard signals.

[0081] The number of MCIO connectors can be multiple. Figure 1 Schematically, 10 MCIO×8 connectors, namely, MCIO connector 50 to MCIO connector 59 are shown.

[0082] In some examples, Figure 1The MCIO connectors 50 to 59 shown are connected to the processor slot in the following manner:

[0083] The MCIO connector 50 and the MCIO connector 51 are respectively connected to the P7 [7:0] interface and the P7 [15:8] interface of the third processor socket 23;

[0084] The MCIO connector 52 and the MCIO connector 53 are respectively connected to the P6 [7:0] interface and the P6 [15:8] interface of the third processor socket 23;

[0085] The MCIO connector 54 and the MCIO connector 55 are respectively connected to the P7 [7:0] interface and the P7 [15:8] interface of the fourth processor socket 24;

[0086] The MCIO connector 56 and the MCIO connector 57 are respectively connected to the P6 [7:0] interface and the P6 [15:8] interface of the fourth processor socket 24;

[0087] The MCIO connector 58 and the MCIO connector 59 are connected to the Open Compute Project 3.0 (OCP 3.0) connector 6 .

[0088] Among them, the OCP 3.0 connector and the MCIO connector 58 and the MCIO connector 59 are arranged at the rear end of the main board body, and can be connected to the positions of the MCIO connectors 50 to MCIO connectors 57 through cables to realize PCIe 5.0 signal connection with the CPU3 installed in the third processor slot 23 or with the CPU4 installed in the fourth processor slot 24. For example, connecting to the MCIO connectors 50 to MCIO connectors 53 can realize PCIe 5.0 signal connection with the CPU3 installed in the third processor slot 23.

[0089] In some embodiments, a Slimline connector corresponding to the interface of the processor slot may also be provided on the mainboard body 1. The Slimline connector is a multiplexed signal connector, and the pins of the CPU installed in the processor slot connected to it can support both the PCIe protocol and the SATA protocol. The Slimline connector can be connected to a standard SATA interface through an adapter cable, and can provide an interface for the mainboard system to start the operating system and store data.

[0090] There can be multiple Slimline connectors. Figure 1 8 Slimline×4 connectors, namely Slimline connector 71 to Slimline connector 78, are exemplarily shown.

[0091] In some examples, Figure 1 The Slimline connectors 71 to 78 shown are connected to the processor socket in the following manner:

[0092] The Slimline connector 71 is connected to the P8 [7:4] interface of the third processor slot 23, and the Slimline connector 74 is connected to the P8 [3:0] interface of the third processor slot 23;

[0093] The Slimline connector 72 is connected to the P8 [7:4] interface of the fourth processor slot 24 , and the Slimline connector 73 is connected to the P8 [3:0] interface of the fourth processor slot 24 ;

[0094] Slimline connector 75 is connected to the P8[3:0] interface of the second processor socket 22, and Slimline connector 77 is connected to the P8[7:4] interface of the second processor socket 22;

[0095] The Slimline connector 76 is connected to the P8[3:0] interface of the first processor socket 21 , and the Slimline connector 78 is connected to the P8[7:4] interface of the first processor socket 21 .

[0096] The MCIO connector and the Slimline connector may be collectively referred to as cable connectors. The motherboard may be provided with only the MCIO connector, only the Slimline connector, or both the MCIO connector and the Slimline connector. Figure 1 FIG. 4 exemplarily shows a situation where an MCIO connector and a Slimline connector are provided on the mainboard body at the same time.

[0097] The cable connector includes a front cable connector disposed at the front end of the mainboard body. Figure 1 MCIO connectors 50 to 57 are front MCIO connectors, which can be connected to front PCIe devices via cables, such as NVMe (Non-Volatile Memory Express) backplanes, PCIe Slots, other PCIe adapter boards, etc. Slimline connectors 71 and 72 are front Slimline connectors, which can be connected to NVMe or SATA devices via cables.

[0098] The cable connector may also include a rear cable connector disposed at the rear end of the mainboard body. Figure 1 Slimline connector 77 and Slimline connector 78 are rear Slimline connectors.

[0099] In the server motherboard of this embodiment, the PCIe 5.0 signal can be connected to the front MCIO connector, such as MCIO connector 50 to MCIO connector 57, or to the rear PCIe 5.0 Slot, such as PCIe slot 41 to PCIe slot 44. The PCIe slot 41 to PCIe slot 44 are connected to the interface of the corresponding processor slot.

[0100] The PCIe 4.0 signal may be connected to a front Slimline connector, such as Slimline connector 71 and Slimline connector 72 , or may be connected to a rear Slimline connector, such as Slimline connector 77 and Slimline connector 78 .

[0101] In some embodiments, the server motherboard further includes: a baseboard management controller BMC (Baseboard Management Controller) chip 8 disposed on the motherboard body 1. The BMC chip 8 may be integrated with a graphics card, so that a PCIe signal of the BMC chip 8 may be connected to an interface of the first processor slot 21, such as the P8[8] interface of the first processor slot 21, to achieve system VGA (Video Graphics Array) display requirements.

[0102] In some embodiments, the server motherboard further includes: a CPLD (Complex Programming logic device) chip 9 disposed on the motherboard body 1, which is a programming logic device that can be used to control the power-on and power-off timing of the motherboard and perform other logic controls on the motherboard.

[0103] In this embodiment, the first processor slot to the fourth processor slot, the four processor slots are interconnected in pairs, providing a hardware foundation for achieving a higher data processing capability. The embodiment of the present invention is not limited to this, in other embodiments, the four processor slots may only interconnect part (such as two or three) of the processors, or the four processor slots may be interconnected in other ways such as series or parallel connection.

[0104] Second implementation method

[0105] The server motherboard of this embodiment is basically the same as the server motherboard of the first embodiment, except that in the first embodiment, different processor slots on the motherboard body 1 are interconnected by dual interfaces. In this embodiment, different processor slots on the motherboard body 1 are interconnected by a single interface. Single interface interconnection means that in two interconnected processor slots, one processor slot is connected to an interface of another processor slot through only one interface. That is to say, in two interconnected processor slots, each processor slot is interconnected through only one interface.

[0106] See also Figure 5 In some embodiments, the single interface interconnection between different processor sockets on the mainboard body 1 can be implemented as follows:

[0107] The first interface 2101 in the first interface group 210 and the first interface 2201 in the second interface group 220 are connected correspondingly via a connection line L12 arranged on the mainboard body 1;

[0108] The second interface 2102 in the first interface group and the first interface 2301 in the third interface group are connected correspondingly via a connection line L13 arranged on the mainboard body 1;

[0109] The third interface 2103 in the first interface group and the first interface 2401 in the fourth interface group are connected correspondingly via a connection line L14 arranged on the mainboard body 1;

[0110] The second interface 2202 in the second interface group and the second interface 2302 in the third interface group are connected correspondingly via a connection line L23 arranged on the mainboard body 1;

[0111] The third interface 2203 in the second interface group and the second interface 2402 in the fourth interface group are connected correspondingly via a connection line L24 arranged on the mainboard body 1;

[0112] The third interface 2303 in the third group of interfaces and the third interface 2403 in the fourth group of interfaces are correspondingly connected via a connection line L34 arranged on the mainboard body 1 .

[0113] See also Figure 5The first group of interfaces 210 of the first processor slot 21 may also include a G1 interface, a G3 interface, and a G5 interface that support an inter-processor interconnection protocol; the second group of interfaces 220 of the second processor slot 22 may also include a G1 interface, a G3 interface, and a G4 interface that support an inter-processor interconnection protocol; the third group of interfaces 230 of the third processor slot 23 may also include a G1 interface, a G3 interface, and a G5 interface that support an inter-processor interconnection protocol; the third group of interfaces 240 of the fourth processor slot 22 may also include a G1 interface, a G3 interface, and a G4 interface that support an inter-processor interconnection protocol.

[0114] Single interface interconnection between different processor sockets on the motherboard body 1, except Figure 2 In addition to the interconnection methods illustrated, the interconnection can also be implemented through or in conjunction with other interfaces that support the inter-processor interconnection protocol.

[0115] Figure 5 The G1 interface, G2 interface, G3 interface, G4 interface and G5 interface of each processor slot shown in the figure, in addition to supporting the inter-processor interconnection protocol, can also support the PCIe (Peripheral Component Interconnect Express) protocol and the SATA (Serial Advanced Technology Attachment) protocol.

[0116] There are no other G ports participating in the interconnection in each processor slot (i.e., ports that support the inter-processor interconnection protocol). These G ports can transmit 16 signals in parallel (also called G x16 ports). Each G x16 port can be used to connect 2 MCIOx8 connectors, or to connect PCIE slots or onboard PCIE devices to expand more PCIE devices.

[0117] See also Figure 5 In addition to the interface supporting the inter-processor interconnection protocol, each processor slot also has an interface supporting the PCIe protocol and the SATA protocol, such as the P6 interface and the P7 interface.

[0118] An embodiment of the present invention further provides a server, which includes a housing, in which a server mainboard as described in any of the aforementioned embodiments is arranged to provide service data processing capabilities and add more application scenarios.

[0119] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0120] The various embodiments in this specification are described in a related manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0121] The drawings of the embodiments of the present application only relate to the structures related to the embodiments of the present application, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other to obtain new embodiments.

[0122] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A server motherboard, characterized in that: include: Main board body; A first processor slot, a second processor slot, a third processor slot and a fourth processor slot are arranged on the mainboard body; wherein the first processor slot is used to install the first processor, the second processor slot is used to install the second processor, the third processor slot is used to install the third processor, and the fourth processor slot is used to install the fourth processor; A plurality of memory slots are arranged on the mainboard body, wherein the first processor slot, the second processor slot, the third processor slot and the fourth processor slot are respectively connected to different memory slots; in, The first processor socket has a first group of interfaces for connecting to the pins of the first processor, the second processor socket has a second group of interfaces for connecting to the pins of the second processor, the third processor socket has a third group of interfaces for connecting to the pins of the third processor, and the fourth processor socket has a fourth group of interfaces for connecting to the pins of the fourth processor; Among the four groups of interfaces consisting of the first group of interfaces, the second group of interfaces, the third group of interfaces and the fourth group of interfaces, each group of interfaces includes multiple interfaces, and at least two groups of interfaces are correspondingly connected through at least one interface; the interfaces correspondingly connected between different groups of interfaces are interfaces that support the inter-processor interconnection protocol.

2. The server motherboard according to claim 1, characterized in that: The first interface in the first group of interfaces is connected to the first interface in the second group of interfaces, the second interface in the first group of interfaces is connected to the first interface in the third group of interfaces, and the third interface in the first group of interfaces is connected to the first interface in the fourth group of interfaces; The second interface in the second group of interfaces is connected to the second interface in the third group of interfaces correspondingly, and the third interface in the second group of interfaces is connected to the second interface in the fourth group of interfaces correspondingly; The third interface in the third group of interfaces is correspondingly connected to the third interface in the fourth group of interfaces.

3. The server motherboard according to claim 1, characterized in that: The first interface in the first group of interfaces is correspondingly connected to the first interface in the second group of interfaces; The second interface in the first group of interfaces is connected correspondingly to the second interface in the second group of interfaces; The third interface in the first group of interfaces is connected correspondingly to the first interface in the third group of interfaces; The fourth interface in the first group of interfaces is connected correspondingly to the second interface in the third group of interfaces; The fifth interface in the first group of interfaces is correspondingly connected to the first interface in the fourth group of interfaces; The sixth interface in the first group of interfaces is connected correspondingly to the second interface in the fourth group of interfaces; The third interface in the second group of interfaces is correspondingly connected to the third interface in the third group of interfaces; The fourth interface in the second group of interfaces is correspondingly connected to the fourth interface in the third group of interfaces; The fifth interface in the second group of interfaces is connected correspondingly to the third interface in the fourth group of interfaces; The sixth interface in the second group of interfaces is correspondingly connected to the fourth interface in the fourth group of interfaces; The fifth interface in the third group of interfaces is correspondingly connected to the fifth interface in the fourth group of interfaces; The sixth interface in the third group of interfaces is connected correspondingly to the sixth interface in the fourth group of interfaces.

4. The server motherboard according to claim 1, characterized in that: There are eight groups of memory slots arranged on the mainboard body, each group of memory slots includes 6 memory slots; The first processor slot, the second processor slot, the third processor slot and the fourth processor slot are each connected to two groups of memory slots.

5. The server motherboard according to claim 4, characterized in that: Between each processor slot and the two groups of memory slots connected, each memory channel is connected to a dual in-line memory module slot; or, Between each processor socket and the two groups of memory sockets connected thereto, four memory channels are respectively connected to two dual in-line memory module sockets, and the other four memory channels are respectively connected to one dual in-line memory module socket.

6. The server motherboard according to claim 4, characterized in that: The first processor socket and the second processor socket are arranged at intervals along a first direction of the mainboard body; The third processor socket and the fourth processor socket are also arranged at intervals along the first direction of the mainboard body; and The fourth processor socket and the first processor socket are arranged at intervals along the second direction of the mainboard body, and the third processor socket and the second processor socket are also arranged at intervals along the second direction of the mainboard body; The memory slots arranged on the mainboard body include a first group of memory slots, a second group of memory slots, a third group of memory slots, a fourth group of memory slots, a fifth group of memory slots, a sixth group of memory slots, a seventh group of memory slots and an eighth group of memory slots; The first group of memory slots and the second group of memory slots are arranged in parallel on two opposite sides of the first processor slot; wherein the second direction of the first group of memory slots and the second group of memory slots is consistent with the second direction of the mainboard body; The third group of memory slots and the fourth group of memory slots are arranged in parallel on two opposite sides of the second processor slot; the third group of memory slots are arranged in parallel and adjacent to the second group of memory slots; The fifth group of memory slots and the sixth group of memory slots are arranged in parallel on two opposite sides of the third processor slot; wherein the second direction of the fifth group of memory slots and the sixth group of memory slots is also consistent with the second direction of the mainboard body; The seventh group of memory slots and the eighth group of memory slots are arranged in parallel on two opposite sides of the fourth processor slot; the seventh group of memory slots is arranged in parallel and adjacent to the sixth group of memory slots.

7. The server motherboard according to claim 1, characterized in that: Also includes: A cable connector disposed on the mainboard body, the cable connector correspondingly connected to an interface of at least one processor slot; The cable connector includes: an internal cable interconnection system MCIO connector and / or a slimline connector.

8. The server motherboard according to claim 7, characterized in that: The cable connector includes a front cable connector arranged at the front end of the mainboard body and / or a rear cable connector arranged at the rear end of the mainboard body.

9. The server motherboard according to claim 1, characterized in that: Also includes: At least one PCIe 5.0 slot is arranged on the mainboard body, and the at least one PCIe 5.0 slot is correspondingly connected to an interface of at least one processor slot.

10. The server motherboard according to claim 1, characterized in that: Also includes: An Open Compute Project Standard OCP 3.0 connector is disposed at the rear end of the motherboard body and an internal cable interconnection system MCIO connector connected to the OCP 3.0 connector.

11. The server motherboard according to claim 1, wherein: Also includes: A baseboard management controller is arranged on the mainboard body, wherein a graphics card is integrated in the baseboard management controller, and a PCIe signal of the baseboard management controller is connected to an interface of the first processor slot.

12. A server, characterized in that: It comprises a shell, in which the server mainboard according to any one of claims 1 to 11 is arranged.

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