Four-way interconnection system, system on chip and computer equipment

Abstract

The embodiment of the utility model provides a four-way interconnection system, a system on chip and computer equipment, and the four-way interconnection system comprises four processors which are connected with one another; one processor comprises four paths of interconnection ports, and the four paths of interconnection ports are provided with at least three target communication ports adopting a chip interconnection bus; wherein a plurality of interconnection channels are formed among the four processors, one interconnection channel is connected with two target communication ports of different processors through a chip interconnection bus, and the two target communication ports connected with different interconnection channels are different; one processor corresponds to at least three interconnection channels in the plurality of interconnection channels, and the interconnection channels corresponding to different processors are partially repeated; wherein one processor is connected with the other three processors through at least three corresponding interconnection channels, and one interconnection channel corresponding to one processor is connected with the processor and the other processor. According to the embodiment of the invention, data transmission among the four processors can be realized.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of processor technology, and in particular to a four-way interconnection system, a system on a chip, and a computer device. Background Art

[0002] Chip systems such as SOC (System on Chip) can adopt a multi-processor architecture to process different tasks simultaneously or multiple tasks in parallel through multiple processors, thereby improving the processing performance of the chip system.

[0003] One form of multi-processor architecture is formed by four processors, that is, a multi-processor architecture is formed by four processors. In order to realize the data transmission requirements between the four processors, it is necessary to build a topology structure connecting the four processors, which is called a four-way interconnection system. In this context, how to provide a four-way interconnection system to realize data transmission between the four processors has become a technical problem that technicians in this field need to solve urgently. Utility Model Content

[0004] In view of this, embodiments of the present application provide a four-way interconnection system, a system on chip, and a computer device to implement data transmission between four processors.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a four-way interconnection system, comprising: four processors connected to each other; one processor comprising a four-way interconnection port, wherein the four-way interconnection port is provided with at least three target communication ports using a chip interconnection bus;

[0007] Wherein, a plurality of interconnection channels are formed between the four processors, one interconnection channel connects two target communication ports located in different processors through a chip interconnection bus, and the two target communication ports connected by different interconnection channels are different;

[0008] One processor corresponds to at least three interconnection channels among the multiple interconnection channels, and the interconnection channels corresponding to different processors are partially repeated; wherein one processor is connected to the other three processors through the corresponding at least three interconnection channels, and one interconnection channel corresponding to one processor connects the processor with another processor.

[0009] Optionally, the four processors are distributed in a matrix; the four processors include a first processor, a second processor, a third processor and a fourth processor; wherein the first processor and the third processor are diagonally opposite to each other, and the second processor and the fourth processor are diagonally opposite to each other; the first processor and the fourth processor are horizontally adjacent, and the second processor and the third processor are horizontally adjacent; the first processor and the second processor are vertically adjacent, and the third processor and the fourth processor are vertically adjacent.

[0010] Optionally, the top rows of the first processor and the second processor are opposite to each other, and the top rows of the third processor and the fourth processor are opposite to each other.

[0011] Optionally, a four-way interconnection port of a processor is provided with three target communication ports, and one processor corresponds to three interconnection channels; one target communication port of a processor is connected one-to-one with one target communication port of another processor through one interconnection channel.

[0012] Optionally, the three target communication ports include: a first target communication port and a second target communication port in the same row, and a third target communication port in a different row from the first target communication port and the second target communication port; the row order of the third target communication port is higher than the row order of the first target communication port and the second target communication port.

[0013] Optionally, the third target communication port of the first processor is connected to the third target communication port of the third processor through an interconnection channel; the third target communication port of the second processor is connected to the third target communication port of the fourth processor through an interconnection channel;

[0014] The second target communication port of the first processor is connected to the first target communication port of the fourth processor through an interconnection channel; the first target communication port of the second processor is connected to the second target communication port of the third processor through an interconnection channel;

[0015] The first target communication port of the first processor and the second target communication port of the second processor are connected through an interconnection channel; the first target communication port of the third processor and the second target communication port of the fourth processor are connected through an interconnection channel.

[0016] Optionally, the three target communication ports include: a first target communication port and a second target communication port in the same row, and a third target communication port in a different row from the first target communication port and the second target communication port; the row order of the first target communication port and the second target communication port is higher than the row order of the third target communication port.

[0017] Optionally, the second target communication port of the first processor is connected to the first target communication port of the third processor via an interconnection channel; the first target communication port of the second processor is connected to the second target communication port of the fourth processor via an interconnection channel;

[0018] The third target communication port of the first processor is connected to the third target communication port of the fourth processor through an interconnection channel; the third target communication port of the second processor is connected to the third target communication port of the third processor through an interconnection channel;

[0019] The first target communication port of the first processor is connected to the second target communication port of the second processor through an interconnection channel; the second target communication port of the third processor is connected to the first target communication port of the fourth processor through an interconnection channel;

[0020] Optionally, the four-way interconnection ports of the first processor and the second processor include: a first target communication port, a second target communication port, and a third target communication port in the same column; the four-way interconnection ports of the third processor and the fourth processor include: a first target communication port, a second target communication port in the same column, and a fourth target communication port in other columns; the row order of the first target communication port is higher than the row order of the second target communication port, and the row order of the second target communication port is higher than the row order of the third target communication port, and the row order of the fourth target communication port is the same as the row order of the second target communication port.

[0021] Optionally, the second target communication port of the first processor is connected to the fourth target communication port of the third processor through an interconnection channel; the second target communication port of the second processor is connected to the fourth target communication port of the fourth processor through an interconnection channel;

[0022] The third target communication port of the first processor is connected to the third target communication port of the fourth processor through an interconnection channel; the third target communication port of the second processor is connected to the third target communication port of the third processor through an interconnection channel;

[0023] The first target communication port of the first processor is connected to the first target communication port of the second processor via an interconnection channel; the first target communication port of the third processor is connected to the first target communication port of the fourth processor via an interconnection channel.

[0024] Optionally, the three target communication ports include: a first target communication port and a second target communication port located in the same row, and a third target communication port located in the same column as the first target communication port; the row order of the first target communication port and the second target communication port is higher than the row order of the third target communication port.

[0025] Optionally, the third target communication port of the first processor is connected to the third target communication port of the third processor through an interconnection channel; the third target communication port of the second processor is connected to the third target communication port of the fourth processor through an interconnection channel;

[0026] The second target communication port of the first processor is connected to the first target communication port of the fourth processor through an interconnection channel; the first target communication port of the second processor is connected to the second target communication port of the third processor through an interconnection channel;

[0027] The first target communication port of the first processor and the second target communication port of the second processor are connected through an interconnection channel; the first target communication port of the third processor and the second target communication port of the fourth processor are connected through an interconnection channel.

[0028] Optionally, the four-way interconnection port has multiple communication ports, three of the multiple communication ports are target communication ports using a chip interconnection bus; the multiple communication ports are 4 communication ports, or 6 communication ports, or 8 communication ports.

[0029] Optionally, a four-way interconnection port of a processor is provided with six target communication ports, and one processor corresponds to six interconnection channels; one target communication port of a processor is connected one-to-one with one target communication port of another processor through one interconnection channel.

[0030] Optionally, the six target communication ports include: a first target communication port and a second target communication port arranged in order in the first row, a third target communication port and a fourth target communication port arranged in order in the second row, and a fifth target communication port and a sixth target communication port arranged in order in the third row; the row order of the first row is higher than the row order of the second row and the third row, and the row order of the second row is higher than the row order of the third row.

[0031] Optionally, the third target communication port of the first processor is connected to the fourth target communication port of the third processor through an interconnection channel; the fourth target communication port of the first processor is connected to the third target communication port of the third processor through an interconnection channel; the fourth target communication port of the second processor is connected to the third target communication port of the fourth processor through an interconnection channel;

[0032] The fifth target communication port of the first processor is connected to the sixth target communication port of the fourth processor through an interconnection channel; the sixth target communication port of the first processor is connected to the fifth target communication port of the fourth processor through an interconnection channel; the sixth target communication port of the second processor is connected to the fifth target communication port of the third processor through an interconnection channel; the fifth target communication port of the second processor is connected to the sixth target communication port of the third processor through an interconnection channel;

[0033] The first target communication port of the first processor and the second target communication port of the second processor are connected through an interconnection channel; the second target communication port of the first processor and the first target communication port of the second processor are connected through an interconnection channel; the second target communication port of the third processor and the first target communication port of the fourth processor are connected through an interconnection channel; the first target communication port of the third processor and the second target communication port of the fourth processor are connected through an interconnection channel.

[0034] Optionally, the four-way interconnection port has multiple communication ports, six of the multiple communication ports are target communication ports using a chip interconnection bus; the multiple communication ports are 6 communication ports, or 8 communication ports.

[0035] In a second aspect, an embodiment of the present application provides a system on chip, including the four-way interconnection system as described in the first aspect above.

[0036] In a third aspect, an embodiment of the present application provides a computer device, comprising the four-way interconnection system as described in the first aspect above, or the system on chip as described in the second aspect above.

[0037] An embodiment of the present application provides a four-way interconnection system and a computer device, wherein the four-way interconnection system includes: four processors connected to each other; one processor includes a four-way interconnection port, and the four-way interconnection port is provided with at least three target communication ports using a chip interconnection bus; wherein a plurality of interconnection channels are formed between the four processors, and one interconnection channel connects two target communication ports located in different processors through a chip interconnection bus, and the two target communication ports connected by different interconnection channels are different; one processor corresponds to at least three interconnection channels among the plurality of interconnection channels, and there is partial duplication of interconnection channels corresponding to different processors; wherein one processor is connected to the other three processors through the corresponding at least three interconnection channels, and one interconnection channel corresponding to one processor connects the processor with one other processor.

[0038] It can be seen that the four-way interconnection system provided in the embodiment of the present application connects the target communication ports of the four processors one-to-one through the chip external interconnection bus. By setting the target communication port using the chip interconnection bus in the four-way interconnection port of the processor, and then connecting the two target communication ports in different processors using the chip interconnection bus to form an interconnection channel, the four processors can be connected through the interconnection channel to achieve four-way interconnection between the four processors, providing a basis for data transmission between the four processors, and the connection method of the four-way interconnection of the processor is convenient and efficient, which can simplify the four-way interconnection design of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technical personnel in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0040] Figure 1 is an example diagram of the interconnection between four processors provided in an embodiment of the present application;

[0041] Figure 2 is an example diagram of processor position distribution of a four-way interconnection system provided in an embodiment of the present application;

[0042] Figure 3 is a structural example diagram of a four-way interconnection system provided in an embodiment of the present application;

[0043] Figure 4 is a first connection example diagram of a four-way interconnection system provided in an embodiment of the present application;

[0044] Figure 5is a second connection example diagram of the four-way interconnection system provided in an embodiment of the present application;

[0045] Figure 6 is a third connection example diagram of the four-way interconnection system provided in an embodiment of the present application;

[0046] Figure 7 is a fourth connection example diagram of the four-way interconnection system provided in an embodiment of the present application;

[0047] Figure 8 This is a fifth connection example diagram of the four-way interconnection system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0049] A processor is a type of computer hardware whose main function is to perform calculations and logical operations. It is a core component in a computer system and is responsible for processing and executing applications, operating systems, and other computer instructions. Depending on the usage scenario, processors can be divided into general-purpose processors and special-purpose processors. General-purpose processors are processors used to execute a wide range of applications, such as CPUs (Central Processing Units). Special-purpose processors are processors designed for specific computing tasks or applications, such as GPUs (Graphics Processing Units) or neural processors.

[0050] Four-way interconnect refers to the interconnection between four processors. The design of four-way interconnect enables data to be transmitted between four processors. Four-way interconnect can be used to build SMP (Symmetric Multi-Processing) systems, in which each processor has the ability to directly access shared memory and coordinate task allocation and data sharing through four-way interconnect.

[0051] In the case of interconnection between four processors, the four processors can be connected through their respective four-way interconnection ports to achieve interconnection between the four processors. In the connection system, the four-way interconnection port of the processor is a communication interface that allows multiple independent channels or paths for data transmission.

[0052] For ease of understanding, Figure 1An exemplary diagram showing the interconnection between four processors is shown in FIG. Figure 1 , processor 1, processor 2, processor 3, and processor 4 may be respectively provided with four-way interconnection ports 100, so that processor 1 and processor 2 may be connected through the four-way interconnection port, processor 1 and processor 3 may be connected through the four-way interconnection port, processor 1 and processor 4 may be connected through the four-way interconnection port, processor 2 and processor 3 may be connected through the four-way interconnection port, and processor 2 and processor 4 may be connected through the four-way interconnection port to realize the interconnection between processor 1, processor 2, processor 3, and processor 4. Among them, the interconnection mode of the four-way interconnection may be DC coupling or AC coupling, wherein DC coupling is also called direct current coupling, and AC coupling is also called alternating current coupling.

[0053] Furthermore, in order to achieve normal communication between the four interconnected processors, the embodiment of the present application can set the position distribution of the processors to facilitate the subsequent interconnection between the processors. Figure 2 An exemplary diagram showing the processor position distribution of the four-way interconnection system provided by the present application is shown as follows: Figure 2 As shown, the four-way interconnection system includes four processors connected to each other, namely processor 1, processor 2, processor 3 and processor 4. The four processors are arranged in a matrix to form a rectangle, and processor 1 is located at the lower left corner. The other three processors can be arranged in a clockwise manner according to the size of the number. Figure 2 As shown, the positions of other processors are: processor 2 is located at the upper left corner, processor 3 is located at the upper right corner, and processor 4 is located at the lower right corner, and processor 1 and processor 2 are located opposite to each other in the top row, and processor 3 and processor 4 are located opposite to each other in the top row.

[0054] The positions of the processors can be set according to actual needs. The embodiment of the present application does not limit the method for sorting the positions of the multiple processors. However, no matter how the positions of the processors are set, the rectangle formed by the four processors has diagonal, vertically adjacent and horizontally adjacent physical positions. The above-mentioned physical positions can be as follows: Figure 2 shown.

[0055] exist Figure 2 On the basis of, in order to realize the normal communication between the four interconnected processors, the four-way interconnection port of the processor can be provided with a communication port using the chip interconnection bus, so as to realize the interconnection between the processors through the communication port using the chip interconnection bus in the four-way interconnection port of the processor. Based on this, Figure 3 The following is an exemplary diagram showing a structure of a four-way interconnection system provided in an embodiment of the present application. Figure 3As shown, the four-way interconnection system includes four processors connected to each other, namely, a first processor 1, a second processor 2, a third processor 3 and a fourth processor 4. That is, the four processors connected to each other may include a first processor 1 (i.e., processor 1), a second processor 2 (i.e., processor 2), a third processor 3 (i.e., processor 3), and a fourth processor 4 (i.e., processor 4).

[0056] Among them, the four processors are distributed in a matrix; among them, the first processor 1 and the third processor 3 are diagonally opposite to each other, and the second processor 2 and the fourth processor 4 are diagonally opposite to each other; the first processor 1 and the fourth processor 4 are horizontally adjacent, and the second processor 2 and the third processor 3 are horizontally adjacent; the first processor 1 and the second processor 2 are vertically adjacent, and the third processor 3 and the fourth processor 4 are vertically adjacent.

[0057] For any processor, the processor may include a four-way interconnection port 100, and the four-way interconnection port 100 may include multiple communication ports, such as a high-speed Serdes (serializer / deserializer) port. In an optional implementation, the communication ports in the four-way interconnection port 100 are arranged in a matrix in rows and columns, so that the row order and column order can be defined in the four-way interconnection port; the row with the first row in the row order is called the top row, so that when the four processors are arranged in a matrix, the top rows of the first processor 1 and the second processor 2 are opposite, and the top rows of the third processor 3 and the fourth processor 4 are opposite. In an optional implementation, data communication can be carried out between processors through a chip interconnection bus, so that at least part of the communication ports in the four-way interconnection port can use the chip interconnection bus. For ease of explanation, the communication port using the chip interconnection bus can be called a target communication port. The chip interconnection bus is a bus that realizes mutual connection and communication between processors, and is used for interconnection and intercommunication between processors. Through the chip interconnection bus, different processors can exchange information and transmit data.

[0058] Among them, the target communication ports in the four-way interconnection ports of the four processors are connected one-to-one through the chip interconnection bus, that is, a target communication port in one processor is connected to a target communication port in another processor through the chip interconnection bus, thereby forming an interconnection channel for data transmission with other processors.

[0059] It can be seen that the four-way interconnection system provided in the embodiment of the present application realizes four-way interconnection between the four processors by setting some of the communication ports among the multiple four-way interconnection ports of the processor as target communication ports, and then connects the target communication ports in the four processors one-to-one through the chip interconnection bus to form multiple interconnection channels, thereby realizing four-way interconnection between the four processors and providing a basis for data transmission between the four processors.

[0060] At the same time, since the interconnection channels of the four processors are connected one-to-one, the interconnection channels of different interconnections between the four processors do not interfere with each other. The embodiment of the present application can select different interconnection channels between the four processors according to needs to transmit different data information, making the connection mode of the four-way interconnection of the processors convenient and efficient, and can simplify the four-way interconnection design of the processors.

[0061] As an optional implementation, among four interconnected processors, one processor may include a four-way interconnection port, and the four-way interconnection port is provided with at least three target communication ports using a chip interconnection bus; wherein, multiple interconnection channels are formed between the four processors, and one interconnection channel connects two target communication ports located in different processors through the chip interconnection bus, and the two target communication ports connected by different interconnection channels are different; one processor corresponds to at least three interconnection channels among the multiple interconnection channels, and there is partial duplication of interconnection channels corresponding to different processors; wherein, one processor is connected to the other three processors through the corresponding at least three interconnection channels, and one interconnection channel corresponding to one processor connects the processor with one other processor.

[0062] In some embodiments, a processor's four-way interconnection port is provided with three target communication ports, and one processor corresponds to three interconnection channels; one target communication port of one processor is connected to one target communication port of another processor through one interconnection channel in a one-to-one manner. On the basis, the setting of the target communication port of the processor's four-way interconnection port may include any of the following:

[0063] In case 1, for any processor among the four processors, the three target communication ports of the processor are two target communication ports in the same row of the four-way interconnection port, and an independent target communication port in any other row.

[0064] In the optional example of case one, Figure 4 The first connection example diagram of the four-way interconnection system provided in the embodiment of the present application is shown as an example. Figure 4 As shown, if the row order of the independent target communication port is higher than the row order of the two target communication ports in the same row, the three target communication ports in the four-way interconnection port are: the first target communication port 101 and the second target communication port 102 in the same row, and the third target communication port 103 in a different row from the first target communication port 101 and the second target communication port 102; wherein the row order of the third target communication port 103 is higher than the row order of the first target communication port 101 and the second target communication port 102.

[0065] In the optional example of case one, Figure 5The second connection example diagram of the four-way interconnection system provided in the embodiment of the present application is exemplarily shown, as shown in FIG. Figure 5 As shown, if the row order of two target communication ports in the same row is higher than the row order of an independent target communication port, the three target communication ports in the four-way interconnection port are: a first target communication port 101 and a second target communication port 102 in the same row, and a third target communication port 103 in a different row from the first target communication port 101 and the second target communication port 102; the row order of the first target communication port 101 and the second target communication port 102 is higher than the row order of the third target communication port 103.

[0066] In case 2, the three target communication ports of the first processor and the second processor are located in the same column; the two target communication ports of the third processor and the fourth processor are located in the same column, and the other target communication port is located in a different column; and the three target communication ports of one processor are distributed in three rows, and the three rows in which the target communication ports of the four processors are distributed are the same.

[0067] In the optional example of case 2, Figure 6 The third connection example diagram of the four-way interconnection system provided in the embodiment of the present application is shown as an example. Figure 6 As shown, the four-way interconnection ports of the first processor 1 and the second processor 2 are: the first target communication port 101, the second target communication port 102, and the third target communication port 103 in the same column; the four-way interconnection ports of the third processor 3 and the fourth processor 4 are: the first target communication port 101, the second target communication port 102 in the same column, and the fourth target communication port 104 in other columns; the row order of the first target communication port 101 is higher than the row order of the second target communication port 102, the row order of the second target communication port 102 is higher than the row order of the third target communication port 103, and the row order of the fourth target communication port 104 is the same as the row order of the second target communication port 102.

[0068] Case three, for any processor among the four processors, the target communication ports of the processor are two target communication ports in the same row of the four-way interconnection port, and an independent target communication port located in an adjacent row, and the independent target communication port (located in the adjacent row) is adjacent to any target communication port of the two target communication ports (located in the same row); wherein the row order of the two target communication ports located in the same row is higher than the row order of the independent target communication port located in the adjacent row.

[0069] In the optional example of case three, Figure 7 The fourth connection example diagram of the four-way interconnection system provided in the embodiment of the present application is exemplarily shown, as shown in FIG. Figure 7As shown, the three target communication ports in the four-way interconnection port are: a first target communication port 101 and a second target communication port 102 located in the same row, and a third target communication port 103 located in the same column as the first target communication port 101; the row order of the first target communication port 101 and the second target communication port 102 is higher than the row order of the third target communication port 103, and the third target communication port 103 is adjacent to the first target communication port 101.

[0070] In other embodiments, a processor's four-way interconnection port is provided with six target communication ports, and one processor corresponds to six interconnection channels; one target communication port of one processor is connected to one target communication port of another processor through one interconnection channel in a one-to-one manner. On this basis, the setting of the target communication port can be:

[0071] In case 4, the number of target communication ports of the processor is six, and one row has two target communication ports, and the six target communication ports are arranged through three rows of four-way interconnection ports.

[0072] In the optional example of case four, Figure 8 The fifth connection example diagram of the four-way interconnection system provided in the embodiment of the present application is exemplarily shown, as shown in FIG. Figure 8 As shown, the six target communication ports in the four-way interconnection port are: a first target communication port 101 and a second target communication port 102 arranged in sequence in the first row, a third target communication port 103 and a fourth target communication port 104 arranged in sequence in the second row, and a fifth target communication port 105 and a sixth target communication port 106 arranged in sequence in the third row; the row order of the first row is higher than the row order of the second row and the third row, and the row order of the second row is higher than the row order of the third row.

[0073] In an optional implementation, for case 1, when the target communication ports of the processor are two target communication ports in the same row, and an independent target communication port in any other row. If the row order of the independent target communication port is higher than the row order of the two target communication ports in the same row, the connection mode between the four processors can be:

[0074] For the diagonal processors, the independent target communication ports are connected through an interconnection channel;

[0075] For horizontally adjacent processors, the columns in the same row are in reverse order, and the nearest target communication ports are connected through interconnection channels;

[0076] For vertically adjacent processors, the remaining unconnected target communication ports in the same row are connected through an interconnection channel; the row order and column order of the two remaining unconnected target communication ports are the same.

[0077] In a further optional example, for situation one, Figure 4 The first connection example diagram of the four-way interconnection system provided in the embodiment of the present application is shown exemplarily, with reference to Figure 4 The three target communication ports in the four-way interconnect port 100 may include: a first target communication port 101 and a second target communication port 102 in the same row, and an independent target communication port (e.g., a third target communication port) 103 in any other row; wherein the row order of the independent target communication port is higher than the row order of the two target communication ports in the same row.

[0078] like Figure 4 As shown, the connection relationship between the four processors can be:

[0079] The third target communication port 103 of the first processor 1 is connected to the third target communication port 103 of the third processor 3 through an interconnection channel; the third target communication port 103 of the second processor 2 is connected to the third target communication port 103 of the fourth processor 4 through an interconnection channel;

[0080] The second target communication port 102 of the first processor 1 is connected to the first target communication port 101 of the fourth processor 4 through an interconnection channel; the first target communication port 101 of the second processor 2 is connected to the second target communication port 102 of the third processor 3 through an interconnection channel;

[0081] The first target communication port 101 of the first processor 1 and the second target communication port 102 of the second processor 2 are connected through an interconnection channel; the first target communication port 101 of the third processor 3 and the second target communication port 102 of the fourth processor 4 are connected through an interconnection channel.

[0082] In an optional implementation, for case 1, if the row order of two target communication ports in the same row is higher than the row order of independent target communication ports, the connection mode between the four processors may be:

[0083] For diagonal processors, the columns in the same row have the same order, and the target communication ports at the right end of the processors are connected through interconnection channels;

[0084] For horizontally adjacent processors, independent target communication ports are connected through an interconnect channel;

[0085] For vertically adjacent processors, the remaining unconnected target communication ports in the same row are connected through an interconnection channel; the column order of the two remaining unconnected target communication ports is reversed and the distance is shortest.

[0086] In a further optional example, for situation one, Figure 5 The second connection example diagram of the four-way interconnection system provided in the embodiment of the present application is shown as an example. Figure 5 The three target communication ports in the four-way interconnection port 100 may include: a first target communication port 101 and a second target communication port 102 in the same row, and an independent target communication port (third target communication port) 103 in any other row; wherein the row order of the two target communication ports in the same row is higher than the row order of the independent target communication port;

[0087] like Figure 5 As shown, the connection relationship between the four processors can be:

[0088] The second target communication port 102 of the first processor 1 is connected to the first target communication port 101 of the third processor 3 through an interconnection channel; the first target communication port 101 of the second processor 2 is connected to the second target communication port 102 of the fourth processor 4 through an interconnection channel;

[0089] The third target communication port 103 of the first processor 1 is connected to the third target communication port 103 of the fourth processor 4 through an interconnection channel; the third target communication port 103 of the second processor 2 is connected to the third target communication port 103 of the third processor 3 through an interconnection channel;

[0090] The first target communication port 101 of the first processor 1 and the second target communication port 102 of the second processor 2 are connected through an interconnection channel; the second target communication port 102 of the third processor 3 and the first target communication port 101 of the fourth processor 4 are connected through an interconnection channel.

[0091] In an optional implementation, for situation 2 (the three target communication ports of the first processor and the second processor are located in the same column; the two target communication ports of the third processor and the fourth processor are located in the same column, and the other target communication port is located in a different column), when the three target communication ports of one processor are distributed in three rows, and the three rows in which the target communication ports of four processors are distributed are the same, the connection mode between the four processors may be:

[0092] For the diagonally located processor, the target communication port with the second highest row order is connected through the interconnection channel;

[0093] For the target communication ports with the lowest row order in the horizontally adjacent processors, they are connected through the interconnection channel;

[0094] For vertically adjacent processors, the target communication ports with the highest row order are connected through the interconnect channel.

[0095] In a further optional example, for situation 2, Figure 6 The third connection example diagram of the four-way interconnection system provided in the embodiment of the present application is shown exemplarily, with reference to Figure 6 , the three target communication ports in the four-way interconnection port 100 of the first processor 1 and the second processor 2 may include: a first target communication port 101, a second target communication port 102, and a third target communication port 103 arranged in sequence in the same column;

[0096] The three target communication ports in the four-way interconnection port 100 of the third processor 3 and the fourth processor 4 may include: a first target communication port 101 and a third target communication port 103 arranged in sequence in the same column, and another target communication port (e.g., a fourth target communication port) 104 located in a different column;

[0097] Furthermore, the three target communication ports of one processor are distributed in three rows, and the target communication ports of four processors are distributed in the same three rows;

[0098] like Figure 6 As shown, the connection relationship between the four processors can be:

[0099] The second target communication port 102 of the first processor 1 is connected to the fourth target communication port 104 of the third processor 3 through an interconnection channel; the second target communication port 102 of the second processor 2 is connected to the fourth target communication port 104 of the fourth processor 4 through an interconnection channel;

[0100] The third target communication port 103 of the first processor 1 is connected to the third target communication port 103 of the fourth processor 4 through an interconnection channel; the third target communication port 103 of the second processor 2 is connected to the third target communication port 103 of the third processor 3 through an interconnection channel;

[0101] The first target communication port 101 of the first processor 1 and the first target communication port 101 of the second processor 2 are connected through an interconnection channel; the first target communication port 101 of the third processor 3 and the first target communication port 101 of the fourth processor 4 are connected through an interconnection channel.

[0102] In an optional implementation, for situation three, for any processor among the four processors, the target communication port of the processor is two target communication ports in the same row of the four-way interconnection port, and an independent target communication port located in an adjacent row, and the independent target communication port (located in the adjacent row) is adjacent to any target communication port of the two target communication ports (located in the same row); wherein, when the row order of the two target communication ports located in the same row is higher than the row order of the independent target communication port located in the adjacent row, the connection mode between the four processors may be:

[0103] For two diagonal processors, independent target communication ports are connected through interconnection channels;

[0104] For horizontally adjacent processors, the target communication ports in the same row with reverse column order and closest distance are connected through the interconnection channel;

[0105] For vertically adjacent processors, the remaining unconnected target communication ports in the same row are connected via an interconnection channel; the column order of the remaining unconnected target communication ports is reversed.

[0106] In a further optional example, for situation three, Figure 7 The fourth connection example diagram of the four-way interconnection system provided in the embodiment of the present application is exemplarily shown, with reference to Figure 7 , the three target communication ports in the four-way interconnection port 100 may include: a first target communication port 101 and a second target communication port 102 arranged in sequence in the same row; and a third target communication port 103 located in the same column as the first target communication port 101, the row order of the first target communication port 101 and the second target communication port 102 being higher than the row order of the third target communication port 103;

[0107] like Figure 7 As shown, the connection relationship between the four processors can be:

[0108] The third target communication port 103 of the first processor 1 is connected to the third target communication port 103 of the third processor 3 through an interconnection channel; the third target communication port 103 of the second processor 2 is connected to the third target communication port 103 of the fourth processor 4 through an interconnection channel;

[0109] The second target communication port 102 of the first processor 1 is connected to the first target communication port 101 of the fourth processor 4 through an interconnection channel; the first target communication port 101 of the second processor 2 is connected to the second target communication port 102 of the third processor 3 through an interconnection channel;

[0110] The first target communication port 101 of the first processor 1 and the second target communication port 102 of the second processor 2 are connected through an interconnection channel; the first target communication port 101 of the third processor 3 and the second target communication port 102 of the fourth processor 4 are connected through an interconnection channel.

[0111] In optional examples, for the examples of Case 1, Case 2, and Case 3, the four-way interconnection port of the processor has multiple communication ports, three of the multiple communication ports are target communication ports using a chip interconnection bus; the multiple communication ports are 4 communication ports, or 6 communication ports, or 8 communication ports.

[0112] In an optional implementation, for situation 4, the number of target communication ports of the processor is six, and a row has two target communication ports. When the six target communication ports are arranged in three rows of four-way interconnection ports, the connection mode between the four processors can be:

[0113] For the target communication ports in the second row of two diagonal processors with reverse column order, they are connected through an interconnection channel;

[0114] For horizontally adjacent processors, the target communication ports in the third row with the columns in reverse order are connected via an interconnection channel;

[0115] For vertically adjacent processors, target communication ports in the first row with the same column order are connected through an interconnection channel.

[0116] In a further optional example, for situation four, Figure 8 The fifth connection example diagram of the four-way interconnection system provided in the embodiment of the present application is exemplarily shown, with reference to Figure 8 The six target communication ports in the four-way interconnection port 100 may include: a first target communication port 101 and a second target communication port 102 located in a first row, a third target communication port 103 and a fourth target communication port 104 located in a second row, and a fifth target communication port 105 and a sixth target communication port 106 located in a third row; the row order of the first row is higher than the row order of the second row and the third row, and the row order of the second row is higher than the row order of the third row;

[0117] like Figure 8 As shown, the connection relationship between the four processors can be:

[0118] The third target communication port 103 of the first processor 1 is connected to the fourth target communication port 104 of the third processor 3 through an interconnection channel; the fourth target communication port 104 of the first processor 1 is connected to the third target communication port 103 of the third processor 3 through an interconnection channel; the fourth target communication port 104 of the second processor 2 is connected to the third target communication port 103 of the fourth processor 4 through an interconnection channel; the third target communication port 103 of the second processor 2 is connected to the fourth target communication port 104 of the fourth processor 4 through an interconnection channel;

[0119] The fifth target communication port 105 of the first processor 1 is connected to the sixth target communication port 106 of the fourth processor 4 through an interconnection channel; the sixth target communication port 106 of the first processor 1 is connected to the fifth target communication port 105 of the fourth processor 4 through an interconnection channel; the sixth target communication port 106 of the second processor 2 is connected to the fifth target communication port 105 of the third processor 3 through an interconnection channel; the fifth target communication port 105 of the second processor 2 is connected to the sixth target communication port 106 of the third processor 3 through an interconnection channel;

[0120] The first target communication port 101 of the first processor 1 and the second target communication port 102 of the second processor 2 are connected through an interconnection channel; the second target communication port 102 of the first processor 1 and the first target communication port 101 of the second processor 2 are connected through an interconnection channel; the second target communication port 102 of the third processor 3 and the first target communication port 101 of the fourth processor 4 are connected through an interconnection channel; the first target communication port 101 of the third processor 3 and the second target communication port 102 of the fourth processor 4 are connected through an interconnection channel.

[0121] In an optional example, for the example of case four, the four-way interconnect port of the processor has multiple communication ports, six of the multiple communication ports are target communication ports using a chip interconnect bus; the multiple communication ports are 6 communication ports, or 8 communication ports.

[0122] It should be noted that the target communication ports in the same row, the first row, the second row and the third row of the four-way interconnection port of the processor may be the target communication ports of the processor located in any row of the four-way interconnection port, and the embodiments of the present application are not limited to this.

[0123] It should be noted that when the embodiment of the present application numbers the target communication ports (for example, numbering the three target communication ports as the first to the third target communication ports), a target communication port with a certain number does not specifically refer to a fixed target communication port. The numbering of the target communication ports is only for the convenience of explaining the setting scheme of the target communication ports, and the numbering has no special meaning.

[0124] The embodiment of the present application provides a connection method of the four-way interconnection of the processor under different circumstances, which can be applicable to different connection scenarios of the four-way interconnection of the processor and has high applicability. In addition, the connection method of the four-way interconnection of the processor is convenient and efficient, and can simplify the four-way interconnection system of the processor.

[0125] The embodiment of the present application also provides a system on chip, which may be, for example, a SOC chip. In the embodiment of the present application, the system on chip may include a four-way interconnection system provided in the embodiment of the present application.

[0126] An embodiment of the present application further provides a computer device, such as a terminal device or a server device, and the computer device may include the four-way interconnection system provided by an embodiment of the present application, or the system on chip provided by an embodiment of the present application.

[0127] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0128] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A four-way interconnection system, characterized in that: include: Four processors connected to each other; one processor includes a four-way interconnect port, and the four-way interconnect port is provided with at least three target communication ports using a chip interconnect bus; Wherein, a plurality of interconnection channels are formed between the four processors, one interconnection channel connects two target communication ports located in different processors through a chip interconnection bus, and the two target communication ports connected by different interconnection channels are different; One processor corresponds to at least three interconnection channels among the multiple interconnection channels, and the interconnection channels corresponding to different processors are partially repeated; wherein one processor is connected to the other three processors through the corresponding at least three interconnection channels, and one interconnection channel corresponding to one processor connects the processor with another processor.

2. The four-way interconnection system according to claim 1, characterized in that: The four processors are distributed in a matrix; the four processors include a first processor, a second processor, a third processor and a fourth processor; wherein the first processor and the third processor are diagonally opposite to each other, and the second processor and the fourth processor are diagonally opposite to each other; the first processor and the fourth processor are horizontally adjacent to each other, and the second processor and the third processor are horizontally adjacent to each other; the first processor and the second processor are vertically adjacent to each other, and the third processor and the fourth processor are vertically adjacent to each other.

3. The four-way interconnection system according to claim 2, characterized in that: The top rows of the first processor and the second processor are opposite to each other, and the top rows of the third processor and the fourth processor are opposite to each other.

4. The four-way interconnection system according to claim 3, characterized in that: A four-way interconnection port of a processor is provided with three target communication ports, and one processor corresponds to three interconnection channels; one target communication port of a processor is connected one-to-one with one target communication port of other processors through one interconnection channel.

5. The four-way interconnection system according to claim 4, characterized in that: The three target communication ports include: a first target communication port and a second target communication port in the same row, and a third target communication port in a different row from the first target communication port and the second target communication port; the row order of the third target communication port is higher than the row order of the first target communication port and the second target communication port.

6. The four-way interconnection system according to claim 5, characterized in that: The third target communication port of the first processor is connected to the third target communication port of the third processor through an interconnection channel; the third target communication port of the second processor is connected to the third target communication port of the fourth processor through an interconnection channel; The second target communication port of the first processor is connected to the first target communication port of the fourth processor through an interconnection channel; the first target communication port of the second processor is connected to the second target communication port of the third processor through an interconnection channel; The first target communication port of the first processor and the second target communication port of the second processor are connected through an interconnection channel; the first target communication port of the third processor and the second target communication port of the fourth processor are connected through an interconnection channel.

7. The four-way interconnection system according to claim 4, characterized in that: The three target communication ports include: a first target communication port and a second target communication port in the same row, and a third target communication port in a different row from the first target communication port and the second target communication port; the row order of the first target communication port and the second target communication port is higher than the row order of the third target communication port.

8. The four-way interconnection system according to claim 7, characterized in that: The second target communication port of the first processor is connected to the first target communication port of the third processor through an interconnection channel; the first target communication port of the second processor is connected to the second target communication port of the fourth processor through an interconnection channel; The third target communication port of the first processor is connected to the third target communication port of the fourth processor through an interconnection channel; the third target communication port of the second processor is connected to the third target communication port of the third processor through an interconnection channel; The first target communication port of the first processor and the second target communication port of the second processor are connected through an interconnection channel; the second target communication port of the third processor and the first target communication port of the fourth processor are connected through an interconnection channel.

9. The four-way interconnection system according to claim 4, characterized in that: The four-way interconnection ports of the first processor and the second processor include: a first target communication port, a second target communication port, and a third target communication port in the same column; the four-way interconnection ports of the third processor and the fourth processor include: a first target communication port, a second target communication port in the same column, and a fourth target communication port in other columns; the row order of the first target communication port is higher than the row order of the second target communication port, and the row order of the second target communication port is higher than the row order of the third target communication port, and the row order of the fourth target communication port is the same as the row order of the second target communication port.

10. The four-way interconnection system according to claim 9, characterized in that: The second target communication port of the first processor is connected to the fourth target communication port of the third processor through an interconnection channel; the second target communication port of the second processor is connected to the fourth target communication port of the fourth processor through an interconnection channel; The third target communication port of the first processor is connected to the third target communication port of the fourth processor through an interconnection channel; the third target communication port of the second processor is connected to the third target communication port of the third processor through an interconnection channel; The first target communication port of the first processor is connected to the first target communication port of the second processor via an interconnection channel; the first target communication port of the third processor is connected to the first target communication port of the fourth processor via an interconnection channel.

11. The four-way interconnection system according to claim 4, characterized in that: The three target communication ports include: a first target communication port and a second target communication port located in the same row, and a third target communication port located in the same column as the first target communication port; the row order of the first target communication port and the second target communication port is higher than the row order of the third target communication port.

12. The four-way interconnection system according to claim 11, characterized in that: The third target communication port of the first processor is connected to the third target communication port of the third processor through an interconnection channel; the third target communication port of the second processor is connected to the third target communication port of the fourth processor through an interconnection channel; The second target communication port of the first processor is connected to the first target communication port of the fourth processor through an interconnection channel; the first target communication port of the second processor is connected to the second target communication port of the third processor through an interconnection channel; The first target communication port of the first processor and the second target communication port of the second processor are connected through an interconnection channel; the first target communication port of the third processor and the second target communication port of the fourth processor are connected through an interconnection channel.

13. The four-way interconnection system according to any one of claims 4 to 12, characterized in that: The four-way interconnection port has multiple communication ports, three of which are target communication ports using a chip interconnection bus; the multiple communication ports are 4 communication ports, or 6 communication ports, or 8 communication ports.

14. The four-way interconnection system according to claim 3, characterized in that: A four-way interconnection port of a processor is provided with six target communication ports, and one processor corresponds to six interconnection channels; one target communication port of a processor is connected one-to-one with one target communication port of other processors through one interconnection channel.

15. The four-way interconnection system according to claim 14, characterized in that: The six target communication ports include: a first target communication port and a second target communication port arranged in order in the first row, a third target communication port and a fourth target communication port arranged in order in the second row, and a fifth target communication port and a sixth target communication port arranged in order in the third row; the row order of the first row is higher than the row order of the second row and the third row, and the row order of the second row is higher than the row order of the third row.

16. The four-way interconnection system according to claim 15, characterized in that: The third target communication port of the first processor is connected to the fourth target communication port of the third processor through an interconnection channel; the fourth target communication port of the first processor is connected to the third target communication port of the third processor through an interconnection channel; the fourth target communication port of the second processor is connected to the third target communication port of the fourth processor through an interconnection channel; The fifth target communication port of the first processor is connected to the sixth target communication port of the fourth processor through an interconnection channel; the sixth target communication port of the first processor is connected to the fifth target communication port of the fourth processor through an interconnection channel; the sixth target communication port of the second processor is connected to the fifth target communication port of the third processor through an interconnection channel; the fifth target communication port of the second processor is connected to the sixth target communication port of the third processor through an interconnection channel; The first target communication port of the first processor and the second target communication port of the second processor are connected through an interconnection channel; the second target communication port of the first processor and the first target communication port of the second processor are connected through an interconnection channel; the second target communication port of the third processor and the first target communication port of the fourth processor are connected through an interconnection channel; the first target communication port of the third processor and the second target communication port of the fourth processor are connected through an interconnection channel.

17. The four-way interconnection system according to any one of claims 14 to 16, characterized in that: The four-way interconnection port has multiple communication ports, six of which are target communication ports using a chip interconnection bus; the multiple communication ports are 6 communication ports, or 8 communication ports.

18. A system on chip, characterized in that: Comprising a four-way interconnection system as claimed in any one of claims 1-17.

19. A computer device, characterized in that: It comprises the four-way interconnection system as claimed in any one of claims 1 to 17, or the system on chip as claimed in claim 18.

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