Display device

Abstract

The utility model relates to a display device. A display device according to one or more embodiments may include: a substrate; a first electrode, a second electrode, a third electrode, and a fourth electrode, the first electrode and the third electrode being integrally formed to be electrically connected to each other, the second electrode and the fourth electrode being integrally formed to be electrically connected to each other, the first electrode, the second electrode, the third electrode, and the fourth electrode being spaced apart from each other over the substrate; a first dummy electrode and a second dummy electrode spaced apart from each other over the substrate and electrically insulated from the first electrode, the second electrode, the third electrode, and the fourth electrode; and a light emitting element electrically connected to the first electrode and the second electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0042654 filed in the Korean Intellectual Property Office on March 31, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a repair method thereof. Background Art

[0004] Recently, as interest in information display increases, research and development of display devices have been continuously conducted. Utility Model Content

[0005] Embodiments may provide a display having improved reliability and a method of repairing the same by reducing or preventing the possibility of dark spot defects in pixels.

[0006] One or more embodiments provide a display device, comprising: a substrate; a first electrode, a second electrode, a third electrode, and a fourth electrode, the first electrode and the third electrode being integrally formed to be electrically connected to each other, the second electrode and the fourth electrode being integrally formed to be electrically connected to each other, the first electrode, the second electrode, the third electrode, and the fourth electrode being spaced apart from each other above the substrate; a first dummy electrode and a second dummy electrode being spaced apart from each other above the substrate and electrically insulated from the first electrode, the second electrode, the third electrode, and the fourth electrode; and a light-emitting element being electrically connected to the first electrode and the second electrode.

[0007] The display device may further include: a pixel circuit layer over the substrate and including a transistor electrically connected to the third electrode; and a common line over the substrate and integrally formed with the second electrode and the fourth electrode to be electrically connected to the second electrode and the fourth electrode.

[0008] The second electrode and the fourth electrode may branch from the common line in one direction.

[0009] The first electrode may include two or more first sub-electrodes spaced apart from each other, wherein the second electrode includes two or more second sub-electrodes spaced apart from each other.

[0010] The first sub-electrodes may be electrically connected to each other, and the second sub-electrodes may be electrically connected to each other.

[0011] The display device may further include: a first connection line over the substrate and electrically connecting the first sub-electrodes; and a second connection line over the substrate and electrically connecting the second sub-electrodes.

[0012] The first sub-electrode may have a width different from that of the third electrode, wherein the second sub-electrode has a width different from that of the fourth electrode.

[0013] The first sub-electrodes may have the same respective widths, wherein the second sub-electrodes have the same respective widths.

[0014] At least one of the first sub-electrodes may have a width different from the other first sub-electrodes, wherein at least one of the second sub-electrodes has a width different from the other second sub-electrodes.

[0015] The light emitting element may have a horizontal structure in which its first end and second end are on the same plane, and may include: a semiconductor structure including a first semiconductor layer, an active layer above the first semiconductor layer, and a second semiconductor layer above the active layer; a first contact electrode on the semiconductor structure and electrically connected to the first semiconductor layer at the second end; and a second contact electrode on the semiconductor structure and electrically connected to the second semiconductor layer at the first end.

[0016] The first semiconductor layer may include an n-type semiconductor layer doped with an n-type dopant, wherein the second semiconductor layer includes a p-type semiconductor layer doped with a p-type dopant.

[0017] The display device may also include: a first combining electrode, between the first end of the light emitting element and the first sub-electrode, and connecting the light emitting element and the first sub-electrode; and a second combining electrode, between the second end of the light emitting element and the second sub-electrode, and connecting the light emitting element and the second sub-electrode.

[0018] The display device may further include a cover layer over the light emitting element, an optical layer over the cover layer, and an overcoat layer over the optical layer.

[0019] One or more embodiments provide a display device, comprising: a substrate; a first electrode, which is above the substrate and includes two or more first sub-electrodes; a second electrode, which is above the substrate and includes two or more second sub-electrodes; a third electrode, which is spaced apart from the first electrode and the second electrode; a fourth electrode, which is spaced apart from the first electrode, the second electrode and the third electrode; a light-emitting element, which is electrically connected to the first electrode and the second electrode; a first bridging electrode, one end of which is electrically connected to the second sub-electrode and the other end of which is electrically connected to the third electrode; and a second bridging electrode, one end of which is electrically connected to the first sub-electrode and the other end of which is electrically connected to the fourth electrode.

[0020] The light emitting element may include a second end electrically connected to the first sub-electrode and a first end electrically connected to the second sub-electrode, the first end and the second end are on the same plane, wherein the p-type semiconductor layer is at the first end and the n-type semiconductor layer is at the second end.

[0021] The display device may also include: a pixel circuit layer above the substrate and including a transistor electrically connected to the third electrode; and a common line above the substrate and electrically connected to the fourth electrode, wherein the first sub-electrode is electrically connected to the fourth electrode and the common line through the second bridging electrode, and wherein the second sub-electrode is electrically connected to the third electrode and the transistor through the first bridging electrode.

[0022] The first sub-electrodes may be electrically connected to each other, wherein the second sub-electrodes may be electrically connected to each other.

[0023] In a repair method for a display device according to one or more embodiments, the display device may include: a substrate; a first electrode, which is above the substrate and includes two or more first sub-electrodes; a second electrode, which is electrically separated from the first electrode above the substrate and includes two or more second sub-electrodes; a third electrode, which is electrically connected to the first sub-electrode; a fourth electrode, which is electrically connected to the second sub-electrode; a first dummy electrode and a second dummy electrode, which are spaced apart from each other above the substrate; and a light-emitting element, which is electrically connected to the first sub-electrode and the second sub-electrode, and the repair method includes: using a laser to electrically separate the first sub-electrode and the third electrode from each other; using a laser to electrically separate the second sub-electrode and the fourth electrode from each other; forming a first bridging electrode connecting one end of the first dummy electrode to the second sub-electrode; connecting the other end of the first dummy electrode to the third electrode by laser welding; forming a second bridging electrode connecting one end of the second dummy electrode to the first sub-electrode; and connecting the other end of the second dummy electrode to the fourth electrode by laser welding.

[0024] The light emitting element may include a second end electrically connected to the first sub-electrode and the third electrode, and a first end electrically connected to the second sub-electrode and the fourth electrode, wherein the second end and the first end are on the same plane, wherein the p-type semiconductor layer is at the first end, and wherein the n-type semiconductor layer is at the second end.

[0025] The display device may also include: a pixel circuit layer above the substrate and including a transistor electrically connected to the third electrode; and a common line above the substrate and electrically connected to the fourth electrode, wherein the first sub-electrode is electrically connected to the fourth electrode and the common line through the second bridging electrode, and wherein the second sub-electrode is electrically connected to the third electrode and the transistor through the first bridging electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and together with the description serve to explain aspects of the disclosure.

[0027] Figure 1 is a schematic plan view showing a display device according to one or more embodiments.

[0028] Figure 2 yes Figure 1 Schematic cross-sectional view of a display panel.

[0029] Figure 3 It is shown that the Figure 1 A schematic circuit diagram showing the electrical connection relationship of the components in each of the pixels shown.

[0030] Figure 4 is a schematic plan view illustrating a sub-pixel according to one or more embodiments.

[0031] Figure 5 It is along Figure 4 A schematic cross-sectional view taken along line I-I' in FIG.

[0032] Figures 6 to 10 is a schematic plan view showing a sub-pixel according to an embodiment.

[0033] Fig.11A and Fig. 11B It is shown in Figure 4 Schematic plan view of the state of transferring the light-emitting element in a sub-pixel.

[0034] Fig.12 It is along Fig.11A A schematic cross-sectional view taken along line II to II' in FIG.

[0035] Fig.13 yes Fig.12 Schematic cross-sectional view of a light-emitting element.

[0036] Fig.14 It is along Fig.11A 1 is a schematic cross-sectional view taken along line II-II′ in FIG. 1 and illustrates a sub-pixel according to one or more embodiments.

[0037] Fig.15 It is along Fig.11A 1 is a schematic cross-sectional view taken along line II-II′ in FIG. 1 , and illustrates a sub-pixel including a defective light emitting element in which a defect occurs.

[0038] Fig.16 and Fig.17 It shows the repair Fig.15 Schematic plan view of a method for removing a defective light-emitting element. DETAILED DESCRIPTION

[0039] Aspects of some embodiments of the present disclosure and methods for implementing them can be more easily understood by reference to the detailed description of the embodiments and the accompanying drawings. These embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or unnecessary processes, elements and techniques for a complete understanding of aspects of the present disclosure by those of ordinary skill in the art can be omitted. Unless otherwise stated, in all drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0040] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments illustrated herein. The present disclosure encompasses all modifications, equivalents, and substitutions within the conceptual and technical scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined in part or in its entirety or in combination with one another, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0041] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, cross-hatching and / or shading are generally used in the drawings to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements.

[0042] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. In this way, deviations from the illustrated shapes, for example, due to manufacturing techniques and / or tolerances, are expected. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the illustrated shapes of elements, layers, or regions, but will include deviations in shapes, for example, caused by manufacturing.

[0043] For example, an implanted region shown as a rectangle will typically have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted region to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. In other examples, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring various embodiments.

[0044] For ease of explanation, spatial relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper side", etc. may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the figure. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as being "below", "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. The device can have another orientation (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this indicates that the first part is arranged at the upper or lower side of the second part, without being limited to its upper side based on the direction of gravity.

[0045] In addition, the phrase "in a plan view" means when the object portion is observed from above, and the phrase "in a schematic cross-sectional view" means when the schematic cross-sectional view obtained by vertically cutting the object portion is observed from the side. The term "overlap" or "overlapping" means that the first object can be above or below the second object, or on one side of the second object, and means that the second object can be above or below the first object, or on one side of the first object. In addition, the term "overlap" may include stacking, stacking, facing or facing, extending throughout, covering or partially covering, or any other suitable term as will be understood and appreciated by a person of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "separated from..." or "set beside..." or "offset from..." and any other suitable equivalents as will be understood and appreciated by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is inserted between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, but still facing each other.

[0046] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be formed directly on, or directly on, or directly connected to, or directly coupled to, another element, layer, region, or component, or indirectly formed on, or indirectly on, or indirectly connected to, or indirectly coupled to, another element, layer, region, or component such that there may be one or more intervening elements, layers, regions, or components. Additionally, this may generally mean direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it may be directly electrically connected or directly electrically coupled to another layer, region and / or component, or there may be an intermediate layer, region or component. However, "directly connected / directly coupled" or "directly on..." means that one component is directly connected / coupled to another component or on another component without an intermediate component. In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the situation that the part is "directly below" another part, but also includes the situation that another part exists between the part and another part. At the same time, other expressions describing the relationship between components, such as "between..." and "directly between..." or "adjacent to" and "directly adjacent to", can be similarly interpreted. In addition, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0047] For the purposes of this disclosure, when following an element of a list, expressions such as “at least one of…” or “any one of…” or “one or more of…” modify the elements of the entire list rather than modifying individual elements of the list. For example, “at least one of X, Y, and Z,” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, or only Y, or only Z, or any combination of two or more of X, Y, and Z (such as, for example, XYZ, XYY, YZ, and ZZ), or any variation thereof. Similarly, expressions such as “at least one of A and B” may include A, B, or A and B. As used herein, “or” generally means “and / or,” and the term “and / or” includes any and all combinations of one or more of the relevant listed items. For example, expressions such as “A and / or B” may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases, when preceding or following elements of a list, modify the entire list of elements and do not modify the individual elements of the list.

[0048] It will be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or advantage, but are only used to distinguish an element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first section described below can be referred to as the second element, second component, second area, second layer or second section. Describing an element as a "first" element may not require or may not imply the presence of a second element or other elements. The terms "first", "second", etc. may also be used in this article to distinguish between different categories or different groups of elements. For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0049] In the example, the first direction DR1, the second direction DR2 and / or the third direction DR3 are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2 and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0050] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprises", "comprising", "have", "having", "includes" and "including" specify the presence of the features, wholes, steps, operations, elements and / or parts described, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or combinations thereof.

[0051] When one or more embodiments can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described order.

[0052] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. In view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the value and means within an acceptable range of deviation of the particular value determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, "may" used in describing embodiments of the present disclosure means "one or more embodiments of the present disclosure."

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0054] Figure 1 is a schematic plan view showing a display device DD according to one or more embodiments. Figure 2 yes Figure 1 Schematic cross-sectional view of a display panel DP.

[0055] exist Figure 1 and Figure 2 , for convenience of description, the structure of the display device DD (eg, the display panel DP provided in the display device DD) is briefly illustrated centered on the display area DA that displays an image.

[0056] refer to Figure 1 and Figure 2 According to one or more embodiments, the display panel DP (or display device DD) may be configured in various shapes. For example, the display panel DP may have a rectangular plate shape having two pairs of sides parallel to each other. However, the present disclosure is not limited thereto. In the case where the display panel DP is configured in a rectangular plate shape, one pair of sides may be configured to be longer than the other pair of sides among the two pairs of sides. Figure 1 , a direction along which the long side extends is indicated as a second direction DR2, and a direction along which the short side extends is indicated as a first direction DR1.

[0057] At least a portion of the display panel DP may have flexibility and may be folded at the flexible portion, but the present disclosure is not limited thereto.

[0058] The display panel DP may display an image. The display panel DP may be a self-luminous display panel or a non-luminous display panel.

[0059] The display panel DP may include a substrate SUB and pixels PXL (or sub-pixels SPX) disposed in the substrate SUB.

[0060] The substrate SUB may include a transparent insulating material, but the present disclosure is not limited thereto.The substrate SUB may be a rigid substrate or a flexible substrate.

[0061] The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0062] The flexible substrate may be one of a film substrate and a plastic substrate including a polymerized organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the present disclosure is not limited thereto.

[0063] One area of ​​the substrate SUB may be set as a display area DA in which the pixel PXL may be positioned. The remaining area of ​​the substrate SUB may be set as a non-display area NDA. For example, the substrate SUB may include a display area DA including a pixel area in which each pixel PXL (or sub-pixel SPX) is positioned, and a non-display area NDA located around the display area DA (or adjacent to the display area DA).

[0064] The non-display area NDA may be positioned adjacent to the display area DA. The non-display area NDA may be disposed at at least one side of the display area DA. For example, the non-display area NDA may surround the periphery (or edge) of the display area DA. A wiring portion electrically connected to each pixel PXL and a driver electrically connected to the wiring portion to drive the pixel PXL may be disposed in the non-display area NDA.

[0065] The pixel PXL may be disposed in the display area DA of the substrate SUB. The pixel PXL may include a light emitting element that emits white light and / or colored light, and may include a pixel circuit for driving the light emitting element. The pixel circuit may include at least one transistor electrically connected to the light emitting element. The pixel PXL may emit light of one color among red, green, and blue, but the present disclosure is not limited thereto. The pixel PXL may emit light of one color among cyan, magenta, yellow, and white.

[0066] The pixel PXL may be provided in plurality and may be arranged in a matrix along a pixel row extending in a first direction DR1 and a pixel column extending in a second direction DR2 intersecting the first direction DR1. The arrangement form of the pixel PXL is not particularly limited, and the pixel PXL may be arranged in various forms. According to one or more embodiments, if a plurality of pixels PXL are provided, they may be provided with different areas (or sizes). For example, in the case where the pixel PXL emits light of different colors, the area (or size) and / or shape of the pixel PXL may be provided differently for each color.

[0067] The driver may control driving of the pixel PXL by providing a signal (eg, a predetermined signal) and a voltage (eg, a predetermined voltage) to each pixel PXL through a wiring portion.

[0068] The display panel DP (or pixel PXL) may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and a cover layer CVL.

[0069] The pixel circuit layer PCL may be located on the substrate SUB and may include a transistor and a signal line electrically connected to the transistor. For example, the transistor may have a structure in which a semiconductor pattern and a gate electrode are sequentially stacked and an insulating layer is interposed therebetween. The semiconductor pattern may include amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon, an organic semiconductor and / or an oxide semiconductor. The gate electrode may include at least one of aluminum (Al), copper (Cu), titanium (Ti) and molybdenum (Mo), but the present disclosure is not limited thereto. In addition, the pixel circuit layer PCL may include at least one insulating layer.

[0070] The display element layer DPL may be located on the pixel circuit layer PCL. The display element layer DPL may include a light emitting element for emitting light.

[0071] The cover layer CVL may be selectively located on the display element layer DPL.

[0072] The cover layer CVL may be arranged to cover the display element layer DPL, and may protect the display element layer DPL from external impact. The cover layer CVL may be a packaging substrate or packaging film composed of multiple layers. In the case where the cover layer CVL is a packaging film, it may include an inorganic film and / or an organic film. For example, the cover layer CVL may have a structure in which an inorganic layer, an organic layer, and an inorganic layer are stacked sequentially. The cover layer CVL may reduce or prevent air and moisture from penetrating from the outside into the display element layer DPL and the pixel circuit layer PCL.

[0073] Figure 3 It is shown that the Figure 1 Schematic circuit diagram of the electrical connection relationship of components in each of the pixels PXL shown.

[0074] exist Figure 3 In the figure, for the convenience of description, for example, a pixel PXL (or sub-pixel SPX) positioned in an i-th pixel row (or i-th horizontal line) and a j-th pixel column is shown, where i and j may be natural numbers greater than 0.

[0075] refer to Figures 1 to 3 The pixel PXL (or sub-pixel SPX) may include an emission unit EMU that generates light having brightness corresponding to the data signal. In addition, the pixel PXL may include a pixel circuit PXC for driving the emission unit EMU.

[0076] The emission unit EMU may include a light emitting element LD electrically connected between a first power line PL1 receiving a voltage of a first driving power source VDD and a second power line PL2 receiving a voltage of a second driving power source VSS. For example, the emission unit EMU may include a first electrode EL1 electrically connected to the first driving power source VDD via the pixel circuit PXC and via the first power line PL1, may include a second electrode EL2 electrically connected to the second driving power source VSS via the second power line PL2, and may include a light emitting element LD electrically connected between the first electrode EL1 and the second electrode EL2. In one or more embodiments, the first electrode EL1 may be an anode, and the second electrode EL2 may be a cathode.

[0077] The light emitting element LD may include a first terminal EP1 electrically connected to the first electrode EL1, and may include a second terminal EP2 electrically connected to the second electrode EL2. The first driving power supply VDD and the second driving power supply VSS may have different potentials. In this case, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to be higher than or equal to the threshold voltage of the light emitting element LD during the emission period of the pixel PXL.

[0078] As described above, the light emitting element LD may constitute an effective light source of the emitting unit EMU.

[0079] The light emitting element LD may emit light having a brightness corresponding to the driving current provided by the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may provide a driving current corresponding to the grayscale value of the corresponding frame data to the emission component EMU. The driving current provided to the emission component EMU may flow through the light emitting element LD. Therefore, the emission component EMU may emit light when the light emitting element LD emits light having a brightness corresponding to the driving current.

[0080] In the case where the pixel PXL (or subpixel SPX) is positioned in the i-th pixel row and the j-th pixel column in the display area DA, the pixel circuit PXC of the pixel PXL may be electrically connected to the i-th scan line Si and the j-th data line Dj.

[0081] The pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0082] The first transistor T1 may be a driving transistor for controlling a driving current applied to the light emitting element LD, and may be electrically connected between the first driving power source VDD and the light emitting element LD. For example, the first terminal of the first transistor T1 may be electrically connected to the first driving power source VDD through the first power source line PL1, the second terminal of the first transistor T1 may be electrically connected to the light emitting element LD, and the gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 may control the amount of driving current applied to the light emitting element LD from the first driving power source VDD according to the voltage applied to the first node N1. The first terminal of the first transistor T1 may be a source electrode, and the second terminal of the first transistor T1 may be a drain electrode.

[0083] The second transistor T2 may be a switching transistor that selects and activates the pixel PXL in response to a scan signal, and may be electrically connected between the j-th data line Dj and the first node N1. The first terminal of the second transistor T2 may be electrically connected to the j-th data line Dj, the second terminal of the second transistor T2 may be electrically connected to the first node N1 (or the gate electrode of the first transistor T1), and the gate electrode of the second transistor T2 may be electrically connected to the i-th scan line Si. The first terminal and the second terminal of the second transistor T2 may be different terminals. For example, if the first terminal is a source electrode, the second terminal may be a drain electrode.

[0084] If a scan signal of a gate-on voltage (e.g., a low level voltage) is provided from the i-th scan line Si to electrically connect the j-th data line Dj and the first node N1, the second transistor T2 may be turned on. In this case, a data signal of a corresponding frame may be provided to the j-th data line Dj. Therefore, the data signal may be transmitted to the first node N1. The data signal transmitted to the first node N1 may be charged into the storage capacitor Cst.

[0085] One electrode of the storage capacitor Cst may be electrically connected to the first driving power source VDD and the other electrode may be electrically connected to the first node N1. The storage capacitor Cst may charge a voltage corresponding to the data signal supplied to the first node N1 and may maintain the charged voltage until a data signal of the next frame is supplied.

[0086] Figure 3 A pixel circuit PXC is shown, which includes a second transistor T2 for transmitting a data signal to a pixel PXL (or a sub-pixel SPX), a storage capacitor Cst for storing the data signal, and a first transistor T1 for providing a driving current corresponding to the data signal to the light-emitting element LD. However, the present disclosure is not limited thereto. The structure of the pixel circuit PXC can be changed differently. For example, the pixel circuit PXC may also include at least one transistor element, such as a transistor element for compensating for a threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling the emission time of the light-emitting element LD, or other circuit elements such as a boost capacitor for raising the voltage of the first node N1.

[0087] In the following embodiments, for convenience of description, a horizontal direction on a plane (eg, in a plan view) is indicated as a first direction DR1, a vertical direction on the plane is indicated as a second direction DR2, and a vertical direction on a cross-sectional view is indicated as a third direction DR3.

[0088] Figure 4 is a schematic plan view showing a sub-pixel SPX according to one or more embodiments.

[0089] exist Figure 4 In the figure, for the convenience of description, illustration of components located below the third via layer VIA3 will be omitted.

[0090] refer to Figures 1 to 4 The sub-pixel SPX (or pixel PXL) may include first, second, third and fourth electrodes EL1, EL2, EL3 and EL4 spaced apart from each other on the third via layer VIA3. In addition, the sub-pixel SPX may further include a common line COL, a first dummy electrode DME1 and a second dummy electrode DME2.

[0091] The common line COL may have a closed ring shape surrounding the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 and the first and second dummy electrodes DME1 and DME2 in one area of ​​the display area DA in which the sub-pixel SPX is located. However, the present disclosure is not limited thereto, and the common line COL may be provided in various shapes. The common line COL may be electrically connected to the reference electrode 1 through the second contact hole CH2. Figure 3 Therefore, the voltage of the second driving power source VSS may be supplied to the common line COL.

[0092] The first dummy electrode DME1 may extend in the first direction DR1 and may be spaced apart from the common line COL, the second dummy electrode DME2, and the first, second, third, and fourth electrodes EL1, EL2, EL3, and EL4. Figure 3 ) In the process of the dark spot defect of the sub-pixel SPX that occurs when the reverse connection occurs, the first dummy electrode DME1 can be formed by a laser welding process as a first bridge electrode BRE1 that electrically connects the third electrode EL3 and the second electrode EL2 (refer to Fig.17 ).

[0093] The second dummy electrode DME2 may extend in the first direction DR1 and may be spaced apart from the common line COL, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4, and the first dummy electrode DME1. In the process of repairing the dark spot defect of the sub-pixel SPX that occurs if the light emitting element LD is reversely connected, the second dummy electrode DME2 may be formed as a second bridge electrode BRE2 (refer to FIG. 1 ) for electrically connecting the first electrode EL1 and the fourth electrode EL4 by a laser welding process. Fig.17 ).

[0094] The first electrode EL1 may be spaced apart from the common line COL. The first electrode EL1 may be electrically connected to the third electrode EL3 through the third connection line CNL3. The first electrode EL1 may have a bar shape extending in the second direction DR2, but the present disclosure is not limited thereto.

[0095] In one or more embodiments, the first electrode EL1 may include at least two first sub-electrodes. For example, the first electrode EL1 may include four first sub-electrodes. The four first sub-electrodes may include a 1-1st sub-electrode SUE1_1, a 1-2nd sub-electrode SUE1_2, a 1-3rd sub-electrode SUE1_3, and a 1-4th sub-electrode SUE1_4. The 1-1st sub-electrode SUE1_1, the 1-2nd sub-electrode SUE1_2, the 1-3rd sub-electrode SUE1_3, and the 1-4th sub-electrode SUE1_4 may be arranged along the first direction DR1 and may be electrically connected to each other through the first connection line CNL1.

[0096] The first connection line CNL1 may extend in the first direction DR1 and may be positioned between adjacent first sub-electrodes to electrically connect the first sub-electrodes to each other. For example, the first connection line CNL1 may be positioned between the 1-1st sub-electrode SUE1_1 and the 1-2nd sub-electrode SUE1_2, between the 1-2nd sub-electrode SUE1_2 and the 1-3rd sub-electrode SUE1_3, and / or between the 1-3rd sub-electrode SUE1_3 and the 1-4th sub-electrode SUE1_4, respectively. The first connection line CNL1 may be integrally formed with the 1-1st sub-electrode SUE1_1, the 1-2nd sub-electrode SUE1_2, the 1-3rd sub-electrode SUE1_3, and the 1-4th sub-electrode SUE1_4.

[0097] The width W1 of the 1-1st sub-electrode SUE1_1 (for example, the width in the first direction DR1), the width W1 of the 1-2nd sub-electrode SUE1_2 (for example, the width in the first direction DR1), the width W1 of the 1-3rd sub-electrode SUE1_3 (for example, the width in the first direction DR1), and the width W1 of the 1-4th sub-electrode SUE1_4 (for example, the width in the first direction DR1) may be the same, but the present disclosure is not limited thereto. According to one or more embodiments, one or more of the width W1 of the 1-1st sub-electrode SUE1_1, the width W1 of the 1-2nd sub-electrode SUE1_2, the width W1 of the 1-3rd sub-electrode SUE1_3, and the width W1 of the 1-4th sub-electrode SUE1_4 may be different from each other.

[0098] The second electrode EL2 may branch from the common line COL along the second direction DR2. The second electrode EL2 may be integrally formed with the common line COL and electrically connected to the common line COL. The second electrode EL2 may have a bar shape extending in the second direction DR2, but the present disclosure is not limited thereto. Since the common line COL is electrically connected to the second power line PL2 through the second contact hole CH2, the second electrode EL2 may be electrically connected to the second power line PL2. In one or more embodiments, the second electrode EL2 may be electrically connected to the second end EP2 (reference Figure 3 )'s cathode.

[0099] In one or more embodiments, the second electrode EL2 may include at least two second sub-electrodes. For example, the second electrode EL2 may include four second sub-electrodes. The four second sub-electrodes may include a 2-1st sub-electrode SUE2_1, a 2-2nd sub-electrode SUE2_2, a 2-3rd sub-electrode SUE2_3, and a 2-4th sub-electrode SUE2_4. The 2-1st sub-electrode SUE2_1, the 2-2nd sub-electrode SUE2_2, the 2-3rd sub-electrode SUE2_3, and the 2-4th sub-electrode SUE2_4 may be arranged along the first direction DR1 and may be electrically connected to each other through the second connection line CNL2.

[0100] The second connection line CNL2 may extend in the first direction DR1 and may be positioned between adjacent second sub-electrodes to electrically connect the second sub-electrodes to each other. The second connection line CNL2 may be positioned, for example, between the 2-1st sub-electrode SUE2_1 and the 2-2nd sub-electrode SUE2_2, between the 2-2nd sub-electrode SUE2_2 and the 2-3rd sub-electrode SUE2_3, and between the 2-3rd sub-electrode SUE2_3 and the 2-4th sub-electrode SUE2_4. The second connection line CNL2 may be integrally formed with the 2-1st sub-electrode SUE2_1, the 2-2nd sub-electrode SUE2_2, the 2-3rd sub-electrode SUE2_3, and the 2-4th sub-electrode SUE2_4.

[0101] The width W2 of the 2-1st sub-electrode SUE2_1 (for example, the width in the first direction DR1), the width W2 of the 2-2nd sub-electrode SUE2_2 (for example, the width in the first direction DR1), the width W2 of the 2-3rd sub-electrode SUE2_3 (for example, the width in the first direction DR1), and the width W2 of the 2-4th sub-electrode SUE2_4 (for example, the width in the first direction DR1) may be the same, but the present disclosure is not limited thereto. According to one or more embodiments, one or more of the width W2 of the 2-1st sub-electrode SUE2_1, the width W2 of the 2-2nd sub-electrode SUE2_2, the width W2 of the 2-3rd sub-electrode SUE2_3, and the width W2 of the 2-4th sub-electrode SUE2_4 may be different from each other.

[0102] In a plan view, the 1-1th sub-electrode SUE1_1 and the 2-4th sub-electrode SUE2_4 may be positioned to face each other in the first direction DR1, but the present disclosure is not limited thereto.

[0103] The third electrode EL3 may be spaced apart from the first electrode EL1, the second electrode EL2, and the common line COL. The third electrode EL3 may be electrically connected to the first electrode EL1 through the third connection line CNL3. For example, the third electrode EL3 may be electrically connected to the 1st-4th sub-electrode SUE1_4 through the third connection line CNL3.

[0104] The third connection line CNL3 may extend in the first direction DR1 and may be positioned between the third electrode EL3 and the 1st-4th sub-electrodes SUE1_4 to electrically connect the third electrode EL3 and the 1st-4th sub-electrodes SUE1_4. In one or more embodiments, the third electrode EL3, the third connection line CNL3, and the 1st-4th sub-electrodes SUE1_4 (or the first electrode EL1) may be integrally formed.

[0105] The third electrode EL3 may be electrically connected to the reference electrode through the first contact hole CH1. Figure 3 Some components of the pixel circuit PXC described above are, for example, electrically connected to the first transistor T1. Since the third electrode EL3 is electrically connected to the first electrode EL1 through the third connection line CNL3, the first electrode EL1 may be electrically connected to the first transistor T1. In one or more embodiments, the first electrode EL1 may be electrically connected to the first terminal EP1 (refer to Figure 3 ) anode.

[0106] The third electrode EL3 may include a first portion extending along the first direction DR1 and a second portion extending along the second direction DR2. A width W3 of the second portion of the third electrode EL3 (eg, a width in the first direction DR1) may be greater than a width W1 of the first sub-electrode, but the present disclosure is not limited thereto.

[0107] The fourth electrode EL4 may be spaced apart from the first electrode EL1, the second electrode EL2, and the third electrode EL3. The fourth electrode EL4 may branch from the common line COL along the second direction DR2. In one or more embodiments, the common line COL, the second electrode EL2, and the fourth electrode EL4 may be integrally formed. The fourth electrode EL4 may be electrically connected to the second power line PL2.

[0108] The fourth electrode EL4 may have a strip shape extending in the second direction DR2, but the present disclosure is not limited thereto. A width W4 (e.g., a width in the first direction DR1) of the fourth electrode EL4 may be greater than a width W2 of the second sub-electrode, but the present disclosure is not limited thereto. According to one or more embodiments, a width W2 of the second sub-electrode may be greater than a width W4 of the fourth electrode EL4.

[0109] In the following, we will mainly refer to Figure 5 A stack structure (or a cross-sectional view structure) of the sub-pixel SPX (or the pixel PXL) according to the above-described embodiment is described.

[0110] Figure 5 It is along Figure 4 A schematic cross-sectional view taken along line I-I' in FIG.

[0111] exist Figure 5 , one sub-pixel SPX (or pixel PXL) is simply illustrated such that each electrode is illustrated as a single-layer electrode and each insulating layer is illustrated as a single-layer insulating layer, but the present disclosure is not limited thereto.

[0112] refer to Figures 1 to 5 , the sub-pixel SPX may include a substrate SUB, a pixel circuit layer PCL located on the substrate SUB, and an electrode located on the pixel circuit layer PCL.

[0113] The substrate SUB may include a transparent insulating material. The substrate SUB may be a rigid substrate or a flexible substrate. The substrate SUB may include a first surface SF1 and a second surface SF2 opposite to each other in the third direction DR3. The first surface SF1 may be a surface on which the light emitting element LD (refer to FIG. 1 ) is mounted. Figure 3 ) and the second surface SF2 may be a surface on which an intermediate electrode CTE electrically connected to the flexible film is positioned.

[0114] The sub-pixel SPX (or pixel PXL) may include a third passivation layer PAS3, a fourth via layer VIA4, and a fourth passivation layer PAS4, which are sequentially stacked on or under the second surface SF2 of the substrate SUB in a direction opposite to the third direction DR3.

[0115] The third passivation layer PAS3 may be positioned on / under the second surface SF2 of the substrate SUB, may protect the second surface SF2 of the substrate SUB, and may planarize the second surface SF2. The third passivation layer PAS3 may be an inorganic insulating layer including an inorganic material. The third passivation layer PAS3 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) at least one of.

[0116] The intermediate electrode CTE may be located on the third passivation layer PAS3. The intermediate electrode CTE may provide a voltage or signal received from the flexible film to the side connection line through a lead. The intermediate electrode CTE may be electrically connected to the flexible film through a conductive member (or a connection film).

[0117] The intermediate electrode CTE may include a first intermediate electrode CTE1 and a second intermediate electrode CTE2. The first intermediate electrode CTE1 may be positioned on one surface (or lower surface) of the third passivation layer PAS3. The first intermediate electrode CTE1 may be a single layer or multiple layers made of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and alloys thereof. The second intermediate electrode CTE2 may be positioned on one surface (or lower surface) of the first intermediate electrode CTE1. The second intermediate electrode CTE2 may include a transparent conductive material (TCO), such as ITO or IZO.

[0118] The fourth through hole layer VIA4 may be located above / below a portion of the third passivation layer PAS3 and the intermediate electrode CTE. The fourth through hole layer VIA4 may be an organic insulating layer including an organic material. The fourth through hole layer VIA4 may include at least one of a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin. The fourth through hole layer VIA4 may planarize the second surface SF2 of the substrate SUB.

[0119] The fourth passivation layer PAS4 may be located on the fourth via layer VIA4 and the intermediate electrode CTE to protect the intermediate electrode CTE. The fourth passivation layer PAS4 may include the same material as the third passivation layer PAS3, or may include a suitable material selected from among the materials disclosed as materials constituting the third passivation layer PAS3.

[0120] The pixel circuit layer PCL may be disposed and / or formed on the first surface SF1 of the substrate SUB.

[0121] The pixel circuit PXC may be located in the pixel circuit layer PCL. The pixel circuit layer PCL may include at least one insulating layer located on the first surface SF1 of the substrate SUB. For example, the pixel circuit layer PCL may include a buffer layer BFL, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer ILD, a first through hole layer VIA1, a first passivation layer PAS1, a second through hole layer VIA2, a second passivation layer PAS2, and a third through hole layer VIA3, which are sequentially stacked on the first surface SF1 of the substrate SUB along a third direction DR3.

[0122] The buffer layer BFL may be entirely located on (eg, above) the first surface SF1 of the substrate SUB. The buffer layer BFL may reduce or prevent impurities from diffusing into the transistor T. The buffer layer BFL may be an inorganic insulating layer including an inorganic material. The buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) or may include at least one of aluminum oxide (Al x O y ) of the metal oxide. The buffer layer BFL may be provided as a single layer, or as a multilayer including a double layer. In the case where the buffer layer BFL is provided as a plurality of layers, each layer may be formed of the same material or a different material. Depending on the material and process conditions of the substrate SUB, the buffer layer BFL may be omitted.

[0123] The first gate insulating layer GI1 may be entirely located on / over the buffer layer BFL, but the present disclosure is not limited thereto. According to one or more embodiments, the first gate insulating layer GI1 may be partially located on / over the buffer layer BFL. The first gate insulating layer GI1 may include the same material as the buffer layer BFL described above, or may include a suitable material selected from the materials disclosed as materials constituting the buffer layer BFL. For example, the first gate insulating layer GI1 may include an inorganic insulating layer including an inorganic material.

[0124] The second gate insulating layer GI2 may be entirely located on / over the first gate insulating layer GI1, but the present disclosure is not limited thereto. According to one or more embodiments, the second gate insulating layer GI2 may be partially located on / over the first gate insulating layer GI1. The second gate insulating layer GI2 may include the same material as the first gate insulating layer GI1. For example, the second gate insulating layer GI2 may be an inorganic insulating layer including an inorganic material.

[0125] The interlayer insulating layer ILD may be entirely disposed and / or formed on / over the second gate insulating layer GI2. The interlayer insulating layer ILD may include the same material as the second gate insulating layer GI2, or may include one or more suitable materials selected from the materials disclosed as materials constituting the buffer layer BFL.

[0126] The first via layer VIA1 may be integrally disposed and / or formed on / over the interlayer insulating layer ILD. The first via layer VIA1 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ). The organic insulating layer may include, for example, at least one of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin. The first through-hole layer VIA1 may have a flat surface to mitigate the step difference caused by the components located therebelow. The first through-hole layer VIA1 may include an organic insulating layer including an organic material.

[0127] The first passivation layer PAS1 may be integrally disposed and / or formed on / over the first via layer VIA1. The first passivation layer PAS1 may be an inorganic insulating layer including an inorganic material. The first passivation layer PAS1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) at least one of.

[0128] The second via layer VIA2 may be integrally disposed and / or formed on / over the first passivation layer PAS1. The second via layer VIA2 may include the same material as the first via layer VIA1, or may include a suitable material selected from the materials disclosed as the material constituting the first via layer VIA1. For example, the second via layer VIA2 may be an organic insulating layer including an organic material.

[0129] The second passivation layer PAS2 may be integrally disposed and / or formed on / over the second via layer VIA2. The second passivation layer PAS2 may include the same material as the first passivation layer PAS1. The second passivation layer PAS2 may be an inorganic insulating layer including an inorganic material.

[0130] The third via layer VIA3 may be integrally disposed and / or formed on / over the second passivation layer PAS2. The third via layer VIA3 may include the same material as the first via layer VIA1. For example, the third via layer VIA3 may be an organic insulating layer including an organic material.

[0131] The pixel circuit layer PCL may include at least one conductive layer located between the insulating layers described above. For example, the pixel circuit layer PCL may include a first conductive layer located between the substrate SUB and the buffer layer BFL, a second conductive layer located between the first gate insulating layer GI1 and the second gate insulating layer GI2, a third conductive layer located between the second gate insulating layer GI2 and the interlayer insulating layer ILD, a fourth conductive layer located between the interlayer insulating layer ILD and the first via layer VIA1, a fifth conductive layer located between the first passivation layer PAS1 and the second via layer VIA2, and a sixth conductive layer located between the second passivation layer PAS2 and the third via layer VIA3.

[0132] The first conductive layer may be formed of a single layer, the single layer being made of one selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag) and alloys thereof, or a mixture thereof. Alternatively, the first conductive layer may be formed as a double-layer or multi-layer structure made of a low-resistance material such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) or silver (Ag) to reduce line resistance. Each of the second to sixth conductive layers may include the same material as the first conductive layer, or include one or more suitable materials selected from the materials disclosed as materials constituting the first conductive layer, but the present disclosure is not limited thereto.

[0133] The pixel circuit layer PCL may include a pixel circuit PXC and a plurality of electrodes and lines electrically connected to the pixel circuit PXC. For example, the pixel circuit layer PCL may include a lower metal pattern BML, a transistor T, a storage capacitor Cst, a connection electrode CCE, an anode connection line ACL, and a bridge pattern BRP. However, the present disclosure is not limited thereto.

[0134] The lower metal pattern BML may absorb or block light incident from the second surface SF2 of the substrate SUB to the pixel circuit PXC. The lower metal pattern BML may be a first conductive layer located between the substrate SUB and the buffer layer BFL. According to one or more embodiments, the lower metal pattern BML may be electrically connected to the transistor T. In this case, the driving range of the voltage (e.g., a predetermined voltage) provided to the gate electrode GE of the transistor T may be widened. In the case where the lower metal pattern BML is electrically connected to the transistor T, the channel area CHA of the transistor T may be stabilized. When the lower metal pattern BML is electrically connected to the transistor T, the floating of the lower metal pattern BML may be reduced or prevented.

[0135] The transistor T may include a semiconductor pattern and a gate electrode GE overlapping a region of the semiconductor pattern. For example, the transistor T may be a reference Figure 3 A first transistor T1 is described.

[0136] The semiconductor pattern may be located on / over the buffer layer BFL. The semiconductor pattern may include a channel area CHA, a first terminal TE1, and a second terminal TE2. The first terminal TE1 and the second terminal TE2 may become a conductor by heat treating the semiconductor pattern (or by doping the semiconductor pattern with high concentration impurities). For example, the semiconductor pattern may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. As another example, the semiconductor pattern may include a first active layer and a second active layer located on different layers. In this case, the first active layer may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, or amorphous silicon, and the second active layer may include an oxide semiconductor.

[0137] The gate electrode GE may be located on / over the first gate insulating layer GI1. The gate electrode GE may be a second conductive layer located between the first gate insulating layer GI1 and the second gate insulating layer GI2. The gate electrode GE may overlap with the channel area CHA of the semiconductor pattern. The first gate insulating layer GI1 located between the semiconductor pattern and the gate electrode GE may insulate the channel area CHA of the semiconductor pattern from the gate electrode GE.

[0138] The second conductive layer may include a lower electrode LE of the storage capacitor Cst.

[0139] According to one or more embodiments, the lower electrode LE may be electrically connected to the gate electrode GE of the transistor T.

[0140] The second conductive layer including the gate electrode GE and the lower electrode LE may be composed of a single layer or a plurality of layers. The second gate insulating layer GI2 may be located on / over the second conductive layer described above.

[0141] The upper electrode UE of the storage capacitor Cst may be located on / above the second gate insulating layer GI2. The upper electrode UE may be a third conductive layer positioned between the second gate insulating layer GI2 and the interlayer insulating layer ILD. The upper electrode UE may overlap with the lower electrode LE, and the second gate insulating layer GI2 is interposed between them to form a capacitor. In the case where the overlapping area of ​​the lower electrode LE and the upper electrode UE is large, the capacitance of the storage capacitor Cst may increase. The third conductive layer including the upper electrode UE may be composed of a single layer or multiple layers.

[0142] An interlayer insulating layer ILD may be located on / over the upper electrode UE.

[0143] The connection electrode CCE may be located on / over the interlayer insulating layer ILD. The connection electrode CCE may be a fourth conductive layer positioned between the interlayer insulating layer ILD and the first via layer VIA1. The connection electrode CCE may be connected to the second terminal TE2 of the transistor T through a contact hole penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1. The fourth conductive layer including the connection electrode CCE may be composed of a single layer or multiple layers.

[0144] The first via layer VIA1 may be located on / over the fourth conductive layer. The first via layer VIA1 may planarize an upper surface of the fourth conductive layer.

[0145] The first passivation layer PAS1 may be on / over the first via layer VIA1 .

[0146] The anode connection line ACL may be located on / over the first passivation layer PAS1. The anode connection line ACL may be a fifth conductive layer positioned between the first passivation layer PAS1 and the second via layer VIA2.

[0147] The anode connection line ACL may be electrically connected to the connection electrode CCE through a contact hole penetrating the first passivation layer PAS1 and the first via layer VIA1. The anode connection line ACL may be electrically connected to the second terminal TE2 of the transistor T through the connection electrode CCE.

[0148] The fifth conductive layer including the anode connection line ACL may be composed of a single layer or a plurality of layers.

[0149] The second via layer VIA2 may be located on / over the fifth conductive layer. The second via layer VIA2 may planarize an upper surface of the fifth conductive layer.

[0150] The second passivation layer PAS2 may be on / over the second via layer VIA2 .

[0151] The bridge pattern BRP may be located on / over the second passivation layer PAS2. The bridge pattern BRP may be a sixth conductive layer positioned between the second passivation layer PAS2 and the third through-hole layer VIA3. The bridge pattern BRP may be electrically connected to the anode connection line ACL through a contact hole penetrating the second passivation layer PAS2 and the second through-hole layer VIA2. The bridge pattern BRP may be electrically connected to the transistor T through the anode connection line ACL and the connection electrode CCE. The sixth conductive layer including the bridge pattern BRP may be composed of a single layer or multiple layers.

[0152] The pixel circuit layer PCL may include a first power line PL1 (refer to FIG. 1 ) to which a voltage of a first driving power source VDD is applied. Figure 3 ) and a second power supply line PL2 (reference Figure 3). For example, the first power line PL1 and the second power line PL2 may be located on / over the same layer as the bridge pattern BRP. For example, the first power line PL1 and the second power line PL2 may be a sixth conductive layer located on / over the second passivation layer PAS2.

[0153] The third via layer VIA3 may be entirely located on / over the sixth conductive layer. The third via layer VIA3 may flatten the upper surface of the sixth conductive layer. In one or more embodiments, the third via layer VIA3 may include a first contact hole CH1 exposing a portion of the bridge pattern BRP. In addition, the third via layer VIA3 may be partially opened to include a second contact hole CH2. For example, the third via layer VIA3 may include a second contact hole CH2 exposing a portion of the second power line PL2.

[0154] The seventh conductive layer may be located on / over the pixel circuit layer PCL having the configuration described above. The seventh conductive layer may include a first electrode EL1, a second electrode EL2, a third electrode EL3, a fourth electrode EL4, and a common line COL located on / over the third through hole layer VIA3 of the pixel circuit layer PCL. The seventh conductive layer may include a suitable material selected from the materials disclosed as the materials constituting the first conductive layer, and may be composed of a single layer or multiple layers.

[0155] The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be spaced apart from each other on the third through-hole layer VIA3. In one or more embodiments, the first electrode EL1 and the third electrode EL3 may be integrally formed to be electrically connected to each other. The second electrode EL2 and the fourth electrode EL4 may branch from the common line COL. The second electrode EL2, the fourth electrode EL4, and the common line COL may be integrally formed to be electrically connected to each other.

[0156] The third electrode EL3 may be electrically connected to some components of the pixel circuit layer PCL, such as the transistor T, through the first contact hole CH1 of the third via layer VIA3. The common line COL may be electrically connected to some components of the pixel circuit layer PCL, such as the second power line PL2, through the second contact hole CH2 of the third via layer VIA3.

[0157] In one or more embodiments, the first electrode EL1 may include four first sub-electrodes, and the second electrode EL2 may include four second sub-electrodes. For example, the first electrode EL1 may include a 1-1st sub-electrode SUE1_1, a 1-2nd sub-electrode SUE1_2, a 1-3rd sub-electrode SUE1_3, and a 1-4th sub-electrode SUE1_4. The second electrode EL2 may include a 2-1st sub-electrode SUE2_1, a 2-2nd sub-electrode SUE2_2, a 2-3rd sub-electrode SUE2_3, and a 2-4th sub-electrode SUE2_4.

[0158] In the above-described embodiment(s), the first electrode EL1 (or the first sub-electrode) may be electrically connected to the light emitting element LD (refer to Figure 3 ), and the second electrode EL2 (or the second sub-electrode) may be a cathode electrically connected to the second end EP2 of the light emitting element LD. According to one or more embodiments, each of the first electrode EL1 and the second electrode EL2 may be a binding electrode bound (coupled) to the light emitting element LD. Each of the first electrode EL1 and the second electrode EL2 may be a binding electrode bound to the light emitting element LD to electrically connect the light emitting element LD and the pixel circuit PXC.

[0159] The first electrode EL1 , the second electrode EL2 , the third electrode EL3 , the fourth electrode EL4 , the common line COL, the first dummy electrode DME1 , and the second dummy electrode DME2 may be formed by the same process, positioned at the same layer, and include the same material.

[0160] A seventh conductive layer including the first electrode EL1, the second electrode EL2, the third electrode EL3, the fourth electrode EL4, the common line COL, the first dummy electrode DME1 and the second dummy electrode DME2 may be located on the third through hole layer VIA3 and may be composed of a conductive material having a reflectivity (e.g., a predetermined reflectivity) so that light emitted from the light emitting element LD is reflected in the display device DD (see Figure 1 ) in the image display direction (or forward direction) of the display device DD. The conductive material may include an opaque metal, which is suitable for (or conducive to) reflecting the light emitted from the light emitting element LD in the image display direction (or desired direction) of the display device DD. The opaque metal may include, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti) or its alloy. According to one or more embodiments, the seventh conductive layer may include a transparent conductive material. The transparent conductive material may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO), conductive polymers (such as poly (3,4-ethylenedioxythiophene) (PEDOT)), etc. In the case where the seventh conductive layer includes a transparent conductive material, a separate conductive layer made of an opaque metal may be further included to reflect the light emitted from the light emitting element LD in the image display direction of the display device DD. However, the material of the seventh conductive layer is not limited to the above-described materials.

[0161] The seventh conductive layer may be provided and / or formed as a single layer, but the present disclosure is not limited thereto. According to one or more embodiments, the seventh conductive layer may be provided and / or formed as a multilayer structure in which at least two materials of metal, alloy, conductive oxide and conductive polymer are stacked. The seventh conductive layer may be formed of a multilayer including at least a double layer.

[0162] Will refer to it later FIG. 11A to FIG. 13 The sub-pixel SPX (or pixel PXL) including the light emitting element LD coupled to the first electrode EL1 and the second electrode EL2 is described in detail.

[0163] Figures 6 to 10 is a schematic plan view showing a sub-pixel SPX according to an embodiment.

[0164] Regarding the shapes of the first electrode EL1 and the second electrode EL2, Figures 6 to 10 Shown with Figure 4 Corresponding modified examples of one or more embodiments.

[0165] about Figures 6 to 10 In order to avoid overlapping descriptions, the implementation methods of the present invention will mainly be described except for the differences from the implementation methods described above.

[0166] refer to Figure 6 The subpixel SPX (or pixel PXL) may include first, second, third and fourth electrodes EL1, EL2, EL3 and EL4 spaced apart from each other on the third via layer VIA3. In addition, the subpixel SPX may include a common line COL, a first dummy electrode DME1 and a second dummy electrode DME2.

[0167] The first electrode EL1 may include a 1-1st sub-electrode SUE1_1, a 1-2nd sub-electrode SUE1_2, a 1-3rd sub-electrode SUE1_3, and a 1-4th sub-electrode SUE1_4. The 1-1st sub-electrode SUE1_1, the 1-2nd sub-electrode SUE1_2, the 1-3rd sub-electrode SUE1_3, and the 1-4th sub-electrode SUE1_4 may be arranged along the first direction DR1 and may be electrically connected to each other through a first connection line CNL1. The 1-1st sub-electrode SUE1_1, the 1-2nd sub-electrode SUE1_2, the 1-3rd sub-electrode SUE1_3, and the 1-4th sub-electrode SUE1_4 may be arranged along the first direction DR1 and may be electrically connected to each other through a fourth connection line CNL4. The first connection line CNL1 may be positioned at one end (e.g., one end adjacent to the second dummy electrode DME2) of each of the 1-1st sub-electrode SUE1_1, the 1-2nd sub-electrode SUE1_2, the 1-3rd sub-electrode SUE1_3, and the 1-4th sub-electrode SUE1_4. The fourth connection line CNL4 may be positioned at a central region of each of the 1-1st sub-electrode SUE1_1, the 1-2nd sub-electrode SUE1_2, the 1-3rd sub-electrode SUE1_3, and the 1-4th sub-electrode SUE1_4 in a direction in which it extends. The positions of the first connection line CNL1 and the fourth connection line CNL4 are not limited to the above.

[0168] The first electrode EL1 including the 1-1 sub-electrode SUE1_1, the 1-2 sub-electrode SUE1_2, the 1-3 sub-electrode SUE1_3, and the 1-4 sub-electrode SUE1_4 electrically connected to each other through the first connection line CNL1 and the fourth connection line CNL4 may have a mesh shape in a plan view. In the first electrode EL1 including the 1-1 sub-electrode SUE1_1, the 1-2 sub-electrode SUE1_2, the 1-3 sub-electrode SUE1_3, and the 1-4 sub-electrode SUE1_4 connected to each other through the first connection line CNL1 and the fourth connection line CNL4, even if a short-circuit defect or the like occurs in some of the first sub-electrodes, a signal (for example, a predetermined signal) may be provided to the light emitting element LD (reference signal) through the remaining first sub-electrodes Figure 3 )'s first end EP1.

[0169] The second electrode EL2 may include a 2-1st sub-electrode SUE2_1, a 2-2nd sub-electrode SUE2_2, a 2-3rd sub-electrode SUE2_3, and a 2-4th sub-electrode SUE2_4. The 2-1st sub-electrode SUE2_1, the 2-2nd sub-electrode SUE2_2, the 2-3rd sub-electrode SUE2_3, and the 2-4th sub-electrode SUE2_4 may be arranged along the first direction DR1 and may be electrically connected to each other through the second connection line CNL2. The 2-1st sub-electrode SUE2_1, the 2-2nd sub-electrode SUE2_2, the 2-3rd sub-electrode SUE2_3, and the 2-4th sub-electrode SUE2_4 may be arranged along the first direction DR1 and may be electrically connected to each other through the fifth connection line CNL5.

[0170] The second electrode EL2 including the 2-1st sub-electrode SUE2_1, the 2-2nd sub-electrode SUE2_2, the 2-3rd sub-electrode SUE2_3, and the 2-4th sub-electrode SUE2_4 electrically connected to each other through the second connection line CNL2 and the fifth connection line CNL5 may have a grid shape in a plan view. In the second electrode EL2 including the 2-1st sub-electrode SUE2_1, the 2-2nd sub-electrode SUE2_2, the 2-3rd sub-electrode SUE2_3, and the 2-4th sub-electrode SUE2_4 connected to each other through the second connection line CNL2 and the fifth connection line CNL5, even if a short circuit defect or the like occurs in some of the second sub-electrodes, a signal (e.g., a predetermined signal) may be provided to the second end EP2 of the light emitting element LD through the remaining second sub-electrodes.

[0171] According to one or more embodiments, Figure 7 As shown, the four second sub-electrodes included in the second electrode EL2 may be electrically connected to each other without a separate connection line extending in the first direction DR1. Each of the four second sub-electrodes may be formed integrally with the common line COL and may branch from the common line COL in the second direction DR2. In this case, the four second sub-electrodes may be one region of the common line COL.

[0172] According to one or more embodiments, Figure 8As shown, the first electrode EL1 may include two first sub-electrodes spaced apart from each other. For example, the first electrode EL1 may include a 1-1 sub-electrode SUE1_1 and a 1-2 sub-electrode SUE1_2 spaced apart from each other. The first connection line CNL1 may be positioned between the 1-1 sub-electrode SUE1_1 and the 1-2 sub-electrode SUE1_2, and the 1-1 sub-electrode SUE1_1 and the 1-2 sub-electrode SUE1_2 may be electrically connected to each other through the first connection line CNL1. The 1-1 sub-electrode SUE1_1, the 1-2 sub-electrode SUE1_2, and the first connection line CNL1 may be integrally formed. In this case, the first connection line CNL1 may be considered as a region of the 1-1 sub-electrode SUE1_1 or a region of the 1-2 sub-electrode SUE1_2. In one or more embodiments, the 1-1 sub-electrode SUE1_1 and the 1-2 sub-electrode SUE1_2 may have the same width in the first direction DR1, but the present disclosure is not limited thereto.

[0173] Similarly, if Figure 8 As shown, the second electrode EL2 may include two second sub-electrodes spaced apart from each other. For example, the second electrode EL2 may include a 2-1st sub-electrode SUE2_1 and a 2-2nd sub-electrode SUE2_2 spaced apart from each other. The second connection line CNL2 may be positioned between the 2-1st sub-electrode SUE2_1 and the 2-2nd sub-electrode SUE2_2. The 2-1st sub-electrode SUE2_1 and the 2-2nd sub-electrode SUE2_2 may be electrically connected to each other through the second connection line CNL2. The 2-1st sub-electrode SUE2_1, the 2-2nd sub-electrode SUE2_2, and the second connection line CNL2 may be formed integrally. In this case, the second connection line CNL2 may be considered as a region of the 2-1st sub-electrode SUE2_1 or a region of the 2-2nd sub-electrode SUE2_2. In one or more embodiments, the 2-1st sub-electrode SUE2_1 and the 2-2nd sub-electrode SUE2_2 may have the same width in the first direction DR1, but the present disclosure is not limited thereto.

[0174] The first electrode EL1 may include a plurality of first sub-electrodes, wherein at least one first sub-electrode has a different width from the remaining first sub-electrodes. Fig. 9As shown, the first electrode EL1 may include a 1-1th sub-electrode SUE1_1, a 1-2th sub-electrode SUE1_2, and a 1-3th sub-electrode SUE1_3, and a width W5 (e.g., a width in the first direction DR1) of the 1-1th sub-electrode SUE1_1 may be greater than a width W1 of the 1-2nd sub-electrode SUE1_2 and the 1-3rd sub-electrode SUE1_3. The width W5 of the 1-1st sub-electrode SUE1_1 may be less than a width W3 of the third electrode EL3, but the present disclosure is not limited thereto. According to one or more embodiments, the width W5 of the 1-1st sub-electrode SUE1_1 may be equal to or greater than a width W3 of the third electrode EL3. According to one or more other embodiments, the width W5 of the 1-1st sub-electrode SUE1_1 may be less than a width W1 of the 1-2nd sub-electrode SUE1_2 and the 1-3rd sub-electrode SUE1_3. In addition, among the 1-1st sub-electrode SUE1_1, the 1-2nd sub-electrode SUE1_2, and the 1-3rd sub-electrode SUE1_3, the 1-2nd sub-electrode SUE1_2 or the 1-3rd sub-electrode SUE1_3 may have a greater width than the remaining first sub-electrode.

[0175] The second electrode EL2 may include a plurality of second sub-electrodes, wherein at least one second sub-electrode has a different width from the remaining second sub-electrodes. Fig. 9 As shown, the second electrode EL2 may include a 2-1st sub-electrode SUE2_1, a 2-2nd sub-electrode SUE2_2, and a 2-3rd sub-electrode SUE2_3, and a width W6 (e.g., a width in the first direction DR1) of the 2-1st sub-electrode SUE2_1 may be greater than a width W2 of the 2-2nd sub-electrode SUE2_2 and the 2-3rd sub-electrode SUE2_3. The width W6 of the 2-1st sub-electrode SUE2_1 may be less than a width W4 of the fourth electrode EL4, but the present disclosure is not limited thereto. According to one or more embodiments, the width W6 of the 2-1st sub-electrode SUE2_1 may be equal to or greater than a width W4 of the fourth electrode EL4. According to one or more other embodiments, the width W6 of the 2-1st sub-electrode SUE2_1 may be less than a width W2 of the 2-2nd sub-electrode SUE2_2 and the 2-3rd sub-electrode SUE2_3. Among the 2-1st sub-electrode SUE2_1, the 2-2nd sub-electrode SUE2_2, and the 2-3rd sub-electrode SUE2_3, the 2-2nd sub-electrode SUE2_2 or the 2-3rd sub-electrode SUE2_3 may have a greater width than the remaining second sub-electrode.

[0176] Although one or more embodiments have been described in which the first electrode EL1 includes a plurality of first sub-electrodes and the second electrode EL2 includes a plurality of second sub-electrodes, the present disclosure is not limited thereto. Fig.10As shown, the first electrode EL1 may be composed of one first sub-electrode SUE1, and the second electrode EL2 may be composed of one second sub-electrode SUE2. The first electrode EL1 (or the first sub-electrode SUE1) may be electrically connected to the third electrode EL3 through the connection line CNL, and the second electrode EL2 (or the second sub-electrode SUE2) may branch from the common line COL in the second direction DR2 together with the fourth electrode EL4. The width W7 (for example, the width in the first direction DR1) of the first electrode EL1 (or the first sub-electrode SUE1) may be greater than the width W3 of the third electrode EL3, but the present disclosure is not limited thereto. The width W8 (for example, the width in the first direction DR1) of the second electrode EL2 (or the second sub-electrode SUE2) may be greater than the width W4 of the fourth electrode EL4, but the present disclosure is not limited thereto.

[0177] Fig.11A and Fig. 11B It is shown in Figure 4 A schematic plan view of a state in which the light-emitting element LD is transferred in the sub-pixel SPX. Fig.12 It is along Fig.11A A schematic cross-sectional view taken along line II to II' in FIG. Fig.13 yes Fig.12 Schematic cross-sectional view of a light emitting element LD.

[0178] Fig.11A and Fig. 11B The embodiments of FIG. 1 show different embodiments related to the alignment position of the light emitting element LD. For example, Fig.11A One or more embodiments are shown in which the light emitting element LD is aligned between the first electrode EL1 and the second electrode EL2 in a direction parallel to the first direction DR1, and Fig. 11B One or more embodiments are shown in which the light emitting element LD is aligned between the first electrode EL1 and the second electrode EL2 in a direction inclined with respect to the first direction DR1 (or the second direction DR2 ).

[0179] about FIG. 11A to FIG. 13 In order to avoid overlapping descriptions, the implementation methods of the present invention will mainly be described except for the differences from the implementation methods described above.

[0180] refer to FIG. 11A to FIG. 13 , the sub-pixel SPX (or pixel PXL) may include a substrate SUB, a pixel circuit layer PCL and a display element layer DPL.

[0181] The display element layer DPL may include electrodes, common lines COL, dummy electrodes, and light emitting elements LD.

[0182] The electrodes may include a first electrode EL1, a second electrode EL2, a third electrode EL3, and a fourth electrode EL4 spaced apart from each other on a third through hole layer VIA3 of the pixel circuit layer PCL. The first electrode EL1 and the third electrode EL3 may be electrically connected to each other through a third connection line CNL3. The second electrode EL2 and the fourth electrode EL4 may branch from the common line COL in the second direction DR2 and may be electrically connected to each other. The first electrode EL1 may include a 1-1st sub-electrode SUE1_1, a 1-2nd sub-electrode SUE1_2, a 1-3rd sub-electrode SUE1_3, and a 1-4th sub-electrode SUE1_4. The second electrode EL2 may include a 2-1st sub-electrode SUE2_1, a 2-2nd sub-electrode SUE2_2, a 2-3rd sub-electrode SUE2_3, and a 2-4th sub-electrode SUE2_4.

[0183] In a plan view, the common line COL may be provided in a form surrounding the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4, and may be electrically connected to the reference electrode through a second contact hole CH2 penetrating the third via layer VIA3. Figure 3 Described second driving power supply VSS.

[0184] The dummy electrodes may include first and second dummy electrodes DME1 and DME2 spaced apart from the common line COL and the electrodes. The first and second dummy electrodes DME1 and DME2 may be positioned on the third via layer VIA3 and may be electrically insulated from the first, second, third, and fourth electrodes EL1, EL2, EL3, and EL4 and the common line COL unless the light emitting element LD is reversely connected between the electrodes and a repair process is required.

[0185] The light emitting element LD may be coupled to the first electrode EL1 and the second electrode EL2, respectively. Fig.13 As shown, the light emitting element LD may include a semiconductor structure 10, a first contact electrode 15, and a second contact electrode 16. The semiconductor structure 10 may be formed by mesa-etching the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 after sequentially forming the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. The light emitting element LD having a package shape may be formed by sequentially forming the first contact electrode 15 and the second contact electrode 16 on the semiconductor structure 10, but the present disclosure is not limited thereto.

[0186] In the light emitting element LD, the length in the vertical direction, the length in the horizontal direction, and the length in the thickness direction of the substrate SUB may be several micrometers to hundreds of micrometers, respectively.

[0187] The light emitting element LD may be formed by growing on a semiconductor substrate (such as a silicon wafer). The light emitting element LD may be directly transferred to the first electrode EL1 and the second electrode EL2 of the display element layer DPL on the silicon wafer. Alternatively, the light emitting element LD may be transferred to the first electrode EL1 and the second electrode EL2 of the display element layer DPL by an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material (such as PDMS) or silicon as a transfer substrate.

[0188] In one or more embodiments, the light emitting element LD may include a first end EP1 contacting the first electrode EL1 (or the first sub-electrode), and a second end EP2 contacting the second electrode EL2 (or the second sub-electrode). The light emitting element LD may be a light emitting element (or a light emitting diode) having a horizontal structure in which the first end EP1 and the second end EP2 are located on the same plane. The second contact electrode 16 electrically connected to the second semiconductor layer 13 may be positioned at the first end EP1, and the first contact electrode 15 electrically connected to the first semiconductor layer 11 may be positioned at the second end EP2.

[0189] The semiconductor structure 10 may emit light through recombination of electrons and holes according to current flowing between the first contact electrode 15 and the second contact electrode 16. The semiconductor structure 10 may include a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13.

[0190] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may be an n-type semiconductor layer including at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductive dopant (or n-type dopant, such as Si, Ge, Sn, Se, etc.). However, the material constituting the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 may be formed of various other materials. In one or more embodiments, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant).

[0191] The active layer 12 (or light emitting layer) may be located on a portion of one surface of the first semiconductor layer 11. The active layer 12 may include a material having a single quantum well structure or a multiple quantum well structure. In the case where the active layer 12 includes a material having a multiple quantum well structure, the active layer 12 may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but the present disclosure is not limited thereto. Alternatively, the active layer 12 may have a structure in which a semiconductor material having a high energy band gap is alternately stacked with a semiconductor material having a low energy band gap, and may include group III to group V semiconductor materials according to the wavelength range of the emitted light. The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0192] The second semiconductor layer 13 may be located on one surface of the active layer 12, and may provide holes to the active layer 12. The second semiconductor layer 13 may include a semiconductor layer of a different type from the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer including at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant (or p-type dopant), such as Mg, Zn, Ca, Ba, etc. However, the material constituting the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be formed of various other materials. In one or more embodiments, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant).

[0193] The first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 may be arranged on a semiconductor substrate in a sequentially stacked structure. Here, the semiconductor substrate may include a semiconductor material, such as a sapphire substrate or a silicon substrate. After the semiconductor substrate is used as a growth substrate for growing the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the semiconductor substrate may be separated from the first semiconductor layer 11 by a process of separating the substrate. Here, the process of separating the substrate may be a laser lift-off method, a chemical lift-off method, or the like. When the growth substrate is removed from the semiconductor structure 10, the semiconductor structure 10 may have a thin thickness. The semiconductor structure 10 described above may have a size as small as micrometers (or micrometers), but the present disclosure is not limited thereto.

[0194] The first contact electrode 15 may be disposed and / or formed on the semiconductor structure 10. For example, the first contact electrode 15 may be disposed and / or formed on the first semiconductor layer 11 to be electrically separated from the active layer 12 and the second semiconductor layer 13. The first contact electrode 15 may be in ohmic contact with the first semiconductor layer 11. In one or more embodiments, the first contact electrode 15 may be positioned at the second end EP2 (or n-type end) of the light emitting element LD and may contact the second bonding electrode BDE2 for bonding.

[0195] The second contact electrode 16 may be disposed and / or formed on the semiconductor structure 10. For example, the second contact electrode 16 may be disposed and / or formed on the second semiconductor layer 13. The second contact electrode 16 may be in ohmic contact with the second semiconductor layer 13. In one or more embodiments, the second contact electrode 16 may be positioned at the first end EP1 (or p-type end) of the light emitting element LD and may contact the first bonding electrode BDE1 for bonding.

[0196] The first contact electrode 15 and the second contact electrode 16 may include a conductive material. For example, the first contact electrode 15 and the second contact electrode 16 may include an opaque metal, wherein chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni) and oxides or alloys thereof are used alone or in combination, but the present disclosure is not limited thereto. According to one or more embodiments, the first contact electrode 15 and the second contact electrode 16 may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO). According to one or more embodiments, the first contact electrode 15 and the second contact electrode 16 may be a solder bump.

[0197] According to one or more embodiments, the light emitting element LD may further include an insulating film surrounding the outer peripheral surface of the semiconductor structure 10 .

[0198] The light emitting element LD may be coupled (connected) to the first electrode EL1 and the second electrode EL2 through a coupling electrode. For example, the first end EP1 (or p-type end) of the light emitting element LD may be coupled to the first electrode EL1 (or the first sub-electrode) through the first coupling electrode BDE1. The second end EP2 (or n-type end) of the light emitting element LD may be coupled to the second electrode EL2 (or the second sub-electrode) through the second coupling electrode BDE2. Each of the first coupling electrode BDE1 and the second coupling electrode BDE2 may be selected from a group including gold (Au) and tin (Sn) having a suitable coupling strength (or adhesive strength) to facilitate the generation and growth of intermetallic compounds, but the present disclosure is not limited thereto. According to one or more embodiments, the first coupling electrode BDE1 and the second coupling electrode BDE2 may be omitted.

[0199] The light emitting element LD may be located on the third through hole layer VIA3 so that the first end EP1 (or the first combined electrode BDE1) of the light emitting element LD is positioned on the first electrode EL1, and the second end EP2 (or the second combined electrode BDE2) of the light emitting element LD is positioned on the second electrode EL2. After the light emitting element LD transferred to the transfer substrate by the conveying mechanism or the like is moved over the first electrode EL1 and the second electrode EL2, the light emitting element LD may be re-transferred to the first electrode EL1 and the second electrode EL2.

[0200] The light emitting element LD may overlap with the first electrode EL1 and the second electrode EL2, and the first end EP1 and the second end EP2 of the light emitting element LD may be aligned facing each other between the third electrode EL3 and the fourth electrode EL4 in a direction parallel to the first direction DR1, but the present disclosure is not limited thereto. According to one or more embodiments, the first end EP1 and the second end EP2 of the light emitting element LD may be aligned facing each other between the third electrode EL3 and the fourth electrode EL4 in a direction inclined relative to the first direction DR1 (or the second direction DR2).

[0201] In the case where the first end EP1 (or p-type end) of the light emitting element LD is positioned on the first electrode EL1 and the second end EP2 (or n-type end) of the light emitting element LD is positioned on the second electrode EL2, the light emitting element LD and the corresponding electrodes may be electrically connected to each other by a bonding process using a suitable bonding method. As the bonding method, for example, an anisotropic conductive film (AFC) bonding method, a laser assisted bonding (LAB) method, an ultrasonic bonding method, a convex ball surface mounting (ball grid array, BGA) method, a pressure and heat bonding (thermocompression bonding, TC) method, etc. may be used, but the present disclosure is not limited thereto.

[0202] In the case where the first end EP1 (or p-type end) of the light emitting element LD is electrically connected to the first electrode EL1 and the second end EP2 (or n-type end) of the light emitting element LD is electrically connected to the second electrode EL2, the light emitting element LD may be forward connected between the first electrode EL1 and the second electrode EL2. Figure 3 ) flows to the second power line PL2 (reference Figure 3 ), the driving current may flow to the third electrode EL3 and the first electrode EL1 electrically connected to the third electrode EL3 through the first contact hole CH1. Therefore, the light emitting element LD may emit light having a brightness corresponding to the driving current.

[0203] In one or more embodiments, because the first electrode EL1 that contacts and is electrically connected to the first end EP1 (or the first combined electrode BDE1) of the light emitting element LD includes a plurality of first sub-electrodes, and because the second electrode EL2 that contacts and is electrically connected to the second end EP2 (or the second combined electrode BDE2) of the light emitting element LD includes a plurality of second sub-electrodes, a plurality of current paths for current to flow from the first electrode EL1 to the second electrode EL2 can be provided. Therefore, even if the first end EP1 of the light emitting element LD contacts at least some of the first sub-electrodes, and / or the second end EP2 of the light emitting element LD contacts at least some of the second sub-electrodes, each end of the light emitting element LD and the corresponding electrode can be stably electrically connected to each other. Therefore, the reliability of the sub-pixel SPX (or the display device DD) can be improved.

[0204] After the light emitting element LD is transferred onto the first electrode EL1 and the second electrode EL2, a light emitting inspection may be performed on the light emitting element LD. If there is no defect in the light emitting element LD, the sub-pixel SPX (or the display device DD) may be completed. However, if the light emitting element LD does not emit light during the light emitting inspection, and the sub-pixel SPX is visually identified as a dark spot defect, a repair process may be performed depending on the type of defect in the light emitting element LD. For example, in the process of transferring the light emitting element LD onto the first electrode EL1 and the second electrode EL2, due to conditions within the device (e.g., alignment accuracy) or air flow in the environment within the device, the light emitting element LD may be reversely connected between the first electrode EL1 and the second electrode EL2, and a dark spot defect may occur in the sub-pixel SPX. In this case, a repair process may be performed to change the direction of the current in the sub-pixel SPX to the opposite direction so that the current flows through the reversely connected light emitting element LD. The following will refer to Figures 15 to 17 The repair process of the reverse-connected light emitting element LD is described in detail.

[0205] Fig.14 It is along Fig.11A 1 is a schematic cross-sectional view taken along line II-II′ in FIG. 1 and illustrates a sub-pixel SPX according to one or more embodiments.

[0206] About Fig.14 In order to avoid overlapping descriptions, the corresponding one or more embodiments will mainly describe the differences from the above-described embodiments.

[0207] refer to Fig.11A and Fig.14 , the sub-pixel SPX may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL and an overcoat layer OC.

[0208] The display element layer DPL may include first, second, third and fourth electrodes EL1, EL2, EL3 and EL4, first and second dummy electrodes DME1 and DME2, a common line COL, a light emitting element LD, a cover layer CVL and an optical layer OTL.

[0209] The covering layer CVL may be located on the seventh conductive layer including the first electrode EL1, the second electrode EL2, the third electrode EL3 and the fourth electrode EL4, the first dummy electrode DME1 and the second dummy electrode DME2, the common line COL and the light emitting element LD to cover the seventh conductive layer and the light emitting element LD. The covering layer CVL may be a packaging substrate or a packaging film composed of a plurality of layers. The covering layer CVL may reduce or prevent oxygen and moisture from entering the light emitting element LD and the pixel circuit layer PCL from the outside. According to one or more embodiments, the covering layer CVL may be a planarization layer that mitigates the step difference caused by the components located therebelow.

[0210] The optical layer OTL may be located on the cover layer CVL.

[0211] The optical layer OTL may convert the light emitted from the light emitting element LD into light having appropriate color reproducibility, and may output the light, thereby improving the light output efficiency of each sub-pixel SPX (or each pixel PXL). The optical layer OTL may include a color filter layer having a color filter and a light blocking pattern. According to one or more embodiments, the optical layer OTL may include a color conversion layer having color conversion particles that convert the light emitted from the light emitting element LD into light of a corresponding color (or light having appropriate color reproducibility).

[0212] The overcoat layer OC may be located on the optical layer OTL. The overcoat layer OC may cover the lower member including the optical layer OTL. The overcoat layer OC may protect the above-described lower member from foreign substances such as dust.

[0213] Fig.15 It is along Fig.11A 1 is a schematic cross-sectional view taken along line II-II′ in FIG. 1 and illustrates a sub-pixel SPX including a defective light emitting element LD′ in which a defect occurs. Fig.16 and Fig.17 It shows the repair Fig.15 Schematic plan view of a method for producing a defective light emitting element LD'.

[0214] refer to Figures 15 to 17 , the sub-pixel SPX (or the pixel PXL) may include a defective light emitting element LD′ reversely connected between the first electrode EL1 and the second electrode EL2.

[0215] As reference FIG. 11A to FIG. 13As described above, since the first end EP1 (or the first combined electrode BDE1) contacts and is electrically connected to the second electrode EL2, and the second end EP2 (or the second combined electrode BDE2) contacts and is electrically connected to the first electrode EL1 in the process of transferring the light emitting element LD to the first electrode EL1 and the second electrode EL2, the defective light emitting element LD' may be a reverse light emitting element with a bad alignment direction. The defective light emitting element LD' may be connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to the correctly oriented light emitting element LD. Therefore, even if a driving voltage (e.g., a predetermined driving voltage, such as a forward driving voltage) is applied between the first electrode EL1 and the second electrode EL2, the defective light emitting element LD' may remain in an inactive state, and thus current may substantially not flow.

[0216] The sub-pixel SPX including the defective light emitting element LD' may be visually identified as a dark spot defect, and a repair process may be performed to resolve the dark spot defect. The repair process may be performed using a laser. In the repair process, for example, the electrical connection between the first electrode EL1 and the third electrode EL3 and the electrical connection between the second electrode EL2 and the fourth electrode EL4 may be disconnected by using a laser, and then the corresponding electrodes and the corresponding dummy electrodes may be electrically connected to each other by a laser welding process.

[0217] like Fig.16 As shown, in the first electrode separation area ESA1 between the first electrode EL1 (or the first sub-electrode) and the third electrode EL3, the third connection line CNL3 (reference Fig.11A ), so as to electrically separate the first electrode EL1 and the third electrode EL3. In addition, in the second electrode separation area ESA2 between the second electrode EL2 (or the second sub-electrode) and the common line COL, a portion of the second electrode EL2 (or each second sub-electrode) may be removed by using a laser to electrically separate the second electrode EL2 and the common line COL. Therefore, the second electrode EL2 and the fourth electrode EL4 may be electrically separated (or disconnected) from each other.

[0218] The third electrode EL3 may be electrically connected to the transistor T through the first contact hole CH1 of the third via layer VIA3, and the fourth electrode EL4 may be electrically connected to the second driving power source VSS (reference line COL) through the second contact hole CH2 of the third via layer VIA3. Figure 3 ). The first electrode EL1 (or the first sub-electrode) electrically separated from the third electrode EL3 and the second electrode EL2 (or the second sub-electrode) electrically separated from the fourth electrode EL4 may be floated.

[0219] As described above, after the first electrode EL1 and the second electrode EL2 are floated by disconnecting the electrical connection between the electrodes using laser, a process of electrically connecting the first dummy electrode DME1 and the second dummy electrode DME2 to the first electrode EL1 and the second electrode EL2 using laser may be performed. Fig.17 As shown, a first bridging electrode BRE1 electrically connecting the third electrode EL3 and the second electrode EL2, and a second bridging electrode BRE2 electrically connecting the fourth electrode EL4 and the first electrode EL1 may be formed. The first bridging electrode BRE1 may be formed by a laser welding process, so that one end (or the first end) of the first dummy electrode DME1 is connected to the second electrode EL2 (for example, the 2nd-4th sub-electrode SUE2_4), and the other end (or the second end) of the first dummy electrode DME1 is connected to the third electrode EL3. The second bridging electrode BRE2 may be formed by a laser welding process, so that one end (or the first end) of the second dummy electrode DME2 is connected to the first connection line CNL1 (or the first sub-electrode), and the other end (or the second end) of the second dummy electrode DME2 is connected to the fourth electrode EL4.

[0220] The second electrode EL2 may be electrically connected to the third electrode EL3 through the first bridging electrode BRE1, and the first electrode EL1 may be electrically connected to the fourth electrode EL4 through the second bridging electrode BRE2. Therefore, the second electrode EL2 may be electrically connected to the transistor T of the pixel circuit layer PCL through the third electrode EL3 and the first contact hole CH1 of the third through-hole layer VIA3, and the first electrode EL1 may be electrically connected to the second driving power source VSS through the fourth electrode EL4 and the second contact hole CH2 of the third through-hole layer VIA3. Therefore, current may flow between the second electrode EL2 and the first electrode EL1. For example, current may flow from the second electrode EL2 to the first electrode EL1. In this case, the second electrode EL2 may be an anode, and the first electrode EL1 may be a cathode. In this way, by repairing the sub-pixel SPX in which a dark spot defect has occurred, the direction of the current flowing from the first electrode EL1 to the second electrode EL2 may be changed to the direction of the current flowing from the second electrode EL2 to the first electrode EL1. Therefore, the defective light-emitting element LD' may be connected in the forward direction between the second electrode EL2 and the first electrode EL1. Therefore, the reliability of the display device DD can be improved by repairing the sub-pixel SPX in which the dark spot defect has occurred, so that the defective light emitting element LD′ can be driven as the light emitting element LD which is an effective light source.

[0221] Generally (e.g., conventionally), if a dark spot defect occurs in the sub-pixel SPX due to a defective light emitting element LD' reversely connected between the first electrode EL1 and the second electrode EL2, a repair process of removing the defective light emitting element LD' with a laser and re-transferring another light emitting element LD to the first electrode EL1 and the second electrode EL2 may be performed. In this case, a process of removing the defective light emitting element LD' and a process of re-transferring another light emitting element LD to the first electrode EL1 and the second electrode EL2 may be added. Therefore, the manufacturing efficiency of the display device DD may be reduced, and the light emitting element LD may be unnecessarily wasted, thereby increasing the manufacturing cost of the display device DD.

[0222] However, in the above-described embodiment, after the light emitting element LD is transferred to the first electrode EL1 and the second electrode EL2, if the light emitting element LD is determined to be a defective light emitting element LD' that is reversely connected between the first electrode EL1 and the second electrode EL2, the electrical connection between the first electrode EL1 and the third electrode EL3 and the electrical connection between the second electrode EL2 and the fourth electrode EL4 can be disconnected, and the direction of the current flowing from the first electrode EL1 to the second electrode EL2 can be changed to the direction of the current flowing from the second electrode EL2 to the first electrode EL1 by forming the first bridging electrode BRE1 and the second bridging electrode BRE2. Therefore, the sub-pixel SPX in which the dark spot defect has occurred can be properly repaired. Therefore, other defective light emitting elements LD' can be driven as light emitting elements LD that are effective light sources. According to the above-described embodiment, the manufacturing efficiency of the display device DD can be improved, and the manufacturing cost of the display device DD can be reduced by reducing or preventing unnecessary waste of the light emitting element LD.

[0223] According to the display device and the repair method thereof according to the embodiment of the present disclosure, even if a dark spot defect occurs in a sub-pixel, the reliability of the display device can be improved by appropriately repairing the defective light emitting element.

[0224] According to an embodiment of the present disclosure, instead of replacing a defective light-emitting element that is reversely connected between electrodes, a portion of the electrode can be removed by using a laser, and the electrode is connected to a dummy electrode (or a bridge electrode) by a laser welding process, thereby connecting the defective light-emitting element forward between the electrodes. Therefore, by using a defective light-emitting element as an effective light source, unnecessary waste of the light-emitting element can be reduced or prevented, and thus the manufacturing cost of the display device can be reduced.

[0225] According to the embodiment of the present disclosure, since a plurality of sub-electrodes contacting and electrically connected to each end of a light emitting element are provided, a plurality of current paths can be provided between the light emitting element and the sub-electrodes, and thus the reliability of the display device can be improved.

[0226] Aspects according to the embodiments are not limited to the above disclosed contents, and more various aspects are included in the present specification.

[0227] As described above, the best embodiment of the present disclosure has been disclosed through the detailed description and the accompanying drawings. However, those skilled in the art or those of ordinary skill in the art will appreciate that various modifications and changes are possible without departing from the technical scope of the present disclosure as set forth in the appended claims.

[0228] Therefore, the technical protection scope of the present disclosure is not limited to the detailed description in the specification, but should be determined by the appended claims.

Claims

1. Display device, It is characterized in that The display device comprises: substrate; a first electrode, a second electrode, a third electrode, and a fourth electrode, the first electrode and the third electrode being integrally formed to be electrically connected to each other, the second electrode and the fourth electrode being integrally formed to be electrically connected to each other, and the first electrode, the second electrode, the third electrode, and the fourth electrode being spaced apart from each other over the substrate; a first dummy electrode and a second dummy electrode spaced apart from each other over the substrate and electrically insulated from the first electrode, the second electrode, the third electrode, and the fourth electrode; and A light emitting element is electrically connected to the first electrode and the second electrode.

2. The display device according to claim 1, It is characterized in that The display device further includes: a pixel circuit layer over the substrate and including a transistor electrically connected to the third electrode; and A common line is formed over the substrate and integrally with the second electrode and the fourth electrode to be electrically connected to the second electrode and the fourth electrode.

3. The display device according to claim 2, It is characterized in that The first electrode includes two or more first sub-electrodes spaced apart from each other, wherein the second electrode comprises two or more second sub-electrodes spaced apart from each other, and The first sub-electrodes are electrically connected to each other, and the second sub-electrodes are electrically connected to each other.

4. The display device according to claim 3, It is characterized in that The display device further includes: a first connection line, which is above the substrate and electrically connects the first sub-electrodes; and A second connecting line is above the substrate and electrically connects the second sub-electrodes.

5. The display device according to claim 3, It is characterized in that The light emitting element has a horizontal structure with a first end and a second end thereof being on the same plane, and comprises: A semiconductor structure comprising a first semiconductor layer, an active layer above the first semiconductor layer, and a second semiconductor layer above the active layer; a first contact electrode on the semiconductor structure and electrically connected to the first semiconductor layer at the second end; and A second contact electrode is on the semiconductor structure and electrically connected to the second semiconductor layer at the first end.

6. The display device according to claim 5, It is characterized in that The first semiconductor layer includes an n-type semiconductor layer doped with an n-type dopant, and The second semiconductor layer includes a p-type semiconductor layer doped with a p-type dopant.

7. The display device according to claim 6, It is characterized in that The display device further includes: a first combining electrode between the first end of the light emitting element and the first sub-electrode and coupling the light emitting element with the first sub-electrode; and The second combining electrode is between the second end of the light emitting element and the second sub-electrode, and couples the light emitting element and the second sub-electrode.

8. Display device, It is characterized in that The display device comprises: substrate; a first electrode, over the substrate, and comprising two or more first sub-electrodes; a second electrode, over the substrate, and comprising two or more second sub-electrodes; a third electrode spaced apart from the first electrode and the second electrode; a fourth electrode spaced apart from the first electrode, the second electrode and the third electrode; a light emitting element electrically connected to the first electrode and the second electrode; a first bridging electrode having one end electrically connected to the second sub-electrode and the other end electrically connected to the third electrode; and A second bridging electrode has one end electrically connected to the first sub-electrode and the other end electrically connected to the fourth electrode.

9. The display device according to claim 8, It is characterized in that The light emitting element includes a second end electrically connected to the first sub-electrode and a first end electrically connected to the second sub-electrode, the first end and the second end are on the same plane, and Wherein, a p-type semiconductor layer is at the first end, and an n-type semiconductor layer is at the second end.

10. The display device according to claim 9, It is characterized in that The display device further includes: a pixel circuit layer over the substrate and including a transistor electrically connected to the third electrode; and a common line over the substrate and electrically connected to the fourth electrode, wherein the first sub-electrode is electrically connected to the fourth electrode and the common line through the second bridge electrode, and The second sub-electrode is electrically connected to the third electrode and the transistor through the first bridge electrode.

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