Display device

Abstract

A display device is disclosed. The display device includes: a substrate including a display area in which a plurality of emission areas configured to emit light for displaying an image are arranged; a plurality of light emitting units positioned on the substrate and respectively corresponding to the plurality of emission regions; and a partition wall on the substrate, corresponding to a non-emission region that is a boundary between the plurality of emission regions, and having a variable width in at least one direction. The partition wall includes a plate corresponding to the non-emission region; and a post protruding from at least a portion of the plate to each of the plurality of emission regions, and having a width greater than a width of the plate. Accordingly, the display device may prevent easy deformation of the partition wall while reducing luminance degradation due to the partition wall.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2022-0172320 filed in the Korean Intellectual Property Office on December 12, 2022, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0003] As the information age progresses, the demand for display devices for displaying images has increased in many different forms. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigators, and smart TVs.

[0004] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light emitting display device.

[0005] Examples of the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro light-emitting display device including a micro light-emitting element. Utility Model Content

[0006] The display device may include a plurality of light emitting units corresponding to a plurality of emission areas for emitting light for displaying an image, and a partition wall surrounding the light emitting unit. However, as the width of the partition wall increases, the width of the light emitting unit decreases, thereby reducing the brightness. On the other hand, as the width of the partition wall decreases, it is easier to deform the partition wall, thereby reducing the display quality, lifespan, and yield.

[0007] Therefore, an object of the present invention is to provide a display device which can prevent easy deformation of a partition wall while reducing brightness degradation caused by the partition wall.

[0008] The display device may include at least one light-emitting element disposed on a pixel electrode corresponding to each of the emission regions. However, due to misalignment, the light-emitting element may not be disposed on the central portion of the pixel electrode, but may be disposed on a portion of the edge of the pixel electrode. That is, not all of the misaligned light-emitting elements can be supported by the pixel electrode. In this case, since the common electrode is difficult to be disposed flatly on the light-emitting element, defects such as fracture or increased local resistance may occur.

[0009] Therefore, aspects and features of embodiments of the present disclosure also provide a display device that can prevent defects of a common electrode due to misaligned light emitting elements and a method of manufacturing the display device.

[0010] However, the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects and features of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0011] According to one or more embodiments of the present disclosure, a display device may include: a substrate including a display area, in which a plurality of emission areas configured to emit light for displaying an image are arranged; a plurality of light-emitting units positioned on the substrate and corresponding to the plurality of emission areas, respectively; and a partition wall on the substrate corresponding to a non-emission area as a boundary between the plurality of emission areas and having a variable width in at least one direction, wherein the partition wall may include: a plate corresponding to the non-emission area; and a column protruding from at least a portion of the plate to each of the plurality of emission areas and having a width greater than a width of the plate, wherein each of the plurality of light-emitting units may include: a light-emitting element on the substrate, wherein a minimum distance between the columns corresponding to both sides of any one of the plurality of light-emitting units may be greater than a width of the light-emitting element.

[0012] Each of the plurality of light emitting units may have a light emitting surface configured to emit light and a rear surface opposite to the light emitting surface, wherein the rear surface of each of the plurality of light emitting units may have at least one corner or at least one side having a shape corresponding to the shape of the partition wall.

[0013] In the thickness direction of the substrate, the height of each pillar may be equal to the height of the board, and the light emitting surface of each of the plurality of light emitting units may have at least one corner or at least one side in a shape corresponding to that of the pillar.

[0014] Each pillar may correspond to corners of four adjacent light emitting units, and a light emitting surface and a rear surface of each of the plurality of light emitting units may have a quadrangular shape with each corner formed by the pillar.

[0015] Each column may correspond to a corner of two light emitting units adjacent to each other in one direction, and the light emitting surface and the rear surface of each of the plurality of light emitting units may be formed in a quadrilateral shape in which corners corresponding to both ends of one side extending in one direction are formed by columns.

[0016] Each column corresponds to a corner of two light emitting units adjacent to each other in one direction and a portion of one side of a light emitting unit that may be adjacent to the two light emitting units in another direction, and the light emitting surface and the rear surface of each of the plurality of light emitting units may have a quadrilateral shape in which corners corresponding to both ends of one side extending in one direction and a portion of the other side extending in one direction are formed by the columns.

[0017] Each pillar may be between two adjacent light emitting units, and a light emitting surface and a rear surface of each of the plurality of light emitting units may include a combination of curved sides convex toward a center of the light emitting unit.

[0018] 2n columns can be positioned side by side between two light-emitting units adjacent in one direction, and can include a first column having a cross-sectional shape protruding toward one of the two adjacent light-emitting units and a second column having a cross-sectional shape protruding toward the other of the two adjacent light-emitting units, wherein n can be a natural number of 1 or greater, the first column and the second column can be alternately arranged between the two adjacent light-emitting units, and the first column and the second column adjacent to each other can be point symmetrical to each other, wherein the plate can correspond to the space between the two light-emitting units adjacent in another direction and the space between the first column and the second column, and the light-emitting surface and the rear surface of each of the plurality of light-emitting units can have a quadrilateral shape, the quadrilateral shape including one side formed by the first column and the other side facing the one side and formed by the second column.

[0019] The height of each pillar may be less than that of the board, the rear surface of each of the plurality of light emitting units may be surrounded by the pillar, and the light emitting surface of each of the plurality of light emitting units may be surrounded by the board and may have a width greater than that of the rear surface.

[0020] In a thickness direction of the substrate, a height of each pillar may be smaller than a light emission height of the light emitting element, and the light emission height may correspond to an angle at which light is emitted from the light emitting element.

[0021] According to one or more embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate including a display area, in which a plurality of emission areas configured to emit light for displaying an image are arranged; a plurality of light-emitting units on the substrate and corresponding to the plurality of emission areas, respectively; and a partition wall on the substrate corresponding to a non-emission area as a boundary between the plurality of emission areas and having a variable width in at least one direction. The partition wall comprises: a plate corresponding to the non-emission area; and a column protruding from at least a portion of the plate to each of the plurality of emission areas and having a width greater than the width of the plate.

[0022] Each of the plurality of light-emitting units includes: a light-emitting element disposed on a substrate; and a light-controlling layer disposed on the substrate to cover the light-emitting element and configured to control the characteristics of light emitted from the light-emitting element. Each of the plurality of light-emitting units has a light-emitting surface corresponding to the light-controlling layer and configured to emit light and a rear surface opposite to the light-emitting surface. The rear surface of each of the light-emitting units has at least one corner or at least one side having a shape corresponding to the shape of the partition wall.

[0023] A minimum distance between the pillars corresponding to both sides of any one of the light emitting units is greater than a width of the light emitting element.

[0024] In the thickness direction of the substrate, the height of each pillar is equal to the height of the board, and the light emitting surface of each of the plurality of light emitting units has at least one corner or at least one side in a shape corresponding to that of the pillar.

[0025] Each column corresponds to the corners of four adjacent light emitting units. The light emitting surface and the rear surface of each of the plurality of light emitting units are in a quadrilateral shape with each corner formed by the column.

[0026] Each column corresponds to a corner of two light emitting units adjacent to each other in one direction. The light emitting surface and the rear surface of each of the light emitting units are formed into a quadrilateral shape in which corners corresponding to both ends of one side extending in one direction are formed by the column.

[0027] Each column corresponds to a corner of two light emitting units adjacent to each other in one direction and a portion of one side of a light emitting unit adjacent to the two light emitting units in another direction. The light emitting surface and the rear surface of each of the light emitting units have a quadrilateral shape in which corners corresponding to both ends of one side extending in one direction and a portion of the other side extending in one direction are formed by the column.

[0028] Each column is between two adjacent light emitting units. The light emitting surface and the rear surface of each of the plurality of light emitting units include a combination of curved sides convex toward the center of the light emitting unit.

[0029] 2n columns are positioned side by side between two adjacent light-emitting units. The 2n columns include a first column having a cross-sectional shape protruding toward one of the two adjacent light-emitting units in one direction and a second column having a cross-sectional shape protruding toward the other of the two adjacent light-emitting units, wherein n is a natural number of 1 or greater. The first column and the second column are alternately arranged between the two adjacent light-emitting units. The first column and the second column adjacent to each other are point-symmetrical to each other.

[0030] The plate corresponds to the space between two light emitting units adjacent in another direction and the space between the first column and the second column. The light emitting surface and the rear surface of each of the plurality of light emitting units have a quadrilateral shape including one side formed by the first column and another side facing the side and formed by the second column.

[0031] The height of each column is less than the height of the board. The rear surface of each of the light emitting units is surrounded by the columns. The light emitting surface of each of the light emitting units is surrounded by the board and has a width greater than the width of the rear surface.

[0032] In the thickness direction of the substrate, the height of each pillar is less than the light emission height of the light emitting element. The light emission height corresponds to the angle at which light is emitted from the light emitting element.

[0033] Each column has a predetermined width.

[0034] Each column includes an inclined surface facing the light emitting element, and has a width that gradually decreases toward the board.

[0035] Each column includes a curved surface facing the light emitting element, and has a width that gradually decreases toward the board.

[0036] The partition wall further includes a buffer between each column and the plate. The buffer has a width smaller than a width of each column and larger than a width of the plate.

[0037] The height of each column is less than the height of the board. The rear surface of each of the plurality of light emitting units is surrounded by the board and the column. The light emitting surface of each of the plurality of light emitting units is surrounded by the board and has a width greater than the width of the rear surface.

[0038] Each pillar corresponds to the corners of four adjacent light emitting units. A rear surface of each of the plurality of light emitting units has a quadrilateral shape with each corner formed by the pillar.

[0039] The display device also includes: a pixel electrode on the substrate and corresponding to each of the multiple emission areas; a pixel connection electrode between the pixel electrode and the light-emitting element; a common connection electrode on the substrate and corresponding to the non-emission area; a planarization layer between the common connection electrode and the partition wall; an insulating layer covering the side surface of each of the pixel electrode, the pixel connection electrode, the light-emitting element, the common connection electrode, the planarization layer and the partition wall; a common electrode corresponding to the emission area and the non-emission area and covering the insulating layer; and a reflective layer corresponding to the side surface of each of the pixel electrode, the pixel connection electrode, the light-emitting element, the common connection electrode, the insulating layer and the partition wall and on the common electrode.

[0040] A portion of the partition wall includes the same layer as that of the light emitting element.

[0041] According to another aspect of the present disclosure, a display device is provided, which includes: a substrate including a display area, in which a plurality of emission areas are arranged; a plurality of pixel electrodes on the substrate and respectively corresponding to the plurality of emission areas; a plurality of dummy patterns on the substrate and corresponding to non-emission areas between the plurality of emission areas; a plurality of light-emitting elements corresponding to the plurality of emission areas; a planarization layer between the plurality of light-emitting elements and covering the plurality of pixel electrodes and the plurality of dummy patterns; and a common electrode on the plurality of light-emitting elements and the planarization layer and corresponding to the plurality of emission areas and the non-emission areas.

[0042] The plurality of light emitting elements are spaced apart from each other by a distance within the same range in at least one direction. Each of the plurality of emission regions corresponds to two or more of the plurality of light emitting elements. Two or more light emitting elements corresponding to an emission region among the plurality of emission regions are on a pixel electrode of the emission region.

[0043] Among two or more light emitting elements corresponding to the emission area, some light emitting elements at an edge of the emission area are supported by dummy patterns adjacent to the edge of the emission area among the plurality of dummy patterns.

[0044] One or more dummy patterns are between two pixel electrodes adjacent to each other in one direction. The dummy patterns between two pixel electrodes adjacent to each other in one direction are positioned parallel to the two pixel electrodes and spaced apart from the two pixel electrodes.

[0045] Each of the plurality of light emitting elements has a first width in one direction. The pixel electrodes are spaced apart from each other by a first distance in one direction. The first distance is greater than the first width.

[0046] The pixel electrode of the emission area and the dummy pattern adjacent to the emission area are spaced apart from each other by a second distance in one direction. The second distance is less than half of the first width.

[0047] Each of the plurality of dummy patterns has a second width in one direction, and a sum of the second width and the second distance is greater than half of the first width.

[0048] When one dummy pattern among the plurality of dummy patterns is between two pixel electrodes adjacent to each other along one direction, a sum of the second width and twice the second distance is smaller than the first distance.

[0049] A dummy pattern adjacent to the emission region among the plurality of dummy patterns has a thickness within the same range as a thickness of the pixel electrode of the emission region.

[0050] The plurality of dummy patterns include the same material as that of the pixel electrode.

[0051] The plurality of dummy patterns include an insulating material.

[0052] The display device further comprises a transistor array layer on the substrate, and comprises a plurality of thin film transistors corresponding to the plurality of emission regions and a via layer covering the plurality of thin film transistors. The pixel electrode and the dummy pattern are on the via layer of the transistor array layer.

[0053] The display device further includes: a color conversion array layer on the common electrode; and a color filter layer on the color conversion array layer. The plurality of emission regions include a first emission region corresponding to a first color, a second emission region corresponding to a second color in a wavelength band lower than that of the first color, and a third emission region corresponding to a third color in a wavelength band lower than that of the second color. The color conversion array layer includes a first color conversion pattern corresponding to the first emission region and including a first color conversion member configured to convert at least a portion of light emitted from the plurality of light emitting elements into light of the first color, a second color conversion pattern corresponding to the second emission region and including a second color conversion member configured to convert at least a portion of light emitted from the light emitting elements into light of the second color, and a partition wall pattern corresponding to the non-emission region. The color filter layer includes a first color filter corresponding to the first emission region and configured to transmit light of the first color, a second color filter corresponding to the second emission region and configured to transmit light of the second color, a third color filter corresponding to the third emission region and configured to transmit light of the third color, and a light blocking pattern corresponding to the non-emission region.

[0054] The plurality of light emitting elements are configured to emit light of a third color. The color conversion array layer further includes a transmission pattern corresponding to the third emission area and configured to transmit the light emitted from the plurality of light emitting elements.

[0055] The plurality of light emitting elements are configured to emit light in a wavelength band lower than a wavelength band of a third color. The color conversion array layer further includes a third color conversion pattern corresponding to the third emission region and including a third color conversion member configured to convert at least a portion of the light emitted from the plurality of light emitting elements into light of the third color.

[0056] According to one or more embodiments of the present disclosure, a method for manufacturing a display device is provided, the method comprising: preparing a substrate including a display area in which a plurality of emission areas are arranged, and arranging a transistor array layer including a plurality of thin film transistors corresponding to the plurality of emission areas and a via layer covering the plurality of thin film transistors on the substrate; arranging a plurality of pixel electrodes corresponding to the plurality of emission areas and a plurality of dummy patterns corresponding to non-emission areas between the plurality of emission areas on the via layer; preparing a light emitting element array layer positioned on an auxiliary substrate and including a plurality of light emitting elements corresponding to the plurality of emission areas; arranging the light emitting element array layer on the plurality of pixel electrodes, and removing the auxiliary substrate; arranging a planarization layer to fill spaces between the plurality of light emitting elements and to cover the plurality of pixel electrodes and the plurality of dummy patterns; arranging a common electrode corresponding to the plurality of emission areas on the plurality of light emitting elements and the planarization layer; arranging a color conversion array layer on the common electrode; and arranging a color filter layer on the color conversion array layer.

[0057] In the step of arranging a plurality of pixel electrodes and a plurality of dummy patterns, the plurality of pixel electrodes are spaced apart from each other by a first distance in one direction. The pixel electrodes among the plurality of pixel electrodes adjacent to each other in one direction and the dummy patterns among the plurality of dummy patterns are spaced apart from each other by a second distance. The step of preparing a light-emitting element array layer comprises: arranging a semiconductor epitaxial layer on a growth substrate, the semiconductor epitaxial layer comprising a first semiconductor layer of a first conductivity type stacked sequentially, an active layer of a quantum well structure, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of an undoped semiconductor; preparing a plurality of semiconductor structures by patterning the semiconductor epitaxial layer, each of the plurality of semiconductor structures having a first width in one direction; attaching an auxiliary substrate to the semiconductor structure; removing the growth substrate from the semiconductor structure; preparing a light-emitting element by arranging a connecting electrode on each of the semiconductor structures; increasing the distance between the light-emitting elements by stretching the auxiliary substrate; and preparing a light-emitting element array layer in which the light-emitting elements are spaced apart from each other by a third distance in the one direction.

[0058] In the step of arranging a light emitting element array layer on the pixel electrode, two or more light emitting elements corresponding to emission areas among the plurality of emission areas are arranged on the pixel electrode of the emission area, and the first distance is greater than the first width.

[0059] In the step of arranging a plurality of pixel electrodes and the plurality of dummy patterns, each of the plurality of dummy patterns has a second width in the one direction, one or more dummy patterns are between two pixel electrodes adjacent to each other in one direction among the plurality of pixel electrodes, and the dummy pattern between two pixel electrodes adjacent to each other in one direction is parallel to the two pixel electrodes, spaced apart from each of the two pixel electrodes and spaced apart from one of the two pixel electrodes by a second distance in one direction, and in the step of arranging a light emitting element array layer on the pixel electrode, some of the two or more light emitting elements corresponding to one emission area on an edge of one emission area are supported by the dummy pattern adjacent to the edge of one emission area.

[0060] The second distance is less than half of the first width, the sum of the second width and the second distance is greater than half of the first width, and when a dummy pattern is between two pixel electrodes adjacent to each other along one direction, the sum of the second width and twice the second distance is less than the first distance.

[0061] In the step of arranging the plurality of pixel electrodes and the plurality of dummy patterns, the dummy pattern adjacent to one emission region has a thickness within the same range as a thickness of the pixel electrode of the one emission region.

[0062] In the step of arranging a color conversion array layer, the color conversion array layer includes a first color conversion pattern, a second color conversion pattern, and a partition wall pattern, the first color conversion pattern corresponding to the first emission area and including a first color conversion member configured to convert at least a portion of light emitted from the plurality of light emitting elements into light of a first color, the second color conversion pattern corresponding to the second emission area and including a second color conversion member configured to convert at least a portion of light emitted from the light emitting elements into light of a second color, and the partition wall pattern corresponding to the non-emission area, and in the step of arranging a color filter layer, the color filter layer includes: a first color filter corresponding to the first emission area a light-converting pattern corresponding to the non-emitting area and configured to transmit light of the first color; a second color filter corresponding to the second emission area and configured to transmit light of the second color; a third color filter corresponding to the third emission area and configured to transmit light of the third color; and a light blocking pattern corresponding to the non-emitting area, wherein the color conversion array layer further includes one of a transmission pattern and a third color conversion pattern, the transmission pattern corresponding to the third emission area and configured to transmit light emitted from the light emitting element, and the third color conversion pattern corresponding to the third emission area and including a third color conversion member configured to convert at least a portion of light emitted from the plurality of light emitting elements into light of a third color.

[0063] The display device according to the embodiment includes a plurality of light emitting units respectively corresponding to a plurality of emission areas and a partition wall corresponding to a non-emission area as a boundary between the emission areas and having a variable width in at least one direction.

[0064] Since the partition wall includes a portion having a relatively large width, it may not be easily deformed. Therefore, it is possible to prevent the display quality, lifespan, and yield of the display device from being reduced due to the deformation of the partition wall.

[0065] In addition, since the partition wall includes a portion having a relatively small width, a reduction in the width of the light emitting unit due to the partition wall can be reduced. Therefore, a reduction in the brightness of the display device due to the partition wall can be prevented.

[0066] A display device according to another embodiment includes a plurality of dummy patterns corresponding to non-emission regions between the plurality of emission regions, formed at the same layer as the plurality of pixel electrodes, and disposed parallel to the pixel electrodes.

[0067] Therefore, even if some of the plurality of light-emitting elements protrude into the non-emission region due to alignment errors that occur in the process of simultaneously arranging the light-emitting elements on the pixel electrode, they can be supported by the dummy pattern in the non-emission region. Therefore, it is possible to prevent the light-emitting element partially arranged in the non-emission region from tilting due to the step of the pixel electrode. Therefore, this can prevent the local increase in the resistance of the common electrode, thereby preventing the degradation of the display quality.

[0068] The effects of the present disclosure are not limited to the aforementioned effects, and various other effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] These and / or other aspects will become apparent and more easily understood through the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0070] Figure 1 is a plan view of a display device according to one or more embodiments;

[0071] Figure 2 yes Figure 1 a detailed view of section A;

[0072] Figure 3 It is along Figure 2 A cross-sectional view taken along line A'-A";

[0073] Figure 4 yes Figure 2 an exploded perspective view of an example of portion B;

[0074] Figure 5 yes Figure 2 Example equivalent circuit diagram of the emission region of;

[0075] Figure 6 According to the first embodiment Figure 2 a perspective view of an example of a portion C;

[0076] Figure 7 is a diagram showing the first embodiment of the present invention. Figure 2 A plan view of a partition wall portion and a rear surface of a light emitting unit in a portion B;

[0077] Figure 8 It is shown Figure 7 A plan view of an example of a pixel electrode and a common connection electrode;

[0078] Fig. 9 and Fig.10 is shown with Figure 7 A plan view showing an example of process errors associated with arrangement of light emitting elements in FIG.

[0079] Fig.11 It is along Figure 7 A cross-sectional view taken along line D-D';

[0080] Fig.12 It is shown in detail Fig.11 a view of an example of a portion E;

[0081] Fig.13 It is shown in detail Fig.11an example view of a portion F of the;

[0082] Figures 14 to 19 Is to show the layout Fig.12 The light emitting element and Fig.13 A process diagram of a process for producing a partition wall portion;

[0083] Fig. 20 is a diagram showing a method according to the second embodiment Figure 2 A plan view of a partition wall portion and a rear surface of a light emitting unit in a portion B;

[0084] Fig.21 is a diagram showing a method according to the third embodiment Figure 2 A plan view of a partition wall portion and a rear surface of a light emitting unit in a portion B;

[0085] Fig. 22 is a diagram showing a fourth embodiment of the present invention. Figure 2 A plan view of a partition wall portion and a rear surface of a light emitting unit in a portion B;

[0086] Fig.23 is a diagram showing a method according to the fifth embodiment Figure 2 A plan view of a partition wall portion and a rear surface of a light emitting unit in a portion B;

[0087] Fig.24 and Fig.25 is a view showing a modified example of the fifth embodiment;

[0088] Fig.26 is a diagram showing a sixth embodiment of the present invention. Figure 2 A plan view of a partition wall portion and a rear surface of a light emitting unit in a portion B;

[0089] Fig. 27 is a diagram showing a seventh embodiment of the present invention. Figure 2 A plan view of a partition wall portion and a rear surface of a light emitting unit in a portion B;

[0090] Fig.28 is a diagram showing the Figure 2 A plan view of a partition wall portion and a rear surface of a light emitting unit in a portion B;

[0091] Fig.29 It is along Fig.28 A cross-sectional view taken along line G-G';

[0092] Fig.30 , Fig.31 and Fig.32 According to one or more embodiments, Fig.28 A cross-sectional view taken along line G-G';

[0093] Fig.33According to the ninth embodiment Figure 2 a perspective view of an example of a portion C;

[0094] Fig.34 is a diagram showing a ninth embodiment of the present invention. Figure 2 A plan view of a partition wall portion and a rear surface of a light emitting unit in a portion B;

[0095] Fig.35 It is along Fig.34 A cross-sectional view taken along line II';

[0096] Fig.36 It is along Fig.34 A sectional view taken along the line J-J';

[0097] Fig.37 is a diagram showing a method according to the tenth embodiment Figure 2 A plan view of a partition wall portion and a rear surface of a light emitting unit in a portion B;

[0098] Fig.38 , Fig.39 , Fig.40 and Fig.41 is a plan view showing a partition wall portion and a rear surface of a light emitting unit according to an eleventh embodiment and a modified example of the eleventh embodiment;

[0099] Fig.42 is a plan view of a display device according to one or more embodiments;

[0100] Fig.43 yes Fig.42 An example layout diagram of a transistor array layer in a display device of FIG.

[0101] Fig.44 , Fig.45 and Fig.46 yes Fig.43 An equivalent circuit diagram of an example of an emitter region in a transistor array layer;

[0102] Fig.47 is shown with Fig.42 An example layout diagram of a plurality of emission regions corresponding to part A;

[0103] Fig.48 is shown with Fig.47 A plan view of an example of a pixel electrode and a dummy pattern corresponding to part B;

[0104] Fig.49 It is along Fig.48 A cross-sectional view of an example of a surface cut along line CC';

[0105] Fig.50 yes Fig.49A cross-sectional view of an example of a transistor array layer;

[0106] Fig.51 yes Fig.49 a detailed cross-sectional view of a portion D of;

[0107] Fig.52 It is along Fig.48 A cross-sectional view of an example of a surface cut along line CC';

[0108] Fig.53 and Fig.54 It is shown Fig.48 A plan view of an example of an alignment error of a light emitting element shown in FIG.

[0109] Fig.55 It is along Fig.53 A cross-sectional view of an example of a surface cut along line D-D';

[0110] Fig.56 yes Fig.55 A cross-sectional view of a comparative example;

[0111] Figures 57 to 63 is shown with Fig.47 A plan view of an example of a pixel electrode and a dummy pattern corresponding to part B;

[0112] Fig.64 is shown with Fig.42 A plan view of an example of a plurality of emission regions corresponding to portion A;

[0113] Fig.65 and Fig.66 is shown with Fig.64 A plan view of an example of a pixel electrode and a dummy pattern corresponding to part F;

[0114] Fig.67 is a flowchart illustrating a method of manufacturing a display device according to one or more embodiments;

[0115] Fig.68 It is shown that the preparation Fig.67 A flowchart of the operation of the light emitting element array layer in FIG.

[0116] Figure 69 to Figure 84 It is shown Fig.67 and Fig.68 A process diagram for each operation. DETAILED DESCRIPTION

[0117] One or more embodiments will now be described more fully below with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Throughout this disclosure, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0118] In order to describe the embodiments of the present disclosure, some of the parts (components) that are not related to the description may not be provided.

[0119] It will be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0120] In addition, the phrase "in a plan view" refers to when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" refers to when a schematic cross-section taken by vertically cutting the object portion is viewed from the side. The term "overlapping" or its variants means that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "overlapping" may include stacking, stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "spaced apart from" or "offset from" or "offset from" and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object, although still facing each other, are understood to be indirectly opposite to each other.

[0121] For ease of description, spatially relative terms such as "below", "under", "lower (lower part)", "above", "upper (upper part)", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It will be understood that in addition to the orientation depicted in the drawings, the spatially relative terms are intended to also cover different orientations of the device in use or operation. For example, in the case of a device shown in the flipped drawings, a device positioned "below" or "beneath" another device may be placed "above" the other device. Thus, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatially relative terms may be interpreted differently depending on the orientation.

[0122] When an element is referred to as being "connected" or "coupled" to another element, the element may be "directly connected" or "directly coupled" to the other element, or "indirectly connected" or "indirectly coupled" to the other element with one or more intervening elements interposed therebetween. It will also be understood that when the terms "comprises," "including," "having," and / or variations thereof are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0123] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or to facilitate its description and explanation. For example, when discussing a "first element" in the description, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be referred to in a similar manner without departing from the teachings and scope of the present disclosure.

[0124] As used herein, the term "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (e.g., characteristics of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0125] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for the purposes of its meaning and interpretation. For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or". In the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." for the purposes of its meaning and interpretation. For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0126] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an ideal or overly formal sense unless clearly defined in the specification.

[0127] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0128] Figure 1 is a plan view of a display device 100 according to one or more embodiments. Figure 2 yes Figure 1 Detailed view of section A.

[0129] In this specification, the display device 100 according to one or more embodiments is mainly described as an ultra-small light-emitting diode display device (for example, a micro light-emitting diode display device or a nano light-emitting diode display device) including an ultra-small light-emitting diode (micro light-emitting diode or nano light-emitting diode), but one or more embodiments of the present disclosure are not limited to this.

[0130] In addition, in the present disclosure, the display device 100 according to one or more embodiments is described, focusing on the case where the light-emitting elements of a plurality of light-emitting units are arranged on the circuit array layer 120 arranged on the substrate 110. However, it should be noted that one or more embodiments of the present disclosure are not limited thereto. For example, the display device 100 according to one or more embodiments may also be a light-emitting diode on silicon (LEDoS) display device in which a light-emitting diode is arranged as a light-emitting element on a semiconductor circuit board formed by a semiconductor process using a silicon wafer.

[0131] In addition, in the present disclosure, the first direction DR1 refers to the horizontal direction of the display device 100, the second direction DR2 refers to the vertical direction of the display device 100, and the third direction DR3 refers to the thickness direction of the display device 100 or the thickness direction of the semiconductor circuit board. In this case, "left", "right", "upper", and "lower" refer to directions when the display device 100 is viewed in a plan view. For example, "right side" refers to one side in the first direction DR1, "left side" refers to the other side in the first direction DR1, "upper side" refers to one side in the second direction DR2, and "lower side" refers to the other side in the second direction DR2. In addition, "top" refers to one side in the third direction DR3, and "bottom" refers to the other side in the third direction DR3.

[0132] Reference Figure 1 , the display device 100 according to one or more embodiments may be shaped as a flat panel.

[0133] For example, the display device 100 may have a quadrilateral planar shape having long sides in the first direction DR1 and short sides in the second direction DR2. However, the planar shape of the display device 100 is not limited thereto, and the display device 100 may also have a polygonal, circular, elliptical, or irregular planar shape other than the quadrilateral shape.

[0134] The display device 100 is a device for displaying a moving image or a still image. The display device 100 can be used as a display screen in a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra mobile PC (UMPC) and in various products such as a television, a notebook computer, a monitor, a billboard, and / or an Internet of Things (IoT) device.

[0135] The display device 100 includes a display area DA configured to emit light for displaying an image and a non-display area NDA disposed around the display area DA along an edge or periphery of the display area DA and not displaying an image.

[0136] The display area DA may follow the planar shape of the display device 100. For example, the display area DA may have a Figure 1 The quadrilateral shape shown in .

[0137] The display area DA may be disposed at the center (eg, central portion) of the display device 100 .

[0138] The non-display area NDA may be located around the display area DA along an edge or periphery of the display area DA (eg, may surround the display area DA along an edge or periphery of the display area DA).

[0139] The non-display area NDA may include a first pad (or "pad") portion PDA1 and a second pad portion PDA2 arranged on both sides of the display area DA in the second direction DR2, a first common connection area CCA1 arranged between the display area DA and the first pad portion PDA1, and a second common connection area CCA2 arranged between the display area DA and the second pad portion PDA2.

[0140] Reference Figure 2 , the display device 100 may include a plurality of emission areas EA arranged in the display area DA and configured to emit light for displaying an image.

[0141] The emission area EA may include first, second, and third emission areas EA1, EA2, and EA3 configured to emit light of different colors. In addition, a combination of the first to third emission areas EA1 to EA3 adjacent to each other may form a pixel PX, which is the smallest light-emitting unit that can display white light.

[0142] That is, the display device 100 includes a plurality of pixels PX arranged in a matrix in the display area DA and configured to emit light of their respective brightness and color, and each of the pixels PX is composed of first to third emission areas EA1 to EA3 adjacent to each other.

[0143] In one or more embodiments of the present disclosure, the case where each of the pixels PX includes three emission areas EA1 to EA3 corresponding to different colors is described as an example. However, the embodiments of the present disclosure are not limited thereto. For example, each of the pixels PX may also include four emission areas.

[0144] The first emission area EA1 is an area that emits light of a first color (hereinafter, referred to as "first light"). The first light may be light in a blue band. The blue band may be about 370nm to 460nm, but one or more embodiments of the present disclosure are not limited thereto.

[0145] The second emission area EA2 is an area that emits light of a second color in a wavelength band higher than the wavelength band of the first color (hereinafter, referred to as "second light"). The second light may be light in a green wavelength band. The green wavelength band may be about 480nm to 560nm, but one or more embodiments of the present disclosure are not limited thereto.

[0146] The third emission area EA3 is an area that emits light of a third color in a wavelength band higher than the wavelength band of the second color (hereinafter, referred to as "third light"). The third light may be light in a red wavelength band. The red wavelength band may be about 600nm to 750nm, but one or more embodiments of the present disclosure are not limited thereto.

[0147] The first emission region EA1, the second emission region EA2 and the third emission region EA3 may be alternately arranged along the first direction DR1. For example, the first emission region EA1, the second emission region EA2 and the third emission region EA3 may be arranged along the first direction DR1 in this order.

[0148] The first emission areas EA1 may be arranged side by side in the second direction DR2. The second emission areas EA2 may be arranged side by side in the second direction DR2. The third emission areas EA3 may be arranged side by side in the second direction DR2.

[0149] The first pad part PDA1 may be disposed at an upper side of the display device 100. The first pad part PDA1 may include a circuit board connected to an external circuit board CB (see FIG. Figure 3 )'s first pad PD1.

[0150] The second pad portion PDA2 may be disposed at the lower side of the display device 100. The second pad portion PDA2 may include a circuit board for connecting to an external circuit board CB (see FIG. Figure 3 The second pad PDA2 may also be omitted.

[0151] Each of the first common connection area CCA1 and the second common connection area CCA2 may include a plurality of common connection electrodes CCE.

[0152] Figure 3 It is along Figure 2 A cross-sectional view taken along line A'-A".

[0153] Reference Figure 3 According to one or more embodiments, the display device 100 may include a substrate 110, a circuit array layer 120 disposed on the substrate 110, a common connection electrode CCE disposed on the circuit array layer 120 in a first common connection area CCA1, a common electrode CE disposed on the circuit array layer 120 and covering the common connection electrode CCE, a first pad PD1 disposed on the circuit array layer 120 in a first pad portion PDA1, and a pad connection electrode PDE disposed on the first pad PD1.

[0154] The first pad PD1 may be connected to the common connection electrode CCE through a wiring of the circuit array layer 120 .

[0155] The pad connection electrode PDE may be electrically connected to a pad CPD of a circuit board CB fixed on one side of the substrate 110 through a wire WR.

[0156] The circuit board CB may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), a flexible printed circuit (FPC), or a flexible film such as a chip on film (COF).

[0157] The common connection electrode CCE and the pad connection electrode PDE may be made of the same layer and the same material.

[0158] The display device 100 may further include an insulating layer INS covering a side (eg, a side surface) of each of the first pad PD1 , the common connection electrode CCE, and the pad connection electrode PDE.

[0159] Figure 4 yes Figure 2 An exploded perspective view of an example of portion B.

[0160] Reference Figure 4According to one or more embodiments, the display device 100 includes a substrate 110, a plurality of light emitting units 130, and a partition wall portion (i.e., a partition wall) 140, the substrate 110 including a display area DA in which a plurality of emission areas EA are arranged, the plurality of light emitting units 130 are disposed on the substrate 110 and correspond to the emission areas EA, respectively, and the partition wall portion (i.e., a partition wall) 140 is disposed on the substrate 110 and corresponds to a non-emission area as a boundary between the emission areas EA.

[0161] The substrate 110 may be provided in the form of a rigid flat plate. Alternatively, the substrate 110 may be provided in the form of a flexible flat plate that is easily deformable (eg, bendable, foldable, or rollable).

[0162] The substrate 110 may be made of an insulating material such as glass, quartz and / or a polymer resin. Here, the polymer material may be, for example, polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP) and / or a combination thereof.

[0163] Optionally, the substrate 110 may be made of a metal material or a silicon wafer.

[0164] The substrate 110 supports the circuit array layer 120 , the light emitting cells 130 , and the partition wall portion 140 .

[0165] Each of the light emitting units 130 includes a light emitting element LE disposed on the substrate 110 .

[0166] The light emitting element LE may have an upper surface of a polygonal shape (such as a quadrangular shape), a circular shape, an elliptical shape, or an irregular shape.

[0167] The display device 100 according to the described embodiment may further include a circuit array layer 120 disposed on the substrate 110. The circuit array layer 120 may include a plurality of pixel circuit units respectively corresponding to the emission areas EA. Figure 5 Describe the pixel circuit unit.

[0168] The light emitting unit 130 and the partition wall portion 140 may be disposed on the circuit array layer 120 .

[0169] The display device 100 according to the described embodiment may further include a color filter layer 160 disposed on the light emitting unit 130 and the partition wall portion 140. The color filter layer 160 may include a first color filter 161 corresponding to the first emission area EA1, a second color filter 162 corresponding to the second emission area EA2, and a third color filter 163 corresponding to the third emission area EA3. The color filter layer 160 may further include a light blocking portion 164 corresponding to a non-emission area.

[0170] The first color filter 161 covers the light emitting unit 130 of the first emission area EA1 and transmits the first light.

[0171] The second color filter 162 covers the light emitting unit 130 of the second emission area EA2 and transmits the second light.

[0172] The third color filter 163 covers the light emitting unit 130 of the third emission area EA3 and transmits the third light.

[0173] The display device 100 according to the described embodiment may further include a protective layer 150 covering the light emitting unit 130 and the partition wall portion 140. In this case, the color filter layer 160 may be disposed on the protective layer 150.

[0174] Each of the light emitting units 130 may be sealed with a protective layer 150 .

[0175] For example, the protective layer 150 may be made of a material selected from silicon oxide (SiO 2 ) layer, aluminum oxide (Al 2 O 3 ) layer and hafnium oxide (HfO x ) layer, but the embodiments of the present disclosure are not limited thereto.

[0176] The display device 100 according to the described embodiment may further include a protective substrate 170 disposed on the color filter layer 160. However, this is merely an example, and the embodiments of the present disclosure are not limited thereto.

[0177] The protection substrate 170 may be attached to the color filter layer 160 through a suitable adhesive layer (eg, a predetermined adhesive layer).

[0178] The protective substrate 170 may be made of SiO 2The protective substrate 170 is made of a glass material as its main component. Optionally, the protective substrate 170 can be made of a plastic material. The plastic material can be one or more selected from polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl compound, polyimide, polycarbonate (PC), cellulose triacetate (TAC) and cellulose acetate propionate (CAP).

[0179] Figure 5 yes Figure 2 An example equivalent circuit diagram of the emission area EA.

[0180] Reference Figure 5 The display device 100 includes a plurality of pixel circuit units PXC, each corresponding to the emission area EA and connected to the light emitting elements LE of the emission area EA. The pixel circuit unit PXC may be implemented as a circuit array layer 120.

[0181] Each of the pixel circuit units PXC may include one or more thin film transistors T1 and T2 .

[0182] For example, Figure 5 As shown in , the pixel circuit unit PXC may include a first thin film transistor T1 connected to the light emitting element LE, and a second thin film transistor T2 and a storage capacitor CST connected to the first thin film transistor T1.

[0183] The first thin film transistor T1 may be connected in series to the light emitting element LE between a power line PL supplying a first driving power VDD and a common line CL supplying a second driving power VSS having a voltage level lower than that of the first driving power VDD.

[0184] That is, a first electrode of the first thin film transistor T1 may be connected to the power line PL, and a second electrode of the first thin film transistor T1 may be connected to the anode of the light emitting element LE.

[0185] In addition, the cathode of the light emitting element LE may be connected to the common line CL.

[0186] The second thin film transistor T2 may be connected between the gate electrode of the first thin film transistor T1 and the data line DL supplying a data signal corresponding to each emission area EA. In addition, the gate electrode of the second thin film transistor T2 may be connected to the scan line SL supplying a scan signal for selecting whether to write a data signal.

[0187] The storage capacitor CST may be connected between a first node N1 and a second node N2. The first node N1 is a contact point between the gate electrode of the first thin film transistor T1 and the second thin film transistor T2, and the second node N2 is a contact point between the first thin film transistor T1 and the power line PL. That is, the storage capacitor CST is connected between the gate electrode and the first electrode of the first thin film transistor T1.

[0188] When the second thin film transistor T2 is turned on based on the scan signal of the scan line SL, the data signal of the data line DL is supplied to the gate electrode of the first thin film transistor T1 and the storage capacitor CST through the turned-on second thin film transistor T2. Therefore, the first thin film transistor T1 is turned on based on the data signal, and the driving current corresponding to the data signal is supplied to the light emitting element LE through the turned-on first thin film transistor T1. In addition, the first thin film transistor T1 can remain turned on based on the voltage charged in the storage capacitor CST.

[0189] Next, the display device 100 according to one or more embodiments will be described.

[0190] Figure 6 According to the first embodiment Figure 2 A perspective view of an example of portion C. Figure 7 is a diagram showing the first embodiment of the present invention. Figure 2 FIG. 1 is a plan view of a partition wall portion 140 and a rear surface 132 a of a light emitting unit 130 in a portion B of FIG. Figure 8 It is shown Figure 7 2 is a plan view of an example of a pixel electrode PE and a common connection electrode CCE.

[0191] Reference Figure 6 The display device 100a according to the first embodiment includes a partition wall portion 140 which is disposed on the substrate 110, corresponds to a non-emission area which is a boundary between the plurality of emission areas EA, and has a variable width in at least one direction.

[0192] The partition wall portion 140 includes a plate portion (i.e., plate) 141 corresponding to the non-emission area and a pillar portion (i.e., pillar) 142a protruding from at least a portion of the plate portion 141 to each of the emission areas EA and having a width greater than that of the plate portion 141.

[0193] Each of the light emitting units 130 may include a light emitting element LE disposed on the substrate 110 and a light control layer LCL disposed on the substrate 110 to cover the light emitting element LE and configured to control characteristics of light emitted from the light emitting element LE.

[0194] The light control layer LCL may include scattering particles that scatter the light of the light emitting element LE.

[0195] Alternatively, the light control layer LCL may include not only scattering particles but also wavelength conversion particles that convert the light of the light emitting element LE into light of a higher wavelength band. For example, the wavelength conversion particles may be quantum dots.

[0196] For example, when the light emitting element LE of the light emitting unit 130 emits the first light in the lowest band among the first light, the second light and the third light, the light control layer LCL of the light emitting unit 130 corresponding to the first emission area EA1 may include only scattering particles and may scatter and transmit the first light emitted from the light emitting element LE.

[0197] On the other hand, the light control layer LCL of the light emitting unit 130 corresponding to the second emission area EA2 configured to emit the second light of a higher wavelength band than the first light may include first wavelength conversion particles that convert the first light of the light emitting element LE into the second light. Therefore, the light emitting unit 130 corresponding to the second emission area EA2 may emit the second light into which the first light of the light emitting element LE has been converted by the first wavelength conversion particles of the light control layer LCL.

[0198] In addition, the light control layer LCL of the light emitting unit 130 corresponding to the third emission area EA3 configured to emit the third light of the wavelength band higher than the wavelength band of the second light may include second wavelength conversion particles that convert the first light of the light emitting element LE into the third light. Therefore, the light emitting unit 130 corresponding to the third emission area EA3 can emit the third light into which the first light of the light emitting element LE has been converted by the second wavelength conversion particles of the light control layer LCL.

[0199] However, this is merely an example, and the wavelength band of light of the light emitting element LE and the light control layer LCL of each of the light emitting units 130 is not limited thereto.

[0200] Each of the light emitting units 130 has a light emitting surface 131 a corresponding to the light control layer LCL and configured to emit light, and a rear surface 132 a opposite to the light emitting surface 131 a .

[0201] According to the first embodiment, the partition wall portion 140 has a variable width in at least one direction. To this end, the partition wall portion 140 may include a portion that protrudes into each emission area EA and thus has a width greater than that of the non-emission area. Therefore, the rear surface 132a of each of the light emitting units 130 may have at least one corner or at least one side formed in a shape corresponding to the shape of the partition wall portion 140.

[0202] According to the first embodiment, the partition wall portion 140 includes a plate portion 141 corresponding to the non-emission area and a pillar portion 142 a protruding from at least a portion of the plate portion 141 into each emission area EA and having a width greater than that of the plate portion 141 .

[0203] The pillar portion 142a of the partition wall portion 140 may correspond to each corner of each emission area EA.

[0204] In addition, in the third direction DR3 , the height of the column portion 142 a may be equal to the height of the plate portion 141 .

[0205] Therefore, the light emitting surface 131 a and the rear surface 132 a of each of the light emitting units 130 may be formed in a quadrangular shape having each corner deformed by the column portion 142 a of the partition wall portion 140 .

[0206] Reference Figure 7 , the column part 142a of the partition wall part 140 according to the first embodiment may correspond to the corners of the four adjacent light emitting units 130. That is, the column part 142a of the first embodiment may be provided in a cylindrical shape partially provided at the corners of the light emitting surface 131a and the rear surface 132a of the four adjacent light emitting units 130.

[0207] As described above, according to the first embodiment, the partition wall portion 140 includes the pillar portion 142 a protruding from the plate portion 141 to the corner of each of the plurality of emission areas EA and having a width greater than that of the plate portion 141 .

[0208] That is, the width W12 a of the column portion 142 a in the first direction DR1 is greater than the width W11 of the plate portion 141 in the first direction DR1 .

[0209] In addition, a width W22a of the column portion 142a in the second direction DR2 is greater than a width W21 of the plate portion 141 in the second direction DR2.

[0210] Since the pillar portion 142a having a width greater than that of the plate portion 141 is interposed between portions of the plate portion 141 having a width corresponding to the width of the non-emission region, the strength of the partition wall portion 140 can be increased. Therefore, the partition wall portion 140 can be prevented from being easily deformed due to a physical impact, etc. Therefore, it is possible to prevent the display quality, lifespan, and yield of the display device 100 from being reduced due to easy deformation of the partition wall portion 140.

[0211] In addition, since the entire partition wall portion 140 is not formed to have the width of the pillar portion 142a, it is possible to prevent the width of the emission area EA from being significantly reduced due to the enhanced partition wall portion 140. Therefore, it is possible to prevent the brightness of the emission area EA from being greatly reduced due to the partition wall portion 140.

[0212] Reference Figure 7 and Figure 8 , the display device 100a according to the first embodiment may include a plurality of pixel electrodes PE respectively corresponding to the emission areas EA.

[0213] In addition, the display device 100a according to the first embodiment may further include a common connection electrode CCE corresponding to a non-emission area as a boundary between the emission areas EA and spaced apart from each of the pixel electrodes PE. When the common connection electrode CCE is disposed in the display area DA, the resistance of the common electrode CE may be reduced.

[0214] However, this is merely an example, and the common connection electrode CCE may not be disposed in the display area DA but may be disposed only in the first and second common connection areas CCA1 and CCA2 of the non-display area NDA.

[0215] like Figure 7 As shown in , the light emitting element LE of each of the light emitting units 130 may be disposed on the pixel electrode PE.

[0216] In addition, a minimum distance G1a or G2a between the column portions 142a corresponding to both sides of the light emitting unit 130 is greater than the width of the light emitting element LE of the light emitting unit 130 .

[0217] That is, a minimum distance G1a between the column portions 142a corresponding to both sides of the light emitting unit 130 in the first direction DR1 is greater than a width W1LE of the light emitting element LE of the light emitting unit 130 in the first direction DR1.

[0218] In addition, a minimum distance G2a between the column portions 142a corresponding to both sides of the light emitting unit 130 in the second direction DR2 is greater than a width W2LE of the light emitting element LE of the light emitting unit 130 in the second direction DR2.

[0219] In this case, a distance margin between each light emitting element LE and the partition wall portion 140 may be maintained regardless of the pillar portion 142 a protruding into the emission area EA.

[0220] Fig. 9 and Fig.10 is shown with Figure 7 1 is a plan view of an example of process errors associated with the arrangement of the light emitting elements LE.

[0221] Reference Fig. 9 When a process error S1 occurs in the process of arranging the light emitting element LE in which the light emitting element LE is offset to either side of the first direction DR1 relative to the partition wall portion 140, a distance margin M1 between each light emitting element LE and the partition wall portion 140 in the first direction DR1 may not be affected by the column portion 142a of the partition wall portion 140.

[0222] Here, the distance margin M1 between each light emitting element LE and the partition wall portion 140 in the first direction DR1 may include a first margin M11 and a second margin M12, wherein the first margin M11 corresponds to the partition wall portion 140 adjacent to the light emitting element LE on one side in the first direction DR1, and the second margin M12 corresponds to the partition wall portion 140 adjacent to the light emitting element LE on the other side in the first direction DR1.

[0223] In addition, refer to Fig.10 When a process error S2 occurs in the process of arranging the light emitting element LE in which the light emitting element LE is offset to either side in the second direction DR2 relative to the partition wall portion 140, a distance margin M2 between each light emitting element LE and the partition wall portion 140 in the second direction DR2 may not be affected by the column portion 142a of the partition wall portion 140.

[0224] Here, the distance margin M2 between each light emitting element LE and the partition wall portion 140 in the second direction DR2 may include a third margin M21 and a fourth margin M22, wherein the third margin M21 corresponds to the partition wall portion 140 adjacent to the light emitting element LE on one side in the second direction DR2, and the fourth margin M22 corresponds to the partition wall portion 140 adjacent to the light emitting element LE on the other side in the second direction DR2.

[0225] As described above, according to the first embodiment, the minimum distance G1a or G2a between the pillar portions 142a corresponding to both sides of the light emitting unit 130 is greater than the width of the light emitting element LE of the light emitting unit 130. Therefore, it is possible to prevent the distance margin M1 or M2 between the light emitting element LE and the partition wall portion 140 from being reduced due to the pillar portion 142a.

[0226] Fig.11 It is along Figure 7 A cross-sectional view taken along line D-D'. Fig.12 It is shown in detail Fig.11 An example view of section E. Fig.13 It is shown in detail Fig.11 An example view of section F.

[0227] Reference Fig.11According to the first embodiment, the display device 100a may further include: a pixel electrode PE, which is arranged on the substrate 110 and corresponds to each of the emission areas EA; a pixel connection electrode PCE, which is arranged between the pixel electrode PE and the light emitting element LE; a common connection electrode CCE, which is arranged on the substrate 110 and corresponds to the non-emission area NEA which is a boundary between the emission areas EA; a planarization layer PLL, which is arranged between the common connection electrode CCE and the partition wall portion 140; an insulating layer INS, which covers the side surface of each of the pixel electrode PE, the pixel connection electrode PCE, the light emitting element LE, the common connection electrode CCE, the planarization layer PLL and the partition wall portion 140; a common electrode CE, which corresponds to the emission area EA and the non-emission area NEA and covers the insulating layer INS, the partition wall portion 140 and the light emitting element LE; and a reflective layer RL, which corresponds to the side surface of each of the pixel electrode PE, the pixel connection electrode PCE, the light emitting element LE, the common connection electrode CCE, the planarization layer PLL and the partition wall portion 140, and is arranged on the common electrode CE.

[0228] The light control layer LCL of each of the light emitting cells 130 may be disposed between portions of the reflective layer RL corresponding to the side of the partition wall portion 140 to cover the light emitting element LE and the common electrode CE.

[0229] The pixel electrode PE may include one or more selected from gold (Au), copper (Cu), aluminum (Al), and tin (Sn).

[0230] The pixel connection electrode PCE and the common connection electrode CCE may be made of the same layer. The pixel connection electrode PCE and the common connection electrode CCE may include one or more selected from gold (Au), copper (Cu), aluminum (Al) and tin (Sn). Optionally, the common connection electrode CCE may include a first layer and a second layer, the first layer including one or more selected from gold (Au), copper (Cu), aluminum (Al) and tin (Sn), and the second layer is disposed on the first layer and includes one or more selected from gold (Au), copper (Cu), aluminum (Al) and tin (Sn).

[0231] The light emitting element LE may be disposed on the pixel connection electrode PCE. The light emitting element LE may be a vertical light emitting diode element including an anode and a cathode facing each other in the third direction DR3. For example, the length of the light emitting element LE in the third direction DR3 may be about 1 μm to 5 μm.

[0232] The light emitting element LE may be a micro light emitting diode or a nano light emitting diode.

[0233] The planarization layer PLL may be designed to offset the step difference caused by the pixel electrode PE.

[0234] The planarization layer PLL may be made of a material selected from silicon oxide (SiO 2 ) layer, aluminum oxide (Al 2 O 3 ) layer and hafnium oxide (HfO x ) layers, but the embodiments of the present specification are not limited thereto.

[0235] The insulating layer INS is designed to insulate the pixel electrode PE and the common electrode CE from each other.

[0236] The insulating layer INS may be made of a material selected from silicon oxide (SiO 2 ) layer, aluminum oxide (Al 2 O 3 ) layer and hafnium oxide (HfO x ) layers, but the embodiments of the present disclosure are not limited thereto.

[0237] The common electrode CE may include a transparent conductive material. For example, the common electrode CE may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0238] The reflective layer RL reflects light traveling in directions other than the third direction DR3 among the light emitted from each light emitting unit 130. The reflective layer RL may include a metal material having a high reflectivity, such as aluminum (Al). The thickness of the reflective layer RL may be about 0.1 μm. The light efficiency of each light emitting unit 130 may be improved by the reflective layer RL.

[0239] The light control layer LCL may be made of a matrix resin in which at least scattering particles among scattering particles and wavelength conversion particles are dispersed. The matrix resin may include a light-transmitting organic material. For example, the matrix resin may include one or more selected from epoxy resin, acrylic resin, cardo resin, and imide resin.

[0240] The wavelength conversion particles may be quantum dots, quantum rods, fluorescent materials and / or phosphorescent materials. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI compound nanocrystals or a combination thereof.

[0241] Each quantum dot may include a core and a shell covering the core. The core may be, for example, but is not limited to, selected from CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InP, InAs, InSb, SiC, Ca, Se, In, P, Fe, Pt, Ni, Co, Al, Ag, Au, Cu, FePt, Fe 2 O 3 , Fe 3 O 4 The shell may include, but is not limited to, for example, one or more selected from ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, HgTe, AlN, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, GaSe, InN, InP, InAs, InSb, TlN, TlP, TlAs, TlSb, PbS, PbSe, and PbTe.

[0242] The scattering particles may include metal oxide particles or silicon dioxide (SiO 2 ) or organic particles. For example, the metal oxide can be selected from titanium oxide (TiO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 ), zinc oxide (ZnO) and tin oxide (SnO 2 ) or more thereof. In addition, the organic particles may include acrylic resin and / or polyurethane resin. The scattering particles may have a diameter of several nanometers to several tens of nanometers.

[0243] Reference Fig.12 , the light emitting element LE may include a first semiconductor layer SEM1 , an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, and a second semiconductor layer SEM2 which are stacked in the third direction DR3 .

[0244] The first semiconductor layer SEM1 may be disposed on the pixel connection electrode PCE. The first semiconductor layer SEM1 may be doped with a first conductivity type dopant such as Mg, Zn, Ca, Sr, and / or Ba. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg. The thickness of the first semiconductor layer SEM1 may be about 30 nm to 200 nm.

[0245] The electron blocking layer EBL may be disposed on the first semiconductor layer SEM1. The electron blocking layer EBL may be a layer for suppressing or preventing too many electrons from flowing into the active layer MQW. For example, the electron blocking layer EBL may be p-AlGaN doped with p-type Mg. The thickness of the electron blocking layer EBL may be about 10 nm to 50 nm. The electron blocking layer EBL may also be omitted.

[0246] The active layer MQW may be disposed on the electron blocking layer EBL. The active layer MQW may emit light by recombination of electron-hole pairs according to an electrical signal received through the first semiconductor layer SEM1 and the second semiconductor layer SEM2. The active layer MQW may emit first light having a central wavelength band within a range of 450 nm to 495 nm, that is, light in a blue wavelength band.

[0247] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, it may have a structure in which a plurality of well layers and a plurality of barrier layers are alternately stacked. Here, the well layer may be made of InGaN, and the barrier layer may be made of GaN or AlGaN, but the embodiments of the present disclosure are not limited thereto. The well layer may have a thickness of about 1 nm to 4 nm, and the barrier layer may have a thickness of 3 nm to 10 nm.

[0248] Alternatively, the active layer MQW may have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked, or may include different group III to group V semiconductor materials according to the wavelength band of the light emitted therefrom. The light emitted from the active layer MQW is not limited to the first light (e.g., light in the blue wavelength band). In some cases, a second light (e.g., light in the green wavelength band) or a third light (e.g., light in the red wavelength band) may be emitted.

[0249] The superlattice layer SLT may be disposed on the active layer MQW. The superlattice layer SLT may be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer SLT may be made of InGaN or GaN. The thickness of the superlattice layer SLT may be about 50 nm to 200 nm. The superlattice layer SLT may also be omitted.

[0250] The second semiconductor layer SEM2 may be disposed on the superlattice layer SLT. The second semiconductor layer SEM2 may be doped with a second conductive type dopant such as Si, Ge, Se, or Sn. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The thickness of the second semiconductor layer SEM2 may be about 500 μm to about 1 μm.

[0251] Reference Fig.13, a portion of the partition wall portion 140 may be made of the same layer as the light emitting element LE.

[0252] That is, the partition wall portion 140 may include a first wall portion WP1 made of the same layer as the light emitting element LE and a second wall portion WP2 provided on the first wall portion WP1 and made of a mask for patterning the semiconductor stacked body.

[0253] The first wall portion WP1 may include a first semiconductor layer SEM1 (see Fig.12 ) The first wall layer WL1 and the electron blocking layer EBL (see Fig.12 ) The second wall layer WL2 made of the same layer and the active layer MQW (see Fig.12 ) The third wall layer WL3 made of the same layer and the superlattice layer SLT (see Fig.12 ) a fourth wall layer WL4 made of the same layer, and a fifth wall layer WL5 made of the same layer as the second semiconductor layer SEM2.

[0254] In addition, the partition wall portion 140 has a thickness sufficient to surround the light control layer LCL and is arranged to be higher than the light emitting element LE. Therefore, the first wall portion WP1 of the partition wall portion 140 may further include a sixth wall layer WL6 arranged on the fifth wall layer WL5. The sixth wall layer WL6 may be made of the same material as that of the second semiconductor layer SEM2. Alternatively, the sixth wall layer WL6 may be made of an undoped semiconductor material.

[0255] The second wall portion WP2 may include a seventh wall layer WL7 made of the same layer as the first mask layer corresponding to the light emitting element LE and an eighth wall layer WL8 made of the same layer as the second mask layer corresponding to the partition wall portion 140 .

[0256] Figures 14 to 19 Is to show the layout Fig.12 The light emitting element LE and Fig.13 FIG. 1 is a process diagram of a process for manufacturing the partition wall portion 140 .

[0257] Reference Fig.14 , a circuit array layer 120 is arranged on the substrate 110, and a pixel electrode PE of each emission area EA is arranged on the circuit array layer 120. Then, a pixel connection electrode PCE is arranged on the pixel electrode PE, a common connection electrode CCE of the non-emission area NEA is arranged, and a planarization layer PLL is arranged to cover the pixel connection electrode PCE and the common connection electrode CCE. Next, the planarization layer PLL is mirror-polished until the upper surface of the pixel connection electrode PCE is exposed.

[0258] The semiconductor stacked body 200 is bonded to the planarization layer PLL processed to expose the upper surface of the pixel connection electrode PCE.

[0259] The semiconductor stack 200 may include a first layer 201 corresponding to the first semiconductor layer SEM1 , a second layer 202 corresponding to the electron blocking layer EBL, a third layer 203 corresponding to the active layer MQW, a fourth layer 204 corresponding to the superlattice layer SLT, and a fifth layer 205 corresponding to the second semiconductor layer SEM2 .

[0260] In addition, the semiconductor stacked body 200 may further include a sixth layer which is provided on the fifth layer 205 and corresponds to the sixth wall layer WL6 of the partition wall portion 140 .

[0261] Reference Fig.15 , first mask layers 211 and 212 and a second mask layer 220 are arranged on the semiconductor stacked body 200 .

[0262] The first mask layers 211 and 212 may include an element mask pattern 211 corresponding to the light emitting element LE to be disposed in a portion of the center of each emission area EA and a partition wall mask pattern 212 corresponding to the partition wall portion 140 to be disposed in the non-emission area NEA.

[0263] The first mask layers 211 and 212 may be made of a material selected from silicon oxide (SiO 2 ) layer, aluminum oxide (Al 2 O 3 ) layer and hafnium oxide (HfO x The thickness of the first mask layers 211 and 212 may be about 1 μm to 2 μm.

[0264] The second mask layer 220 is disposed on the partition wall mask pattern 212. The second mask layer 220 may include a metal material such as nickel (Ni). The thickness of the second mask layer 220 may be about 0.01 μm to 1 μm.

[0265] Reference Fig.16 , the light emitting element LE and the partition wall portion 140 can be separated by patterning the semiconductor stacked body 200 in a region where the first mask layers 211 and 212 and the second mask layer 220 are not provided.

[0266] The planarization layer PLL is also patterned when the semiconductor stacked body 200 is patterned for arranging the partition wall portion 140. Therefore, the planarization layer PLL may have the same width as that of the partition wall portion 140. Therefore, the partition wall portion 140 may be disposed on the planarization layer PLL covering a portion of the common connection electrode CCE.

[0267] Next, in a region where the second mask layer 220 is not provided (ie, in a region corresponding to the element mask pattern 211 ), the light emitting element LE may be provided by patterning the semiconductor stacked body 200 to a portion of the fifth layer 205 .

[0268] The light emitting element LE may be disposed on most of the upper surface of the pixel connection electrode PCE. Alternatively, the light emitting element LE may be aligned with the pixel connection electrode PCE in the third direction DR3.

[0269] Next, the insulating layer INS is disposed to cover the light emitting element LE and the partition wall portion 140 .

[0270] Reference Fig.17 , a horizontal portion of the insulating layer INS is removed by mirror processing to produce an insulating layer INS covering the side surface of each of the pixel electrode PE, the pixel connection electrode PCE, the light emitting element LE, the common connection electrode CCE, the planarization layer PLL and the partition wall portion 140.

[0271] The insulating layer INS may remain on the edge of the pixel connection electrode PCE.

[0272] The insulating layer INS may insulate the pixel electrode PE and the pixel connection electrode PCE, and the first semiconductor layer SEM1 of the light emitting element LE connected to the pixel electrode PE and the pixel connection electrode PCE, etc. from the common electrode CE.

[0273] Reference Fig.18 , the common electrode CE is arranged by stacking a conductive layer on the entire surface of the substrate 110 to cover the insulating layer INS.

[0274] Since the insulating layer INS covers the side of the common connection electrode CCE, the common electrode CE may contact the upper surface of the common connection electrode CCE. Therefore, the common electrode CE may be electrically connected to the common connection electrode CCE.

[0275] Reference Fig.19 , a reflective layer RL is stacked on the common electrode CE, and then a horizontal portion of the reflective layer RL is removed by mirror processing to produce a reflective layer RL disposed on the common electrode CE and corresponding to a side surface of each of the pixel electrode PE, the pixel connection electrode PCE, the light emitting element LE, the common connection electrode CCE, the planarization layer PLL, and the partition wall portion 140.

[0276] According to the first embodiment, the partition wall portion 140 includes a column portion 142a having a cylindrical shape and corresponding to the corners of the four adjacent light emitting units 130. However, the embodiments of the present disclosure are not limited to the first embodiment, and the partition wall portion 140 may be variously modified as long as it includes a plate portion 141 and a column portion 142a having a width greater than that of the plate portion 141.

[0277] Hereinafter, display devices according to other embodiments will be described.

[0278] Fig. 20 is a diagram showing a method according to the second embodiment Figure 2 FIG. 1 is a plan view of a partition wall portion 140 and a rear surface 132 b of a light emitting unit 130 in a portion B of FIG.

[0279] Reference Fig. 20 The display device 100b according to the second embodiment is the same as the display device 100a of the first embodiment, except that the partition wall portion 140 includes a column portion 142b corresponding to the corners of four adjacent light emitting units 130 and having a prism shape with a quadrangular cross section. Therefore, any redundant description will be omitted below.

[0280] According to the second embodiment, the width W12b of the column portion 142b in the first direction DR1 is greater than the width W11 of the plate portion 141 in the first direction DR1, and the width W22b of the column portion 142b in the second direction DR2 is greater than the width W21 of the plate portion 141 in the second direction DR2. Therefore, the strength of the partition wall portion 140 can be increased by the column portion 142b.

[0281] In addition, the minimum distance G1b between the column portions 142b corresponding to both sides of the light emitting unit 130 in the first direction DR1 is greater than the width W1LE of the light emitting element LE in the first direction DR1. In addition, the minimum distance G2b between the column portions 142b corresponding to both sides of the light emitting unit 130 in the second direction DR2 is greater than the width W2LE of the light emitting element LE in the second direction DR2. Therefore, the distance margin between the light emitting element LE and the partition wall portion 140 can be maintained regardless of the column portions 142b.

[0282] According to the second embodiment, since the column portion 142 b of the partition wall portion 140 has a prism shape, the width of the rear surface 132 b of each light emitting unit 130 can be reduced by the reduction of the partition wall portion 140 .

[0283] Fig.21 is a diagram showing a method according to the third embodiment Figure 2 FIG. 1 is a plan view of a partition wall portion 140 and a rear surface 132 c of the light emitting unit 130 in portion B of FIG.

[0284] Reference Fig.21 The display device 100c according to the third embodiment is the same as the display device 100a of the first embodiment, except that the partition wall portion 140 includes a column portion 142c disposed between two adjacent light emitting units 130. Therefore, any redundant description will be omitted below.

[0285] According to the third embodiment, the pillar portion 142c is disposed in a region where the sides of two light emitting units 130 corresponding to two adjacent emission areas EA face each other. The pillar portion 142c may have a cross-section that convexly protrudes into the two emission areas EA.

[0286] Here, since the plate portion 141 is partially disposed at the corners of four adjacent light emitting units 130 , both ends of the column portion 142 c may contact the plate portion 141 .

[0287] According to the third embodiment, the width W12c of the column portion 142c in the first direction DR1 is greater than the width W11 of the plate portion 141 in the first direction DR1, and the width W22c of the column portion 142c in the second direction DR2 is greater than the width W21 of the plate portion 141 in the second direction DR2. Therefore, the strength of the partition wall portion 140 can be increased by the column portion 142c.

[0288] In addition, the minimum distance G1c between the column portions 142c corresponding to both sides of the light emitting unit 130 in the first direction DR1 is greater than the width W1LE of the light emitting element LE in the first direction DR1. In addition, the minimum distance G2c between the column portions 142c corresponding to both sides of the light emitting unit 130 in the second direction DR2 is greater than the width W2LE of the light emitting element LE in the second direction DR2. Therefore, the distance margin between the light emitting element LE and the partition wall portion 140 can be maintained regardless of the column portions 142c.

[0289] Since the column portion 142 c of the third embodiment corresponds to the side surface of the light emitting unit 130 , the strength of the partition wall portion 140 may be increased more effectively.

[0290] In addition, due to the column part 142c, the light emitting surface and the rear surface 132c of each of the light emitting units 130 can be composed of a combination of curved sides convex toward the center. That is, the side surface of each light emitting unit 130 is formed into a curved shape corresponding to the shape of the column part 142c. Therefore, since the total reflection through the reflective layer RL is reduced, the light efficiency of the light emitting unit 130 can be improved.

[0291] Fig. 22 is a diagram showing a fourth embodiment of the present invention. Figure 2FIG. 1 is a plan view of a partition wall portion 140 and a rear surface 132 d of a light emitting unit 130 in a portion B of FIG.

[0292] Reference Fig. 22 The display device 100d according to the fourth embodiment is the same as the display device 100a of the first embodiment and the display device 100c of the third embodiment, except that the partition wall portion 140 includes a side column portion 1421 provided between two adjacent light emitting units 130 and a corner column portion 1422 corresponding to the corners of four adjacent light emitting units 130. Therefore, any redundant description will be omitted below.

[0293] According to the fourth embodiment, the width W121 or W221 of the portion of the side column portion 1421 corresponding to the center of each light emitting unit 130 may be similar to the width of the non-emission area NEA. In addition, the side column portion 1421 may have a smaller width toward the corner column portion 1422. That is, the width W121' or W221' of another portion of the side column portion 1421 adjacent to the corner column portion 1422 is smaller than the width W121 or W221 of the portion of the side column portion 1421 parallel to the center of each light emitting unit 130. In this case, although the strength of the partition wall portion 140 is slightly increased by the side column portion 1421, the width of the rear surface 132d of each light emitting unit 130 can be reduced by the reduction of the side column portion 1421.

[0294] The corner column portion 1422 has a width W122 in the first direction DR1 greater than the width W121 of the side column portion 1421 in the first direction DR1, and a width W222 in the second direction DR2 greater than the width W221 of the side column portion 1421 in the second direction DR2. Therefore, the strength of the partition wall portion 140 can be increased by the corner column portion 1422.

[0295] In addition, the minimum distance G1d between the corner column portions 1422 corresponding to both sides of the light emitting unit 130 in the first direction DR1 is greater than the width W1LE of the light emitting element LE in the first direction DR1. In addition, the minimum distance G2d between the corner column portions 1422 corresponding to both sides of the light emitting unit 130 in the second direction DR2 is greater than the width W2LE of the light emitting element LE in the second direction DR2. Therefore, the distance margin between the light emitting element LE and the partition wall portion 140 can be maintained regardless of the corner column portion 142d.

[0296] As described above, since the partition wall portion 140 according to the fourth embodiment further includes the corner column portion 1422, the strength thereof can be further increased.

[0297] Fig.23 is a diagram showing a method according to the fifth embodiment Figure 2FIG. 1 is a plan view of a partition wall portion 140 and a rear surface 132 e of the light emitting unit 130 in portion B of FIG.

[0298] Reference Fig.23 , except that the partition wall portion 140 includes the partition walls arranged side by side along one direction ( Fig.23 The display device 100e according to the fifth embodiment is the same as the display device 100a of the first embodiment except for 2n column portions 142e1 and 142e2 (where n is a natural number of 1 or more) between two light emitting units 130 adjacent to each other. Therefore, any redundant description will be omitted below.

[0299] The 2n column portions 142 e 1 and 142 e 2 include a first column portion 142 e 1 having a cross-sectional shape convex toward any one of two adjacent light emitting cells 130 and a second column portion 142 e 2 having a cross-sectional shape convex toward the other of the two adjacent light emitting cells 130 .

[0300] The plate portion 141 may be disposed along another direction ( Fig.23 DR2 in the figure) between two adjacent light emitting units 130 and along another direction ( Fig.23 DR2 in the figure) between the first column portion 142e1 and the second column portion 142e2 adjacent to each other.

[0301] According to the fifth embodiment, the first column portions 142 e 1 and the second column portions 142 e 2 are alternately disposed between two adjacent light emitting cells 130 .

[0302] In addition, in the other direction ( Fig.23 The first column portion 142e1 and the second column portion 142e2 disposed adjacent to each other and alternately on the DR2 in the figure may be point symmetrical to each other. Alternatively, the first column portion 142e1 and the second column portion 142e2 disposed on both sides of the light emitting unit 130 may be point symmetrical to each other.

[0303] Therefore, the light emitting surface and the rear surface 132e of each light emitting unit 130 may have a quadrilateral shape including one side deformed by the first pillar portion 142e1 and the other side facing the upper side and deformed by the second pillar portion 142e2.

[0304] According to the fifth embodiment, the width W12e1 of the first column portion 142e1 and the width W12e2 of the second column portion 142e2 in the first direction DR1 are greater than the width W11 of the plate portion 141 in the first direction DR1. Therefore, the strength of the partition wall portion 140 can be increased by the first column portion 142e1 and the second column portion 142e2.

[0305] In addition, the minimum distance G1e between the first column portion 142e1 and the second column portion 142e2 corresponding to both sides of the light emitting unit 130 in the first direction DR1 is greater than the width W1LE of the light emitting element LE in the first direction DR1. Therefore, the distance margin between the light emitting element LE and the partition wall portion 140 can be maintained regardless of the first column portion 142e1 and the second column portion 142e2.

[0306] According to the fifth embodiment, not only the strength of the partition wall portion 140 is increased by the column portions 142e1 and 142e2, but also a reduction in the width of each light emitting unit 130 due to the protrusion of the column portions 142e1 and 142e2 can be reduced.

[0307] Although in the other direction ( Fig.23 The first column portion 142e1 and the second column portion 142e2 adjacent to each other on DR2) in FIG. Fig.23 The two electrodes are point-symmetrical with each other, but this is only an example.

[0308] Fig.24 and Fig.25 : is a view showing a modified example of the fifth embodiment.

[0309] Reference Fig.24 , the first column portion 142e1 and the second column portion 142e2 according to the first modified example 100e' of the fifth embodiment are arranged in one direction ( Fig.23 In other words, the first column portion 142e1 and the second column portion 142e2 may be axially symmetrical to each other between the two light emitting units 130.

[0310] According to the first modified example, the total width W12e of the first and second column portions 142e1 and 142e2 arranged side by side in the first direction DR1 is greater than the width W11 of the plate portion 141 in the first direction DR1. Therefore, the strength of the partition wall portion 140 can be increased by the first and second column portions 142e1 and 142e2.

[0311] In addition, according to the first modified example, the minimum distance G1e between the first column portion 142e1 and the second column portion 142e2 corresponding to both sides of the light emitting unit 130 in the first direction DR1 is greater than the width W1LE of the light emitting element LE in the first direction DR1. Therefore, the distance margin between the light emitting element LE and the partition wall portion 140 can be maintained regardless of the first column portion 142e1 and the second column portion 142e2.

[0312] Optionally, refer to Fig.25According to the second modified example 100e" of the fifth embodiment, the partition wall portion 140 may include a first column portion 142e1, a second column portion 142e2, a third column portion 142e3 and a fourth column portion 142e4, each of which protrudes from a portion of one side of each light emitting unit 130 into the light emitting unit 130.

[0313] The first column portion 142e1 and the second column portion 142e2 may be disposed on both sides of the light emitting unit 130 in the first direction DR1, respectively.

[0314] The third column portion 142e3 and the fourth column portion 142e4 may be disposed on both sides of the light emitting unit 130 in the second direction DR2, respectively.

[0315] According to the second modified example, the minimum distance G1e between the first column portion 142e1 and the second column portion 142e2 corresponding to both sides of the light emitting unit 130 in the first direction DR1 is greater than the width W1LE of the light emitting element LE in the first direction DR1. In addition, the minimum distance G2e between the third column portion 142e3 and the fourth column portion 142e4 corresponding to both sides of the light emitting unit 130 in the second direction DR2 is greater than the width W2LE of the light emitting element LE in the second direction DR2. Therefore, the distance margin between the light emitting element LE and the partition wall portion 140 can be maintained regardless of the first column portion 142e1, the second column portion 142e2, the third column portion 142e3, and the fourth column portion 142e4.

[0316] Fig.26 is a diagram showing a sixth embodiment of the present invention. Figure 2 FIG. 1 is a plan view of a partition wall portion 140 and a rear surface 132 f of the light emitting unit 130 in portion B of FIG.

[0317] Reference Fig.26 , except that the plurality of emission areas EA are arranged side by side in the first direction DR1 but not in the second direction DR2, and the partition wall portion 140 includes Fig.26 The display device 100f according to the sixth embodiment is the same as the display device 100a of the first embodiment except for the column portion 142f corresponding to the corners of two light emitting units 130 adjacent to each other on DR1 in FIG. Therefore, any redundant description will be omitted below.

[0318] The plate portion 141 may be disposed between the column portions 142f adjacent to each other in one direction (eg, DR1). The plate portion 141 may be disposed near the light emitting unit 130 in another direction (eg, DR2).

[0319] According to the sixth embodiment, the pillar portions 142f protrude to two corners of one side of each light emitting unit 130. Therefore, the light emitting surface and the rear surface 132f of each light emitting unit 130 may have a quadrilateral shape whose corners corresponding to both ends of one side extending in one direction (e.g., DR1) are deformed by the pillar portions 142f.

[0320] According to the sixth embodiment, the width W12f of each column portion 142f in the first direction DR1 is greater than the width W11 of the plate portion 141 in the first direction DR1, and the maximum width W22f of the partition wall portion 140 in the second direction DR2 is greater than the width W21 of the plate portion 141 in the second direction DR2. Therefore, the strength of the partition wall portion 140 can be increased by the column portion 142f.

[0321] In addition, the minimum distance G1f between the column portions 142f corresponding to both sides of the light emitting unit 130 in the first direction DR1 is greater than the width W1LE of the light emitting element LE in the first direction DR1. In addition, the minimum distance G2f between the partition wall portions 140 corresponding to both sides of the light emitting unit 130 in the second direction DR2 is greater than the width W2LE of the light emitting element LE in the second direction DR2. Therefore, the distance margin between the light emitting element LE and the partition wall portion 140 can be maintained regardless of the column portion 142f.

[0322] According to the sixth embodiment, since only two corners of each light emitting unit 130 are deformed by the pillar portion 142 f , reduction in the width of the light emitting unit 130 by the pillar portion 142 f may be reduced.

[0323] Fig. 27 is a diagram showing a seventh embodiment of the present invention. Figure 2 FIG. 1 is a plan view of a partition wall portion 140 and a rear surface 132g of the light emitting unit 130 in portion B of FIG.

[0324] Reference Fig. 27 , except that the partition wall portion 140 includes a Fig. 27 The corners of two light emitting units 130 adjacent to each other in one direction (DR1) and in another direction (eg, Fig. 27 The display device 100g according to the seventh embodiment is the same as the display device 100f according to the sixth embodiment except for the column portion 142g corresponding to a portion of one side of one light emitting unit 130 adjacent to the two light emitting units 130 on DR2 in FIG. Therefore, any redundant description will be omitted below.

[0325] According to the seventh embodiment, the light emitting surface and the rear surface 132g of each of the light emitting units 130 may have a shape in which the light emitting surface and the rear surface 132g are aligned in one direction (eg, Fig. 27The corresponding corners at both ends of one side extending on DR1) and in this direction (for example, Fig. 27 A portion of the other side extending on DR1) in the figure is deformed into a quadrilateral shape by the column portion 142g.

[0326] According to the seventh embodiment, the maximum width W12g of each column portion 142g in the first direction DR1 is greater than the width W11 of the plate portion 141 in the first direction DR1, and the maximum width W22g of each column portion 142g in the second direction DR2 is greater than the width W21 of the plate portion 141 in the second direction DR2. Therefore, the strength of the partition wall portion 140 can be increased by the column portion 142g.

[0327] In addition, the minimum distance G1g between the column portions 142g corresponding to both sides of the light emitting unit 130 in the first direction DR1 is greater than the width W1LE of the light emitting element LE in the first direction DR1. In addition, the minimum distance G2g between the column portions 142g corresponding to both sides of the light emitting unit 130 in the second direction DR2 is greater than the width W2LE of the light emitting element LE in the second direction DR2. Therefore, the distance margin between the light emitting element LE and the partition wall portion 140 can be maintained regardless of the column portions 142g.

[0328] According to the seventh embodiment, since each column portion 142g is aligned with the corners of the two light emitting units 130 and in another direction ( Fig.26 DR2 in FIG. 1 corresponds to a portion of one side of a light emitting unit 130 adjacent to the two light emitting units 130, so the strength of the partition wall portion 140 can be further increased compared to the sixth embodiment.

[0329] Fig.28 is a diagram showing the Figure 2 FIG. 1 is a plan view of a partition wall portion 140 and a rear surface 132 h of the light emitting unit 130 in portion B of FIG. Fig.29 It is along Fig.28 A cross-sectional view taken along line G-G'.

[0330] Reference Fig.28 and Fig.29 The display device 100h according to the eighth embodiment is the same as the display device 100a of the first embodiment, except that the partition wall portion 140 includes a column portion 142h1 provided at a side of each light emitting unit 130 and having a height lower than that of the plate portion 141. Therefore, any redundant description will be omitted below.

[0331] According to the eighth embodiment, the width W12h of the column portion 142h1 in the first direction DR1 is greater than the width W11 of the plate portion 141 in the first direction DR1, and the width W22h of the column portion 142h1 in the second direction DR2 is greater than the width W21 of the plate portion 141 in the second direction DR2. Therefore, the strength of the partition wall portion 140 can be increased by the column portion 142h1.

[0332] In addition, the minimum distance G1h between the column portions 142h1 corresponding to both sides of the light emitting unit 130 in the first direction DR1 is greater than the width W1LE of the light emitting element LE in the first direction DR1. In addition, the minimum distance G2h between the column portions 142h1 corresponding to both sides of the light emitting unit 130 in the second direction DR2 is greater than the width W2LE of the light emitting element LE in the second direction DR2. Therefore, the distance margin between the light emitting element LE and the partition wall portion 140 can be maintained regardless of the column portions 142h1.

[0333] According to the eighth embodiment, since the height of the pillar portion 142 h 1 is smaller than the height of the plate portion 141 , the light emitting surface of each light emitting unit 130 is not affected by the pillar portion 142 h 1 .

[0334] That is, the light emitting surface of each light emitting unit 130 is surrounded by the plate portion 141. In addition, the rear surface 132h of each light emitting unit 130 is surrounded by the pillar portion 142h1.

[0335] Therefore, it is possible to prevent the width of the light emitting surface of each light emitting unit 130 from being reduced by the pillar portion 142h1.

[0336] In addition, a height H1 of the pillar portion 142 h 1 from the substrate 110 may be smaller than a light emission height LEH of the light emitting element LE from the substrate 110 .

[0337] The light emission height LEH of the light emitting element LE may correspond to at least one of a width of the light emitting element LE, a width of a light emitting surface, a height of the light emitting element LE from the substrate 110, and an angle at which light is emitted from the light emitting element LE.

[0338] Since the height H1 of the column portion 142h1 is limited as described above, the column portion 142h1 is not disposed in the region where the light emitting element LE emits light. Therefore, the influence of the column portion 142h1 on the light emission characteristics of the light emitting element LE can be eliminated.

[0339] According to the eighth embodiment, not only the strength of the partition wall portion 140 is improved by the pillar portion 142h1, but also the width of the light emitting surface of each light emitting unit 130 can be prevented from being reduced.

[0340] exist Fig.29, the column portion 142h1 according to the eighth embodiment has a desired width (eg, a predetermined width) greater than the width of the plate portion 141. However, this is merely an example, and the column portion 142h1 may also have a variable width.

[0341] Fig.30 , Fig.31 and Fig.32 According to one or more other embodiments, Fig.28 A cross-sectional view taken along line G-G'.

[0342] Reference Fig.30 The column portion 142 h 2 according to the first example of the eighth embodiment may include an inclined surface facing the light emitting element LE, and may have a width gradually decreasing toward the plate portion 141 .

[0343] In this case, since the reflective layer RL has an inclined surface due to the pillar portion 142h2, the traveling direction of light around the light emitting element LE is likely to be changed into the third direction DR3 by the reflective layer RL. Therefore, the light efficiency of the light emitting unit 130 can be improved.

[0344] Reference Fig.31 The column portion 142 h 3 according to the second example of the eighth embodiment may include a curved surface facing the light emitting element LE, and may have a width gradually decreasing toward the plate portion 141 .

[0345] In this case, since the reflective layer RL has a curved surface in the form of an exponential function curve due to the column part 142h3, the traveling direction of light around the light emitting element LE is likely to be changed to the third direction DR3 by the reflective layer RL, and total reflection can be reduced. Therefore, the light efficiency of the light emitting unit 130 can be further improved.

[0346] Reference Fig.32 The partition wall portion 140 according to the third example of the eighth embodiment may further include a buffer portion 142 h 4 provided between the column portion 142 h 1 and the plate portion 141 .

[0347] The buffer portion 142 h 4 may have a width smaller than that of the pillar portion 142 h 1 and greater than that of the plate portion 141 .

[0348] In this case, since the deformation of the plate portion 141 can be reduced by the buffer portion (ie, buffer member) 142h4, the strength of the partition wall portion 140 can be further increased.

[0349] Fig.33 According to the ninth embodiment Figure 2 A perspective view of an example of portion C. Fig.34 is a diagram showing a ninth embodiment of the present invention. Figure 2 FIG. 1 is a plan view of a partition wall portion 140 and a rear surface 132 h of the light emitting unit 130 in portion B of FIG. Fig.35 It is along Fig.34 A cross-sectional view taken along line II'. Fig.36 It is along Fig.34 A cross-sectional view taken along line J-J'.

[0350] Reference Fig.33 , Fig.34 , Fig.35 and Fig.36 The display device 100i according to the ninth embodiment is the same as the display device 100a of the first embodiment and the display device 100h of the eighth embodiment, except that the partition wall portion 140 includes a column portion 142i protruding from a portion of the plate portion 141 to the side or corner of each light emitting unit 130 and having a height lower than that of the plate portion 141. Therefore, any redundant description will be omitted below.

[0351] like Fig.34 As shown in FIG. 1 , according to the ninth embodiment, the width W12i of the column portion 142i in the first direction DR1 is greater than the width W11 of the plate portion 141 in the first direction DR1, and the width W22i of the column portion 142i in the second direction DR2 is greater than the width W21 of the plate portion 141 in the second direction DR2. Therefore, the strength of the partition wall portion 140 can be increased by the column portion 142i.

[0352] In addition, the minimum distance G1i between the column portions 142i corresponding to both sides of the light emitting unit 130 in the first direction DR1 is greater than the width W1LE of the light emitting element LE in the first direction DR1. In addition, the minimum distance G2i between the column portions 142i corresponding to both sides of the light emitting unit 130 in the second direction DR2 is greater than the width W2LE of the light emitting element LE in the second direction DR2. Therefore, the distance margin between the light emitting element LE and the partition wall portion 140 can be maintained regardless of the column portions 142i.

[0353] like Fig.33 As shown in FIG. 1 , according to the ninth embodiment, the height of each column portion 142i in the third direction DR3 is smaller than the height of the plate portion 141 in the third direction DR3. Therefore, only the rear surface 132i of each light emitting unit 130 may be deformed by the column portion 142i, and the light emitting surface 131i of each light emitting unit 130 may not be deformed by the column portion 142i.

[0354] That is to say, Fig.33 , Fig.35 and Fig.36As shown in FIG. 1 , the light emitting surface 131i of each light emitting unit 130 is surrounded by the plate portion 141. Therefore, the light emitting surface 131i of each light emitting unit 130 may be formed in a shape corresponding to the shape of the emission area EA.

[0355] Therefore, it is possible to prevent the width of the light emitting surface 131i of each light emitting unit 130 from being reduced by the column portion 142i.

[0356] In addition, if Fig.33 and Fig.36 As shown in , because the pillar portion 142 i protrudes to a portion of each light emitting unit 130 , the rear surface 132 i of each light emitting unit 130 is surrounded by the plate portion 141 and the pillar portion 142 i .

[0357] Therefore, the width of the rear surface 132i of each light emitting unit 130 may be reduced by the reduction of the pillar portion 142i.

[0358] According to the ninth embodiment, each column portion 142i may correspond to the corners of four adjacent light emitting units 130. That is, each column portion 142i may be partially disposed at the corners of four adjacent light emitting units 130 and may have a column shape having a circular or elliptical cross section.

[0359] In other words, the rear surface 132i of each light emitting unit 130 may have a quadrilateral shape in which each corner is deformed by the pillar portion 142i.

[0360] As described above, according to the ninth embodiment, although the partition wall portion 140 includes the column portion 142i, the width reduction of the light emitting surface 131i of each light emitting unit 130 can be prevented and the width reduction of the rear surface 132i of each light emitting unit 130 can be reduced.

[0361] Fig.37 is a diagram showing a method according to the tenth embodiment Figure 2 FIG. 1 is a plan view of a partition wall portion 140 and a rear surface 132 j of the light emitting unit 130 in portion B of FIG.

[0362] Reference Fig.37 The display device 100j according to the tenth embodiment is the same as the display device 100i according to the ninth embodiment, except that the column portion 142j of the partition wall portion 140 has a prism shape having a quadrangular cross section. Therefore, any redundant description will be omitted below.

[0363] According to the tenth embodiment, since the pillar portion 142 j of the partition wall portion 140 has a prism shape, the width of the rear surface 132 j of each light emitting unit 130 can be reduced by the reduction of the partition wall portion 140 .

[0364] Different from the above description, each emission area EA may also be formed in a circular or elliptical shape instead of a quadrilateral shape.

[0365] Fig.38 , Fig.39 , Fig.40 and Fig.41 140 ′ and rear surfaces of light emitting units 130 k , 130 k 1 , 130 k 2 , and 130 k 3 according to the eleventh embodiment and a modified example of the eleventh embodiment.

[0366] Reference Fig.38 , the display device 100k according to the eleventh embodiment is the same as the display device 100a of the first embodiment, except that the rear surface of each of the plurality of light emitting units 130k corresponding to the plurality of emission areas EA is deformed into a circular or elliptical shape by the partition wall portion 140'. Therefore, any redundant description will be omitted below.

[0367] According to the eleventh embodiment, the light emitting unit 130k may include a first light emitting unit EP1 corresponding to each first emission region configured to emit the first light, a second light emitting unit EP2 corresponding to each second emission region configured to emit the second light, and a third light emitting unit EP3 corresponding to each third emission region configured to emit the third light. In addition, each pixel PX may be implemented as a combination of the first light emitting unit EP1, the second light emitting unit EP2, and the third light emitting unit EP3 at least partially overlapped with each other.

[0368] The partition wall portion 140' according to the eleventh embodiment may include an inner partition wall portion 143 and an outer partition wall portion 144, wherein the inner partition wall portion 143 is disposed at a boundary between the first light emitting unit EP1, the second light emitting unit EP2, and the third light emitting unit EP3 constituting each pixel PX, and the outer partition wall portion 144 corresponds to an area around the pixel PX.

[0369] Each of the inner and outer partition wall portions 143 and 144 may have a variable width in a plane corresponding to the first and second directions DR1 and DR2 .

[0370] Reference Fig.39 , except that four light emitting units 130k1 form one group, the display device 100k1 according to the first example of the eleventh embodiment is similar to Fig.38 Therefore, any redundant description will be omitted below.

[0371] Here, any two of the four light emitting cells 130k1 included in one light emitting cell group may emit light of the same color, another may emit light of another color, and another may emit light of another color.

[0372] The light emitting units 130k1 emitting light of the same color may be arranged side by side in a diagonal direction.

[0373] The inner partition wall portion 143k1 according to the first example of the eleventh embodiment may include a first inner partition wall portion 1431 corresponding to a region between two light emitting units 130k1 adjacent to each other in one direction in each light emitting unit group, and a second inner partition wall portion 1432 corresponding to a region between four light emitting units 130k1 included in each light emitting unit group.

[0374] In addition, the outer partition wall portion 144 according to the first example of the eleventh embodiment may be provided around the light emitting cell group.

[0375] Reference Fig.40 , except that two light emitting units 130k2 arranged side by side in the first direction DR1 form one group, the display device 100k2 according to the second example of the eleventh embodiment is similar to Fig.38 Therefore, any redundant description will be omitted below.

[0376] Here, the first light emitting cell EP1, the third light emitting cell EP3, and the second light emitting cell EP2 may be alternately disposed along the first direction DR1 and the second direction DR2.

[0377] The inner partition wall portion 143k2 according to the second example of the eleventh embodiment may be provided between two light emitting cells 130k2 included in each light emitting cell group.

[0378] The outer partition wall portion 144 according to the second example of the eleventh embodiment may be provided around the light emitting cell group.

[0379] Reference Fig.41 , except that two light emitting units 130k3 arranged side by side in the second direction DR2 form one group, the display device 100k3 according to the third example of the eleventh embodiment is similar to Fig.38 Therefore, any redundant description will be omitted below.

[0380] Here, the first light emitting cells EP1 may be arranged side by side in the first direction DR1, the second light emitting cells EP2 may be arranged side by side in the first direction DR1, and the third light emitting cells EP3 may be arranged side by side in the first direction DR1.

[0381] In addition, the first light emitting cell EP1, the third light emitting cell EP3, and the second light emitting cell EP2 may be alternately disposed along the second direction DR2.

[0382] The inner partition wall portion 143k3 according to the third example of the eleventh embodiment may be provided between two light emitting cells 130k3 included in each light emitting cell group.

[0383] The outer partition wall portion 144 according to the third example of the eleventh embodiment may be provided around the light emitting cell group.

[0384] Next, a display device according to another embodiment will be described.

[0385] Fig.42 is a plan view of a display device 100 according to one or more embodiments.

[0386] Reference Fig.42 The display device 100 according to the described embodiment may be applied to a smart phone, a mobile phone, a tablet PC, a personal digital assistant (PDA), a PMP, a television, a game console, a watch-type electronic device, a head-mounted display, a PC monitor, a notebook computer, a car navigation system, a car dashboard, a digital camera, a video camera, an outdoor billboard, an electronic display board, a medical device, an inspection device, various household appliances such as a refrigerator and a washing machine, and / or an Internet of Things (IoT) device. In the present disclosure, a television will be described as an example of a display device, and the television may have a high resolution or an ultra-high resolution, such as HD, UHD, 4K, and / or 8K.

[0387] The display device 100 according to the described embodiment can be variously classified according to the display method. For example, the display device 100 can be classified as an organic light-emitting display device, an inorganic electroluminescent (EL) display device, a quantum dot light-emitting display device (QED), a micro-light-emitting diode display device, a nano-light-emitting diode display device, a plasma display device (PDP), a field emission display (FED) device, a cathode ray tube (CRT) display device, a liquid crystal display (LCD) device and / or an electrophoretic display (EPD) device. As an example of the display device 100, a micro-light-emitting diode display device will be described below. Unless special distinction is required, the micro-light-emitting diode display device applied to the embodiment will be simply abbreviated as a display device. However, one or more embodiments are not limited to micro-light-emitting diode display devices, and other display devices listed above or known in the art may also be applied within the scope of sharing the technical spirit of the present disclosure.

[0388] In the drawings, the first direction DR1 indicates the horizontal direction of the display device 100, the second direction DR2 indicates the vertical direction of the display device 100, and the third direction DR3 indicates the thickness direction of the display device 100. In this case, "left", "right", "upper", and "lower" refer to directions when the display device 100 is viewed in a plan view. For example, "right side" refers to one side in the first direction DR1, "left side" refers to the other side in the first direction DR1, "upper side" refers to one side in the second direction DR2, and "lower side" refers to the other side in the second direction DR2. In addition, "top" refers to one side in the third direction DR3, and "bottom" refers to the other side in the third direction DR3.

[0389] In a plan view, the display device 100 according to the described embodiment may have a square shape, for example, a square shape. In addition, when the display device 100 is a television, it may be in a rectangular shape with a long side positioned in the horizontal direction. However, the embodiments of the present disclosure are not limited thereto, and the long side may also be positioned in the vertical direction, or the display device 100 may be rotatably mounted so that the long side may be variably positioned in the horizontal direction or in the vertical direction. The display device 100 may also have a circular or elliptical shape.

[0390] The display device 100 may include a display area DPA and a non-display area NDA along an edge or periphery of the display area DPA. The display area DPA may be an effective area in which an image is displayed. In a plan view, the display area DPA may have a square shape similar to the overall shape of the display device 100, but the embodiments of the present disclosure are not limited thereto. That is, the display area DPA may have any one of a polygonal shape, a circular shape, and an elliptical shape, or may have a combination of straight lines and curves.

[0391] The display area DPA may include a plurality of pixels PX. The pixels PX may be arranged in a matrix direction. For example, the pixels PX may be arranged along rows and columns of the matrix. In a plan view, each of the pixels PX may be a rectangle or a square. However, the embodiments of the present disclosure are not limited thereto, and each of the pixels PX may also be in a rhombus planar shape with each side inclined relative to the side of the display device 100.

[0392] The pixel PX may be a basic unit for displaying various colors including white and various brightness levels.

[0393] As will be referred to later Fig.47 and Fig.64 As described above, for color display, each of the pixels PX may be composed of two or more emission areas LEA adjacent to each other and corresponding to different colors (see Fig.47 and Fig.64 )constitute.

[0394] For example, two or more emission areas LEA (see Fig.47 and Fig.64 ) may include at least one first emission area LEA1 corresponding to a first color (see Fig.47 and Fig.64 ), at least one second emission area LEA2 corresponding to a second color different from the first color (see Fig.47 and Fig.64 ) and at least one third emission area LEA3 corresponding to a third color different from the first color and the second color (see Fig.47 and Fig.64 ). Here, the first color, the second color, and the third color may be red, green, and blue, respectively.

[0395] Therefore, each of the pixels PX may display color and brightness corresponding to mixed light of the first color light emitted from the first emission area LEA1, the second color light emitted from the second emission area LEA2, and the third color light emitted from the third emission area LEA3.

[0396] In addition, the emission areas LEA constituting the pixel PX may be arranged in the display area DPA along the first direction DR1 or the second direction DR2. Here, the emission areas corresponding to the same color may be arranged side by side with each other in any one of the first direction DR1 and the second direction DR2. In addition, the emission areas corresponding to different colors may be alternately arranged in a stripe type or in the other direction of the first direction DR1 and the second direction DR2. type, but the present disclosure is not limited thereto. The arrangement structure may be referred to as an RGBG matrix structure (eg, Matrix structure or RGBG structure (for example, structure)). is a registered trademark of Samsung Display Co., Ltd. of South Korea. However, this is only an example, and the arrangement form of the emission area LEA according to one or more embodiments is not limited to Fig.47 and Fig.64 The arrangement shown in , and can be changed as needed.

[0397] The non-display area NDA may be disposed around the display area DPA along an edge or periphery of the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. For example, when the display area DPA has a quadrilateral shape, the non-display area NDA may be disposed adjacent to four sides of the display area DPA. The non-display area NDA may correspond to a frame of the display device 100.

[0398] A driving circuit or a driving element for driving the display area DPA may be disposed in the non-display area NDA. In the described embodiment, the pad portion may be disposed on the first side (eg, Fig.42 The display device 100 may be provided in a non-display area NDA adjacent to the lower side of the display device 100, and an external device EXD may be mounted on the pad electrode of the pad portion. Examples of the external device EXD may include a connection film, a printed circuit board, a driver chip DIC, a connector, and / or a wiring connection film. The scan driver SDR may be provided on a second side (e.g., Fig.42 In the non-display area NDA adjacent to the left side of ).

[0399] Fig.43 yes Fig.42 The transistor array layer TFTL (see FIG. Fig.49 ) example layout diagram.

[0400] The display device 100 may include a plurality of emission areas LEA (see Fig.49 ) corresponding to a plurality of thin film transistors of the transistor array layer TFTL (see Fig.49 The transistor array layer TFTL is designed to drive the emission area LEA alone (see Fig.49 ).

[0401] Reference Fig.43 The transistor array layer TFTL may include a plurality of wirings disposed in the display area DPA. Here, the wirings may include a scan line SCL, a sensing signal line SSL, a data line DTL, an initialization voltage line VIL, and a first power line ELVDL.

[0402] The scan lines SCL and the sensing signal lines SSL may extend in the first direction DR1. The scan lines SCL and the sensing signal lines SSL may be connected to a scan driver SDR.

[0403] The scan driver SDR may be disposed in a portion of the non-display area NDA adjacent to one side of the display area DPA in the first direction DR1. Alternatively, the scan driver SDR may be disposed in a portion of the non-display area NDA adjacent to both sides of the display area DPA in the first direction DR1.

[0404] The scan driver SDR may include a driving circuit corresponding to each scan line SCL and each sensing signal line SSL.

[0405] The scan driver SDR may be connected to one end of the signal connection line CWL.

[0406] The other end of the signal connection line CWL may be connected to the external device EXD through a pad WPD_CW provided at an edge of the non-display area NDA (see FIG. Fig.42 ).

[0407] The data line DTL and the initialization voltage line VIL may extend in a second direction DR2 crossing the first direction DR1 .

[0408] The first power line ELVDL may include a portion extending in the second direction DR2. Alternatively, the first power line ELVDL may have a mesh structure further including a portion extending in the first direction DR1. The first power line ELVDL according to the described embodiment is not limited to Fig.43 The first power line ELVDL is shown in FIG.

[0409] End portions of the data line DTL, the initialization voltage line VIL, and the first power line ELVDL may be respectively connected to wiring pads WPD disposed in the non-display area NDA.

[0410] A wiring pad WPD_DT of a data line DTL (hereinafter, referred to as a “data pad”), a wiring pad WPD_RV of an initialization voltage line VIL (hereinafter, referred to as an “initialization voltage pad”), and a wiring pad WPD_ELVDL of a first power line ELVDL may be disposed in a pad portion PDA as an edge of the non-display area NDA.

[0411] External device EXD (see Fig.42 ) can be mounted on the wiring pad WPD.

[0412] The external device EXD may be mounted on the wiring pad WPD through an anisotropic conductive film, ultrasonic bonding, or the like.

[0413] The transistor array layer TFTL may further include a plurality of pixel driving circuits respectively corresponding to the plurality of emission areas LEA arranged in the display area DPA. The pixel driving circuits of the emission areas LEA may be connected to the above wirings and may respectively supply driving currents to the light emitting elements of the emission areas.

[0414] Each of the pixel driving circuits of the emission area LEA may include at least one thin film transistor and at least one capacitor. The number of transistors and capacitors included in each pixel driving circuit and their connection forms may be variously changed.

[0415] An example of a pixel driving circuit will now be described. However, this is merely an example, and the pixel driving circuit according to the described embodiment is not limited to Fig.44 , Fig.45 and Fig.46 The pixel driving circuit shown in , and may also have other various modified structures such as a 2T1C structure, a 7T1C structure, and a 6T1C structure.

[0416] Fig.44 , Fig.45 and Fig.46 yes Fig.43 FIG. 5 is an equivalent circuit diagram of an example of an emission area LEA in a transistor array layer TFTL.

[0417] Reference Fig.44 , the pixel driving circuit of the emission area LEA may include a driving transistor DTR, a first transistor STR1, a second transistor STR2, and a storage capacitor CST.

[0418] The driving transistor DTR is connected in series to the light emitting element LE between a first power line ELVDL supplied with a first power supply voltage and a second power line ELVSL supplied with a second power supply voltage. When the voltage difference between the gate electrode and the source electrode is equal to or greater than the threshold voltage, the driving transistor DTR is turned on and a driving current corresponding to the voltage difference between the gate electrode and the source electrode is supplied to the light emitting element LE.

[0419] The driving transistor DTR may have a gate electrode connected to the first transistor STR1, a source electrode connected to the light emitting element LE, and a drain electrode connected to the first power line ELVDL. Optionally, according to the structure of the driving transistor DTR, the drain electrode of the driving transistor DTR may be connected to the light emitting element LE, and the source electrode may be connected to the first power line ELVDL.

[0420] The first transistor STR1 is connected between the data line DTL and the driving transistor DTR. The gate electrode of the first transistor STR1 is connected to the scan line SCL. The first transistor STR1 is turned on based on the scan signal of the scan line SCL, and supplies the data signal of the data line DTL to the gate electrode of the driving transistor DTR.

[0421] One end of the storage capacitor CST may be connected to a node between the drive transistor DTR and the first transistor STR1 (at the gate electrode of the drive transistor DTR), and the other end may be connected to a node between the drive transistor DTR and the light emitting element LE (at the source electrode of the drive transistor DTR). The storage capacitor CST may be charged with a data signal supplied through the turned-on first transistor STR1. That is, the storage capacitor CST may maintain a voltage difference between the gate electrode and the source electrode of the drive transistor DTR.

[0422] The second transistor STR2 is connected between the driving transistor DTR (e.g., the source electrode of the driving transistor DTR) and the initialization voltage line VIL. The gate electrode of the second transistor STR2 is connected to the sensing signal line SSL. The second transistor STR2 can be turned on based on the sensing signal of the sensing signal line SSL, and the potential of the node between the driving transistor DTR and the light emitting element LE can be initialized to the initialization voltage of the initialization voltage line VIL.

[0423] The driving transistor DTR, the first transistor STR1 and the second transistor STR2 may be configured as thin film transistors. Fig.44 The driving transistor DTR, the first transistor STR1 and the second transistor STR2 are all N-type metal oxide semiconductor field effect transistors (MOSFETs), but one or more embodiments are not limited to Fig.44 That is, at least some of the driving transistor DTR, the first transistor STR1 and the second transistor STR2 may also be P-type MOSFETs.

[0424] Reference Fig.45 , the pixel driving circuit of the emission area LEA according to an example may include a driving transistor DTR, first to sixth transistors STR1 to STR6 , and a storage capacitor CST.

[0425] The driving transistor DTR is connected in series to the light emitting element LE between the first power line ELVDL and the second power line ELVSL.

[0426] That is, a first electrode (eg, source electrode) of the driving transistor DTR may correspond to the first power line ELVDL, and a second electrode (eg, drain electrode) of the driving transistor DTR may correspond to a first electrode (eg, anode) of the light emitting element LE.

[0427] A second electrode (eg, cathode) of the light emitting element LE may be connected to the second power line ELVSL.

[0428] A parasitic capacitance Cel may be formed at both ends of the light emitting element LE.

[0429] The storage capacitor CST may be connected between the gate electrode of the driving transistor DTR and the first power line ELVDL.

[0430] The first transistor STR1 (including transistors ST1-1 and ST1-2 connected in series) may be connected between the gate electrode of the drive transistor DTR and the second electrode (e.g., drain electrode) of the drive transistor DTR. When the first transistor STR1 is turned on based on the gate signal of the write scan line GWL, the gate electrode of the drive transistor DTR and the second electrode of the drive transistor DTR may be changed to the same potential (e.g., the drive transistor DTR may be diode-connected).

[0431] The second transistor STR2 may be connected between the data line DTL and a first electrode (eg, source electrode) of the driving transistor DTR. When the second transistor STR2 is turned on based on a gate signal of the write scan line GWL, a data signal of the data line DTL may be transmitted to the first electrode of the driving transistor DTR.

[0432] Here, when a voltage difference between the gate electrode of the driving transistor DTR and the first electrode of the driving transistor DTR is equal to or greater than a threshold voltage, the driving transistor DTR is turned on and generates a driving current corresponding to the voltage difference between the gate electrode and the source electrode.

[0433] The third transistor STR3 (including transistors ST3-1 and ST3-2 connected in series) can be connected between the gate electrode of the driving transistor DTR and the initialization voltage line VIL. When the third transistor STR3 is turned on by the gate signal of the initialization scan line GIL, the potential of the gate electrode of the driving transistor DTR can be initialized to the voltage of the initialization voltage line VIL.

[0434] The fourth transistor STR4 may be connected between the first electrode (eg, anode) of the light emitting element LE and the initialization voltage line VIL. When the fourth transistor STR4 is turned on by the gate signal of the control scan line GCL, the potential of the first electrode (eg, anode) of the light emitting element LE may be initialized to the voltage of the initialization voltage line VIL.

[0435] The fifth transistor STR5 may be connected between the first power line ELVDL and the driving transistor DTR.

[0436] The sixth transistor STR6 may be connected between the driving transistor DTR and the light emitting element LE.

[0437] When the fifth transistor STR5 and the sixth transistor STR6 are turned on by the gate signal of the emission line EL, the driving current generated by the driving transistor DTR may be supplied to the light emitting element LE.

[0438] The active layer of each of the first to sixth transistors STR1 to STR6 and the driving transistor DTR may be made of one or more selected from polysilicon, amorphous silicon, and oxide semiconductors. For example, the semiconductor layer of each of the first to sixth transistors STR1 to STR6 and the driving transistor DTR may be made of polysilicon by a low temperature polysilicon (LTPS) process.

[0439] Although the first to sixth transistors STR1 to STR6 and the driving transistor DTR are Fig.45 is formed as a P-type MOSFET, but one or more embodiments are not limited to Fig.45 , at least some of the first to sixth transistors STR1 to STR6 and the driving transistor DTR may also be formed as N-type MOSFETs.

[0440] The first power supply voltage of the first power line ELVDL, the second power supply voltage of the second power line ELVSL, and the initialization voltage of the initialization voltage line VIL may be set in consideration of characteristics of the driving transistor DTR and characteristics of the light emitting element LE.

[0441] Reference Fig.46 , except that the first transistor STR1 and the third transistor STR3 are formed as N-type MOSFETs, the pixel driving circuit of the emission area LEA according to the example Fig.45 Therefore, any redundant description will be omitted below.

[0442] Reference Fig.46 The driving transistor DTR, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5 and the sixth transistor STR6 are formed as P-type MOSFETs. The active layer of each of the driving transistor DTR, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5 and the sixth transistor STR6 may be made of polysilicon.

[0443] An active layer of each of the first transistor STR1 and the third transistor STR3 formed as an N-type MOSFET may be made of an oxide semiconductor.

[0444] In addition, a gate electrode of the first transistor STR1 formed as an N-type MOSFET may be connected to the control scan line GCL, but not to the write scan line GWL. That is, the first transistor STR1 may be turned on by a gate signal of the control scan line GCL.

[0445] The write scan line GWL may be alternatively connected to a gate electrode of the fourth transistor STR4 formed as a P-type MOSFET.

[0446] Here, the gate signal controlling the scan line GCL and the gate signal initializing the scan line GIL may be a gate high voltage for turning on the N-type MOSFET.

[0447] On the other hand, the gate signal of the write scanning line GWL and the gate signal of the emission line EL may be a gate low voltage for turning on the P-type MOSFET.

[0448] The pixel driving circuit according to the described embodiments is not limited to Figures 44 to 46 , and in addition Figures 44 to 46 In addition to the structure shown in , it can also be formed with other known circuit structures that can be adopted by those skilled in the art.

[0449] Fig.47 is shown with Fig.42 FIG. 1 is a layout diagram of an example of a plurality of emission areas LEA corresponding to portion A. FIG.

[0450] Reference Fig.47 , the display device 100 according to the described embodiment includes a plurality of emission areas LEA arranged in a display area DPA.

[0451] Each of the emission areas LEA may be a basic unit that displays a specific color at a desired brightness (eg, a predetermined brightness) to display an image.

[0452] The emission area LEA includes a first emission area LEA1 emitting light of a first color, a second emission area LEA2 emitting light of a second color, and a third emission area LEA3 emitting light of a third color.

[0453] Here, the first color, the second color, and the third color may correspond to different main peak wavelengths.

[0454] For example, the second color may correspond to a main peak wavelength lower than that of the first color, and the third color may correspond to a main peak wavelength lower than that of the second color. In this case, the first color may be red corresponding to a wavelength band of about 600nm to 750nm, the second color may be green corresponding to a wavelength band of about 480nm to 560nm, and the third color may be blue corresponding to a wavelength band of about 370nm to 460nm.

[0455] According to the described embodiment, the first, second and third emission areas LEA1, LEA2 and LEA3 may be arranged side by side along the second direction DR2. In addition, the first, second and third emission areas LEA1, LEA2 and LEA3 may be alternately arranged along the first direction DR1.

[0456] In this case, each of the plurality of pixels PX may be composed of a combination of one first emission area LEA1, one second emission area LEA2, and one third emission area LEA3 adjacent to each other in the first direction DR1. However, this is merely an example, and the configuration of each pixel PX according to the described embodiment is not limited to Fig.47 The construction shown in , and can be changed as needed.

[0457] The emission areas LEA are spaced apart from each other in the first direction DR1 and the second direction DR2, and a region between the emission areas LEA is a non-emission area NEA that does not emit light in the display area DPA.

[0458] Fig.48 is shown with Fig.47 A portion B corresponds to a plan view of an example of a pixel electrode PE and a dummy pattern DMP.

[0459] Reference Fig.48 The display device 100 according to the described embodiment includes a plurality of pixel electrodes PE corresponding to emission areas LEA respectively, a plurality of dummy patterns DMP corresponding to non-emission areas NEA between the emission areas LEA, and a light emitting element array layer including a plurality of light emitting elements LE corresponding to the emission areas LEA.

[0460] The pixel electrodes PE correspond to the emission areas LEA, respectively. Like the emission areas LEA, the pixel electrodes PE may be spaced apart from each other in each of the first direction DR1 and the second direction DR2.

[0461] For example, the pixel electrodes PE may be spaced apart from each other by a distance G1 (eg, a predetermined distance G1 , hereinafter, referred to as a 'first distance') in the first direction DR1 .

[0462] according to Fig.48 In the first example B1, the dummy pattern DMP is disposed in the non-emission area NEA between the pixel electrodes PE corresponding to the emission area LEA. The dummy pattern DMP is spaced apart from the pixel electrode PE. That is, the dummy pattern DMP is formed as an island pattern.

[0463] For example, one or more dummy patterns DMP may be disposed between every two pixel electrodes PE adjacent to each other in at least one direction (eg, the first direction DR1 ) of the first direction DR1 and the second direction DR2 .

[0464] That is to say, Fig.48 As shown in, when the first emission area LEA1, the second emission area LEA2 and the third emission area LEA3 are alternately arranged side by side along the first direction DR1, one dummy pattern DMP may be set between the pixel electrode PE_LEA1 of the first emission area LEA1 and the pixel electrode PE_LEA2 of the second emission area LEA2, one dummy pattern DMP may be set between the pixel electrode PE_LEA2 of the second emission area LEA2 and the pixel electrode PE_LEA3 of the third emission area LEA3, and one dummy pattern DMP may be set between the pixel electrode PE_LEA3 of the third emission area LEA3 and the pixel electrode PE_LEA1 of the first emission area LEA1.

[0465] Here, the dummy patterns DMP are alternately and side by side arranged with the pixel electrodes PE in the first direction DR1. The width of each dummy pattern DMP in the second direction DR2 may be in the same range as the width of each pixel electrode PE in the second direction DR2.

[0466] The light emitting elements LE are disposed on the pixel electrodes PE respectively corresponding to the emission areas LEA, and are spaced apart from each other in the first direction DR1 and the second direction DR2.

[0467] The light emitting elements LE may be spaced apart from each other by a distance G3 (hereinafter referred to as a "third distance") within the same range in at least one direction of the first direction DR1 and the second direction DR2. Here, the same range may refer to a range including a margin that can be considered the same. For example, the same range may include a margin within ±15%. However, this is merely an example, and the definition of the same range may be changed according to the size and resolution of the display device 100.

[0468] The sum of the third distance G3 between the light emitting elements LE in the first direction DR1 and the width W1 of each light emitting element LE in the first direction DR1 (hereinafter referred to as the “first width”) is smaller than the width W3 of each pixel electrode PE in the first direction DR1 (hereinafter referred to as the “third width”).

[0469] Therefore, at least one light emitting element LE may be disposed on each of the pixel electrodes PE.

[0470] In other words, each of the emission areas LEA may correspond to two or more light emitting elements LE.

[0471] That is, two or more light emitting elements LE adjacent to each other in the first direction DR1 or the second direction DR2 may be disposed on each of the pixel electrodes PE corresponding to the emission area LEA.

[0472] To this end, the width W3 of each of the pixel electrodes PE in the first direction DR1 may be greater than the sum of at least one times the first width W1 of each light emitting element LE and at least one times the third distance G3 between the light emitting elements LE in the first direction DR1.

[0473] In the first direction DR1 or the second direction DR2 , the width of each of the pixel electrodes PE, the width of each of the light emitting elements LE, and the distance between the light emitting elements LE may be maintained within the same range.

[0474] In this case, even in a process of arranging the light emitting elements LE on the pixel electrodes PE concurrently (eg, simultaneously), the same number of light emitting elements LE may be disposed on each of the pixel electrodes PE.

[0475] Here, the number of light emitting elements LE disposed on each of the pixel electrodes PE may correspond to the width of the pixel electrode PE, the width of each light emitting element LE, and the distance between the light emitting elements LE. The number of light emitting elements LE disposed on each of the pixel electrodes PE is not limited to Fig.48 The number of light emitting elements LE provided on each of the pixel electrodes PE is shown in FIG. 1 and may be changed based on the width of each pixel electrode PE, the width of each light emitting element LE, and the distance between the light emitting elements LE.

[0476] In one or more embodiments, the light emitting elements LE are not arranged individually one by one, but are arranged all at once. As a result, some of the light emitting elements LE are partially disposed in the non-emission area NEA. That is, as will be described later Fig.53 and Fig.54 As shown in FIG. 1 , due to process errors, some of the light emitting elements LE may be partially disposed on each pixel electrode PE and the non-emission area NEA, or may be disposed in the non-emission area NEA.

[0477] Here, if the light emitting element LE disposed in the non-emission area NEA between any two pixel electrodes PE is partially disposed on both of the two pixel electrodes PE, a display defect in which the light emitting element LE is driven by at least one of the two pixel electrodes PE may occur.

[0478] To prevent this, a first distance G1 between pixel electrodes PE adjacent to each other in the first direction DR1 may be selected within a range greater than a first width W1 of each light emitting element LE in the first direction DR1 (ie, G1>W1).

[0479] In this case, some of the light emitting elements LE partially disposed in the non-emission area NEA due to an alignment error in the first direction DR1 may be connected to only one pixel electrode PE and thus may be driven by only a driving current supplied through the one pixel electrode PE.

[0480] In addition, the display device 100 according to the described embodiment includes a plurality of dummy patterns DMP disposed in the non-emission area NEA between the emission areas LEA.

[0481] Therefore, some of the light emitting elements LE partially disposed in the non-emission area NEA due to the alignment error can be supported by the dummy pattern DMP disposed in the non-emission area NEA. Therefore, it is possible to prevent the light emitting elements LE disposed on the edge of the pixel electrode PE due to the alignment error in the first direction DR1 from tilting due to the step of the pixel electrode PE.

[0482] That is, even if there are light emitting elements LE protruding into the non-emission area NEA due to all the light emitting elements LE being arranged at once, the inclination defect of these light emitting elements LE can be prevented by the dummy pattern DMP.

[0483] like Fig.48 As shown in , when the dummy pattern DMP is disposed between pixel electrodes PE adjacent to each other along the first direction DR1, the pixel electrode PE of the emission area LEA and the dummy pattern DMP adjacent to the emission area LEA may be spaced apart from each other by a distance G2 (e.g., a predetermined distance G2, hereinafter referred to as a "second distance") in the first direction DR1.

[0484] Assuming that a tilt defect of the light emitting element LE occurs when the light emitting element LE protrudes into the non-emission area NEA by a distance greater than a threshold, the second distance G2 between the pixel electrode PE and the dummy pattern DMP may be set equal to or less than the threshold of the tilt defect.

[0485] For example, if more than half of the light emitting element LE is disposed in the non-emission area NEA, the center of gravity of the light emitting element LE will not be supported by the pixel electrode PE, resulting in a tilt defect of the light emitting element LE. Therefore, the threshold of the tilt defect may be half of the width of the light emitting element LE in the first direction DR1 (i.e., the first width W1).

[0486] Therefore, the second distance G2 between the pixel electrode PE and the dummy pattern DMP adjacent to each other can be selected within a range greater than 0 and less than or equal to half of the first width W1 of the light emitting element LE (ie, 0 <G2≤(W1) / 2)。

[0487] In this case, a tilt defect of the light emitting element LE partially disposed in the non-emission area NEA may be prevented by the dummy pattern DMP.

[0488] Each of the dummy patterns DMP may have a predetermined width W2 (hereinafter, referred to as a 'second width') in the first direction DR1.

[0489] When each dummy pattern DMP is spaced apart from two adjacent pixel electrodes PE on both sides along the first direction DR1 by the same second distance G2, a sum (W2+2×G2) of the second width W2 of the dummy pattern DMP and twice (2×G2) of the second distance G2 may correspond to the first distance G1 between two adjacent pixel electrodes PE in the first direction DR1 (i.e., (W2+2×G2)≒G1) or may be less than the first distance G1 between two adjacent pixel electrodes PE in the first direction DR1 (i.e., (W2+2×G2)≒G1). <G1)。

[0490] In addition, the sum of the second width W2 and the second distance G2 may be selected within a range greater than half of the first width W1 (ie, W2+G2>(W1) / 2, W2>(W1) / 2-G2).

[0491] In this case, a portion of the light emitting element LE protruding into the non-emission area NEA that protrudes farthest from the edge of the pixel electrode PE may be supported by the dummy pattern DMP. That is, one side of the light emitting element LE protruding into the non-emission area NEA in the first direction DR1 may be supported by the pixel electrode PE, and the other side in the first direction DR1 may be supported by the dummy pattern DMP. Therefore, the reliability of the dummy pattern DMP for preventing the tilt defect of the light emitting element LE may be improved.

[0492] Fig.49 It is along Fig.48 A cross-sectional view taken along line CC'. Fig.50 yes Fig.49 FIG. 4 is a cross-sectional view of an example of a transistor array layer TFTL. Fig.51 yes Fig.49 Detailed cross-sectional view of portion D.

[0493] Reference Fig.49 The display device 100 according to the described embodiment includes a substrate SUB including a display area DPA (see Fig.42), a plurality of pixel electrodes PE disposed on a substrate SUB and corresponding to the emission areas LEA respectively, a plurality of dummy patterns DMP disposed on the substrate SUB and corresponding to the non-emission areas NEA between the emission areas LEA, a light emitting element array layer EML including a plurality of light emitting elements LE corresponding to the emission areas LEA, a planarization layer PLL disposed between the light emitting elements LE and covering the pixel electrodes PE and the dummy patterns DMP, and a common electrode CE disposed on the light emitting element array layer EML and the planarization layer PLL and corresponding to the emission areas LEA and the non-emission areas NEA.

[0494] The substrate SUB may be a rigid substrate made of a glass material. Alternatively, the substrate SUB may be a flexible substrate that can be bent, folded, or rolled. In this case, the substrate SUB may include an insulating material such as a polymer resin (eg, polyimide (PI)).

[0495] The display device 100 may further include a transistor array layer TFTL disposed on the substrate SUB.

[0496] The transistor array layer TFTL may include a plurality of thin film transistors DTR and STR1 corresponding to the emission area LEA and a via layer VIA covering the thin film transistors DTR and STR1. Fig.50 as shown in .

[0497] The pixel electrode PE and the dummy pattern DMP may be disposed on the via layer VIA.

[0498] The pixel electrode PE can be connected to a plurality of pixel drivers of the transistor array layer TFTL through contact holes CTH penetrating the via layer VIA. Fig.49 As shown in , the pixel electrodes PE may be respectively connected to a plurality of driving transistors DTR.

[0499] Reference Fig.50 The transistor array layer TFTL may include a buffer layer BFL disposed on a substrate SUB, a first gate insulating layer GI1 covering the active layer ACT on the buffer layer BFL, a second gate insulating layer GI2 covering the gate electrode G on the first gate insulating layer GI1, an interlayer insulating layer ILI covering the capacitor electrode CAE on the second gate insulating layer GI2, a first via layer VIA1 covering the source electrode S and the drain electrode D on the interlayer insulating layer ILI, and a second via layer VIA2 covering the anode connection electrode ANDE on the first via layer VIA1.

[0500] Fig.50 The transistor array layer TFTL can be Fig.44 Corresponding to the pixel driving circuit.

[0501] That is to say, Fig.44 and Fig.50 A driving transistor DTR connected to a light emitting element LE and a first transistor STR1 connected to a data line DTL in each pixel driving circuit are shown. The first transistor STR1 has a structure substantially the same as that of the driving transistor DTR. Therefore, unless specifically mentioned, the driving transistor DTR will be mainly described below, and a redundant description of the first transistor STR1 will be omitted.

[0502] The buffer layer BFL is designed to prevent moisture or oxygen from penetrating through the substrate SUB. The buffer layer BFL may be a single layer or a multilayer made of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0503] The active layer ACT corresponds to the channel of each thin film transistor provided in each pixel driving circuit. The active layer ACT may be made of a semiconductor material. For example, the active layer ACT may be made of a semiconductor material selected from amorphous silicon, polycrystalline silicon, and an oxide semiconductor. Here, the oxide semiconductor may include a binary compound (AB) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ) or quaternary compound (AB x C y D z ). For example, the active layer ACT may include indium tin zinc oxide (IGZO).

[0504] The active layer ACT includes a channel area CHA generating a carrier moving path according to a potential of a gate electrode, and first and second conductive areas COA1 and COA2 disposed at both sides of the channel area CHA.

[0505] When the active layer ACT is made of an oxide semiconductor, the first and second conductive regions COA1 and COA2 may be regions that conduct electricity by being exposed to ions or the like.

[0506] Each of the first gate insulating layer GI1 and the second gate insulating layer GI2 may include one or more selected from silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, and the like.

[0507] The gate electrode G on the first gate insulating layer GI1 overlaps the channel area CHA of the active layer ACT in the third direction DR3 .

[0508] The gate electrode G may include, for example, ITO, IZO, ITZO and / or In 2 O 3The metal oxide may include a metal selected from copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg) and nickel (Ni).

[0509] The capacitor electrode CAE on the second gate insulating layer GI2 may at least partially overlap the gate electrode G of the driving transistor DTR in the third direction DR3. In addition, the capacitor electrode CAE may be connected to the source electrode S on the interlayer insulating layer ILI through a hole penetrating the interlayer insulating layer ILI.

[0510] Therefore, the storage capacitor CST (see FIG. Fig.44 ) can be set by the overlapping region between the gate electrode G and the capacitor electrode CAE.

[0511] The interlayer insulating layer ILI may include an inorganic insulating material including one or more selected from silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide.

[0512] The source electrode S on the interlayer insulating layer ILI may be connected to the first conductive area COA1 of the active layer ACT through a hole penetrating the interlayer insulating layer ILI, the second gate insulating layer GI2 , and the first gate insulating layer GI1 .

[0513] The drain electrode D on the interlayer insulating layer ILI may be connected to the second conductive area COA2 of the active layer ACT through a hole penetrating the interlayer insulating layer ILI, the second gate insulating layer GI2 , and the first gate insulating layer GI1 .

[0514] Each of the source electrode S and the drain electrode D may include a material selected from the group consisting of ITO, IZO, ITZO, and In 2 O 3 The present invention may be a single layer or multiple layers made of one or more metal oxides, or may include metals such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg) and / or nickel (Ni).

[0515] The via layer VIA covering the thin film transistors DTR and STR1 may include a first via layer VIA1 covering the source electrode S and the drain electrode D on the interlayer insulating layer ILI and a second via layer VIA2 covering the anode connection electrode ANDE on the first via layer VIA1 .

[0516] The data line DTL may be disposed on the first via layer VIA1 and may be connected to the first transistor STR1 through a hole penetrating the first via layer VIA1 .

[0517] The anode connection electrode ANDE may be connected to the drain electrode D of the driving transistor DTR through a first contact hole CTH1 penetrating the first via layer VIA1 .

[0518] Each of the first via layer VIA1 and the second via layer VIA2 may include an organic insulating material including one or more selected from among acrylic resin, epoxy resin, imide resin, and ester resin.

[0519] Each of the anode connection electrode ANDE and the data line DTL may include a material selected from ITO, IZO, ITZO, and In 2 O 3 The present invention may be a single layer or multiple layers made of metal oxides, or may include a metal selected from copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg) and nickel (Ni).

[0520] Each of the pixel electrodes PE may have a material layer having a high work function (such as titanium oxide (TiO 2 ), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO) or magnesium oxide (MgO)) and a stacked structure of a reflective material layer (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) and / or a mixture thereof).

[0521] The pixel electrode PE may be connected to the anode connection electrode ANDE through a second contact hole CTH2 penetrating the second via layer VIA2 .

[0522] The dummy pattern DMP is designed to prevent the tilt defect of the light emitting element LE caused by the step of the pixel electrode PE. Therefore, in order to prevent the tilt of the light emitting element LE partially disposed on the dummy pattern DMP and the pixel electrode PE, the dummy pattern DMP may have a thickness within the same range as that of the pixel electrode PE so that they are disposed parallel to the pixel electrode PE.

[0523] The dummy pattern DMP may be made of the same material as that of the pixel electrode PE. In this case, the dummy pattern DMP may be kept in a floating state so as not to cause unnecessary electrical signals. That is, the dummy pattern DMP may be in a floating state in which they are not electrically connected to the pixel electrode PE, and may be shaped as an island spaced apart from the pixel electrode PE.

[0524] Alternatively, the dummy pattern DMP may be made of an insulating material having a thickness in the same range as that of the pixel electrode PE. In this case, the dummy pattern DMP may be made of an inorganic insulating material in order to prevent the via layer VIA from being damaged by a patterning process for arranging the dummy pattern DMP.

[0525] like Fig.49 As shown in FIG. 1 , a light emitting element array layer EML including a plurality of light emitting elements LE is disposed on the pixel electrode PE.

[0526] Alternatively, if Fig.53 , Fig.54 and Fig.55 As shown in FIG. 1 , due to an alignment error of the light emitting element array layer EML, some of the light emitting elements LE may be partially disposed on the dummy pattern DMP of the non-emission area NEA.

[0527] Reference Fig.51 , each of the light emitting elements LE may be a vertical light emitting diode element connected between the pixel electrode PE and the common electrode CE facing each other in the third direction DR3.

[0528] In addition, each of the light emitting elements LE may be a micro light emitting diode element. For example, the length of each light emitting element LE in the third direction DR3 may be about 1 μm to 5 μm.

[0529] Each of the light emitting elements LE may be shaped like a column whose width in the first direction DR1 and the second direction DR2 is smaller than the length in the third direction DR3. For example, each of the light emitting elements LE may be shaped like a cylinder, a disk, or a rod. However, the shape of each of the light emitting elements LE is not limited thereto, and may also be modified to include various shapes such as a rod, a wire, and / or a tube, a polygonal prism (such as a cube, a cuboid, and a hexagonal prism), and a shape extending in one direction and having a partially inclined outer surface.

[0530] Each of the light emitting elements LE may include a first semiconductor layer SEM1 and a second semiconductor layer SEM2 doped with dopants of different conductivity types and an active layer MQW disposed between the first semiconductor layer SEM1 and the second semiconductor layer SEM2. In each of the light emitting elements LE, electron-hole pairs may be generated in the active layer MQW by holes and electrons transmitted through the first semiconductor layer SEM1 and the second semiconductor layer SEM2, and photons may be generated by the electron-hole pairs.

[0531] Each of the light emitting elements LE may include a connection electrode CNE, a first semiconductor layer SEM1 , an electron blocking layer EBL, an active layer MQW, a superlattice layer SLT, a second semiconductor layer SEM2 , and a third semiconductor layer SEM3 sequentially disposed in the third direction DR3 .

[0532] The first semiconductor layer SEM1 may be connected to the pixel electrode PE through the connection electrode CNE and the contact electrode CTE, and the second semiconductor layer SEM2 may be connected to the common electrode CE through the third semiconductor layer SEM3. Therefore, electrons and holes generated by the driving current between the pixel electrode PE and the common electrode CE may be transferred to the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0533] Each of the light emitting elements LE may further include a contact electrode CTE disposed between the connection electrode CNE and the pixel electrode PE.

[0534] The contact electrode CTE is designed to improve adhesion characteristics and / or interface characteristics between the connection electrode CNE and the pixel electrode PE.

[0535] Although not shown in detail, the contact electrode CTE may have a multi-layer structure of a conductive material. For example, the contact electrode CTE may include a first contact layer contacting the pixel electrode PE and a second contact layer contacting the connection electrode CNE.

[0536] For example, when the uppermost portion of the pixel electrode PE is made of ITO, the first contact layer may include titanium (Ti). However, this is merely an example, and the first contact layer may be any metal material having excellent adhesion to the pixel electrode PE.

[0537] The second contact layer may be made of a metal material having excellent adhesion to the connection electrode CNE. For example, when the connection electrode CNE is an alloy (SAC305) of copper, silver, and tin, the second contact layer may include copper (Cu) or gold (Au).

[0538] The connection electrode CNE may include a connection layer contacting the contact electrode CTE and a reflective layer contacting the first semiconductor layer SEM1 .

[0539] The connection layer is designed to reduce the resistance between the pixel electrode PE and the first semiconductor layer SEM1, and may be an ohmic connection electrode or a Schottky connection electrode. The connection layer may include at least one selected from gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the connection layer may include an alloy of gold and tin at 9:1, 8:2, or 7:3, or may include an alloy of copper, silver, and tin (SAC305).

[0540] The reflective layer is designed to reflect light from the active layer MQW toward the second semiconductor layer SEM2. The reflective layer may include aluminum (Al) or silver (Ag) or may be an alloy thereof. Optionally, the reflective layer may also include ITO.

[0541] The first semiconductor layer SEM1 on the connection electrode CNE may include a chemical formula of Al x Ga y In 1-x-y The semiconductor material may be a p-type semiconductor doped with a p-type dopant.

[0542] For example, the first semiconductor layer SEM1 may be made of p-type doped AlGaInN, GaN, AlGaN, InGaN, AlN and / or InN.

[0543] The p-type dopant of the first semiconductor layer SEM1 may be selected from Mg, Zn, Ca, Sr, Ba, and the like.

[0544] For example, the first semiconductor layer SEM1 may be p-GaN doped with Mg.

[0545] The thickness of the first semiconductor layer SEM1 may be in the range of, but not limited to, 30 nm to 200 nm.

[0546] The electron blocking layer EBL on the first semiconductor layer SEM1 is designed to suppress or prevent too many electrons from flowing into the active layer MQW, and may also be omitted according to the characteristics of the first semiconductor layer SEM1 and the active layer MQW.

[0547] The electron blocking layer EBL may be p-AlGaN doped with Mg.

[0548] The thickness of the electron blocking layer EBL may be in the range of, but not limited to, 10 nm to 50 nm.

[0549] The active layer MQW may be disposed on the electron blocking layer EBL and may emit light through recombination of electron-hole pairs according to an electrical signal received through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0550] The active layer MQW may emit light of the first color having a central wavelength band of 450nm to 495nm, ie, light in a blue wavelength band. Alternatively, the active layer MQW may emit light having a central wavelength band of 400nm to 420nm, ie, light in an ultraviolet wavelength band.

[0551] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, it may have a structure in which a plurality of well layers and a plurality of barrier layers are alternately stacked. Here, the well layer may be made of InGaN, and the barrier layer may be made of GaN and / or AlGaN, but the embodiments of the present disclosure are not limited thereto. The well layer may have a thickness of about 1 nm to 4 nm, and the barrier layer may have a thickness of 3 nm to 10 nm.

[0552] Alternatively, the active layer MQW may have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked, or may include different group III to group V semiconductor materials according to the wavelength band of light emitted therefrom.

[0553] The wavelength band of light emitted from the active layer MQW may correspond to the composition ratio of the active layer MQW.

[0554] For example, when some of the semiconductor materials of the active layer MQW include indium, the color of the emitted light may vary according to the content of indium. For example, if the content of indium is about 15%, light in the blue band may be emitted. If the content of indium is about 25%, light in the green band may be emitted. If the content of indium is about 35% or more, light in the red band may be emitted.

[0555] The superlattice layer SLT on the active layer MQW is designed to relieve stress between the second semiconductor layer SEM2 and the active layer MQW. The superlattice layer SLT may be omitted depending on the interface characteristics of the second semiconductor layer SEM2 and the active layer MQW.

[0556] For example, the superlattice layer SLT may be made of InGaN and / or GaN. The thickness of the superlattice layer SLT may be about 50 nm to 200 nm.

[0557] The second semiconductor layer SEM2 on the superlattice layer SLT may include a chemical formula of Al x Ga y In 1-x-y The semiconductor material may be N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and may be an n-type semiconductor doped with an n-type dopant.

[0558] For example, the second semiconductor layer SEM2 may be made of one or more selected from among n-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN.

[0559] The n-type dopant of the second semiconductor layer SEM2 may be selected from Si, Ge, Se, and Sn.

[0560] For example, the second semiconductor layer SEM2 may be n-GaN doped with Si.

[0561] The thickness of the second semiconductor layer SEM2 may be in the range of, but not limited to, 2 μm to 4 μm.

[0562] The third semiconductor layer SEM3 between the second semiconductor layer SEM2 and the common electrode CE may be an undoped semiconductor.

[0563] That is, the third semiconductor layer SEM3 may include the same material as that of the second semiconductor layer SEM2, but may be a material not doped with an n-type or p-type dopant. For example, the third semiconductor layer SEM3 may be, but is not limited to, at least one selected from undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN.

[0564] The planarization layer PLL is designed to prevent the common electrode CE on the light emitting element LE from being damaged due to a step difference corresponding to the length of the light emitting element LE in the third direction DR3. The planarization layer PLL is disposed between the light emitting elements LE and covers the pixel electrode PE and the dummy pattern DMP.

[0565] The planarization layer PLL may be made of an organic insulating material, which makes it relatively easy to form the planarization layer PLL thickly. That is, the planarization layer PLL may be made of one or more selected from polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (BCB).

[0566] The planarization layer PLL has a thickness smaller than that of the light emitting element LE so as not to completely cover the light emitting element LE. Therefore, one end of each of the light emitting elements LE may be electrically connected to the pixel electrode PE, and the other end may be electrically connected to the common electrode CE.

[0567] The common electrode CE corresponds to the emission area LEA and the non-emission area NEA and is disposed on the light emitting element array layer EML including the light emitting element LE and on the planarization layer PLL. For example, the common electrode CE may be disposed over at least the entire display area DPA.

[0568] Because the light emitting elements LE are not completely covered by the planarization layer PLL, the common electrode CE may contact at least the third semiconductor layer SEM3 of each of the light emitting elements LE and may be electrically connected to the second semiconductor layer SEM2 of each of the light emitting elements LE.

[0569] Since light of each light emitting element LE is emitted through the common electrode CE, the common electrode CE may be thin enough to transmit the light.

[0570] For example, the common electrode CE may have, but is not limited to, about to Thickness.

[0571] In addition, since the common electrode CE is wider than the pixel electrode PE, the common electrode CE may include a material having a relatively low resistance to reduce sheet resistance.

[0572] For example, the common electrode CE may include a material having low resistance, such as aluminum (Al), silver (Ag), and / or copper (Cu).

[0573] like Fig.49 As shown in , the display device 100 according to the described embodiment may further include a color conversion array layer CCAL disposed on the common electrode CE and a color filter layer CFL disposed on the color conversion array layer CCAL.

[0574] The color conversion array layer CCAL is designed to convert the light of the light emitting element LE into light of a higher wavelength band so that each of the emission areas LEA can display a corresponding color.

[0575] The color filter layer CFL is designed to selectively transmit light of a wavelength band corresponding to the color of each emission area LEA from among the light output from the color conversion array layer CCAL, so that each of the emission areas LEA can display the corresponding color more clearly.

[0576] Therefore, even if the light emitting element array layer EML includes a plurality of light emitting elements LE emitting light of the same wavelength band, the display device 100 can display various colors instead of a single color.

[0577] For example, Fig.49 As shown in, when the light emitting element LE emits light of a third color, the color conversion array layer CCAL may include a first color conversion pattern CCP1 corresponding to the first emission area LEA1, a second color conversion pattern CCP2 corresponding to the second emission area LEA2, a transmission pattern TRP corresponding to the third emission area LEA3, and a partition wall pattern WLP corresponding to the non-emission area NEA.

[0578] The first color conversion pattern CCP1 of the first emission area LEA1 corresponding to the first color may include a first color conversion member WCP1 that converts at least a portion of light from the light emitting element LE into light of the first color in a wavelength band higher than that of the third color.

[0579] The second color conversion pattern CCP2 of the second emission area LEA2 corresponding to the second color may include a second color conversion member WCP2 that converts at least a portion of light from the light emitting element LE into light of the second color in a wavelength band higher than that of the third color.

[0580] The transmissive pattern TRP of the third emission area LEA3 corresponding to the third color guides the light of the light emitting element LE toward the color filter layer CFL.

[0581] For example, the first color conversion pattern CCP1 may include a suitable base resin BRS (eg, a predetermined base resin BRS) having a light-transmitting property and the first color conversion member WCP1 dispersed in the base resin BRS.

[0582] Similarly, the second color conversion pattern CCP2 may include a suitable base resin BRS (eg, a predetermined base resin BRS) having a light-transmitting property and a second color conversion member WCP2 dispersed in the base resin BRS.

[0583] The base resin BRS may be made of an organic material that is cured by ultraviolet light or heat and has a light-transmitting property. For example, the base resin BRS may include one or more selected from epoxy resin, acrylic resin, cardo resin, and imide resin.

[0584] Each of the first and second color conversion members WCP1 and WCP2 may be a quantum dot, a quantum rod, a fluorescent material, and / or a phosphorescent material. For example, a quantum dot may be a particle material that emits light of a specific color when electrons transition from a conduction band to a valence band.

[0585] Specifically, quantum dots can be semiconductor nanocrystal materials. That is, quantum dots can have a specific band gap depending on their composition and size. Therefore, quantum dots can absorb light and then emit light with a unique wavelength. Examples of semiconductor nanocrystals include IV group nanocrystals, II-VI group compound nanocrystals, III-V group compound nanocrystals, IV-VI group compound nanocrystals, and combinations thereof.

[0586] The II-VI compounds can be selected from: binary compounds selected from CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe and MgS; ternary compounds selected from InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, C CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe and MgZnS; and quaternary compounds selected from HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe and HgZnSTe.

[0587] The III-V compounds can be selected from: binary compounds selected from GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs and InSb; ternary compounds selected from GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs and InPSb; and quaternary compounds selected from GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs and InAlPSb.

[0588] The IV-VI compound may be selected from: a binary compound selected from SnS, SnSe, SnTe, PbS, PbSe and PbTe; a ternary compound selected from SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe and SnPbTe; and a quaternary compound selected from SnPbSSe, SnPbSeTe and SnPbSTe. The IV element may be selected from silicon (Si) and germanium (Ge). The IV compound may be a binary compound selected from silicon carbide (SiC) and silicon germanium (SiGe).

[0589] Here, the binary compound, ternary compound and / or quaternary compound may be present in the particle at a uniform concentration, or may be present in the same particle at partially different concentrations. In addition, they may have a core / shell structure in which one quantum dot surrounds another quantum dot. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0590] In the described embodiments, the quantum dot may have a core-shell structure including a core containing the above-mentioned nanocrystals and a shell surrounding the core. The shell of the quantum dot may be used as a protective layer for maintaining semiconductor properties by preventing chemical denaturation of the core and / or as a charging layer for imparting electrophoretic properties to the quantum dot. The shell may be a single layer or multiple layers. The shell of the quantum dot may be, for example, a metal or non-metal oxide, a semiconductor compound, or a combination thereof.

[0591] For example, the metal or non-metal oxide may be, but is not limited to, selected from SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 and binary compounds such as NiO or MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 and / or CoMn 2 O 4 of ternary compounds.

[0592] In addition, the semiconductor compound can be, but is not limited to, selected from CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP and AlSb.

[0593] Alternatively, the first color conversion member WCP1 and the second color conversion member WCP2 may convert the light of the third color emitted from the light emitting element LE into light of a fourth color in a wavelength band between the wavelength band of the first color and the wavelength band of the second color.

[0594] Alternatively, the first color conversion member WCP1 may be a phosphor of a first color that converts the third color light emitted from the light emitting element LE into the first color light. For example, when the third color is blue and the first color is red, the phosphor of the first color may be (Sr, Ca)AlSiN 3 :Eu 2+ or K 2 (Si,Ge,Ti)F 6 :Mn 4+ .

[0595] In addition, the second color conversion member WCP2 may be a second color phosphor that converts the third color light emitted from the light emitting element LE into the second color light. For example, when the third color is blue and the second color is green, the second color phosphor may be selected from β-SiAlON:Eu 2+ , SrGa 2 S 4 :Eu 2+ 、BaAlMg 10 O 17 :Eu 2+ , Mn 2+ 、(Sr,Ba,Mg) 2 SiO 4 :Eu 2+ and (Lu,Y) 3 (Al,Ga) 5 O 12 :Ce 3+ At least one of the following.

[0596] The transmissive pattern TRP may include a base resin BRS (eg, a predetermined base resin BRS) having a light-transmitting property. Alternatively, the transmissive pattern TRP may further include scattering particles.

[0597] For example, the scattering particles may have a size of 10 nm to 500 nm. The scattering particles may be selected from titanium oxide (TiO 2 ), silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ) and zirconium oxide (ZrO 2 ) is made of at least one metal oxide.

[0598] In addition, each of the first color conversion pattern CCP1 and the second color conversion pattern CCP2 may further include scattering particles dispersed in the base resin BRS.

[0599] The partition wall pattern WLP is designed to separate spaces for arranging the first color conversion pattern CCP1, the second color conversion pattern CCP2, and the transmissive pattern TRP. The partition wall pattern WLP may be made of an organic insulating material selected from epoxy resin, acrylic resin, cardo resin, and imide resin.

[0600] The partition wall pattern WLP may have a width in the first direction DR1 or the second direction DR2 in the range of 1 μm to 10 μm.

[0601] The color filter layer CFL may include a first color filter CF1 corresponding to the first emission area LEA1 and transmitting light of a first color, a second color filter CF2 corresponding to the second emission area LEA2 and transmitting light of a second color, a third color filter CF3 corresponding to the third emission area LEA3 and transmitting light of a third color, and a light blocking pattern LBP corresponding to the non-emission area NEA.

[0602] The color filter layer CFL may improve the color purity of light emitted from each of the emission areas LEA.

[0603] In addition, the light blocking pattern LBP may prevent reflection of external light in the non-emission area NEA and prevent color mixing between adjacent emission areas LEA, thereby improving a color gamut.

[0604] In addition, the display device 100 according to the described embodiment may further include a protection layer PTL covering the color filter layer CFL.

[0605] The protective layer PTL may be made of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ) and aluminum nitride (AlN).

[0606] The protection layer PTL may have a thickness of 0.01 μm to 1 μm. However, this is merely an example.

[0607] Fig.49 An example of a case where the plurality of light emitting elements LE emit light of a third color corresponding to the third emission area LEA3 is shown.

[0608] Alternatively, the light emitting element LE may emit light in a wavelength band lower than that of the third color, that is, light in an ultraviolet wavelength band. In this case, the color conversion array layer CCAL may include a third color conversion pattern CCP3 (see Fig.52 ) instead of the transmission pattern TRP.

[0609] Fig.52 It is along Fig.48 A cross-sectional view taken along line CC'.

[0610] In addition, the plurality of light emitting elements LE′ emit light in a wavelength band lower than the wavelength band of the third color, and the color conversion array layer CCAL does not include the transmissive pattern TRP (see Fig.49 ), but includes the third color conversion pattern CCP3 corresponding to the third emission area LEA3, Fig.52 The example shown in Figures 49 to 51 Therefore, any redundant description will be omitted.

[0611] The third color conversion pattern CCP3 may include a base resin BRS (eg, a predetermined base resin BRS) and a third color conversion member WCP3 dispersed in the base resin BRS and converting light from the light emitting element LE′ into light of a third color.

[0612] The third color conversion member WCP3 may be a quantum dot, a quantum rod, a fluorescent material, or a phosphorescent material.

[0613] For example, the third color conversion member WCP3 may be made of BaAlMg 10 O 17 :Eu 2+ Made of fluorescent material.

[0614] As described above, the light emitting elements LE' are not arranged individually one by one but are arranged all at once.

[0615] Therefore, there may be some errors in the alignment between the light emitting elements LE' and the plurality of pixel electrodes PE. That is, due to the alignment errors, not all of the light emitting elements LE' are disposed on the pixel electrode PE, but some of the light emitting elements LE' are partially disposed in the non-emission area NEA.

[0616] Fig.53 and Fig.54 It is shown Fig.48 0 is a plan view of an example of an alignment error of a light emitting element LE shown in FIG.

[0617] Reference Fig.53 , the light emitting element LE may move from the position normally aligned with the pixel electrode PE to one side in the first direction DR1 ( Fig.53 The first alignment error AE1 offset from the right side of the image.

[0618] When the width of the first alignment error AE1 is greater than the second distance G2 between the pixel electrode PE and the dummy pattern DMP, some of the two or more light emitting elements LE arranged on each pixel electrode PE that are partially arranged in the non-emission area NEA due to the first alignment error AE1 may be supported by the dummy pattern DMP adjacent to one side of each pixel electrode PE in the first direction DR1.

[0619] Optionally, refer to Fig.54 , the light emitting element LE may move from the position normally aligned with the pixel electrode PE to the other side in the first direction DR1 ( Fig.54 The second alignment error AE2 (offset to the left side) is present.

[0620] When the width of the second alignment error AE2 is greater than the second distance G2 between the pixel electrode PE and the dummy pattern DMP, some of the two or more light emitting elements LE arranged on each pixel electrode PE that are partially arranged in the non-emission area NEA due to the second alignment error AE2 may be supported by the dummy pattern DMP adjacent to the other side of each pixel electrode PE in the first direction DR1.

[0621] Fig.55 It is along Fig.53 A cross-sectional view taken along line D-D'. Fig.56 yes Fig.55 A cross-sectional view of a comparative example REF.

[0622] First, refer to Fig.56 In the case of the comparative example REF not including the plurality of dummy patterns DMP, some light emitting elements E_LE' abnormally protruding to the non-emission area NEA due to the first alignment error AE1 or the second alignment error AE2 are disposed on the edge of the pixel electrode PE and are tilted due to the step of the pixel electrode PE.

[0623] The inclined light emitting element E_LE' cannot be positioned at the same height as the normally disposed light emitting element N_LE, which may be a factor causing the common electrode CE disposed on the light emitting elements N_LE and E_LE' to be damaged.

[0624] That is, because the common electrode CE is disposed on the inclined surface corresponding to the inclined light emitting element E_LE', it is difficult for the common electrode CE to have a constant thickness on each of the light emitting elements LE. Therefore, the sheet resistance of the common electrode CE varies locally. Therefore, this gradually destroys the uniformity of the brightness characteristics of the light emitting element LE, thereby deteriorating the display quality of the display device 100.

[0625] On the other hand, referring to Fig.55, when a first alignment error AE1 or a second alignment error AE2 corresponding to the first direction DR1 occurs, the two or more light emitting elements LE corresponding to each pixel electrode PE may include a light emitting element N_LE normally disposed on each pixel electrode PE and a light emitting element E_LE abnormally protruding to a non-emission area NEA adjacent to each pixel electrode PE in the first direction DR1.

[0626] Here, according to the described embodiment, a plurality of dummy patterns DMP are disposed at the same layer as the pixel electrode PE and are alternately disposed with the pixel electrode PE in the first direction DR1. Therefore, the light emitting element E_LE abnormally protruding to the non-emission area NEA can be supported by the dummy pattern DMP. Therefore, this can prevent the light emitting element E_LE abnormally protruding to the non-emission area NEA from being tilted due to the step of the pixel electrode PE.

[0627] Therefore, since the common electrode CE can be provided on each of the light emitting elements LE with a uniform thickness, it is possible to prevent a decrease in uniformity of luminance characteristics of the light emitting elements LE and prevent degradation of display quality.

[0628] Next, other examples of the dummy pattern according to the described embodiment will be described.

[0629] Figures 57 to 63 is shown with Fig.47 Part B corresponds to a plan view of another example of the pixel electrode PE and the dummy pattern DMP.

[0630] Reference Fig.57 , except that the second distance G22 between each pixel electrode PE and the dummy pattern DMP is in the same range as half of the first width W1 of the light emitting element LE as a threshold value of the tilt defect, the second example B2 is the same as Figures 48 to 55 The first example B1 is substantially the same as that of FIG. 1 . Therefore, any redundant description will be omitted.

[0631] According to the second example B2, the second width W22 of each dummy pattern DMP may correspond to a value obtained by subtracting a second distance G22 between the dummy pattern DMP and two pixel electrodes PE disposed on both sides of the dummy pattern DMP in the first direction DR1 from the first distance G1 between the pixel electrodes PE (ie, W22=G1-(G22×2)).

[0632] According to the second example B2, since the second distance G22 between each pixel electrode PE and the dummy pattern DMP corresponds to the threshold value of the tilt defect, it is possible to prevent the tilt defect and reduce the ratio of the dummy pattern DMP in the display area DPA.

[0633] Reference Fig.58, except that a dummy pattern DMP disposed between two adjacent pixel electrodes PE is closer to either of the two pixel electrodes PE, the third example B3 is similar to Figures 48 to 55 The first example B1 is substantially the same as that of FIG. 1 . Therefore, any redundant description will be omitted.

[0634] Fig.59 The third example B3 shown in FIG. 1 may be configured such that a plurality of light emitting elements LE are aligned with a plurality of pixel electrodes PE from a position normally aligned with the plurality of pixel electrodes PE to one side in the first direction DR1 ( Fig.59 The first alignment error AE1 corresponds to the offset on the right side of the image.

[0635] That is to say, Fig.59 As shown in FIG. 1 , according to the third example B3 corresponding to the first alignment error AE1, a dummy pattern DMP disposed between two adjacent pixel electrodes PE may be closer to the pixel electrode PE adjacent to the other side in the first direction DR1 among the two pixel electrodes PE. Therefore, the dummy pattern DMP may support the pixel electrode PE disposed between the two adjacent pixel electrodes PE to one side in the first direction DR1 ( Fig.59 The light emitting element LE is offset by a first alignment error AE1 ).

[0636] According to the third example B3, a dummy pattern DMP disposed between two pixel electrodes PE may be spaced apart from the pixel electrode PE adjacent to the other side in the first direction DR1 among the two pixel electrodes PE by a 231st distance G231, and may be spaced apart from the pixel electrode PE adjacent to one side in the first direction DR1 by a 232nd distance G232.

[0637] Here, when the dummy pattern DMP corresponds to the first alignment error AE1, the 231st distance G231 is smaller than the 232nd distance G232 (ie, G231 <G232)。

[0638] A sum of the 231st distance G231 and the second width W23 of each dummy pattern DMP may be equal to or greater than half of the first width W1 of each light emitting element LE (ie, (G231+W23)≥(W1) / 2).

[0639] In this case, it is possible to prevent a tilt defect due to the first alignment error AE1 and further reduce the ratio of the dummy pattern DMP in the display area DPA.

[0640] Fig.58 and Fig.59 A third example B3 corresponding to the first alignment error AE1 is shown. When the third example B3 is aligned with the other side ( Fig.54When corresponding to the second alignment error AE2 shifted by (i.e., to the left side of the pixel electrodes PE), one dummy pattern DMP disposed between two adjacent pixel electrodes PE may be closer to the pixel electrode PE adjacent to one side in the first direction DR1 among the two pixel electrodes PE.

[0641] Reference Fig.60 , except that it also includes auxiliary dummy patterns DMP′ arranged alternately with the plurality of pixel electrodes PE along the second direction DR2, the fourth example B4 is the same as Figures 48 to 55 The first example B1 is substantially the same as that of FIG. 1 . Therefore, any redundant description will be omitted.

[0642] Each of the plurality of light emitting elements LE may have a width W4 (eg, a predetermined width W4, hereinafter referred to as a "fourth width") in the second direction DR2. The light emitting elements LE may be spaced apart from each other by a distance G6 (eg, a predetermined distance G6, hereinafter referred to as a "sixth distance") in the second direction DR2.

[0643] Each of the pixel electrodes PE may have a width W6 (eg, a predetermined width W6, hereinafter referred to as a "sixth width") in the second direction DR2. The pixel electrodes PE may be spaced apart from each other by a distance G4 (eg, a predetermined distance G4, hereinafter referred to as a "fourth distance") in the second direction DR2.

[0644] The auxiliary dummy pattern DMP' may have a width W5 (e.g., a predetermined width W5, hereinafter referred to as a "fifth width") in the second direction DR2. The pixel electrode PE of the emission area LEA and the auxiliary dummy pattern DMP' adjacent to the emission area LEA in the second direction DR2 may be spaced apart from each other by a distance G5 (e.g., a predetermined distance G5, hereinafter referred to as a "fifth distance") in the second direction DR2.

[0645] A fourth distance G4 between the pixel electrodes PE adjacent to each other in the second direction DR2 may be greater than a fourth width W4 of each light emitting element LE in the second direction DR2 (ie, G4>W4).

[0646] In this case, it is possible to prevent a defect in which the light emitting element LE partially disposed in the non-emission area NEA is connected to both of two pixel electrodes PE adjacent to each other in the second direction DR2 due to an alignment error.

[0647] The fifth distance G5 between the pixel electrode PE and the auxiliary dummy pattern DMP′ adjacent to each other in the second direction DR2 may be selected within a range greater than 0 and less than or equal to half of the fourth width W4 of each light emitting element LE (ie, 0 <G5≤(W4) / 2)。

[0648] In this case, a tilt defect of the light emitting element LE partially disposed in the non-emission area NEA between the pixel electrodes PE adjacent to each other in the second direction DR2 may be prevented by the auxiliary dummy pattern DMP′.

[0649] When the auxiliary dummy pattern DMP' is spaced apart from two adjacent pixel electrodes PE on both sides in the second direction DR2 by the same fifth distance G5, the sum (W5+2×G5) of the fifth width W5 of the auxiliary dummy pattern DMP' and twice the fifth distance G5 (2×G5) is equal to the fourth distance G4 between the two pixel electrodes PE adjacent to each other in the second direction DR2. However, in some embodiments, when the auxiliary dummy pattern DMP' is spaced apart from two adjacent pixel electrodes PE on both sides in the second direction DR2 by the same fifth distance G5, the sum (W5+2×G5) of the fifth width W5 of the auxiliary dummy pattern DMP' and twice the fifth distance G5 (2×G5) is less than the fourth distance G4 between the two pixel electrodes PE adjacent to each other in the second direction DR2.

[0650] In addition, the sum of the fifth width W5 and the fifth distance G5 may be selected within a range greater than half of the fourth width W4 (W5+G5>(W4) / 2, W5>(W4) / 2-G5).

[0651] In this case, a portion of the light emitting element LE in the non-emission area NEA protruding between the pixel electrodes PE adjacent to each other in the second direction DR2, which protrudes farthest from the edge of the pixel electrode PE, may be supported by the auxiliary dummy pattern DMP'. That is, one side of the light emitting element LE protruding into the non-emission area NEA in the second direction DR2 may be supported by the pixel electrode PE, and the other side in the second direction DR2 may be supported by the auxiliary dummy pattern DMP'. Therefore, the reliability of the auxiliary dummy pattern DMP' for preventing the tilt defect of the light emitting element LE may be improved.

[0652] That is to say, Fig.61 As shown in FIG. 1 , when a plurality of light emitting elements LE move from positions normally aligned with a plurality of pixel electrodes PE to one side in the second direction DR2 ( Fig.61 When a third alignment error AE3 (on the upper side) is offset, some light emitting elements LE among two or more light emitting elements LE arranged on each pixel electrode PE that are partially arranged in the non-emission area NEA due to the third alignment error AE3 may be supported by the auxiliary dummy pattern DMP' adjacent to one side of each pixel electrode PE in the second direction DR2.

[0653] Reference Fig.62, except that two dummy patterns DMP spaced apart from each other are disposed between two pixel electrodes PE adjacent to each other along the first direction DR1, the fifth example B5 is similar to Figures 48 to 55 Therefore, any redundant description will be omitted.

[0654] For example, among the two dummy patterns DMP disposed between the two pixel electrodes PE_LEA1 and PE_LEA2 adjacent to each other along the first direction DR1, the other side (eg, Fig.62 The dummy pattern DMP on the left side of the first direction DR1 may be spaced apart from the adjacent pixel electrode PE_LEA1 on the other side in the first direction DR1 by a 251th distance G251.

[0655] In addition, among the two dummy patterns DMP disposed between the two pixel electrodes PE_LEA1 and PE_LEA2 adjacent to each other along the first direction DR1, one side (eg, Fig.62 Another dummy pattern DMP (on the right side) may be spaced apart from the adjacent pixel electrode PE_LEA2 on one side in the first direction DR1 by a 252nd distance G252. Here, the 251st distance G251 and the 252nd distance G252 may be within the same range, but embodiments of the present disclosure are not limited thereto.

[0656] Each of the 251st distance G251 and the 252nd distance G252 may be less than or equal to half of the first width W1 of the light emitting element LE (ie, G251, G252≤(W1) / 2).

[0657] Each of the two dummy patterns DMP disposed between the two pixel electrodes PE_LEA1 and PE_LEA2 adjacent to each other in the first direction DR1 may have a 25th width W25 (eg, a predetermined 25th width W25) in the first direction DR1.

[0658] For example, the sum of the 251st distance G251 and the 25th width W25 may be less than or equal to half of the first width W1 of each light emitting element LE (ie, (G251+W25)≤(W1) / 2). In this case, when the light emitting element LE moves toward one side in the first direction DR1 ( Fig.53 When the first alignment error AE1 is offset to the right of the light emitting area NEA, even if the light emitting element LE protrudes into the non-emission area NEA by more than half of the first width W1, at least a portion of the light emitting element LE may be supported by the dummy pattern DMP. Therefore, a tilt defect may be prevented.

[0659] Similarly, the sum of the 252nd distance G252 and the 25th width W25 may be less than or equal to half of the first width W1 of each light emitting element LE ((G252+W25)≤(W1) / 2). In this case, when the light emitting element LE moves to the other side in the first direction DR1 ( Fig.54 When the second alignment error AE2 is offset to the left of the light emitting area NEA, even if the light emitting element LE protrudes into the non-emission area NEA by more than half of the first width W1, at least a portion of the light emitting element LE can be supported by the dummy pattern DMP. Therefore, the tilt defect can be prevented.

[0660] Two dummy patterns DMP disposed between two pixel electrodes PE_LEA1 and PE_LEA2 adjacent to each other in the first direction DR1 may be spaced apart from each other by a 253rd distance G253. The 253rd distance G253 may correspond to a patterning margin of the dummy pattern DMP.

[0661] According to the fifth example B5, when the first alignment error AE1 or the second alignment error AE2 corresponding to the first direction DR1 occurs, the light emitting element LE protruding into the non-emission area NEA may be partially disposed on the pixel electrode PE and one dummy pattern DMP, or may be disposed on two adjacent dummy patterns DMP. Therefore, the inclination defect and the defect that the light emitting element LE in the non-emission area NEA is connected to the two pixel electrodes PE can be prevented.

[0662] Reference Fig.63 The sixth example B6 is similar to the example B7 except that the dummy pattern DMP disposed between the two pixel electrodes PE includes a main portion DMPM protruding toward the two pixel electrodes PE and a line portion DMPL connecting the main portion DMPM. Figures 48 to 55 The first example B1 is substantially the same as that of FIG. 1 . Therefore, any redundant description will be omitted.

[0663] The main portion DMPM of each dummy pattern DMP may face the light emitting element LE at both sides in the first direction DR1.

[0664] The seventh width W7 of each main portion DMPM in the second direction DR2 may be equal to or greater than the fourth width W4 of each light emitting element LE in the second direction DR2. In this case, the light emitting element LE protruding into the non-emission area NEA may be easily supported by the main portion DMPM.

[0665] Each main portion DMPM may be spaced apart from an adjacent pixel electrode PE by a 261st distance G261 in the first direction DR1.

[0666] The 261st distance G261 of each main portion DMPM may be selected within a range exceeding 0 and less than or equal to half of the first width W1 of each light emitting element LE (ie, 0 <G261≤(W1) / 2)。

[0667] The main portion DMPM may have a predetermined 261st width W261 in the first direction DR1.

[0668] A sum (W261+2×G261) of the 261st width W261 of each main portion DMPM and two times (2×G261) of the 261st distance G261 may correspond to the first distance G1 between two pixel electrodes PE adjacent to each other in the first direction DR1.

[0669] In addition, the sum of the 261st width W261 and the 261st distance G261 of each main portion DMPM may be selected within a range greater than half of the first width W1 (ie, (W261+G261)>(W1) / 2).

[0670] In this case, one side of the light emitting element LE protruding into the non-emission area NEA in the first direction DR1 may be supported by the pixel electrode PE, and the other side in the first direction DR1 may be supported by the main portion DMPM of the dummy pattern DMP.

[0671] The line portion DMPL of each dummy pattern DMP may have a predetermined second width W262 in the first direction DR1. Here, the 262nd width W262 of the line portion DMPL is smaller than the 261st width W261 of the main portion DMPM. Therefore, the proportion of the dummy pattern DMP in the display area DPA can be reduced while preventing the tilt defect by the dummy pattern DMP.

[0672] Fig.64 is shown with Fig.42 FIG. 1 is a plan view of another example of a plurality of emission areas LEA corresponding to portion A. FIG. Fig.65 and Fig.66 is shown with Fig.64 A portion F corresponds to a plan view of an example of a pixel electrode PE and a dummy pattern DMP.

[0673] like Fig.64As shown in , the arrangement form of the emission areas LEA according to the example may include a first row in which the first emission areas LEA1 and the third emission areas LEA3 are alternately arranged along the first direction DR1 and a second row in which the second emission areas LEA2 are arranged side by side in the first direction DR1. The first row and the second row may be alternately arranged along the second direction DR2. In addition, the first emission areas LEA1 and the third emission areas LEA3 of the first row may not be side by side with the second emission areas LEA2 of the second row in the second direction DR2, but may be adjacent to the second emission areas LEA2 of the second row in an oblique direction intersecting the first direction DR1 and the second direction DR2.

[0674] In this case, each of the plurality of pixels PX may be composed of one first emission area LEA1 and one third emission area LEA3 adjacent to each other in the first direction DR1 and two second emission areas LEA2 adjacent to them in an oblique direction. However, this is merely an example, and the configuration of each pixel PX according to one or more embodiments is not limited to Fig.64 The construction shown in , and can be changed as needed.

[0675] Reference Fig.65 ,include Fig.64 The display device 100 of the emission area LEA shown in FIG. 1 may include a plurality of pixel electrodes PE_LEA1 , PE_LEA2 , and PE_LEA3 respectively corresponding to the emission areas LEA, a plurality of dummy patterns DMP each disposed in the non-emission area NEA between the pixel electrodes PE adjacent to each other in the first direction DR1 , and a plurality of light emitting elements LE.

[0676] Optionally, refer to Fig.66 ,include Fig.64 The display device 100 of the emission area LEA shown in FIG. 1 may further include auxiliary dummy patterns DMP′ disposed at both sides of each of the pixel electrodes PE_LEA1 and PE_LEA3 in the first emission area LEA1 and the third emission area LEA3 in the second direction DR2 .

[0677] Optionally, with Fig.66 Different from the illustration shown in FIG. 1 , the auxiliary dummy patterns DMP′ may also be disposed on both sides of the pixel electrode PE_LEA2 in each second emission area LEA2 in the second direction DR2 .

[0678] Next, a method of manufacturing a display device according to one or more embodiments will be described.

[0679] Fig.67 is a flowchart illustrating a method of manufacturing the display device 100 according to another embodiment. Fig.68 It is shown that the preparation Fig.49Flowchart of the operation of the light emitting element array layer EML in FIG. Figure 69 to Figure 84 It is shown Fig.67 and Fig.68 A process diagram for each operation.

[0680] Reference Fig.67 The method of manufacturing the display device 100 according to the described embodiment includes: preparing a substrate SUB including a display area DPA in which a plurality of emission areas LEA are arranged, and arranging a transistor array layer TFTL including a plurality of thin film transistors DTR and STR1 corresponding to the emission areas LEA and a via layer VIA covering the thin film transistors DTR and STR1 on the substrate SUB (operation S10); arranging a plurality of pixel electrodes PE corresponding to the emission areas LEA and a plurality of dummy patterns DMP corresponding to non-emission areas NEA between the emission areas LEA on the via layer VIA (operation S20); preparing a display area DPA disposed on an auxiliary substrate and including a plurality of thin film transistors DTR and STR1 corresponding to the emission areas LEA; and a light emitting element array layer EML of a plurality of light emitting elements LE corresponding to the emission area LEA is disposed (operation S30); a light emitting element array layer EML is disposed on the pixel electrode PE and the auxiliary substrate is removed (operation S40); a planarization layer PLL is disposed to fill the space between the light emitting elements LE and cover the pixel electrode PE and the dummy pattern DMP (operation S50); a common electrode CE corresponding to the emission area LEA is disposed on the light emitting elements LE and the planarization layer PLL (operation S60); a color conversion array layer CCAL is disposed on the common electrode CE (operation S70); and a color filter layer CFL is disposed on the color conversion array layer CCAL (operation S80).

[0681] In the step of arranging the pixel electrodes PE and the dummy patterns DMP (operation S20 ), the pixel electrodes PE may be spaced apart from each other by a first distance G1 (eg, a predetermined first distance G1 ) in one direction.

[0682] In addition, in the step of arranging the pixel electrode PE and the dummy pattern DMP (operation S20 ), the pixel electrode PE and the dummy pattern DMP adjacent to each other in one direction may be spaced apart from each other by a second distance G2 (eg, a predetermined second distance G2 ).

[0683] Reference Fig.68, the step of preparing a light emitting element array layer EML (operation S30) may include: arranging a semiconductor epitaxial layer on a growth substrate (operation S31); preparing a plurality of semiconductor structures each having a first width W1 in one direction by patterning the semiconductor epitaxial layer (operation S32); attaching an auxiliary substrate to the semiconductor structure (operation S33); removing the growth substrate from the semiconductor structure (operation S34); preparing a plurality of light emitting elements LE by arranging a connection electrode CNE on each of the semiconductor structures (operation S35); increasing the distance between the light emitting elements LE by stretching the auxiliary substrate (operation S36); and preparing the light emitting element array layer EML (operation S38) when the light emitting elements LE are spaced apart from each other by a third distance G3 (e.g., a predetermined third distance G3) in one direction (operation S37).

[0684] In the step of arranging the semiconductor epitaxial layer (operation S31), the semiconductor epitaxial layer may include a first semiconductor layer of a first conductivity type, an active layer of a quantum well structure, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of an undoped semiconductor sequentially stacked on a growth substrate.

[0685] Reference Fig.69 and Fig.70 , a substrate SUB including the display area DPA is prepared, and a transistor array layer TFTL including a plurality of thin film transistors DTR and STR1 and a via layer VIA covering the thin film transistors DTR and STR1 is disposed on the substrate SUB (operation S10 ).

[0686] like Fig.69 As shown in the figure, the transistor array layer TFTL may include a buffer layer BFL disposed on a substrate SUB, a first gate insulating layer GI1 covering an active layer ACT on the buffer layer BFL, a second gate insulating layer GI2 covering a gate electrode G on the first gate insulating layer GI1, an interlayer insulating layer ILI covering a capacitor electrode CAE on the second gate insulating layer GI2, and a first via layer VIA1 covering a source electrode S and a drain electrode D on the interlayer insulating layer ILI.

[0687] The driving transistor DTR among the thin film transistors included in the transistor array layer TFTL may include an active layer ACT disposed on the buffer layer BFL and including a channel region CHA and first and second conductive regions COA1 and COA2 connected to both sides of the channel region CHA, a gate electrode G disposed on the first gate insulating layer GI1 and overlapping the channel region CHA of the active layer ACT in the third direction DR3, and a drain electrode D and a source electrode S disposed on the interlayer insulating layer ILI.

[0688] The drain electrode D may be connected to the first conductive area COA1 of the active layer ACT through a hole penetrating the interlayer insulating layer ILI, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0689] The source electrode S may be connected to the second conductive area COA2 of the active layer ACT through a hole penetrating the interlayer insulating layer ILI, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0690] The capacitor electrode CAE on the second gate insulating layer GI2 may overlap at least a portion of the gate electrode G of the driving transistor DTR in the third direction DR3 and may be connected to the source electrode S of the driving transistor DTR through a hole penetrating the interlayer insulating layer ILI.

[0691] like Fig.70 As shown in , the transistor array layer TFTL may further include an anode connection electrode ANDE disposed on the first via layer VIA1 and a second via layer VIA2 covering the anode connection electrode ANDE.

[0692] Each of the anode connection electrodes ANDE may be connected to the source electrode S of the driving transistor DTR through a first contact hole CTH1 penetrating the first via layer VIA1 .

[0693] A data line DTL may be further disposed on the first via layer VIA1 .

[0694] Next, a plurality of pixel electrodes PE and a plurality of dummy patterns DMP are disposed on the second via layer VIA2 of the transistor array layer TFTL (operation S20 ).

[0695] The pixel electrodes PE may correspond to the plurality of emission areas LEA1 to LEA3 , respectively, and may be connected to the anode connection electrodes ANDE of the emission areas LEA1 to LEA3 , respectively, through second contact holes CTH2 penetrating the second via layer VIA2 .

[0696] The pixel electrodes PE may be spaced apart from each other by a first distance G1 (eg, a predetermined first distance G1, see Fig.76 ).

[0697] Each of the pixel electrodes PE may have a third width W3 (eg, a predetermined third width W3, see FIG. 5 ) in the first direction DR1. Fig.76 ).

[0698] Each of the dummy patterns DMP may be disposed in the non-emission area NEA and may have a second width W2 (eg, a predetermined second width W2, see FIG. 5 ) in the first direction DR1. Fig.76 ).

[0699] The dummy patterns DMP may be formed at the same layer as the pixel electrode PE, and may have a thickness in the same range as that of the pixel electrode PE in the third direction DR3 such that they are disposed parallel to the pixel electrode PE.

[0700] The pixel electrode PE and the dummy pattern DMP adjacent to each other in the first direction DR1 may be spaced apart from each other by a second distance G2 (eg, a predetermined second distance G2, see Fig.76 ).

[0701] If one dummy pattern DMP is disposed between two pixel electrodes PE adjacent to each other in the first direction DR1 , a sum of the second width W2 and twice the second distance G2 may correspond to the first distance G1 .

[0702] Reference Fig.71 In order to prepare the light emitting element array layer EML, a semiconductor epitaxial layer EPTL is disposed on the growth substrate G_SUB (operation S31 ).

[0703] The semiconductor epitaxial layer EPTL may include a first conductive type first semiconductor layer SEM1 , an active layer MQW of a quantum well structure, a second conductive type second semiconductor layer SEM2 , and a third semiconductor layer SEM3 of an undoped semiconductor sequentially stacked in the third direction DR3 .

[0704] The semiconductor epitaxial layer EPTL may further include an electron blocking layer EBL disposed between the first semiconductor layer SEM1 and the active layer MQW, and a superlattice layer SLT disposed between the active layer MQW and the second semiconductor layer SEM2 .

[0705] The first conductivity type may be a p-type, and the second conductivity type may be an n-type.

[0706] Reference Fig.72 , can be achieved by EPTL (see Fig.71 ) are patterned to prepare each having a first width W1 (for example, a predetermined first width W1, see Fig.76 ) of multiple semiconductor structures SEMS (operation S32).

[0707] The semiconductor structures SEMS may be spaced apart from each other by an initial distance IG in at least one direction (eg, a first direction DR1 ).

[0708] Reference Fig.73 , the auxiliary substrate S_SUB may be attached to the third semiconductor layer SEM3 of the semiconductor structure SEMS (operation S33 ).

[0709] The subsidiary substrate S_SUB may be made of a material that may be stretched in first and second directions DR1 and DR2 corresponding to the arrangement of the semiconductor structure SEMS.

[0710] Reference Fig.74 , the growth substrate G_SUB is removed from the semiconductor structure SEMS (operation S34). Then, a plurality of light emitting elements LE may be prepared by arranging a connection electrode CNE on each of the semiconductor structures SEMS (operation S35).

[0711] A connection electrode CNE may be disposed on the first semiconductor layer SEM1 of each of the semiconductor structures SEMS.

[0712] In addition, each of the light emitting elements LE may further include a contact electrode CTE disposed on the connection electrode CNE.

[0713] That is, each of the light emitting elements LE may include a semiconductor structure SEMS, a connection electrode CNE on the first semiconductor layer SEM1 of the semiconductor structure SEMS, and a contact electrode CTE on the connection electrode CNE.

[0714] Reference Fig.75 , the distance between the light emitting elements LE can be increased by stretching the auxiliary substrate S_SUB (operation S36). Here, the auxiliary substrate S_SUB can be stretched in at least one of the first direction DR1 and the second direction DR2 until the distance between the light emitting elements LE reaches a third distance G3 (e.g., a predetermined third distance G3) (operation S37).

[0715] Therefore, it is possible to prepare a system including a plurality of cells spaced apart from each other in one direction by a distance greater than the initial distance IG (see Fig.74 ) of the light emitting element array layer EML of the light emitting element LE at a third distance G3 (operation S38).

[0716] Next, the light emitting element array layer EML is disposed on the pixel electrode PE, and the auxiliary substrate S_SUB is removed from the light emitting element array layer EML (operation S40 ).

[0717] Reference Fig.76 , the light emitting elements LE on the auxiliary substrate S_SUB may be aligned with the pixel electrode PE. Here, the light emitting elements LE may be aligned between the auxiliary substrate S_SUB and the pixel electrode PE in the third direction DR3. In addition, at least one of the light emitting elements LE may face each pixel electrode PE thereunder.

[0718] Reference Fig.77 , the light emitting element LE can be fixed to the pixel electrode PE. Here, the contact electrode CTE (see Fig.75) can contact the pixel electrode PE.

[0719] Reference Fig.78 , the auxiliary substrate S_SUB may be removed from the third semiconductor layer SEM3 of the light emitting element LE fixed on the pixel electrode PE.

[0720] like Fig.79 As shown in FIG. 1 , in the process of aligning the light emitting element LE on the auxiliary substrate S_SUB with the pixel electrode PE, the light emitting element LE may move from a normal position to one side in the first direction DR1 ( Fig.79 The first alignment error AE1 offset from the right side of the image.

[0721] like Fig.80 As shown in , when the light emitting elements LE are in contact with the pixel electrode PE in a state where the first alignment error AE1 is reflected, some of the light emitting elements LE may protrude into the non-emission area NEA due to the first alignment error AE1.

[0722] However, according to the described embodiment, since the dummy pattern DMP formed at the same layer as the pixel electrode PE and having a thickness within the same range as the thickness of the pixel electrode PE is provided, some of the light emitting elements LE protruding into the non-emission area NEA can be supported by the dummy pattern DMP. Therefore, the tilt defect of the light emitting element LE protruding into the non-emission area NEA due to the alignment error can be prevented.

[0723] Next, refer to Fig.81 , a planarization layer PLL may be disposed to fill the space between the light emitting elements LE and cover the pixel electrode PE and the dummy pattern DMP (operation S50 ).

[0724] Here, the light emitting elements LE may not be completely covered by the planarization layer PLL, and at least the third semiconductor layer SEM3 of each of the light emitting elements LE may be exposed outside the planarization layer PLL.

[0725] Reference Fig.82 , a common electrode CE may be disposed on the light emitting element LE and the planarization layer PLL (operation S60). The common electrode CE may be electrically connected to the exposed third semiconductor layer SEM3 of the light emitting element LE.

[0726] Reference Fig.83 , a color conversion array layer CCAL may be disposed on the common electrode CE (operation S70 ).

[0727] The color conversion array layer CCAL may include a first color conversion pattern CCP1 corresponding to the first emission area LEA1 , a second color conversion pattern CCP2 corresponding to the second emission area LEA2 , and a partition wall pattern WLP corresponding to the non-emission area NEA.

[0728] The first color conversion pattern CCP1 may include a first color conversion member WCP1 that converts at least a portion of light from the light emitting element LE into light of a first color.

[0729] The second color conversion pattern CCP2 may include a second color conversion member WCP2 that converts at least a portion of light from the light emitting element LE into light of a second color.

[0730] When the light emitting element LE emits light of a third color, the color conversion array layer CCAL may further include a transmissive pattern TRP corresponding to the third emission area LEA3 and transmitting the light of the light emitting element LE without changing the color.

[0731] Optionally, when the light emitting element LE emits light of a wavelength band lower than the wavelength band of the third color, the color conversion array layer CCAL may further include a third color conversion pattern CCP3 corresponding to the third emission area LEA3 (see Fig.52 and Fig.84 ). The third color conversion pattern CCP3 may include a third color conversion member WCP3 that converts at least a portion of light from the light emitting element LE into light of a third color.

[0732] Reference Fig.84 , a color filter layer CFL may be disposed on the color conversion array layer CCAL (operation S80 ).

[0733] The color filter layer CFL may include a first color filter CF1 corresponding to the first emission area LEA1 and transmitting light of a first color, a second color filter CF2 corresponding to the second emission area LEA2 and transmitting light of a second color, a third color filter CF3 corresponding to the third emission area LEA3 and transmitting light of a third color, and a light blocking pattern LBP corresponding to the non-emission area NEA.

[0734] In addition, the color filter layer CFL may be covered with a protection layer PTL (eg, a predetermined protection layer PTL).

[0735] As described above, the display device 100 according to the described embodiment includes a dummy pattern DMP disposed in the non-emission area NEA to be parallel to the pixel electrode PE. Therefore, even if some of the light emitting elements LE are disposed in the non-emission area NEA due to an alignment error occurring in a process of arranging the light emitting elements LE concurrently (e.g., simultaneously) on the pixel electrode PE, the tilt defect of these light emitting elements LE can be prevented by the dummy pattern DMP.

[0736] The display device according to one or more embodiments includes a plurality of light emitting units respectively corresponding to a plurality of emission areas and a partition wall portion corresponding to a non-emission area as a boundary between the emission areas and having a variable width in at least one direction.

[0737] Since the partition wall portion includes a portion having a relatively large width, it may not be easily deformed. Therefore, it is possible to prevent the display quality, lifespan, and yield of the display device from being reduced due to the deformation of the partition wall portion.

[0738] In addition, since the partition wall portion includes a portion having a relatively small width, a reduction in the width of the light emitting unit due to the partition wall portion can be reduced. Therefore, a reduction in the brightness of the display device due to the partition wall portion can be prevented.

[0739] The display device according to one or more embodiments includes a plurality of dummy patterns corresponding to non-emitting regions between the plurality of emission regions, formed on the same layer (or at the same layer) as the plurality of pixel electrodes, and arranged parallel to the pixel electrodes.

[0740] Therefore, even if some of the plurality of light-emitting elements protrude into the non-emission region due to alignment errors that occur in the process of arranging the light-emitting elements concurrently (e.g., simultaneously) on the pixel electrode, they can be supported by the dummy pattern in the non-emission region. Therefore, it is possible to prevent the light-emitting element partially disposed in the non-emission region from tilting due to the step of the pixel electrode. Therefore, this can prevent the local increase in the resistance of the common electrode, thereby preventing the degradation of the display quality.

[0741] However, the effects, aspects and features of the present disclosure are not limited to the effects, aspects and features set forth herein. The above and other effects, aspects and features of the present disclosure will become more apparent to those skilled in the art by referring to the claims, drawings and detailed description.

Claims

1. A display device, It is characterized in that The display device comprises: a substrate including a display area in which a plurality of emission areas configured to emit light for displaying an image are arranged; a plurality of light emitting units, positioned on the substrate and corresponding to the plurality of emission areas respectively; and a partition wall, on the substrate, corresponding to a non-emitting region as a boundary between the plurality of emitting regions and having a variable width in at least one direction, wherein the partition wall includes: a plate corresponding to the non-emitting area; and a column protruding from at least a portion of the plate to each of the plurality of emitting areas and having a width greater than a width of the plate, Each of the plurality of light-emitting units comprises: a light-emitting element, on the substrate, Wherein, a minimum distance between the columns corresponding to two sides of any one of the plurality of light-emitting units is greater than a width of the light-emitting element.

2. The display device according to claim 1, It is characterized in that Each of the plurality of light emitting units has a light emitting surface configured to emit light and a rear surface opposite to the light emitting surface, wherein the rear surface of each of the plurality of light emitting units has at least one corner or at least one side having a shape corresponding to a shape of the partition wall.

3. The display device according to claim 2, It is characterized in that In the thickness direction of the substrate, the height of each pillar is equal to the height of the plate, and the light emitting surface of each of the plurality of light emitting units has at least one corner or at least one side in a shape corresponding to that of the pillar.

4. The display device according to claim 3, It is characterized in that Each pillar corresponds to corners of four adjacent light emitting units, and the light emitting surface and the rear surface of each of the plurality of light emitting units have a quadrilateral shape having each corner formed by the pillar.

5. The display device according to claim 3, It is characterized in that Each column corresponds to a corner of two light emitting units adjacent to each other in one direction, and the light emitting surface and the rear surface of each of the plurality of light emitting units are formed into a quadrilateral shape in which corners corresponding to both ends of one side extending in the one direction are formed by the column.

6. The display device according to claim 3, It is characterized in that Each column corresponds to corners of two light emitting units adjacent to each other in one direction and a portion of one side of a light emitting unit adjacent to the two light emitting units in another direction, and the light emitting surface and the rear surface of each of the plurality of light emitting units have a quadrilateral shape in which corners corresponding to both ends of one side extending in the one direction and a portion of the other side extending in the one direction are formed by the column.

7. The display device according to claim 3, It is characterized in that Each pillar is between two adjacent light emitting units, and the light emitting surface and the rear surface of each of the plurality of light emitting units include a combination of curved sides convex toward a center of the light emitting unit.

8. The display device according to claim 3, It is characterized in that 2n columns are positioned side by side between two light emitting units adjacent in one direction, and include a first column having a cross-sectional shape convex toward one of the two adjacent light emitting units and a second column having a cross-sectional shape convex toward the other of the two adjacent light emitting units, wherein n is a natural number of 1 or greater, the first column and the second column are alternately arranged between the two adjacent light emitting units, and the first column and the second column adjacent to each other are point symmetrical to each other, wherein the plate corresponds to a space between two light emitting units adjacent in another direction and a space between the first column and the second column, and the light emitting surface and the rear surface of each of the plurality of light emitting units have a quadrilateral shape including one side formed by the first column and another side facing the one side and formed by the second column.

9. The display device according to claim 1, It is characterized in that Each of the plurality of light emitting units has a light emitting surface configured to emit light and a rear surface opposite to the light emitting surface, a height of each column is smaller than a height of the board, the rear surface of each of the plurality of light emitting units is surrounded by the columns, and the light emitting surface of each of the plurality of light emitting units is surrounded by the board and has a width greater than a width of the rear surface.

10. The display device according to claim 9, It is characterized in that The height of each pillar in a thickness direction of the substrate is smaller than a light emission height of the light emitting element, and the light emission height corresponds to an angle at which light is emitted from the light emitting element.

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