Optoelectronic device

Abstract

An optoelectronic device includes a first superabsorbent structure that penetrates into a semiconductor substrate. The optoelectronic device includes a second superabsorbent structure that penetrates into the semiconductor substrate and is adjacent to the first superabsorbent structure. The optoelectronic device includes a plateau region including a carbon layer, where the plateau region is directly and horizontally between the first and second superabsorbent structures.

Description

Technical Field

[0001] The present disclosure provides optoelectronic devices including an absorptive structure. Background Art

[0002] A digital camera may include an optoelectronic device, such as an image sensor. The image sensor converts an optical image into digital data that can be presented as a digital image. The image sensor includes an array of multiple pixel sensors and supporting logic. The multiple pixel sensors in the array are unit devices for measuring incident light, and the supporting logic facilitates reading the measurement results. The image sensor may include a high absorption region higher than the photodiode of the image sensor to improve the performance of the image sensor, wherein the high absorption region includes multiple structures that increase the amount of incident light absorbed by the photodiode. Utility Model Content

[0003] Current manufacturing techniques for optoelectronic devices including highly absorbing structures may include a series of multiple operations, including a patterning operation using a layer of positive photoresist material, followed by a dry stripping removal operation to remove the layer of positive photoresist material. After this current series of multiple operations, the quantum efficiency of the highly absorbing structure may not meet a threshold to support target performance of the optoelectronic device. As a result, the manufacturing yield of a volume of optoelectronic devices may be reduced.

[0004] Some embodiments described herein provide optoelectronic devices including highly absorbing structures and methods of formation that can reduce handling-induced damage to the device by reducing the number of operations. Additionally, the highly absorbing structures can include greater quantum efficiency.

[0005] Some embodiments of the present disclosure provide an optoelectronic device, comprising: a first high absorption structure, a second high absorption structure, and a platform region. The first high absorption structure penetrates into a semiconductor substrate. The second high absorption structure penetrates into the semiconductor substrate and is adjacent to the first high absorption structure. The platform region comprises a carbon layer. The platform region is directly and horizontally between the first high absorption structure and the second high absorption structure.

[0006] Other embodiments of the present disclosure provide an optoelectronic device, comprising: a first high absorption structure, a second high absorption structure, and a platform region. The first high absorption structure penetrates into a semiconductor substrate. The second high absorption structure penetrates into the semiconductor substrate and is adjacent to the first high absorption structure. The platform region comprises a carbon layer. The platform region is directly and horizontally between the first high absorption structure and the second high absorption structure. Each of the first high absorption structure and the second high absorption structure has a smooth surface inclined to the semiconductor substrate.

[0007] Still other embodiments of the present disclosure provide an optoelectronic device comprising: a first high absorption structure, a second high absorption structure, and a platform region. The first high absorption structure penetrates into a semiconductor substrate. The second high absorption structure penetrates into the semiconductor substrate and is adjacent to the first high absorption structure. The platform region comprises a carbon layer. The platform region is directly and horizontally between the first high absorption structure and the second high absorption structure. The first high absorption structure and the high absorption structure are symmetrical around a central axis of the platform region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure can be described in detail below and in conjunction with the accompanying Figure 1 Please read together for the best understanding. It is noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 is a schematic diagram of an example environment in which the systems and / or methods described herein are implemented;

[0010] Figure 2 is a schematic diagram of a pixel array of an embodiment described herein;

[0011] FIG. 3A to FIG. 3D is a schematic diagram of an embodiment image sensor, the embodiment image sensor including the highly absorbent structure described herein;

[0012] 4A to 4W is a schematic diagram of an embodiment manufacturing process for forming an image sensor including a highly absorbent structure as described herein;

[0013] Figure 5A and Figure 5B is a schematic diagram of an example embodiment of a cavity that may be used to form a highly absorbent structure as described herein;

[0014] Figure 6 is a schematic diagram of an implementation of an embodiment of a photomask pattern described herein;

[0015] Figure 7 yes Figure 1 schematic diagrams of components of multiple embodiments of one or more devices;

[0016] Figure 8 and Fig. 9 is a flow chart of an example process for forming an imaging sensor including the highly absorbent structures described herein.

[0017]

Explanation of symbols

[0018] 100: Environment

[0019] 102:Deposition tools (semiconductor process tools)

[0020] 104: Exposure tools (semiconductor process tools)

[0021] 106: Developer tool (semiconductor process tool)

[0022] 108: Etching tools (semiconductor process tools)

[0023] 110: Planarization tools (semiconductor process tools)

[0024] 112: Plating tools (semiconductor process tools)

[0025] 114: Ion implantation tool (semiconductor process tool)

[0026] 116: Wafer / die transfer tool

[0027] 200: Pixel array

[0028] 202: Pixel sensor

[0029] 202a: Pixel sensor

[0030] 202b: Pixel sensor

[0031] 300: Photoelectric device (image sensor)

[0032] 302: Metal shielding area

[0033] 304: Bonding pad area

[0034] 306: Line area

[0035] 308: Buffer layer

[0036] 310: Intermetallic dielectric layer

[0037] 312: Metallization layer

[0038] 312a: Metallization layer

[0039] 312b: Metallization layer

[0040] 312c: Metallization layer

[0041] 312d: Metallization layer

[0042] 314: Contact

[0043] 316: Undoped silicate glass layer

[0044] 318: Interlayer dielectric layer

[0045] 320: substrate layer

[0046] 322: Photodiode

[0047] 324: Deep Trench Isolation Structure

[0048] 326: High Absorption Area

[0049] 328: Highly absorbent structure

[0050] 328a: Highly absorbent structure

[0051] 328b: Highly absorbent structure

[0052] 328c: Highly absorbent structure

[0053] 330: Platform area

[0054] 332: Anti-reflective coating

[0055] 334: Oxide layer

[0056] 336:Metal shielding layer

[0057] 338: Back-illuminated oxide layer

[0058] 340: Buffer oxide layer

[0059] 342: Filter layer

[0060] 342a: Filter area

[0061] 342b: Filter area

[0062] 344: Microlens layer

[0063] 346: Shallow Trench Isolation Structure

[0064] 348: Bonding pad

[0065] 350: Highly absorbent structure

[0066] 350a: Highly absorbent structure

[0067] 350b: Highly absorbent structure

[0068] 350c: Highly absorbent structure

[0069] 350d: Highly absorbent structure

[0070] 350e: Highly absorbent structure

[0071] 350f: Highly absorbent structure

[0072] 352:Central axis

[0073] 354: Carbon layer

[0074] 400: Implementation Method

[0075] 402: Cavity

[0076] 402a: Cavity

[0077] 402b: Cavity

[0078] 404: Region

[0079] 406: layer of photoresist material

[0080] 408: Opening

[0081] 410: Opening

[0082] 412: Opening

[0083] 414: Opening

[0084] 416: Opening

[0085] 418: Opening

[0086] 420: Opening

[0087] 500: Implementation Method

[0088] 502: Smooth surface

[0089] 504: Cutting Edge

[0090] 506: Pitting

[0091] 600: Implementation method

[0092] 602: Mask pattern

[0093] 604: Mask pattern

[0094] 606: Opaque film characteristics

[0095] 608:Transparent substrate

[0096] 700: Device

[0097] 710: Bus

[0098] 720: Processor

[0099] 730: Memory

[0100] 740: Input component

[0101] 750: Output component

[0102] 760: Communication components

[0103] 800: Craftsmanship

[0104] 810: Block

[0105] 820: Block

[0106] 900: Craftsmanship

[0107] 910: Block

[0108] 920: Block

[0109] 930: Block

[0110] 940: Block

[0111] 950: Block

[0112] AA:Line

[0113] D1: Angle

[0114] D2: Width

[0115] D3: Thickness DETAILED DESCRIPTION

[0116] The disclosure that follows provides many different implementations or embodiments for implementing different features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify the disclosure. Of course, these are merely embodiments and are not restrictive. For example, in the subsequent description, a first feature is formed above or on a second feature, and an implementation in which the first feature and the second feature are formed in direct contact may be included, and an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for the purpose of simplification and clarity, and the repetition itself does not mean the relationship between the various embodiments and / or configurations discussed.

[0117] Additionally, to facilitate describing the relationship of one element or feature to another element or feature as depicted in the drawings, spatially relative terms may be used herein, such as "below," "below," "lower," "above," "upper," "above," "below," and the like. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted similarly accordingly.

[0118] In some cases, an optoelectronic device, such as a complementary metal-oxide image sensor (CIS) device, includes a high absorption (HA) structure that absorbs photons to generate an electric current. Semiconductor manufacturing techniques for fabricating the high absorption structure may include a series of multiple operations, including a patterning operation using a layer of positive photoresist material, followed by a dry stripping removal operation to remove the layer of positive photoresist material. The series of multiple operations may also include a deposition operation to deposit a layer of hard mask material, two or more wet etching operations to form the absorption structure, and a removal operation to remove the layer of hard mask material. After the series of multiple operations, the quantum efficiency of the high absorption structure (e.g., the efficiency with which the high absorption structure absorbs photons) may not meet a threshold to support target performance of the optoelectronic device. As a result, the manufacturing yield of a volume of optoelectronic devices may be reduced.

[0119] Some embodiments described herein provide optoelectronic devices and methods of forming the same. The optoelectronic device is fabricated using a series of multiple operations that include a patterning operation using a layer of a negative photoresist material, followed by a single dry etching operation, a single wet stripping operation, and a single wet etching operation. The series of multiple operations may include a reduced number of operations compared to another series of multiple operations that include a patterning operation using a layer of a positive photoresist material. By reducing the number of operations, damage to the device caused by processing may be reduced. In addition, the high absorption structure may include a greater quantum efficiency compared to another quantum efficiency of another high absorption structure formed by a series of multiple operations that include a patterning operation using a layer of a positive photoresist material.

[0120] In this manner, the manufacturing yield of an optoelectronic device (including such a highly absorbing structure that meets a quantum efficiency threshold) can be increased compared to another optoelectronic device that does not include such a highly absorbing structure. Additionally or alternatively, the amount of various resources used to manufacture a volume of optoelectronic devices (including highly absorbing structures) can be reduced (e.g., the amount of semiconductor manufacturing tools, raw materials, manpower, and / or computing resources, among other embodiments).

[0121] Figure 1 1 is a schematic diagram of an embodiment environment 100 in which the systems and / or methods described herein may be implemented. Figure 1As shown in , environment 100 may include multiple semiconductor process tools 102 to 114 and a wafer / die transfer tool 116. Multiple semiconductor process tools 102 to 114 may include a deposition tool 102, an exposure tool 104, a developer tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, an ion implantation tool 114, and / or another type of semiconductor process tool. The multiple tools included in the embodiment environment 100 may be included in a semiconductor clean room, a semiconductor manufacturing plant, a semiconductor process and / or manufacturing facility, or the like.

[0122] Deposition tool 102 is a semiconductor process tool that includes a semiconductor process chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coating tool that can deposit a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of chemical vapor deposition tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, embodiment environment 100 includes multiple types of deposition tools 102 .

[0123] The exposure tool 104 is a semiconductor process tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep ultraviolet light source, an extreme ultraviolet light (EUV) source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for etching various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0124] The developer tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developer tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by dissolving the exposed or unexposed portions of the photoresist layer using a chemical developer.

[0125] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may etch one or more portions of the substrate using plasma etching or plasma-assisted etching, which may involve using ionized gas to etch one or more portions isotropically or directionally.

[0126] The planarization tool 110 is a semiconductor process tool capable of grinding or flattening individual layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool, and / or another type of planarization tool that grinds or flattens a layer or surface of a deposited or plated material. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free grinding polishing) to grind or flatten the surface of a semiconductor device. The planarization tool 110 may utilize grinding and corrosive chemical slurries, in combination with a grinding pad and a fixed ring (e.g., typically having a larger diameter than the semiconductor device). The grinding pad and the semiconductor device may be pressed together via a dynamic grinding head and maintained in a fixed position via a fixed ring. The dynamic grinding head may be rotated with different rotation axes to remove material and flatten any irregular topography of the semiconductor device, so that the semiconductor device becomes flat or flat.

[0127] The plating tool 112 is a semiconductor process tool capable of plating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion of a substrate with one or more metals. For example, the plating tool 112 may include a copper plating device, an aluminum plating device, a nickel plating device, a tin plating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) plating device, and / or a plating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0128] The ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a source material (e.g., a gas or solid) in an arc chamber. The source material can be provided into the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma, which includes ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward the substrate to implant the ions below the surface of the substrate.

[0129] The wafer / die transport tool 116 includes a mobile robot, a robotic arm, a tram or rail car, and / or another type of device for transporting wafers and / or dies between semiconductor process tools 102-114 and / or to and from other locations such as wafer racks, storage rooms, and / or the like. In some embodiments, the wafer / die transport tool 116 may be a programmed device that is configured to follow a specific path and / or may be semi-automated or automated.

[0130] As combined FIG. 3A to FIG. 3D , FIG. 4E to FIG. 4I , Figure 8 , Fig. 9 , and as described in greater detail elsewhere herein, the semiconductor process tools 102-114 may perform a series of operations related to forming highly absorbing structures for optoelectronic devices. The series of operations includes, for example, patterning a field of multiple openings in a layer of negative photoresist material on a semiconductor substrate. The series of operations includes forming a field of multiple highly absorbing structures within the field of multiple openings by performing a single dry etching operation, wherein the single dry etching operation forms a carbon layer on a surface of the semiconductor substrate, a single wet stripping operation following the single dry etching operation, wherein the single wet stripping operation removes the layer of negative photoresist material, and a single wet etching operation following the single wet stripping operation.

[0131] Additionally or alternatively, the series of operations includes forming a layer of photoresist material on a semiconductor substrate. The series of operations includes forming an opening in the layer of photoresist material to expose a terrace region. The series of operations includes forming a carbon layer within the terrace region. The series of operations includes removing the layer of photoresist material. The series of operations includes forming a highly absorbing structure adjacent to an approximate center of the terrace region.

[0132] Provided in Figure 1 The number and arrangement of the devices shown in FIG. 1 are provided as one or more embodiments. Figure 1 There may be additional devices, fewer devices, different devices, or different arrangements of devices than those shown in FIG. Figure 1 Two or more of the devices shown in the figure may be implemented in a single device, or in Figure 1 A single device shown in the embodiment may be implemented as multiple distributed devices. Additionally or alternatively, a plurality of devices (eg, one or more devices) of one group of environment 100 may perform one or more functions that are described as being performed by another plurality of devices of environment 100.

[0133] Figure 2 2 is a schematic diagram of a pixel array 200 (or a portion thereof) according to an embodiment described herein. The pixel array 200 may be included in an optoelectronic device including a highly absorbing structure, such as a complementary metal oxide image sensor (CIS) device or another type of device.

[0134] Figure 2 2 shows a top view of the pixel array 200. Figure 2 As shown in , pixel array 200 may include a plurality of pixel sensors 202. Figure 2As further shown in FIG. 1 , the pixel sensors 202 can be arranged in a grid. In some embodiments, the pixel sensors 202 are square (e.g., Figure 2 In some embodiments, the pixel sensor 202 includes other shapes, such as a circle, an octagon, a diamond, and / or other shapes.

[0135] Pixel sensor 202 may be configured to sense and / or accumulate incident light (e.g., light directed toward pixel array 200). For example, pixel sensor 202 may absorb and accumulate multiple photons of the incident light in a photodiode. The accumulation of photons in the photodiode may generate a charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a greater intensity or brightness, while a lower amount of charge may correspond to a lower intensity or brightness).

[0136] Pixel array 200 may be electrically connected to a back-end-of-line (BEOL) metallization stack (not shown) of an image sensor. The BEOL metallization stack may electrically connect pixel array 200 to control circuitry that may be used to measure the accumulation of incident light in pixel sensor 202 and convert the measurement result into an electrical signal.

[0137] As mentioned above, providing Figure 2 As an example, other embodiments may differ from the Figure 2 The content described.

[0138] FIG. 3A to FIG. 3D is a schematic diagram of an embodiment image sensor including a highly absorbent structure as described herein. Figure 3A is a schematic diagram of an optoelectronic device 300 (or a portion thereof) according to an embodiment described herein. Figure 3A As shown in , optoelectronic device 300 may include pixel array 200 . Figure 3A A cross-sectional view of an optoelectronic device 300 is shown, including a Figure 2 2 is a cross-sectional view of the pixel array 200 along line AA of FIG. The optoelectronic device 300 may correspond to a complementary metal oxide image sensor (CIS) device or another type of device. The optoelectronic device 300 may be configured to be deployed in various embodiments, such as digital cameras, video recorders, night vision cameras, automotive sensors and cameras, and / or other types of light sensing embodiments.

[0139] As in Figure 3AAs shown in FIG. 1 , the optoelectronic device 300 may include a plurality of regions, such as a pixel array 200, a metal shield region 302, a bonding pad region 304 (also referred to as an E-pad region), and a scribe region 306. The pixel array 200 may include a plurality of pixel sensors 202 of the optoelectronic device 300, such as a pixel sensor 202a and a pixel sensor 202b. In some embodiments, the optoelectronic device 300 includes a plurality of pixel sensors 202a and a plurality of pixel sensors 202b. Figure 3A The number of pixel sensors depicted may be greater than the number of pixel sensors 202 or less than the number of pixel sensors 202 .

[0140] The metal shielding area 302 may include one or more devices that are maintained in an optically dark environment. For example, the metal shielding area 302 may include reference pixels that are used to establish a baseline for the intensity of light for the optoelectronic device 300. In some embodiments, the metal shielding area 302 includes peripheral devices, such as one or more application-specific integrated circuit (ASIC) devices, one or more system-on-chip (SOC) devices, one or more transistors, and / or one or more other components configured to measure the amount of charge stored by the pixel sensor 202 to determine the light intensity of the incident light and / or generate an image and / or video (e.g., a digital image, a digital video).

[0141] Bond pad region 304 may include one or more conductive bond pads (or e-pads) and / or metallization layers through which electrical connections may be established between optoelectronic device 300 and external devices and / or external packages. Scribe region 306 may include an area that separates one semiconductor die or a portion of a semiconductor die that includes optoelectronic device 300 from an adjacent semiconductor die or a portion of a semiconductor die that includes other image sensors and / or other integrated circuits.

[0142] As in Figure 3A As further shown in , the optoelectronic device 300 may include various layers and / or structures. In some embodiments, the optoelectronic device 300 may be mounted and / or fabricated on a carrier substrate (not shown) during one or more semiconductor process operations to form the optoelectronic device 300. Figure 3A As shown in FIG. 3 , the optoelectronic device 300 may include a buffer layer 308. The buffer layer 308 may include a dielectric material, such as silicon oxide (SiO x ), silicon nitride (Si x N y), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, or another dielectric material. The buffer layer 308 can be used as a layer to bond the optoelectronic device 300 to a carrier substrate so that backside processing can be performed on the optoelectronic device 300.

[0143] As in Figure 3A As further shown in FIG. 1 , the optoelectronic device 300 may include an inter-metal dielectric (IMD) layer 310 above and / or on the buffer layer 308. The IMD layer 310 may include one or more layers of dielectric material (e.g., silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated quartz glass (FSG), carbon-doped silicon oxide, or another dielectric material). Each metallization layer 312 can be formed in multiple layers of the intermetallic dielectric layer 310 and / or between multiple layers. The metallization layer 312 may include bonding pads, wires, and / or other types of conductive structures that electrically connect various regions of the optoelectronic device 300 and / or electrically connect various regions of the optoelectronic device 300 to one or more external devices and / or external packages. Multiple metallization layers 312 can be interconnected via contacts 314, which can also be referred to as vias. For example, metallization layer 312a may be electrically connected to metallization layer 312b via one or more contacts 314, metallization layer 312b may be electrically connected to metallization layer 312c via one or more contacts 314, metallization layer 312c may be electrically connected to metallization layer 312d via one or more contacts 314, and so on. Metallization layer 312 and contacts 314 may be referred to as a back-end metallization stack, and may include conductive materials such as gold, copper, silver, cobalt, tungsten, metal alloys, or combinations thereof, among other embodiments.

[0144] As in Figure 3AAs further shown in FIG. 1 , image sensor 300 may include an un-doped silicate glass (USG) layer 316 above and / or on IMD layer 310. Un-doped silicate glass layer 316 may function as an insulator and passivation layer between IMD layer 310 and an interlayer dielectric (ILD) layer 318 above IMD layer 310. ILD layer 318 may include a dielectric material (e.g., silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated quartz glass (FSG), carbon-doped silicon oxide, or another dielectric material).

[0145] The substrate layer 320 may be referred to as a device substrate, on which backside processes of the optoelectronic device 300 are performed. The substrate layer 320 may include a silicon layer, a layer formed of a material including silicon, a III-V compound semiconductor layer such as a gallium arsenide (GaAs) layer, a silicon-on-insulator (SOI) layer, or another type of substrate capable of generating charges from photons of incident light.

[0146] A plurality of photodiodes 322 for pixel sensors 202 in pixel array 200 may be formed within substrate layer 320. A photodiode 322 may include a region of substrate layer 320 doped with multiple types of ions to form a pn junction or a PIN junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) type portion, and an n-type portion). For example, substrate layer 320 may be doped with n-type dopants to form a first portion (e.g., an n-type portion) of photodiode 322, and doped with p-type dopants to form a second portion (e.g., a p-type portion) of photodiode 322. Photodiode 322 may be configured to absorb photons of incident light. The absorption of photons causes photodiode 322 to accumulate charge (referred to as photocurrent) due to the photoelectric effect. Here, photons bombard photodiode 322, which causes the emission of multiple electrons of photodiode 322. The emission of multiple electrons causes the formation of electron-hole pairs, wherein the electrons migrate toward the cathode of photodiode 322 and the holes migrate toward the anode, which generates the photocurrent.

[0147] A plurality of deep trench isolation (DTI) structures 324 may be included in the substrate layer 320. Specifically, the deep trench isolation structures 324 may be formed between each of the plurality of photodiodes 322 of the pixel sensor 202, such that the photodiodes 322 are surrounded by the deep trench isolation structures 324. As an embodiment, the deep trench isolation structures 324 may be formed between the photodiode 322 of the pixel sensor 202a and the pixel sensor 202b, the deep trench isolation structures 324 may be formed between the photodiode 322 of the pixel sensor 202a and the adjacent pixel sensor, the deep trench isolation structures 324 may be formed between the photodiode 322 of the pixel sensor 202b and the adjacent pixel sensor, and so on. The plurality of deep trench isolation structures 324 may form a grid layout, wherein the plurality of deep trench isolation structures 324 extend laterally across the pixel array 200 and intersect at various locations of the pixel array 200. In some embodiments, the deep trench isolation structure 324 may be a backside deep trench isolation (BDTI) structure formed as part of the backside process of the optoelectronic device 300 .

[0148] The deep trench isolation structure 324 may include a trench (e.g., a deep trench) extending down along the photodiode 322 into the substrate layer 320. The deep trench isolation structure 324 may provide optical isolation between the plurality of pixel sensors 202 of the pixel array 200 to reduce the amount of optical crosstalk between adjacent plurality of pixel sensors 202. Specifically, the deep trench isolation structure 324 may absorb, refract, and / or reflect incident light, which may reduce the amount of incident light that travels through a pixel sensor 202 into an adjacent pixel sensor 202 and is absorbed by the adjacent pixel sensor 202.

[0149] One or more high absorption (HA) regions 326 may be located within the substrate layer 320 and within and / or above the one or more photodiodes 322. Each high absorption region 326 may be defined by a shallow trench. One or more high absorption regions 326 may be formed in the same side of the substrate layer 320 as the deep trench isolation structure 324.

[0150] The high absorption region 326 can increase the absorption of incident light for the pixel sensor 202 (thereby increasing the quantum efficiency of the pixel sensor 202) by modifying or changing the direction of the refractive interface between the photodiode 322 of the pixel sensor 202 and the substrate layer 320. The slanted surface of the high absorption structure within the high absorption region 326 changes the direction of the interface between the photodiode 322 and the substrate layer 320 by making this interface slanted relative to the direction of the top surface of the substrate layer 320. For the same incident angle of the incident light, this change in direction can result in a smaller refraction angle compared to a flat surface of the top surface of the substrate layer 320.

[0151] As an example, in combination with Figure 3B In more detail, a field of multiple high-absorbency structures 328a may include multiple adjacent high-absorbency structures, and these adjacent multiple high-absorbency structures have an inverted triangle profile. Figure 3A As shown in , this field of multiple high absorption structures 328a can penetrate into the photodiode 322. Additionally or alternatively, this field of multiple high absorption structures 328a can penetrate into the substrate layer 320.

[0152] Additionally or alternatively, such as in combination with Figure 3C In more detail, a field of multiple high absorbency structures 328b may include adjacent multiple high absorbency structures having an inverted trapezoidal profile, wherein the platform area 330 is directly and horizontally between adjacent high absorbency structures. Figure 3A As shown in , this field of multiple high absorption structures 328b can penetrate into the photodiode 322. Additionally or alternatively, this field of multiple high absorption structures 328b can penetrate into the substrate layer 320.

[0153] Additionally or alternatively, such as in combination with Figure 3D In more detail, a field of multiple high absorbency structures 328c may include multiple adjacent high absorbency structures having an inverted trapezoidal profile, wherein the platform area 330 is directly and horizontally between two adjacent high absorbency structures. Figure 3A As shown in , this field of multiple high absorption structures 328c can penetrate into the photodiode 322. Additionally or alternatively, this field of multiple high absorption structures 328c can penetrate into the substrate layer 320.

[0154] The top surface of the substrate layer 320, the surface of the deep trench isolation structure 324, and the multiple surfaces of the multiple high absorption regions 326 (e.g., the field of high absorption structures 328a, 328b, and / or 328c) may be coated with an antireflective coating (ARC) 332 to reduce reflection of incident light from the photodiode 322 and increase transmission of incident light into the substrate layer 320 and the photodiode 322. The antireflective coating 332 may include a suitable material for reducing reflection of incident light projected toward the photodiode 322, such as a nitrogen-containing material or other embodiments.

[0155] The oxide layer 334 may be located above the substrate layer 320 and above and / or on the anti-reflective coating 332. In addition, the material of the oxide layer 334 may fill the deep trench isolation structure 324 and the high absorption region 326. The oxide layer 334 may function as a passivation layer between the substrate layer 320 and the upper layers of the pixel array 200. In some embodiments, the oxide layer 334 includes an oxide material, such as silicon oxide (SiO x In some embodiments, silicon nitride (SiN x ), Silicon Carbide (SiC x ), or a mixture thereof, such as silicon carbon nitride (SiCN), silicon oxynitride (SiON), or another dielectric material is used instead of the oxide layer 334 as the passivation layer.

[0156] The metal shield layer 336 may be located above the oxide layer 334 (or portions thereof) and / or on the oxide layer 334. The metal shield layer 336 may provide shielding for multiple components and / or multiple devices formed in the metal shielding area 302. The metal shield layer 336 may be formed of a metal material, such as gold, silver, aluminum, a metal alloy, or the like. One or more passivation layers may be formed above the metal shield layer 336 and / or on the metal shield layer 336. For example, a back-illuminated (BSI) oxide layer 338 may be located above multiple portions of the oxide layer 334 and / or on multiple portions of the oxide layer 334, and above the metal shield layer 336 and / or on the metal shield layer 336. As another example, a buffer oxide layer 340 may be located above the back-illuminated oxide layer 338 and / or on the back-illuminated oxide layer 338. In some embodiments, the back-illuminated oxide layer 338 and / or the buffer oxide layer 340 include an oxide material, such as silicon oxide (SiO x In some embodiments, silicon nitride (SiN x ), Silicon Carbide (SiC x), or a mixture thereof, such as silicon carbon nitride (SiCN), silicon oxynitride (SiON), or another dielectric material to replace the back-illuminated oxide layer 338 and / or the buffer oxide layer 340 as a passivation layer.

[0157] A filter layer 342 can be included in the pixel array 200 for one or more pixel sensors 202, above and / or on the buffer oxide layer 340. The filter layer 342 can include one or more visible light color filter regions configured to filter visible light of a particular wavelength or wavelength range (e.g., allowing visible light of a particular wavelength or wavelength range to pass through the filter layer 342), one or more near infrared (NIR) filter regions (e.g., NIR bandpass filter regions) configured to allow wavelengths associated with near infrared light to pass through the filter layer 342 and block light of other wavelengths, one or more near infrared out-of-cut filter regions configured to block near infrared light from passing through the filter layer 342, and / or other types of filter regions. In some embodiments, one or more pixel sensors 202 in the pixel array 200 are each configured with a filter region of the filter layer 342. For example, pixel sensor 202a may be configured with filter region 342a that is higher than photodiode 322 of pixel sensor 202a, pixel sensor 202b may be configured with filter region 342b that is higher than photodiode 322 of pixel sensor 202b, and so on. In some implementations, filter regions may be omitted from filter layer 342 for one or more pixel sensors 202 in pixel array 200 to allow all wavelengths of light to pass through filter layer 342 for one or more pixel sensors 202. In these embodiments, one or more pixel sensors 202 may be configured as white pixel sensors.

[0158] The microlens layer 344 may be included above the filter layer 342 and / or on the filter layer 342. The microlens layer 344 may include a plurality of microlenses. Specifically, the microlens layer 344 may include a corresponding microlens for each of the plurality of pixel sensors 202 included in the pixel array 200. For example, a first microlens may be formed to focus incident light toward the photodiode 322 of the pixel sensor 202a, a second microlens may be formed to focus incident light toward the photodiode 322 of the pixel sensor 202b, and so on.

[0159] As shown in the bond pad region 304 of the optoelectronic device 300, a shallow trench isolation (STI) structure 346 may be located above the interlayer dielectric layer 318 in the bond pad region 304 and / or above the interlayer dielectric layer 318 in the bond pad region 304. The shallow trench isolation structure 346 may provide electrical isolation in the bond pad region 304. For example, the shallow trench isolation structure 346 may electrically isolate the pixel array 200 and / or the metal shield region 302 from other regions of the optoelectronic device 300 and / or other devices formed on the same semiconductor die as the optoelectronic device 300. In some embodiments, the buffer oxide layer 340 may be located above the shallow trench isolation structure 346 in the bond pad region 304 and / or above the shallow trench isolation structure 346 in the bond pad region 304.

[0160] The bonding pad 348 may be located in the bonding pad region 304 above the shallow trench isolation structure 346, and / or above the buffer oxide layer 340 and / or on the buffer oxide layer 340. The bonding pad 348 may extend through the buffer oxide layer 340, through the shallow trench isolation structure 346, and through the interlayer dielectric layer 318 to the intermetallic dielectric layer 310, and may contact one or more metallization layers 312 in the intermetallic dielectric layer 310. The bonding pad 348 may include a conductive material, such as gold, silver, aluminum, copper, aluminum-copper, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, a metal alloy, other metals, or a combination thereof. The bonding pad 348 may provide an electrical connection between the metallization layer 312 of the optoelectronic device 300 and an external device and / or external package.

[0161] Figure 3B Detail of a field of multiple high absorbency structures 328a that may be included in a high absorbency zone 326 is shown. Figure 3B As shown in , the field of multiple high absorption structures 328a includes high absorption structure 350a, which is adjacent to high absorption structure 350b. In some embodiments, high absorption structure 350a and high absorption structure 350b are symmetrical about central axis 352. In some embodiments, the surface of high absorption structure 350a and / or the surface of high absorption structure 350b penetrates into photodiode 322 (and / or substrate layer 320) at angle D1. As an example, angle D1 may be included in the range of about 50 degrees to about 60 degrees. If angle D1 is less than about 50 degrees, or greater than about 60 degrees, the efficiency of high absorption structure 350a and / or high absorption structure 350b in absorbing energy (e.g., incident light) may be reduced. However, other values ​​and ranges of angle D1 are also within the scope of the present disclosure.

[0162] In some embodiments, the high absorbency structure 350a and / or the high absorbency structure 350b comprises an inverted triangular profile. In such a case, the high absorbency structure 350a and / or the high absorbency structure 350b may correspond to an inverted pyramid. Additionally or alternatively, the high absorbency structure 350a and / or the high absorbency structure 350b may correspond to an inverted cone.

[0163] The high absorption structure 350a and / or the high absorption structure 350b may include portions of the photodiode 322. Additionally or alternatively, the high absorption structure 350a and / or the high absorption structure 350b may include portions of the oxide layer 334. Additionally or alternatively, the high absorption structure 350a and / or the high absorption structure 350b may include portions of the anti-reflective coating 332.

[0164] Figure 3C Detail of a field of high absorbency structures 328b that may be included in high absorbency zones 326 is shown. Figure 3C As shown in FIG. 1 , the field of high absorption structure 328b includes high absorption structure 350c, which is adjacent to high absorption structure 350d. In some embodiments, the surface of high absorption structure 350c and / or the surface of high absorption structure 350d penetrate into the photodiode 322 (and / or substrate layer 320).

[0165] In some embodiments, the high absorbency structure 350c and / or the high absorbency structure 350d comprises an inverted triangular profile. In such a case, the high absorbency structure 350c and / or the high absorbency structure 350d may correspond to an inverted pyramid. Additionally or alternatively, the high absorbency structure 350c and / or the high absorbency structure 350d may correspond to an inverted cone.

[0166] The high absorption structure 350c and / or the high absorption structure 350d may include portions of the photodiode 322. Additionally or alternatively, the high absorption structure 350c and / or the high absorption structure 350d may include portions of the oxide layer 334. Additionally or alternatively, the high absorption structure 350c and / or the high absorption structure 350d may include portions of the anti-reflective coating 332.

[0167] As in Figure 3C As further shown in FIG. 3 , the platform region 330 is directly and horizontally located between the high absorbency structure 350c and the high absorbency structure 350d. In some embodiments, the high absorbency structure 350c and the high absorbency structure 350d are symmetrical about a central axis of the platform region 330 (eg, central axis 352).

[0168] In some embodiments, the width D2 of the terrace region may be included in a range of about 100 micrometers (μm) to about 500 micrometers. If the width D2 is less than about 100 micrometers, the plurality of cavities used to form the high absorption structure 350c and / or the high absorption structure 350d may be over-etched. Additionally or alternatively, damage to a device including the high absorption structure 350c and / or the high absorption structure 350d (e.g., the optoelectronic device 300 including the photodiode 322 and / or the substrate layer 320) may occur. If the width is greater than about 500 micrometers, the plurality of cavities used to form the high absorption structure 350c and / or the high absorption structure 350d may be under-etched and may not meet a threshold for performance (e.g., quantum efficiency (QE) performance) for the optoelectronic device. However, other values ​​and ranges for the width D2 are also within the scope of the present disclosure.

[0169] As shown in the enlarged view of the terrace region 330, the carbon layer 354 may be on the top surface of the photodiode 322 (and / or the substrate layer 320). FIG. 4E to FIG. 4J Describing in more detail, the dry etching process included in a series of multiple operations for forming the high absorption structure 350 c and / or the high absorption structure 350 d may include forming the carbon layer 354 .

[0170] Figure 3D Detail of a field of multiple high absorbency structures 328c that may be included in a high absorbency zone 326 is shown. Figure 3D As shown in , the field of multiple high absorption structures 328c includes high absorption structure 350e, which is adjacent to high absorption structure 350f. In some embodiments, the surface of high absorption structure 350e and / or the surface of high absorption structure 350f penetrates into the photodiode 322 (and / or substrate layer 320).

[0171] In some embodiments, the high absorbency structure 350e and / or the high absorbency structure 350f comprises an inverted trapezoidal profile. In such a case, the high absorbency structure 350e and / or the high absorbency structure 350f may correspond to an inverted truncated pyramid shape. Additionally or alternatively, the high absorbency structure 350e and / or the high absorbency structure 350f may correspond to an inverted truncated cone shape. FIG. 4E to FIG. 4J In more detail, the depth of the high absorption structure 350e and / or the high absorption structure 350f (eg, the depth of the truncation) may depend on the length of the wet etching process used to form the cavity of the high absorption structure 350e and / or the high absorption structure 350f.

[0172] The high absorption structure 350e and / or the high absorption structure 350f may include portions of the photodiode 322. Additionally or alternatively, the high absorption structure 350e and / or the high absorption structure 350f may include portions of the oxide layer 334. Additionally or alternatively, the high absorption structure 350e and / or the high absorption structure 350f may include portions of the anti-reflective coating 332.

[0173] As in Figure 3D As further shown in FIG. 3 , the platform region 330 is directly and horizontally between the high absorption structure 350e and the high absorption structure 350f. In some embodiments, the high absorption structure 350e and the high absorption structure 350f are symmetrical about the central axis (e.g., central axis 352) of the platform region 330. As shown in the enlarged view of the platform region 330, the carbon layer 354 can be on the top surface of the photodiode 322 (and / or the substrate layer 320).

[0174] As combined FIG. 3A to FIG. 3D As described, an optoelectronic device (e.g., optoelectronic device 300) may include a first high absorption structure (e.g., high absorption structure 350c) that penetrates into a semiconductor substrate (e.g., substrate layer 320 and / or photodiode 322). The optoelectronic device includes a second high absorption structure (e.g., high absorption structure 350d) that penetrates into the semiconductor substrate and is adjacent to the first high absorption structure. The optoelectronic device includes a terrace region (e.g., terrace region 330) that includes a carbon layer (e.g., carbon layer 354), wherein the terrace region is directly and horizontally between the first high absorption structure and the second high absorption structure.

[0175] Provided FIG. 3A to FIG. 3D The number and arrangement of components, structures, and / or layers shown in the optoelectronic device 300 is provided as an example. In practice, the optoelectronic device 300 may include additional components, structures, and / or layers; fewer components, structures, and / or layers; different components, structures, and / or layers; and / or components, structures, and / or layers that are different from those shown in FIG. FIG. 3A to FIG. 3D The components, structures, and / or layers shown in the drawings may be arranged differently.

[0176] 4A to 4W is a schematic diagram of an example implementation 400 described herein. Example implementation 400 may be an example process for forming optoelectronic device 300 in a field including a plurality of highly absorbing structures 328 within highly absorbing regions 326 .

[0177] As in Figure 4AAs shown in FIG. 3 , the optoelectronic device 300 may include the pixel array 200, the metal shielding region 302, the bonding pad region 304, and the scribe line region 306. In addition, the optoelectronic device 300 may include a substrate layer 320, a shallow trench isolation structure 346 formed in the substrate layer 320, an interlayer dielectric layer 318 formed on the substrate layer 320, and an undoped silicate glass layer 316 formed on the interlayer dielectric layer 318.

[0178] As in Figure 4B As shown in , one or more semiconductor process tools may form intermetallic dielectric layer 310 below and / or above interlayer dielectric layer 318 and above and / or on undoped silicate glass layer 316. For example, deposition tool 102 may deposit intermetallic dielectric layer 310 using a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, or another type of deposition technique.

[0179] As in Figure 4B As further shown in FIG. 1 , one or more semiconductor process tools may form metallization layers 312 and contacts 314 in the intermetallic dielectric layer 310. In some embodiments, a deposition operation or a plating operation may be used to form each metallization layer 312 and each contact 314. For example, the plating tool 112 may apply a voltage across an anode formed by a plating material and a cathode (e.g., a substrate). This voltage causes an electric current to oxidize the anode, which causes the release of plating material ions from the anode. These plating material ions form a plating solution that moves through the plating tank toward the substrate. The plating solution reaches the substrate and deposits the plating material in and / or on the intermetallic dielectric layer 310 to form the metallization layer 312 and the contact 314.

[0180] In some embodiments, forming the metallization layer 312 and the contact 314 may include multiple plating operations. For example, a first portion of the intermetallic dielectric layer 310 may be formed, and the metallization layer 312a may be formed in the first portion of the intermetallic dielectric layer 310. A second portion of the intermetallic dielectric layer 310 may be formed, and the metallization layer 312b (and the contact 314 connecting the metallization layer 312a and the metallization layer 312b) may be formed in the second portion of the intermetallic dielectric layer 310. A third portion of the intermetallic dielectric layer 310 may be formed, and the metallization layer 312c (and the contact 314 connecting the metallization layer 312b and the metallization layer 312c) may be formed in the third portion of the intermetallic dielectric layer 310. A fourth portion of the intermetallic dielectric layer 310 may be formed over the metallization layer 312c to electrically insulate the metallization layer 312c.

[0181] As in Figure 4CAs shown in , one or more semiconductor process tools may form a buffer layer 308 above and / or on the intermetal dielectric layer 310. For example, the deposition tool 102 may deposit the buffer layer 308 on the intermetal dielectric layer 310. In some embodiments, the deposition tool 102 may deposit the buffer layer 308 using a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, or another type of deposition technique. Bonding or attaching the optoelectronic device 300 to a carrier substrate may use the buffer layer 308 so that a backside process may be performed on the optoelectronic device 300 to form one or more layers and / or structures on the backside of the optoelectronic device 300 (e.g., on a side of the substrate layer 320 opposite to a side of the substrate layer 320 where the interlayer dielectric layer 318 is formed).

[0182] As in Figure 4D As shown in , one or more semiconductor process tools may form a plurality of photodiodes 322 in substrate layer 320. For example, implant tool 114 may dope portions of substrate layer 320 using ion implantation techniques to form respective photodiodes 322 for each of a plurality of pixel sensors 202 (e.g., pixel sensor 202a and pixel sensor 202b). Substrate layer 320 may be doped with multiple types of ions to form a pn junction for each photodiode 322. For example, substrate layer 320 may be doped with n-type dopants to form a first portion (e.g., an n-type portion) of photodiode 322, and doped with p-type dopants to form a second portion (e.g., a p-type portion) of photodiode 322. In some embodiments, another technique is used to form photodiode 322, such as diffusion.

[0183] As in Figure 4E As shown in , a plurality of deep trench isolation structures 324 may be formed in the substrate layer 320. Specifically, the deep trench isolation structure 324 may be formed between each of the plurality of photodiodes 322 of the pixel sensor 202. As an embodiment, the deep trench isolation structure 324 may be formed between the photodiode 322 of the pixel sensor 202a and the pixel sensor 202b, the deep trench isolation structure 324 may be formed between the photodiode 322 of the pixel sensor 202a and another adjacent pixel sensor 202, the deep trench isolation structure 324 may be formed between the photodiode 322 of the pixel sensor 202b and another adjacent pixel sensor 202, and so on.

[0184] In some embodiments, one or more semiconductor process tools (e.g., of the plurality of semiconductor process tools 102-114) may be used to form deep trench isolation structures 324 in the substrate layer 320. For example, the deposition tool 102 may form a photoresist layer on the substrate layer 320, the exposure tool 104 may expose the photoresist layer to a radiation source to pattern the photoresist layer, the developer tool 106 may develop and remove portions of the photoresist layer to expose the pattern, and the etch tool 108 may etch portions of the substrate layer 320 to form a plurality of deep trench isolation structures 324 in the substrate layer 320. In some embodiments, after the etch tool 108 etches the substrate layer 320, the photoresist removal tool removes remaining portions of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0185] As in Figure 4E As further shown in FIG. 4F to FIG. 4J In more detail, a plurality of cavities 402 may be formed in one or more regions 404 for a field of a plurality of high-absorption structures (e.g., a plurality of cavities for such a field of a plurality of high-absorption structures 328). The plurality of regions 404 may correspond to a plurality of surface regions of the substrate layer 320 and / or a plurality of surface regions of the one or more photodiodes 322. In some embodiments, the cavities 402 may correspond to an inverted pyramid-shaped cavity region, or an inverted cone-shaped cavity region, among other embodiments.

[0186] As a part of forming the cavity 402, as in Figure 4F As shown in FIG. , a deposition tool (eg, a spin coating tool) Figure 1 Deposition tool 102 of the embodiment of the present invention may deposit layer 406 of photoresist material on and / or over photodiode 322 (and / or on and / or over substrate layer 320). In some embodiments, layer 406 of photoresist material includes a negative photoresist material (e.g., a photoresist in which portions exposed to light become insoluble in a photoresist developer solution). In some embodiments, layer 406 of photoresist material may have a thickness D3 within a range of about 180 nanometers to about 220 nanometers. If thickness D3 is less than about 180 nanometers, layer 406 of photoresist material may not be sufficient to serve as a mask for subsequent etching operations. If thickness D3 is greater than about 220 nanometers, layer 406 of photoresist material may be less than about 220 nanometers, and may be less than about 100 nanometers. Figure 1 However, other values ​​and ranges of thickness D3 are also within the scope of the present disclosure.

[0187] As in Figure 4GAs shown in FIG. 4 , an opening 408 is formed in a layer 406 of photoresist material. The opening 408 may expose the mesa region 330. Forming the opening 408 may include an exposure tool (e.g., in FIG. 4 ) that projects radiation (e.g., light) through a mask. Figure 1 4. The developer tool (e.g., an exposure tool 104) is used to expose a portion of the layer 406 of photoresist material. In the case where the layer 406 of photoresist material comprises a negative photoresist material, a developer tool (e.g., Figure 1 The developer tool 106 ) may remove (eg, dissolve) the exposed portions of the layer 406 of photoresist material to form openings 408 .

[0188] As in Figure 4H As shown in FIG. 3 , a carbon layer 354 is formed within the platform region 330. As one embodiment, and as part of forming the carbon layer 354, an etching tool (e.g., Figure 1 The etching tool 108 and / or another suitable tool may perform a dry etching operation (e.g., a plasma etching operation) using a carbon fluoride-based etchant to remove oxide from the surface of the photodiode 322 (and / or the surface of the substrate layer 320). In such a case, byproducts of the etchant (e.g., carbon radicals) may form a carbon layer 354 on the surface of the photodiode 322 within the mesa region 330.

[0189] As in Fig. 4I As shown in , the layer 406 of photoresist material is removed. As an example, and as part of removing the layer of photoresist material, an etching tool (e.g., Figure 1 The etching tool 108 and / or another suitable tool) may perform a wet stripping operation using a chromium-based solvent.

[0190] As in Figure 4J As shown in FIG. 4 , cavities 402a and 402b are formed within region 404. Cavities 402a and 402b may be formed symmetrically about a central axis (e.g., central axis 352) of platform region 330. As one embodiment, and as part of forming cavities 402a and 402b, an etching tool (e.g., Figure 1 The etching tool and / or another suitable tool) can perform a wet etching operation using an etchant based on tetramethyl ammonium hydroxide (TMAH). Additionally or alternatively, the etching tool can perform a wet etching operation using an etchant based on choline hydroxide.

[0191] In some cases, carbon layer 354 can block the etchant from removing mesa region 330. Additionally or alternatively, the etch rate of carbon layer 354 can be small relative to the etch rate of photodiode 322 (and / or substrate layer 320) for the etchant.

[0192] As in Figure 4J As shown in FIG. 4 , the cavity 402a and / or the cavity 402b include a profile having an inverted triangle shape. Additionally or alternatively, the cavity 402a and / or the cavity 402b may include a profile having an inverted trapezoidal shape.

[0193] In some cases, the shape of the profile may depend on the duration of the wet etching operation. Additionally, in some cases, the duration of the wet etching operation may be sufficient to remove the mesa region 330 (and / or the carbon layer 354).

[0194] The cavity 402a and the cavity 402b are formed using a combination of FIG. 4F to FIG. 4J The described techniques may use a single dry etch operation, a single wet strip operation, and / or a single wet etch operation. Compared to other techniques that use positive photoresist materials and multiple hard mask layers to form cavities 402a and / or 408b, FIG. 4F to FIG. 4J The technique includes reducing the number of operations. In this way, the amount of various resources used to manufacture cavity 402a and / or cavity 402b can be reduced (e.g., the amount of semiconductor manufacturing tools, raw materials, manpower, and / or computing resources, among other embodiments).

[0195] As in Figure 4K As shown in , the anti-reflective coating 332 can be formed above and / or on the substrate layer 320, can be formed in the deep trench isolation structure 324, and can be formed in the cavity 402. Specifically, the semiconductor process tool (e.g., the deposition tool 102) can deposit the anti-reflective coating 332 using a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, or another type of deposition technique. The anti-reflective coating 332 may include a suitable material that is used to reduce reflection of incident light projected toward the photodiode 322. In some embodiments, the semiconductor process tool can form the anti-reflective coating 332 to a thickness ranging from about 200 angstroms to about 1000 angstroms.

[0196] As in Figure 4L As shown in , one or more deep trench isolation structures 324 may be filled with an oxide material. Additionally or alternatively, one or more cavities 402 may be filled with an oxide material to form a field of multiple high absorption structures 328. Specifically, a semiconductor process tool (e.g., deposition tool 102) may deposit the oxide material such that an oxide layer 334 is formed in the deep trench isolation structure 324, in the cavity 402, and over the substrate layer 320. The semiconductor process tool may deposit the oxide material using various chemical vapor deposition techniques and / or atomic layer deposition techniques, such as plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, or plasma enhanced atomic layer deposition.

[0197] As in Figure 4M As shown in FIG. 1 , a plurality of openings 410 (or trenches) may be formed through the oxide layer 334 and the anti-reflective coating 332 in the metal shield region 302, and a plurality of openings 412 (or trenches) may be formed through the oxide layer 334 and the anti-reflective coating 332 in the scribe line region 306 to the substrate layer 320. The openings 410 and 412 may be formed by coating the oxide layer 334 with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing the exposed or unexposed portions of the photoresist (e.g., using a developer tool 106), and etching the openings 410 and 412 into the oxide layer 334 and the anti-reflective coating 332 to the substrate layer 320 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0198] As in Figure 4N As shown in , the metal shield layer 336 can be formed above and / or on the oxide layer 334 and in the openings 410 and 412. The metal shield layer 336 can provide shielding for components and / or devices formed in the metal shield area 302 and the scribe area 306. The metal shield layer 336 can be formed of a metal material, such as gold, silver, aluminum, a metal alloy, or the like. In some embodiments, the semiconductor process tool (e.g., the plating tool 112) can use a plating technique such as electroplating (or electrochemical deposition) to form the metal shield layer 336. In these embodiments, the semiconductor process tool can apply a voltage across an anode formed by the plating material and a cathode (e.g., a substrate). The voltage causes an electric current to oxidize the anode, which causes the release of the plating material ions from the anode. These plating material ions form a plating solution, which swims through the plating tank toward the optoelectronic device 300. The plating solution reaches the optoelectronic device 300 and ions deposit the plating material onto the oxide layer 334 and in the openings 410 and 412 to form the metal shielding layer 336 .

[0199] As in Fig.4OAs shown in , an opening 414 (or trench) may be formed through the metal shield layer 336 in the bond pad region 304 and in a portion of the oxide layer 334, and a plurality of openings 416 (or trenches) may be formed through the metal shield layer 336 and in a portion of the oxide layer 334 in the pixel array 200. The openings 414 and 416 may be formed by coating the metal shield layer 336 with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing the exposed or unexposed portions of the photoresist (e.g., using a developer tool 106), and etching openings 408 and 410 into the metal shield layer and in a portion of the oxide layer 334 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0200] As in Figure 4P As shown in FIG. 4 , a backside illuminated (BSI) oxide layer 338 may be formed in openings 414 and 416 and over metal shield layer 336 and oxide layer 334. Specifically, a semiconductor process tool (e.g., deposition tool 102) may deposit an oxide material (e.g., silicon oxide (SiO x ) or another type of oxide), so that the back-illuminated oxide layer 338 is formed using various chemical vapor deposition techniques and / or atomic layer deposition techniques, such as plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, or plasma enhanced atomic layer deposition.

[0201] As in Figure 4Q As shown in , the back-illuminated oxide layer 338 can be planarized. Specifically, the semiconductor process tool (e.g., planarization tool 110) can perform, for example, a planarization or grinding process, such as chemical mechanical grinding. The chemical mechanical grinding process can include depositing a slurry (or abrasive compound) onto a polishing pad. The carrier substrate including the optoelectronic device 300 can be mounted to a carrier, and the carrier can rotate the carrier substrate when the carrier substrate is pressed against the polishing pad. The slurry and the polishing pad act as an abrasive that grinds or planarizes the back-illuminated oxide layer 338 when the carrier substrate is rotated. The polishing pad can also be rotated to ensure that a continuous supply of slurry is applied to the polishing pad.

[0202] As in Figure 4RAs shown in FIG. 1 , an opening 418 (or trench) may be formed in the bond pad region 304. Specifically, the opening 418 may be formed through the back-illuminated oxide layer 338, through the metal shield layer 336, through the oxide layer 334, through the anti-reflective coating 332, and through the substrate layer 320 to the shallow trench isolation structure 346. The opening 418 may be formed by coating the back-illuminated oxide layer 338 with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing the exposed or unexposed portions of the photoresist (e.g., using a developer tool 106), and etching the opening 418 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0203] As in Figure 4S As shown in FIG. 4 , a buffer oxide layer 340 may be formed over the back-illuminated oxide layer 338 and over the shallow trench isolation structure 346 in the opening 418. Specifically, a semiconductor process tool (eg, a deposition tool 102) may deposit an oxide material (eg, silicon oxide (SiO x ) or another type of oxide), so that the buffer oxide layer 340 is formed using various chemical vapor deposition techniques and / or atomic layer deposition techniques, such as plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, or plasma enhanced atomic layer deposition.

[0204] As in Figure 4T As shown in , an opening 420 (or via) may be formed in the opening 418 of the bond pad region 304. Specifically, the opening 420 may be formed through the buffer oxide layer 340, through the shallow trench isolation structure 346, through the interlayer dielectric layer 318, and to the metallization layer 312 (e.g., metallization layer 312a) in the intermetallic dielectric layer 310. The opening 420 may be formed by coating the buffer oxide layer 340 with a photoresist (e.g., using a deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using an exposure tool 104), removing the exposed or unexposed portions of the photoresist (e.g., using a developer tool 106), and etching the opening 420 based on the pattern in the photoresist (e.g., using an etching tool 108).

[0205] As in Figure 4U, the bonding pad 348 can be formed in the opening 420. For example, a semiconductor process tool (e.g., deposition tool 102 or plating tool 112) can form a metal layer (e.g., an aluminum layer, a gold layer, a silver layer, a metal alloy layer, or another type of metal layer) on the buffer oxide layer 340, on the shallow trench isolation structure 346, and in the opening 420. Removing portions of the metal layer can be performed by coating the metal layer with a photoresist (e.g., using deposition tool 102), forming a pattern in the photoresist by exposing the photoresist to a radiation source (e.g., using exposure tool 104), removing the exposed or unexposed portions of the photoresist (e.g., using developer tool 106), and etching the portions based on the pattern in the photoresist (e.g., using etching tool 108) to form the bonding pad 348.

[0206] As in Figure 4V , a filter layer 342 is formed for a plurality of pixel sensors in pixel array 200. Filter layer 342 can be formed above and / or on buffer oxide layer 340. In some embodiments, a semiconductor process tool (e.g., deposition tool 102) can deposit filter layer 342 using a chemical vapor deposition technique, a physical vapor deposition technique, an atomic layer deposition technique, or another type of deposition technique.

[0207] As in Figure 4W As shown in FIG. 3 , a microlens layer 344 including a plurality of microlenses is formed above and / or on the filter layer 342. The microlens layer 344 may include a corresponding microlens for each of the plurality of pixel sensors 202 included in the pixel array 200. In some embodiments, the microlens layer 344 may be above the high absorption region 326 including the high absorption structure 328.

[0208] As mentioned above, providing 4A to 4W As an example, other embodiments may differ from the 4A to 4W The content described.

[0209] Figure 5A and Figure 5B is a schematic diagram of an example embodiment 500 of a cavity 402 for forming a high absorbency structure as described herein. Figure 5A As shown in the figure, the cavity 402 includes a smooth surface 502 that is inclined to the photodiode 322 (and / or the substrate layer 320). In addition, the cavity 402 may include a tip 504. In some embodiments, as shown in the figure, the tip 504 includes a sharp turn. In some embodiments, the tip 504 includes a rounded turn. In addition, in some embodiments, the tip 504 includes a flat surface.

[0210] In some embodiments, the smooth surface 502 includes <111> Lattice directions (e.g., Miller indices). In some embodiments, the tip comprises <110> Lattice direction.

[0211] As in Figure 5B As shown in , cavity 402 may include pitting depressions 506 in the surface of the cavity. Pitting depressions 506 may include indentations and / or notches corresponding to the scalloped areas.

[0212] Forming the pitting recess 506 may include, for example, performing a dry etching operation using an etching tool (e.g., Figure 1 Additionally or alternatively, forming the pitting recesses 506 may include a laser tool performing a laser operation.

[0213] In some embodiments, pitting depressions 506 increase the surface area within cavity 402 to increase the amount of photons and / or incident light absorbed via photodiode 322. In this manner, a highly absorbing structure (e.g., highly absorbing structure 350) including pitting depressions 506 can have a greater quantum efficiency than another highly absorbing structure that does not include pitting depressions 506. In such a case, the amount of various resources (e.g., the amount of semiconductor manufacturing tools, raw materials, manpower, and / or computing resources, among other embodiments) required to manufacture a volume of optoelectronic devices (e.g., optoelectronic device 300) that meet a performance threshold can be reduced.

[0214] Figure 6 6 is a schematic diagram of an implementation 600 of an embodiment reticle pattern described herein. The embodiment reticle pattern includes reticle pattern 602 and reticle pattern 604. In some embodiments, a field of a plurality of openings patterned in a layer of negative photoresist material (e.g., layer 406 of photoresist material) can be used with reticle pattern 602 and / or reticle pattern 604 as part of forming a field of a plurality of highly absorptive structures (e.g., a field of a plurality of highly absorptive structures 328).

[0215] The mask pattern 602 may correspond to an "opposite tone" mask pattern used with a layer of negative photoresist material (e.g., layer 406 of photoresist material). The mask pattern 602 includes a matrix pattern of opaque film features 606 that may be distributed on a transparent substrate 608. In some embodiments, the opaque film features 606 are formed of a chrome film material and the transparent substrate 608 is formed of a borosilicate material. Each of the plurality of opaque film features 606 may block exposure of the layer of negative photoresist material to radiation (e.g., light) from an exposure tool (e.g., exposure tool 104). In some embodiments, each of the plurality of opaque film features 606 may correspond to an opening (e.g., opening 408) for forming a carbon layer on a photodiode and / or substrate.

[0216] Mask pattern 604 may correspond to an “opposite-tone” mask pattern used with a layer of negative-tone photoresist material (eg, layer 406 of photoresist material). Mask pattern 604 includes a radial pattern of opaque film features 606 that may be distributed on a transparent substrate 608.

[0217] As mentioned above, providing Figure 6 As an example, other embodiments may differ from the Figure 6 In addition, although Figure 6 While the opaque film features 606 are shown to include circular shapes, in other embodiments the opaque film features 606 may include other shapes, such as rectangular, triangular, and / or oval shapes.

[0218] Figure 7 is a schematic diagram of example components of apparatus 700. In some embodiments, one or more of semiconductor process tools 102 to 114 and / or wafer / die transfer tool 116 may include one or more apparatus 700 and / or one or more components of apparatus 700. Figure 7 As shown in , device 700 may include a bus 710 , a processor 720 , a memory 730 , an input component 740 , an output component 750 , and / or a communication component 760 .

[0219] The bus 710 may include one or more components that enable wired and / or wireless communication between the various components of the device 700. The bus 710 may include one or more components that enable wired and / or wireless communication between the various components of the device 700. Figure 7Two or more components of a processor 720 are coupled together, for example, via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 710 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 720 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, a specific application integrated circuit, and / or another type of processing component. Processor 720 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 720 may include one or more processors that are programmable to perform one or more operations or processes described elsewhere herein.

[0220] The memory 730 may include volatile and / or non-volatile memory. For example, the memory 730 may include random access memory (RAM), read only memory (ROM), a hard drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 730 may include internal memory (e.g., random access memory, read only memory, or hard drive), and / or removable memory (e.g., removable via a universal serial bus connection). The memory 730 may be a non-transitory computer-readable medium. The memory 730 may store information related to the operation of the device 700, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, the memory 730 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 720), for example via bus 710. The communicative coupling between processor 720 and memory 730 may enable processor 720 to read and / or process information stored in memory 730 and / or store information in memory 730 .

[0221] Input assembly 740 may enable device 700 to receive input, such as user input and / or sensed input. For example, input assembly 740 may include a touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, global positioning system sensor, accelerometer, gyroscope, and / or actuator. Output assembly 750 may enable device 700 to provide output, such as via a display, speaker, and / or light emitting diode. Communication assembly 760 may enable device 700 to communicate with other devices via wired connection and / or wireless connection. For example, communication assembly 760 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0222] The device 700 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 730) may store a set of multiple instructions (e.g., one or more instructions or program codes) for implementation via a processor 720. The processor 720 may implement multiple instructions of the set to perform one or more operations or processes described herein. In some embodiments, the implementation of multiple instructions of the set via one or more processors 720 causes one or more processors 720 and / or the device 700 to perform one or more operations or processes described herein. In some embodiments, a hard-wired circuit may be used to replace multiple instructions or to be combined with multiple instructions to perform one or more operations or processes described herein. Additionally or alternatively, the processor 720 may be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuits and software.

[0223] Provided in Figure 7 The number and arrangement of components shown in FIG. are provided as an example. Figure 7 , device 700 may include additional components, fewer components, different components, or components in a different arrangement. Additionally or alternatively, a group of multiple components (e.g., one or more components) of device 700 may perform one or more functions described as being performed by another group of multiple components of device 700.

[0224] Figure 8 is a flow chart of an example process 800 for forming an image sensor including a highly absorbent structure. Figure 8 The one or more process blocks of are performed by one or more of the plurality of semiconductor process tools (eg, one or more of the semiconductor process tools 102 to 114). Additionally or alternatively, performing Figure 8 One or more process blocks may be implemented via one or more components of the apparatus 700 , such as a processor 720 , a memory 730 , an input component 740 , an output component 750 , and / or a communication component 760 .

[0225] As in Figure 8 As shown in FIG. 8 , process 800 may include patterning a field of a plurality of openings in a layer of negative photoresist material on a semiconductor substrate (block 810). For example, as described above, one or more of the plurality of semiconductor process tools 102 - 114 may pattern a field of a plurality of openings (e.g., a field of one or more openings 408) in a layer of negative photoresist material (e.g., layer 406 of photoresist material) on a semiconductor substrate (e.g., substrate layer 320 and / or photodiode 322).

[0226] As in Figure 8As further shown in FIG. 8 , process 800 may include forming a field of multiple highly absorbent structures within the field of multiple openings by performing a single dry etch operation, a single wet strip operation after the single dry etch operation, and a single wet etch operation after the single wet strip operation (block 820). For example, as described above, one or more of semiconductor process tools 102-114 may form a field of multiple highly absorbent structures 328 within the field of multiple openings by performing a single dry etch operation, a single wet strip operation after the single dry etch operation, and a single wet etch operation after the single wet strip operation. In some embodiments, the single dry etch operation forms a carbon layer 354 on a surface of the semiconductor substrate. In some embodiments, the single wet strip operation removes a layer of negative photoresist material.

[0227] Process 800 may include additional embodiments, such as any single embodiment or any combination of embodiments described below, and / or be combined with one or more other processes described elsewhere herein.

[0228] In a first embodiment, performing the single dry etching operation includes performing the single dry etching operation using a carbon fluoride based etchant.

[0229] In a second embodiment, alone or in combination with the first embodiment, performing the single wet etching operation includes performing the single wet etching operation using a tetramethylammonium hydroxide based etchant.

[0230] In a third embodiment, either alone or in combination with one or more of the first and second embodiments, performing the single wet etching operation includes performing the single wet etching operation to form a field of multiple inverted pyramid-shaped cavities (e.g., a field of one or more of the multiple cavities 402) penetrating into the semiconductor substrate.

[0231] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, performing this single wet etching operation includes performing this single wet etching operation to form a field of multiple platform areas (for example, one or more of the multiple platform areas 330) and a field of multiple cavity areas (for example, a field of one or more of the multiple cavities 402), wherein this field of multiple cavity areas penetrates into the semiconductor substrate, and wherein this field of multiple platform areas is interspersed between this field of multiple cavity areas.

[0232] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, this single wet etching operation is performed to form a field of multiple smooth surfaces inclined to the semiconductor substrate (for example, a field of one or more of the multiple smooth surfaces 502), and also includes forming pitting depressions 506 in this field of multiple smooth surfaces.

[0233] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, forming pitting depressions 506 in a field of multiple smooth surfaces includes using a dry etching operation to form at least a portion of the pitting depressions 506 in this field of multiple smooth surfaces.

[0234] In a seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, forming pitting depressions 506 in this field of multiple smooth surfaces includes using a laser to operate to form at least a portion of the pitting depressions 506 in this field of multiple smooth surfaces.

[0235] although Figure 8 Several example blocks of process 800 are shown, but in some embodiments, Figure 8 , process 800 may include additional blocks, fewer blocks, different blocks, or blocks in a different arrangement. Additionally or alternatively, two or more blocks of process 800 may be performed in parallel.

[0236] Fig. 9 is a flow chart of an example process 900 for forming an image sensor including a highly absorbent structure. Fig. 9 The one or more process blocks of are performed by one or more of the plurality of semiconductor process tools (eg, one or more of the plurality of semiconductor process tools 102 to 114). Additionally or alternatively, performing Fig. 9 One or more process blocks may be implemented via one or more components of the apparatus 700 , such as a processor 720 , a memory 730 , an input component 740 , an output component 750 , and / or a communication component 760 .

[0237] As in Fig. 9 As shown in FIG. 9 , process 900 may include forming a layer of photoresist material on a semiconductor substrate (block 910). For example, one or more of the plurality of semiconductor process tools 102 to 114 may form a layer 406 of photoresist material on a semiconductor substrate (e.g., substrate layer 320 and / or photodiode 322), as described above.

[0238] As in Fig. 9As further shown in FIG. 9 , process 900 may include forming an opening in the layer of photoresist material to expose the mesa region (block 920). For example, one or more of the plurality of semiconductor process tools 102 to 114 may form opening 408 on the layer of photoresist material 406 to expose the mesa region 330, as described above.

[0239] As in Fig. 9 As further shown in FIG. 9 , the process 900 may include forming a carbon layer within the platform region (block 930 ). For example, one or more of the plurality of semiconductor process tools 102 - 114 may form a carbon layer 354 within the platform region 330 , as described above.

[0240] As in Fig. 9 As further shown in FIG. 9 , the process 900 may include removing the layer of photoresist material (block 940 ). For example, as described above, one or more of the plurality of semiconductor process tools 102 - 114 may remove the layer of photoresist material 406 .

[0241] As in Fig. 9 As further shown in FIG. 9 , the process 900 may include forming a highly absorbent structure adjacent to an approximate center of the platform region (block 950). For example, one or more of the plurality of semiconductor process tools 102 to 114 may form a highly absorbent structure 350 adjacent to an approximate center (e.g., central axis 352) of the platform region 330, as described above.

[0242] Process 900 may include additional embodiments, such as any single embodiment or any combination of embodiments described below, and / or be combined with one or more other processes described elsewhere herein.

[0243] In a first embodiment, removing the layer 406 of photoresist material includes removing the layer 406 of photoresist material using a wet stripping operation, wherein the wet stripping operation uses a chromium-based solvent.

[0244] In a second embodiment, alone or in combination with the first embodiment, forming the high absorption structure 350 includes forming the high absorption structure 350 via performing a wet etching operation, wherein the wet etching operation uses a choline hydroxide etchant.

[0245] In a third embodiment, either alone or in combination with one or more of the first and second embodiments, forming the high absorption structure 350c includes forming the high absorption structure 350c using a wet etching operation, wherein the carbon layer 354 blocks the etchant during the wet etching operation, and wherein the duration of the wet etching operation is sufficient to form an inverted cavity (e.g., cavity 402) having a triangular profile.

[0246] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, forming the high absorption structure 350e includes forming the high absorption structure 350e using a wet etching operation, wherein the carbon layer 354 blocks the etchant during the wet etching operation, and wherein the duration of the wet etching operation is sufficient to form an inverted cavity (e.g., cavity 402) having a trapezoidal profile.

[0247] In a fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, forming the high absorption structure 350a includes forming the high absorption structure 350a using a wet etching operation, wherein the duration of the wet etching operation is sufficient to form an inverted cavity (e.g., cavity 402) having a triangular profile and to remove the platform region 330.

[0248] although Fig. 9 Several example blocks of process 900 are shown, but in some embodiments, Fig. 9 In contrast to the blocks shown in , process 900 includes additional blocks, fewer blocks, different blocks, or blocks in a different arrangement. Additionally or alternatively, two or more blocks of process 900 may be performed in parallel.

[0249] Some embodiments described herein provide optoelectronic devices and methods of forming. The optoelectronic device is manufactured using a series of multiple operations that include a patterning operation using a layer of a negative photoresist material, followed by a single dry etching operation, a single wet stripping operation, and a single wet etching operation. This series of multiple operations may include reducing the number of operations compared to another series of multiple operations that includes a patterning operation using a layer of a positive photoresist material. By reducing the number of operations, damage to the device caused by processing can be reduced. In addition, the high absorption structure may include a greater quantum efficiency compared to another quantum efficiency of another high absorption structure formed by a series of multiple operations (including a patterning operation using a layer of a positive photoresist material).

[0250] In this manner, the manufacturing yield of an optoelectronic device including a high absorption structure that meets a quantum efficiency threshold can be increased compared to another optoelectronic device that does not include the high absorption structure. Additionally or alternatively, the amount of various resources (e.g., the amount of semiconductor manufacturing tools, raw materials, manpower, and / or computing resources, among other embodiments) required to manufacture a volume of optoelectronic devices including the high absorption structure can be reduced.

[0251] As described in more detail above, some embodiments described herein provide an optoelectronic device. The optoelectronic device includes a first high absorption structure that penetrates into a semiconductor substrate. The optoelectronic device includes a second high absorption structure that penetrates into the semiconductor substrate and is adjacent to the first high absorption structure. The optoelectronic device includes a terrace region that includes a carbon layer, wherein the terrace region is directly and horizontally between the first high absorption structure and the second high absorption structure.

[0252] In some embodiments, in the optoelectronic device, each of the first high absorption structure and the second high absorption structure comprises: an inverted triangle profile.

[0253] In some embodiments, in the optoelectronic device, each of the first high absorption structure and the second high absorption structure comprises: an inverted trapezoidal profile.

[0254] In some embodiments, in an optoelectronic device, each of the first high absorption structure and the second high absorption structure comprises: a plurality of surfaces comprising pitting depressions.

[0255] In some embodiments, in an optoelectronic device, the pitting depression comprises: a plurality of scalloped regions extending into the plurality of surfaces.

[0256] In some embodiments, in an optoelectronic device, the terrace region comprises: a width included in a range of about 100 microns to about 500 microns.

[0257] As described in more detail above, some embodiments described herein provide a method. The method includes patterning a field of multiple openings in a layer of negative photoresist material on a semiconductor substrate. The method includes forming a field of multiple highly absorbing structures within the field of multiple openings by performing a single dry etching operation, wherein the single dry etching operation forms a carbon layer on a surface of the semiconductor substrate, performing a single wet stripping operation after the single dry etching operation, wherein the single wet stripping operation removes the layer of negative photoresist material, and performing a single wet etching operation after the single wet stripping operation.

[0258] In some embodiments, in a method of manufacturing an optoelectronic device, performing the single dry etching operation includes: performing the single dry etching operation using a carbon-fluoride based etchant.

[0259] In some embodiments, in a method of manufacturing an optoelectronic device, performing the single wet etching operation includes: performing the single wet etching operation using a tetramethylammonium hydroxide-based etchant.

[0260] In some embodiments, in a method of manufacturing an optoelectronic device, performing the single wet etching operation includes: performing the single wet etching operation to form a field of multiple inverted pyramid-shaped cavity regions, wherein the field of multiple inverted pyramid-shaped cavity regions penetrates into the semiconductor substrate.

[0261] In some embodiments, in a method for manufacturing an optoelectronic device, performing the single wet etching operation includes: performing the single wet etching operation to form a field of multiple platform areas and a field of multiple cavity areas, wherein the field of the multiple cavity areas penetrates into the semiconductor substrate, and wherein the field of the multiple platform areas is dispersed between the fields of the multiple cavity areas.

[0262] In some embodiments, in a method for manufacturing an optoelectronic device, performing the single wet etching operation forms a field of multiple smooth surfaces, the field of multiple smooth surfaces is inclined to the semiconductor substrate, and further includes: forming pitting depressions in the field of multiple smooth surfaces.

[0263] In some embodiments, in the method of manufacturing an optoelectronic device, forming the pitting recess in the field of the plurality of smooth surfaces includes: using a dry etching operation to form at least a portion of the pitting recess in the field of the plurality of smooth surfaces.

[0264] In some embodiments, in the method of manufacturing an optoelectronic device, forming the pitting depression in the field of the plurality of smooth surfaces includes: operating using a laser to form at least a portion of the pitting depression in the field of the plurality of smooth surfaces.

[0265] As described in more detail above, some embodiments described herein provide a method. The method includes forming a layer of photoresist material on a semiconductor substrate. The method includes forming an opening in the layer of photoresist material to expose a platform region. The method includes forming a carbon layer within the platform region. The method includes removing the layer of photoresist material. The method includes forming a high absorption structure adjacent to an approximate center of the platform region.

[0266] In some embodiments, in a method of manufacturing an optoelectronic device, removing the layer of photoresist material includes removing the layer of photoresist material using a wet stripping operation, wherein the wet stripping operation uses a chromium-based solvent.

[0267] In some embodiments, in a method of manufacturing an optoelectronic device, forming the high absorption structure includes: forming the high absorption structure by performing a wet etching operation, wherein the wet etching operation uses a choline hydroxide-based etchant.

[0268] In some embodiments, in a method of manufacturing an optoelectronic device, a wet etching operation is used to form the high absorption structure, wherein the carbon layer blocks multiple etchants during the wet etching operation, and wherein a duration of the wet etching operation is sufficient to form an inverted cavity, the inverted cavity having a triangular profile.

[0269] In some embodiments, in a method of manufacturing an optoelectronic device, forming the high absorption structure includes: using a wet etching operation to form the high absorption structure, wherein the carbon layer blocks multiple etchants during the wet etching operation; and wherein a duration of the wet etching operation is sufficient to form an inverted cavity, the inverted cavity having a trapezoidal profile.

[0270] In some embodiments, in a method of manufacturing an optoelectronic device, forming the high absorption structure includes: using a wet etching operation to form the high absorption structure, wherein a duration of the wet etching operation is sufficient to form an inverted cavity and to remove the platform region, the inverted cavity having a triangular profile.

[0271] Other embodiments of the present disclosure provide an optoelectronic device, comprising: a first high absorption structure, a second high absorption structure, and a platform region. The first high absorption structure penetrates into a semiconductor substrate. The second high absorption structure penetrates into the semiconductor substrate and is adjacent to the first high absorption structure. The platform region comprises a carbon layer. The platform region is directly and horizontally between the first high absorption structure and the second high absorption structure. Each of the first high absorption structure and the second high absorption structure has a smooth surface inclined to the semiconductor substrate.

[0272] In some embodiments, an angle between the smooth surface and the semiconductor substrate is in a range of 50 degrees to 60 degrees.

[0273] Still other embodiments of the present disclosure provide an optoelectronic device comprising: a first high absorption structure, a second high absorption structure, and a platform region. The first high absorption structure penetrates into a semiconductor substrate. The second high absorption structure penetrates into the semiconductor substrate and is adjacent to the first high absorption structure. The platform region comprises a carbon layer. The platform region is directly and horizontally between the first high absorption structure and the second high absorption structure. The first high absorption structure and the high absorption structure are symmetrical around a central axis of the platform region.

[0274] In some embodiments, the first high absorbency structure and the second high absorbency structure have an inverted truncated pyramid shape or an inverted truncated cone shape.

[0275] As used herein, depending on the context, "satisfying a threshold" may mean that a value is greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, or the like.

[0276] As used herein, the term "and / or", when used in conjunction with multiple items, is intended to encompass each individual item in the multiple items as well as any and all combinations of the multiple items. For example, "A and / or B" encompasses "A and B", "A and not B", and "B and not A".

[0277] The above summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for the design or modification of other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A photoelectric device, characterized in that: Include: a first high absorption structure penetrating into a semiconductor substrate; a second high absorption structure penetrating into the semiconductor substrate and adjacent to the first high absorption structure; and A platform region, including a carbon layer, The platform region is directly and horizontally between the first high absorbency structure and the second high absorbency structure.

2. The photovoltaic device according to claim 1, wherein: The first high absorbency structure and the second high absorbency structure each comprise: An inverted triangle outline.

3. The photovoltaic device according to claim 1, wherein: The first high absorbency structure and the second high absorbency structure each comprise: An inverted trapezoidal outline.

4. The photovoltaic device according to claim 1, wherein: The first high absorbency structure and the second high absorbency structure each comprise: Several surfaces contained pitting.

5. The photovoltaic device according to claim 4, characterized in that The pitting pits include: A plurality of scalloped regions extend into the plurality of surfaces.

6. The photovoltaic device according to claim 1, wherein: This platform area includes: A width is included in a range of 100 microns to 500 microns.

7. A photoelectric device, characterized in that: Include: a first high absorption structure penetrating into a semiconductor substrate; a second high absorption structure penetrating into the semiconductor substrate and adjacent to the first high absorption structure; and A platform region, including a carbon layer, wherein the platform region is directly and horizontally between the first high absorbency structure and the second high absorbency structure; Each of the first high absorption structure and the second high absorption structure has a smooth surface inclined to the semiconductor substrate.

8. The photovoltaic device according to claim 7, wherein: The included angle between the smooth surface and the semiconductor substrate is in the range of 50 degrees to 60 degrees.

9. A photoelectric device, characterized in that: Include: a first high absorption structure penetrating into a semiconductor substrate; a second high absorption structure penetrating into the semiconductor substrate and adjacent to the first high absorption structure; and A platform region, including a carbon layer, wherein the platform region is directly and horizontally between the first high absorbency structure and the second high absorbency structure; The first high-absorbency structure and the second high-absorbency structure are symmetrical around a central axis of the platform area.

10. The photovoltaic device according to claim 9, wherein: The first high absorbency structure and the second high absorbency structure have an inverted truncated pyramid shape or an inverted truncated cone shape.

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