Light emitting diode chip

Abstract

The light emitting diode chip comprises a substrate, an epitaxial layer, a transparent conductive layer, a Cr metal layer, electrodes and a passivation layer which are stacked, the transparent conductive layer and the Cr metal layer are arranged on the epitaxial layer at intervals, a P electrode position is arranged on the transparent conductive layer, an N electrode position is arranged on the Cr metal layer, a P electrode is arranged on the P electrode position, and an N electrode is arranged on the N electrode position. Each of the P electrode and the N electrode comprises a high-reflection layer, a filling metal layer and an inert metal layer, an inverted trapezoidal accommodating cavity is defined by the high-reflection layers, an opening is formed in the inverted trapezoidal accommodating cavity, the filling metal layer is arranged in the inverted trapezoidal accommodating cavity, the inert metal layer is arranged on the filling metal layer, and passivation layers are arranged on the epitaxial layer, the transparent conductive layer and the Cr metal layer. The electrodes are arranged to be inverted trapezoidal, the contact area of the electrodes and the epitaxial layer is reduced, the light emitting area of the chip is increased under the condition that current loss is reduced as much as possible, and meanwhile the light emitting effect of the chip is improved through the high reflection layer.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a light emitting diode chip. Background Art

[0002] The electrodes of existing light-emitting diodes are usually manufactured by evaporation. The cross-section of the electrodes manufactured by this method is a trapezoid, that is, a narrow top and wide bottom structure. Under the same material, the electrode resistance is proportional to the electrode length and inversely proportional to the electrode cross-sectional area. Therefore, in order to reduce the electrode resistance of the chip, it is usually chosen to increase the width of the bottom of the electrode and the height of the electrode to increase the electrode cross-sectional area and reduce the electrode resistance. However, if the bottom is too wide, it will block the light, and the metal that is often used in ohmic contact with the chip has a low light reflectivity and will absorb a large amount of emitted light. Utility Model Content

[0003] In view of the above situation, it is necessary to provide a light emitting diode chip to solve the problem in the prior art that the bottom of the electrode is too wide and absorbs a large amount of emitted light.

[0004] A light-emitting diode chip comprises a stacked substrate and an epitaxial layer, a transparent conductive layer and a Cr metal layer are alternately arranged on the epitaxial layer, a P electrode position is arranged on the transparent conductive layer, an N electrode position is arranged on the Cr metal layer, a P electrode is arranged on the P electrode position, and an N electrode is arranged on the N electrode position, the P electrode and the N electrode both comprise a high-reflection layer, a filling metal layer and an inert metal layer, the high-reflection layer arranged at the P electrode position is connected to the transparent conductive layer, the high-reflection layer arranged at the N electrode position is connected to the Cr metal layer, the high-reflection layers enclose an inverted trapezoidal accommodating cavity, an opening is provided on the inverted trapezoidal accommodating cavity, the filling metal layer is arranged in the inverted trapezoidal accommodating cavity, the inert metal layer is arranged on the filling metal layer, and a passivation layer is arranged on the epitaxial layer, the transparent conductive layer and the Cr metal layer.

[0005] Beneficial effects of the utility model:

[0006] The P electrode and the N electrode are set to an inverted trapezoid, but the cross-sectional area of ​​the electrode is not reduced, that is, the contact area between the electrode and the epitaxial layer is reduced without changing the electrode height. Although a transparent conductive layer and a Cr metal layer are provided, the thickness of the transparent conductive layer and the Cr metal layer is usually very thin, so the impact on the current is extremely limited. While minimizing the current loss, the light emitting area of ​​the chip is increased. At the same time, the high reflective layer is used, especially the light emitted from the bottom of the electrode to the side of the electrode. The light emitted by the chip is reflected by the high reflective layer, thereby improving the light emitting effect of the chip.

[0007] Furthermore, the temporary protective layer is arranged on the epitaxial layer, the transparent conductive layer and the Cr metal layer. The temporary protective layer arranged on the transparent conductive layer forms a P electrode position, and the temporary protective layer arranged on the Cr metal layer forms an N electrode position. The P electrode position and the N electrode position are in an inverted trapezoid. The P electrode is arranged at the P electrode position, and the N electrode is arranged at the N electrode position.

[0008] In the utility model, the temporary protection layer is an intermediate process, and the P electrode position and the N electrode position are respectively formed through the temporary protection layer, and the P electrode is arranged at the P electrode position, and the N electrode is arranged at the N electrode position.

[0009] Furthermore, the epitaxial layer includes an N-type GaN layer, a quantum hydrazine layer and a P-type GaN layer arranged from bottom to top, the P-type GaN layer and the N-type GaN layer are distributed in steps, and the distance between the bottom of the P-type GaN layer and the bottom of the N-type GaN layer is 9500Å-13500Å, the transparent conductive layer is arranged on the P-type GaN layer, and the Cr metal layer is arranged on the N-type GaN layer.

[0010] Furthermore, an angle formed by the side surface of the inverted trapezoidal accommodating cavity and the bottom surface of the inverted trapezoidal accommodating cavity is between 102° and 114°.

[0011] Furthermore, the material of the high reflective layer is Al or Ag, the material of the filling metal layer is one of Ti, Ni or Pt, and the material of the inert metal layer is Au or Cu.

[0012] Furthermore, the thickness of the epitaxial layer is between 43500Å and 67500Å.

[0013] Furthermore, the thickness of the Cr metal layer is between 20Å and 80Å.

[0014] Furthermore, the thickness of the temporary protective layer is between 15000Å and 34000Å.

[0015] Furthermore, the material of the temporary protective layer is SiO 2 、Si 3 N 4 、Al 2 O 3 or MgO.

[0016] Furthermore, the material of the passivation layer is SiO 2 、Si 3 N 4 or Al 2 O 3 . BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 This is a schematic diagram of the structure after forming a temporary protective layer in the first embodiment of the utility model;

[0019] Figure 2 It is a structural schematic diagram of the first embodiment of the utility model;

[0020] Figure 3 It is a schematic structural diagram of the epitaxial layer of the first embodiment of the utility model;

[0021] Figure 4 It is a schematic structural diagram of the P electrode of the first embodiment of the utility model.

[0022] Explanation of the accompanying drawings: 1. substrate; 2. epitaxial layer; 21. N-type GaN layer; 22. quantum hydrazine layer; 23. P-type GaN layer; 3. transparent conductive layer; 4. Cr metal layer; 5. electrode layer; 51. P electrode; 511. high reflective layer; 512. filling metal layer; 513. inert metal layer; 52. N electrode; 6. passivation layer; 7. temporary protective layer.

[0023] The embodiments of the utility model will be further described below in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0024] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the embodiments of the present invention, and should not be construed as limiting the present invention.

[0025] In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present utility model, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0027] Embodiment 1

[0028] A light emitting diode chip, such as Figure 1 and Figure 2 As shown, it includes a stacked substrate 1 and an epitaxial layer 2, a transparent conductive layer 3 and a Cr metal layer 4 are spaced apart on the epitaxial layer 2, the electrode layer 5 includes a P electrode 51 and an N electrode 52, the P electrode 51 is arranged on the transparent conductive layer 3, the N electrode 52 is arranged on the Cr metal layer 4, and a passivation layer 6 is arranged on the epitaxial layer 2, the transparent conductive layer 3 and the Cr metal layer 4.

[0029] Specifically, Figures 1 to 4 As shown, the epitaxial layer 2 includes an N-type GaN layer 21, a quantum hydrazine layer 22 and a P-type GaN layer 23 arranged from bottom to top, the P-type GaN layer 23 and the N-type GaN layer 21 are distributed in steps, and the bottom of the P-type GaN layer 23 is 11800Å higher than the bottom of the N-type GaN layer 21, the quantum hydrazine layer 22 is a light-emitting layer, a transparent conductive layer 3 is arranged on the P-type GaN layer 23, a Cr metal layer 4 is arranged on the N-type GaN layer 21, and the transparent conductive layer 3 and the Cr metal layer 4 are arranged alternately.

[0030] Specifically, a temporary protective layer 7 is disposed on the epitaxial layer 2, the transparent conductive layer 3, and the Cr metal layer 4. The temporary protective layer 7 disposed on the transparent conductive layer 3 forms a P electrode position (not shown), and the temporary protective layer 7 disposed on the Cr metal layer 4 forms an N electrode position (not shown). The electrode layer 5 includes a P electrode 51 and an N electrode 52. The P electrode 51 is disposed at the P electrode position, and the N electrode 52 is disposed at the N electrode position. The P electrode 51 and the N electrode 52 both include a high reflective layer 511, a filling metal layer 512, and an inert metal layer 513. The high reflective layer 51 disposed at the P electrode position 1 is connected to the transparent conductive layer 3, a high reflective layer 511 arranged at the N electrode position is connected to the Cr metal layer 4, the high reflective layer 511 is enclosed to form an inverted trapezoidal accommodating cavity, a filling metal layer 512 is arranged in the inverted trapezoidal accommodating cavity (not shown), an opening (not shown) is provided on the inverted trapezoidal accommodating cavity, an inert metal layer 513 is arranged on the filling metal layer 512, and the inert metal layer is located on the opening, the N electrode 52 has the same structure as the P electrode 51, the P electrode 51 and the N electrode 52 are both inverted trapezoidal, and the angle formed by the side surface of the inverted trapezoidal accommodating cavity and the bottom surface of the inverted trapezoidal accommodating cavity is 102°.

[0031] Specifically, after the electrode layer 5 is provided, the temporary protective layer 7 is removed, and the passivation layer 6 is provided on the epitaxial layer 2, the transparent conductive layer 3 and the Cr metal layer 4 to form a protective layer.

[0032] Specifically, the thickness of the epitaxial layer 2 is 50000Å, the thickness of the Cr metal layer 4 is 60Å, the thickness of the temporary protective layer 7 is 26000Å, the material of the high reflective layer 511 in the P electrode 51 is Ag, the material of the filling metal layer 512 in the P electrode 51 is Ti, the material of the inert metal layer 513 in the P electrode 51 is Au, the material of the high reflective layer 511 in the N electrode 52 is Ag, the material of the filling metal layer 512 in the N electrode 52 is Ti, the material of the inert metal layer 513 in the N electrode 52 is Au, and the material of the passivation layer 6 is Si. 3 N 4 The temporary protective layer 7 is made of SiO 2 .

[0033] Specifically, a temporary protective layer 7 was prepared by using a negative resist dry etching process. The lower bottom of the P electrode 51 was 2.2µm, the upper bottom of the P electrode 51 was 2.6µm, the lower bottom of the N electrode 52 was 2.2µm, the upper bottom of the N electrode 52 was 2.6µm. An external current of 100mA and an external voltage of 2.967V were applied. The luminous brightness was 243lm as tested by an integrating sphere.

[0034] Embodiment 2

[0035] The difference from the first embodiment is that:

[0036] Specifically, the angle formed by the side surface of the inverted trapezoidal accommodating cavity and the bottom surface of the inverted trapezoidal accommodating cavity is 107°, the thickness of the epitaxial layer 2 is 43500Å, the thickness of the Cr metal layer 4 is 80Å, the material of the high reflective layer 511 in the P electrode 51 is Al, the material of the filling metal layer 512 in the P electrode 51 is Ni, the material of the inert metal layer 513 in the P electrode 51 is Au, the material of the high reflective layer 511 in the N electrode 52 is Ag, the material of the filling metal layer 512 in the N electrode 52 is Pt, the material of the inert metal layer 513 in the N electrode 52 is Cu, and the material of the passivation layer 6 is Al. 2 O 3 The temporary protective layer 7 is made of SiO 2 .

[0037] Specifically, a temporary protective layer 7 is prepared by a positive resist dry etching process, the lower bottom of the P electrode 51 is 2.4µm, the upper bottom of the P electrode 51 is 2.9µm, the lower bottom of the N electrode 52 is 2.4µm, the upper bottom of the N electrode 52 is 2.9µm, an external current of 100mA and an external voltage of 2.965V are applied, and the luminous brightness is 241lm as tested by an integrating sphere.

[0038] Embodiment 3

[0039] The difference from the first embodiment is that:

[0040] Specifically, the angle formed by the side surface of the inverted trapezoidal accommodating cavity and the bottom surface of the inverted trapezoidal accommodating cavity is 114°, the thickness of the epitaxial layer 2 is 67500Å, the thickness of the Cr metal layer 4 is 20Å, the material of the high reflective layer 511 in the P electrode 51 is Al, the material of the filling metal layer 512 in the P electrode 51 is Pt, the material of the inert metal layer 513 in the P electrode 51 is Au, the material of the high reflective layer 511 in the N electrode 52 is Ag, the material of the filling metal layer 512 in the N electrode 52 is Pt, the material of the inert metal layer 513 in the N electrode 52 is Cu, and the material of the passivation layer 6 is SiO 2 The temporary protective layer 7 is made of SiO 2 .

[0041] Specifically, a temporary protective layer 7 is prepared by a positive resist dry etching process, the lower bottom of the P electrode 51 is 2.3µm, the upper bottom of the P electrode 51 is 2.6µm, the lower bottom of the N electrode 52 is 2.3µm, the upper bottom of the N electrode 52 is 2.6µm, an external current of 100mA and an external voltage of 2.966V are applied, and the luminous brightness is 240lm as tested by an integrating sphere.

[0042] Specifically, using conventional preparation processes, the lower bottom of the P electrode 51 is 2.7µm, the upper bottom of the P electrode 51 is 2.3µm, the lower bottom of the N electrode 52 is 2.7µm, the upper bottom of the N electrode 52 is 2.3µm, the applied current is 100mA, the voltage is 2.965V, and the luminous brightness is 237lm as tested by integrating sphere.

[0043] It should be noted that the conventional process electrode is directly manufactured using a photolithography process, and the conventional process uses a negative photoresist as a mask. After the photolithography development process, the negative photoresist is wide at the top and narrow at the bottom, and the corresponding part without photoresist shielding is narrow at the top and wide at the bottom. The metal electrode is formed by evaporation. Due to the shielding effect of the mask, the cross-section of the metal electrode is a trapezoid with a narrow top and a wide bottom. The liftoff process is used to remove the mask and the metal layer above the mask to obtain the metal electrode; while the first, second and third embodiments all use the photolithography process, A transparent conductive layer 3 and a Cr metal layer 4 are deposited on the epitaxial layer 2, and then an inverted trapezoidal temporary protective layer 7 is made on the transparent conductive layer 3 and the Cr metal layer 4. An inverted trapezoidal accommodating cavity is formed on the transparent conductive layer 3 and the Cr metal layer 4 respectively through a high reflective layer 511, and then a filling metal layer 512 and an inert metal layer 513 are arranged to form a P electrode 51 and an N electrode 52 respectively. The temporary protective layer 7 is removed by a CMP process, and a passivation layer 6 is arranged on the epitaxial layer 2, the transparent conductive layer 3 and the Cr metal layer 4 to form a protective layer.

[0044] In summary, comparing the luminous brightness of the chips of the conventional process, embodiment 1, embodiment 2 and embodiment 3, there are improvements of 2.5%, 1.7% and 1.3% respectively, which is quite obvious for improving the luminous brightness of the chip.

[0045] In summary, the electrode layer 5 including the P electrode 51 and the N electrode 52 is set to an inverted trapezoid, but the cross-sectional area of ​​the electrode layer 5 is not reduced, that is, without changing the height of the electrode layer 5, the contact area between the electrode layer 5 and the epitaxial layer 2 is reduced. Although a transparent conductive layer 3 is provided between the P electrode 51 and the epitaxial layer 2, and a Cr metal layer 4 is provided between the N electrode 52 and the epitaxial layer 2, the thickness of the transparent conductive layer 3 and the Cr metal layer 4 is extremely thin, so the impact on the current is extremely limited. While minimizing the current loss, the light emitting area of ​​the chip is increased. At the same time, the high reflective layer 511 is utilized, especially the light emitted from the bottom of the electrode layer 5 to the side of the electrode layer 5. The light emitted by the chip is reflected by the high reflective layer 511, thereby improving the light emitting effect of the chip.

[0046] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0047] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the utility model patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A light emitting diode chip, characterized in that: The invention comprises a stacked substrate and an epitaxial layer, wherein a transparent conductive layer and a Cr metal layer are alternately arranged on the epitaxial layer, a P electrode position is arranged on the transparent conductive layer, an N electrode position is arranged on the Cr metal layer, a P electrode is arranged on the P electrode position, and an N electrode is arranged on the N electrode position, wherein the P electrode and the N electrode both comprise a high reflective layer, a filling metal layer and an inert metal layer, the high reflective layer arranged at the P electrode position is connected to the transparent conductive layer, the high reflective layer arranged at the N electrode position is connected to the Cr metal layer, the high reflective layers enclose an inverted trapezoidal accommodating cavity, an opening is provided on the inverted trapezoidal accommodating cavity, the filling metal layer is arranged in the inverted trapezoidal accommodating cavity, the inert metal layer is arranged on the filling metal layer, and a passivation layer is arranged on the epitaxial layer, the transparent conductive layer and the Cr metal layer.

2. The light emitting diode chip according to claim 1, characterized in that: The epitaxial layer includes an N-type GaN layer, a quantum hydrazine layer and a P-type GaN layer arranged from bottom to top, the P-type GaN layer and the N-type GaN layer are distributed in steps, and the distance between the bottom of the P-type GaN layer and the bottom of the N-type GaN layer is 9500Å-13500Å, the transparent conductive layer is arranged on the P-type GaN layer, and the Cr metal layer is arranged on the N-type GaN layer.

3. The light emitting diode chip according to claim 1, characterized in that: The angle formed by the side surface of the inverted trapezoidal accommodating cavity and the bottom surface of the inverted trapezoidal accommodating cavity is between 102° and 114°.

4. The light emitting diode chip according to claim 1, characterized in that: The material of the high reflective layer is Al or Ag, the material of the filling metal layer is one of Ti, Ni or Pt, and the material of the inert metal layer is Au or Cu.

5. The light emitting diode chip according to claim 2, characterized in that: The thickness of the epitaxial layer is between 43500Å and 67500Å.

6. The light emitting diode chip according to claim 1, characterized in that: The thickness of the Cr metal layer is between 20Å and 80Å.

7. The light emitting diode chip according to claim 1, characterized in that: The material of the passivation layer is SiO2, Si3N4 or Al2O3.

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