Low-noise high-resistance composite pre-amplification circuit

Abstract

The utility model relates to the field of low-noise amplification, in particular to a low-noise high-resistance composite pre-amplification circuit, which has the advantages of extremely high common input mode voltage resistance, ultralow input noise voltage resistance, ultralow input bias current resistance and innovative input offset voltage correction, and can enable composite amplification to be applied to small-range weak signal amplification. According to the technical scheme, the circuit comprises an input detuning offset adjustment module, a primary composite amplification module and a common mode elimination module, the input detuning offset adjustment module outputs bias voltage to the primary composite amplification module, the primary composite amplification module is mainly composed of a differential pair transistor, a resistor and an operational amplifier, the primary composite amplification module only amplifies differential mode signals, and the common mode elimination module is used for eliminating common mode signals. The primary composite amplification module outputs two paths of signals to the common-mode elimination module, and the common-mode elimination module carries out subtraction on voltages of the two paths of signals to eliminate a common mode of the two paths of signals. The low-noise high-resistance composite amplification circuit is suitable for low-noise high-resistance composite amplification of weak signals.

Description

Technical Field

[0001] The utility model relates to the field of low-noise amplification, in particular to a low-noise high-resistance composite preamplifier circuit. Background Art

[0002] An existing low-noise amplifier circuit, such as a low-noise amplifier circuit disclosed in CN114584079A, comprises a signal input terminal, a signal output terminal, a radio frequency amplifier circuit, a load circuit and a low-frequency filter circuit; the radio frequency amplifier circuit has one end connected to the signal input terminal and the other end connected to the signal output terminal, and is configured to receive a radio frequency input signal and to process the radio frequency input signal.

[0003] The signal is amplified to output the RF amplified signal; the load circuit has one end connected to the output end of the RF amplifier circuit and the other end connected to the power supply end; the low-frequency filter circuit has one end connected to the power supply end and the other end connected to the ground end, and is configured to filter the low-frequency signal outside the working frequency band of the low-noise amplifier circuit. This solution can filter the low-frequency signal outside the working frequency band of the low-noise amplifier circuit and release the low-frequency signal to the ground to ensure that the gain of the low-noise amplifier circuit can meet the requirements when it is stable.

[0004] However, in the field of ultra-precision stress strain measurement and temperature measurement, the noise and input bias current of this solution cannot meet the requirements. At the same time, this solution cannot correct the input offset voltage, nor can it eliminate the common-mode signal after low-noise amplification. Utility Model Content

[0005] The purpose of the utility model is to overcome the shortcomings of the prior art and provide a low-noise high-impedance composite preamplifier circuit, which has the characteristics of extremely high common input mode voltage resistance, ultra-low input noise voltage, ultra-low input bias current, and innovative input offset voltage correction, so that the composite amplifier can be applied to amplify weak signals of small range.

[0006] The utility model adopts the following technical scheme to achieve the above-mentioned purpose. The utility model provides a low-noise high-resistance composite preamplifier circuit, including an input offset adjustment module, a primary composite amplifier module and a common-mode elimination module. The input offset adjustment module outputs a bias voltage to the primary composite amplifier module. The primary composite amplifier module is mainly composed of a differential pair of tubes, a resistor and an operational amplifier. The primary composite amplifier module only amplifies the differential mode signal. The primary composite amplifier module outputs two signals to the common-mode elimination module. The common-mode elimination module makes a difference in the voltages of the two signals to eliminate their common mode.

[0007] Furthermore, the primary composite amplifier module specifically includes a differential pair tube U6, a first field effect tube Q1, a second field effect tube Q2, a third field effect tube Q3, a fourth field effect tube Q4, a third operational amplifier U3, a fourth operational amplifier U4, a first matching resistor network chip, a second matching resistor network chip and a third matching resistor network chip, the first matching resistor network chip includes a first matching resistor R12A, a second matching resistor R12B, a third matching resistor R12C, and a fourth matching resistor R12D, the second matching resistor network chip includes a fifth matching resistor R2A, a sixth matching resistor R2B, a seventh matching resistor R2C, and an eighth matching resistor R2D, the third matching resistor network chip includes a first matching resistor R12A, a second matching resistor R12B, a third matching resistor R12C, and a fourth matching resistor R1 ... The network chip includes a ninth matching resistor R3A, a tenth matching resistor R3B, an eleventh matching resistor R3C, and a twelfth matching resistor R3D. The fourth pin of the differential pair tube U6 is respectively connected to the drain of the first field effect tube Q1 and the source of the third field effect tube Q3. The gate of the first field effect tube Q1 is connected to the source of the first field effect tube Q1. The gate of the first field effect tube Q1 is also connected to the gate of the third field effect tube Q3. The drain of the third field effect tube Q3 is connected to the first input VIN+. The eighth pin of the differential pair tube U6 is respectively connected to the drain of the second field effect tube Q2 and the source of the fourth field effect tube Q4. The gate of the second field effect tube Q2 is connected to the source of the second field effect tube Q2. The gate of the second field effect tube Q2 is connected to the gate of the third field effect tube Q3. The electrode is also connected to the gate of the fourth field effect transistor Q4, the drain of the fourth field effect transistor Q4 is connected to the second input VIN-, the second pin of the differential pair tube U6 is connected between the first matching resistor R12A and the third matching resistor R12C, the sixth pin of the differential pair tube U6 is connected between the second matching resistor R12B and the fourth matching resistor R12D, the third matching resistor R12C is connected to the output end of the third operational amplifier U3, the fourth matching resistor R12D is connected to the output end of the fourth operational amplifier U4, the fifth pin of the differential pair tube U6 is connected to the non-inverting input end of the third operational amplifier U3, the inverting input end of the third operational amplifier U3 is connected between the fifth matching resistor R2A and the seventh matching resistor R2C, and the third The inverting input terminal of the operational amplifier U3 is also connected to the non-inverting input terminal of the third operational amplifier U3 through the seventh matching resistor R2C, the ninth matching resistor R3A and the tenth matching resistor R3B. The seventh pin of the differential pair tube U6 is connected to the non-inverting input terminal of the fourth operational amplifier U4. The inverting input terminal of the fourth operational amplifier U4 is connected between the eighth matching resistor R2D and the sixth matching resistor R2B. The inverting input terminal of the fourth operational amplifier U4 is also connected to the non-inverting input terminal of the fourth operational amplifier U4 through the eighth matching resistor R2D, the eleventh matching resistor R3C and the twelfth matching resistor R3D. The output terminals of the third operational amplifier U3 and the fourth operational amplifier U4 output the signal after primary composite amplification.

[0008] Furthermore, in order to prevent the primary pair tube gain from being too large, the open-loop phase margins of the third operational amplifier U3 and the fourth operational amplifier U4 are too small, causing the feedback loop to oscillate. The primary composite amplification module specifically includes a first capacitor C1, a second capacitor C2, a fifth resistor R5, and a sixth resistor R6. The in-phase input terminal of the third operational amplifier U3 is connected to the output terminal of the third operational amplifier U3 through the fifth resistor R5 and the second capacitor C2, and the in-phase input terminal of the fourth operational amplifier U4 is connected to the output terminal of the fourth operational amplifier U4 through the sixth resistor R6 and the first capacitor C1.

[0009] Furthermore, in order to prevent excessive current when the input signal changes rapidly, the primary composite amplifier module specifically includes a seventh resistor R7 and an eighth resistor R8. The fourth pin of the differential pair tube U6 is connected to the drain of the first field effect tube Q1 and the source of the third field effect tube Q3 through the seventh resistor R7, and the eighth pin of the differential pair tube U6 is connected to the drain of the second field effect tube Q2 and the source of the fourth field effect tube Q4 through the eighth resistor R8.

[0010] Furthermore, in order to improve circuit stability, the primary composite amplifier module specifically includes a tenth resistor R10 and an eleventh resistor R11, the fourth pin of the differential pair tube U6 is grounded through the seventh resistor R7 and the tenth resistor R10, and the eighth pin of the differential pair tube U6 is grounded through the eighth resistor R8 and the eleventh resistor R11.

[0011] Furthermore, the common-mode elimination module specifically includes a common-mode elimination chip U2, a fifth operational amplifier U5, a third capacitor C3, a fourth resistor R4 and a ninth resistor R9. The second pin of the common-mode elimination chip U2 is connected to the output end of the fourth operational amplifier U4, the third pin of the common-mode elimination chip U2 is connected to the output end of the third operational amplifier U3, the sixth pin of the common-mode elimination chip U2 is the output end, the first pin of the common-mode elimination chip U2 is connected to the output end of the fifth operational amplifier U5, the inverting input end of the fifth operational amplifier U5 is connected to the common-mode voltage end Vcom_ADC through the ninth resistor R9, the inverting input end of the fifth operational amplifier U5 is also grounded through the third capacitor C3, and the non-inverting input end of the fifth operational amplifier U5 is connected to the output end of the fifth operational amplifier U5 through the fourth resistor R4.

[0012] Furthermore, the input offset adjustment module specifically includes an offset adjustment chip U1 and a first resistor R1, the eighth pin of the offset adjustment chip U1 outputs a positive bias voltage Vbia+ to between the ninth matching resistor R3A and the tenth matching resistor R3B, the seventh pin of the offset adjustment chip U1 outputs a negative bias voltage Vbia- to between the eleventh matching resistor R3C and the twelfth matching resistor R3D, the first pin of the offset adjustment chip U1 is connected to the power supply voltage AVcc through the first resistor R1, and the fourth and fifth pins of the offset adjustment chip U1 are connected to the external controller.

[0013] Beneficial effects of the utility model:

[0014] The utility model adopts a composite amplifier circuit constructed by low-noise field effect tubes and operational amplifiers, which has the characteristics of extremely high common input mode voltage resistance, ultra-low input noise voltage, ultra-low input bias current, and innovative input offset voltage correction, which can make the composite amplifier applicable to weak signal amplification with a range of only 1mV. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a structural block diagram of a low-noise high-impedance composite preamplifier circuit provided by an embodiment of the utility model;

[0016] Figure 2 This is a schematic diagram of the circuit structure of a part of the primary composite amplifier module provided by the embodiment of the utility model;

[0017] Figure 3 It is another schematic diagram of the circuit structure of the primary composite amplifier module provided by the embodiment of the utility model;

[0018] Figure 4 It is a schematic diagram of the circuit structure of the common mode elimination module provided by the embodiment of the utility model;

[0019] Figure 5 It is a schematic diagram of the circuit structure of an input offset adjustment module provided in an embodiment of the utility model. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present utility model clearer, the technical solution in the embodiments of the present utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the present utility model.

[0021] The utility model provides a low-noise high-impedance composite preamplifier circuit, such as Figure 1As shown, it includes an input offset adjustment module, a primary composite amplification module and a common mode elimination module. The input offset adjustment module outputs a bias voltage to the primary composite amplification module. The primary composite amplification module is mainly composed of a differential pair tube, a resistor and an operational amplifier. The primary composite amplification module only amplifies the differential mode signal. The primary composite amplification module outputs two signals to the common mode elimination module. The common mode elimination module differentiates the voltages of the two signals to eliminate their common mode.

[0022] like Figure 2 , Figure 3As shown, the primary composite amplifier module specifically includes a differential pair tube U6, a first field effect tube Q1, a second field effect tube Q2, a third field effect tube Q3, a fourth field effect tube Q4, a third operational amplifier U3, a fourth operational amplifier U4, a first matching resistor network chip, a second matching resistor network chip and a third matching resistor network chip, wherein the first matching resistor network chip includes a first matching resistor R12A, a second matching resistor R12B, a third matching resistor R12C, and a fourth matching resistor R12D, the second matching resistor network chip includes a fifth matching resistor R2A, a sixth matching resistor R2B, a seventh matching resistor R2C, and an eighth matching resistor R2D, and the third matching resistor network chip includes The ninth matching resistor R3A, the tenth matching resistor R3B, the eleventh matching resistor R3C, and the twelfth matching resistor R3D are included. The fourth pin of the differential pair tube U6 is respectively connected to the drain of the first field effect tube Q1 and the source of the third field effect tube Q3. The gate of the first field effect tube Q1 is connected to the source of the first field effect tube Q1. The gate of the first field effect tube Q1 is also connected to the gate of the third field effect tube Q3. The drain of the third field effect tube Q3 is connected to the first input VIN+. The eighth pin of the differential pair tube U6 is respectively connected to the drain of the second field effect tube Q2 and the source of the fourth field effect tube Q4. The gate of the second field effect tube Q2 is connected to the source of the second field effect tube Q2. The gate of the second field effect tube Q2 is also connected to the The gate of the fourth field effect transistor Q4 is connected, the drain of the fourth field effect transistor Q4 is connected to the second input VIN-, the second pin of the differential pair tube U6 is connected between the first matching resistor R12A and the third matching resistor R12C, the sixth pin of the differential pair tube U6 is connected between the second matching resistor R12B and the fourth matching resistor R12D, the third matching resistor R12C is connected to the output end of the third operational amplifier U3, the fourth matching resistor R12D is connected to the output end of the fourth operational amplifier U4, the fifth pin of the differential pair tube U6 is connected to the non-inverting input end of the third operational amplifier U3, the inverting input end of the third operational amplifier U3 is connected between the fifth matching resistor R2A and the seventh matching resistor R2C, and the third operational amplifier U3 is connected between the fifth matching resistor R2A and the seventh matching resistor R2C. The inverting input terminal of the operational amplifier U3 is also connected to the non-inverting input terminal of the third operational amplifier U3 through the seventh matching resistor R2C, the ninth matching resistor R3A and the tenth matching resistor R3B. The seventh pin of the differential pair tube U6 is connected to the non-inverting input terminal of the fourth operational amplifier U4. The inverting input terminal of the fourth operational amplifier U4 is connected between the eighth matching resistor R2D and the sixth matching resistor R2B. The inverting input terminal of the fourth operational amplifier U4 is also connected to the non-inverting input terminal of the fourth operational amplifier U4 through the eighth matching resistor R2D, the eleventh matching resistor R3C and the twelfth matching resistor R3D. The output terminals of the third operational amplifier U3 and the fourth operational amplifier U4 output the signals after the primary composite amplification.

[0023] In one embodiment of the utility model, the primary composite amplifier module specifically also includes a first capacitor C1, a second capacitor C2, a fifth resistor R5 and a sixth resistor R6. The in-phase input terminal of the third operational amplifier U3 is connected to the output terminal of the third operational amplifier U3 through the fifth resistor R5 and the second capacitor C2. The in-phase input terminal of the fourth operational amplifier U4 is connected to the output terminal of the fourth operational amplifier U4 through the sixth resistor R6 and the first capacitor C1.

[0024] In one embodiment of the utility model, the primary composite amplifier module specifically also includes a seventh resistor R7 and an eighth resistor R8. The fourth pin of the differential pair tube U6 is respectively connected to the drain of the first field effect tube Q1 and the source of the third field effect tube Q3 through the seventh resistor R7, and the eighth pin of the differential pair tube U6 is respectively connected to the drain of the second field effect tube Q2 and the source of the fourth field effect tube Q4 through the eighth resistor R8.

[0025] In an embodiment of the present utility model, the primary composite amplifier module specifically further includes a tenth resistor R10 and an eleventh resistor R11, the fourth pin of the differential pair tube U6 is grounded through the seventh resistor R7 and the tenth resistor R10, and the eighth pin of the differential pair tube U6 is grounded through the eighth resistor R8 and the eleventh resistor R11.

[0026] like Figure 4 As shown, the common-mode elimination module specifically includes a common-mode elimination chip U2, a fifth operational amplifier U5, a third capacitor C3, a fourth resistor R4 and a ninth resistor R9. The second pin of the common-mode elimination chip U2 is connected to the output end of the fourth operational amplifier U4, the third pin of the common-mode elimination chip U2 is connected to the output end of the third operational amplifier U3, the sixth pin of the common-mode elimination chip U2 is the output end, the first pin of the common-mode elimination chip U2 is connected to the output end of the fifth operational amplifier U5, the inverting input end of the fifth operational amplifier U5 is connected to the common-mode voltage end Vcom_ADC through the ninth resistor R9, the inverting input end of the fifth operational amplifier U5 is also grounded through the third capacitor C3, and the non-inverting input end of the fifth operational amplifier U5 is connected to the output end of the fifth operational amplifier U5 through the fourth resistor R4.

[0027] like Figure 5 As shown, the input offset adjustment module specifically includes an offset adjustment chip U1 and a first resistor R1, the eighth pin of the offset adjustment chip U1 outputs a positive bias voltage Vbia+ to between a ninth matching resistor R3A and a tenth matching resistor R3B, the seventh pin of the offset adjustment chip U1 outputs a negative bias voltage Vbia- to between an eleventh matching resistor R3C and a twelfth matching resistor R3D, the first pin of the offset adjustment chip U1 is connected to the power supply voltage AVcc through the first resistor R1, and the fourth and fifth pins of the offset adjustment chip U1 are connected to the external controller.

[0028] The working principle of the utility model is described in detail below.

[0029] The differential pair of tubes U6 is a low-noise field effect pair of tubes N-JFET, whose characteristics meet the requirements of low input noise power supply and extremely high input impedance. However, the lower the noise of the pair of tubes, the greater the Vgs input matching voltage difference, which can reach more than 150mV. Therefore, when using this pair of tubes for pre-composite amplification of 1mV level signals, it is necessary to use a very clever idea to correct its input offset voltage in advance.

[0030] The differential pair tube U6 cooperates with the operational amplifier and resistors to form a primary composite amplifier circuit, Q1 and Q3 form input protection, Q2 and Q4 form the other arm input protection, R10 and R11 are high-resistance pull-down resistors, R7 and R8 prevent the charging and discharging current of Cgs from being too large when the input signal changes rapidly. This resistor cannot be too large, and its thermal noise should be controlled at 0.5nVsHz@1KHz.

[0031] The frequency compensation network R5, C2 and R6, C1 provide phase compensation for the in-phase amplification and the inverting amplification respectively to prevent the open-loop phase margin of U3 and U4 from being too small when the primary tube gain is too large, causing the feedback loop to oscillate.

[0032] The primary composite amplifier only amplifies the differential mode signal. Its differential mode amplifier G=R12A+R12B / R12C+R12D uses integrated resistors, whose model is LT5400. It can maintain excellent gain stability and sample and integrate 4 resistors to ensure the gain consistency of the two arms and improve the common mode rejection ratio.

[0033] In order to improve the bandwidth of the primary composite amplifier, the bootstrap measures are adopted for the differential pair tubes. Through the voltage reference point of the 4-pin input of the operational amplifier U3 and U4, the 3-pin of U3 and U4 is kept stable through the virtual short effect of the operational amplifier, so that the drain level D of the U6 pair tube is kept stable, thereby eliminating the Miller effect of Cgd when it is in amplification, thereby improving the gain-bandwidth product.

[0034] The reference level of the 4-pin input of U3 and U4 is divided by a resistor. The voltage divider resistor uses an integrated proportional resistor to minimize the level difference between the two drain levels of the tube U6, thereby maintaining extremely high common-mode suppression of the differential pair tube.

[0035] The Vgs error of the ultra-low noise differential pair tube U6 can reach 150mV, which is too large for the input differential mode signal of only 1mV, resulting in the inability to increase the amplification factor. If the Vgs error is corrected in advance and its Vgs error is controlled within 10uV, the 1mV signal can be amplified 10000 times (80dB) and sent to the ADC (Analog-to-Digital Converter) for acquisition and back-end digital analysis to achieve ultra-precision signal acquisition and processing. Since there is a quadratic function relationship between Vgs and Id current, Vgs can be adjusted by correcting Id, so the Id of the pair tube is corrected. A digital potentiometer is used, and the center tap is connected to the positive end of the power supply through a resistor, and the two ends of the potentiometer are connected to Vbia+ and Vbia- respectively. By adjusting the digital potentiometer, the current flowing through R3B and R3D is slightly adjusted, so that the Id current of the pair tube can be adjusted, thereby adjusting the excessive Vgs error. R3A, R3B, R3C, and R3D use proportional resistors to maintain an excellent dynamic proportional relationship, which is beneficial for suppressing common-mode signals.

[0036] The primary composite amplifier outputs Vo+ and Vo- contain common-mode signals, which can be realized through the common-mode elimination circuit of the subsequent stage. The common-mode elimination circuit is essentially a differential amplifier, which makes a difference in the voltage of Vo+ and Vo- to eliminate the common mode. The REF of the U2 differential amplifier comes from the U5 follower output. The output impedance Ro of U5 is extremely small, which can eliminate the impedance mismatch introduced by the REF pin, resulting in poor common-mode suppression. R9 and C3 filter the reference common-mode output of the analog-to-digital converter to improve the signal-to-noise ratio of VOUT.

[0037] The above is only a preferred embodiment of the utility model. It should be understood that the utility model is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the utility model, and should be within the scope of protection of the claims attached to the utility model.

Claims

1. A low-noise high-impedance composite preamplifier circuit, characterized in that: It includes an input offset adjustment module, a primary composite amplification module and a common mode elimination module. The input offset adjustment module outputs a bias voltage to the primary composite amplification module. The primary composite amplification module is composed of a differential pair of tubes, a resistor and an operational amplifier. The primary composite amplification module only amplifies differential mode signals. The primary composite amplification module outputs two signals to the common mode elimination module. The common mode elimination module makes a difference in the voltages of the two signals to eliminate their common mode.

2. The low-noise high-impedance composite preamplifier circuit according to claim 1, characterized in that: The primary composite amplifier module specifically includes a differential pair tube (U6), a first field effect tube (Q1), a second field effect tube (Q2), a third field effect tube (Q3), a fourth field effect tube (Q4), a third operational amplifier (U3), a fourth operational amplifier (U4), a first matching resistor network chip, a second matching resistor network chip and a third matching resistor network chip, wherein the first matching resistor network chip includes a first matching resistor (R12A), a second matching resistor (R12B), a third matching resistor (R12C) and a fourth matching resistor (R12D), and the second matching resistor network chip includes a fifth matching resistor (R2A), a sixth matching resistor (R2B), a seventh matching resistor (R2C), a first matching resistor (R12D) and a second matching resistor (R12D). Eight matching resistors (R2D), the third matching resistor network chip includes a ninth matching resistor (R3A), a tenth matching resistor (R3B), an eleventh matching resistor (R3C), and a twelfth matching resistor (R3D), the fourth pin of the differential pair tube (U6) is respectively connected to the drain of the first field effect tube (Q1) and the source of the third field effect tube (Q3), the gate of the first field effect tube (Q1) is connected to the source of the first field effect tube (Q1), the gate of the first field effect tube (Q1) is also connected to the gate of the third field effect tube (Q3), the drain of the third field effect tube (Q3) is connected to the first input (VIN+), the eighth pin of the differential pair tube (U6) is respectively connected to the drain of the second field effect tube (Q2) and the fourth field effect tube (Q3), The source of the differential pair tube (U6) is connected to the source of the second field effect tube (Q4), the gate of the second field effect tube (Q2) is connected to the source of the second field effect tube (Q2), the gate of the second field effect tube (Q2) is also connected to the gate of the fourth field effect tube (Q4), the drain of the fourth field effect tube (Q4) is connected to the second input (VIN-), the second pin of the differential pair tube (U6) is connected between the first matching resistor (R12A) and the third matching resistor (R12C), the sixth pin of the differential pair tube (U6) is connected between the second matching resistor (R12B) and the fourth matching resistor (R12D), the third matching resistor (R12C) is connected to the output end of the third operational amplifier (U3), and the fourth matching resistor (R12D) is connected to the fourth operational amplifier (U4). The output end of the differential pair tube (U6) is connected, the fifth pin of the differential pair tube (U6) is connected to the non-inverting input end of the third operational amplifier (U3), the inverting input end of the third operational amplifier (U3) is connected between the fifth matching resistor (R2A) and the seventh matching resistor (R2C), the inverting input end of the third operational amplifier (U3) is also connected to the non-inverting input end of the third operational amplifier (U3) through the seventh matching resistor (R2C), the ninth matching resistor (R3A) and the tenth matching resistor (R3B), the seventh pin of the differential pair tube (U6) is connected to the non-inverting input end of the fourth operational amplifier (U4), the inverting input end of the fourth operational amplifier (U4) is connected between the eighth matching resistor (R2D) and the sixth matching resistor (R2B),The inverting input terminal of the fourth operational amplifier (U4) is also connected to the non-inverting input terminal of the fourth operational amplifier (U4) through the eighth matching resistor (R2D), the eleventh matching resistor (R3C) and the twelfth matching resistor (R3D), and the output terminals of the third operational amplifier (U3) and the fourth operational amplifier (U4) output the primary composite amplified signal.

3. The low-noise high-impedance composite preamplifier circuit according to claim 2, characterized in that: The primary composite amplification module specifically further comprises a first capacitor (C1), a second capacitor (C2), a fifth resistor (R5) and a sixth resistor (R6); the in-phase input terminal of the third operational amplifier (U3) is connected to the output terminal of the third operational amplifier (U3) via the fifth resistor (R5) and the second capacitor (C2); the in-phase input terminal of the fourth operational amplifier (U4) is connected to the output terminal of the fourth operational amplifier (U4) via the sixth resistor (R6) and the first capacitor (C1).

4. The low-noise high-impedance composite preamplifier circuit according to claim 2, characterized in that: The primary composite amplifier module specifically further comprises a seventh resistor (R7) and an eighth resistor (R8); the fourth pin of the differential pair tube (U6) is respectively connected to the drain of the first field effect tube (Q1) and the source of the third field effect tube (Q3) through the seventh resistor (R7); the eighth pin of the differential pair tube (U6) is respectively connected to the drain of the second field effect tube (Q2) and the source of the fourth field effect tube (Q4) through the eighth resistor (R8).

5. The low-noise high-impedance composite preamplifier circuit according to claim 4, characterized in that: The primary composite amplifier module specifically further includes a tenth resistor (R10) and an eleventh resistor (R11); the fourth pin of the differential pair tube (U6) is grounded through the seventh resistor (R7) and the tenth resistor (R10); and the eighth pin of the differential pair tube (U6) is grounded through the eighth resistor (R8) and the eleventh resistor (R11).

6. The low-noise high-impedance composite preamplifier circuit according to claim 2, characterized in that: The common mode elimination module specifically comprises a common mode elimination chip (U2), a fifth operational amplifier (U5), a third capacitor (C3), a fourth resistor (R4) and a ninth resistor (R9); the second pin of the common mode elimination chip (U2) is connected to the output end of the fourth operational amplifier (U4); the third pin of the common mode elimination chip (U2) is connected to the output end of the third operational amplifier (U3); the sixth pin of the common mode elimination chip (U2) is the output end; the first pin of the common mode elimination chip (U2) is connected to the output end of the fifth operational amplifier (U5); the inverting input end of the fifth operational amplifier (U5) is connected to the common mode voltage end (Vcom_ADC) through the ninth resistor (R9); the inverting input end of the fifth operational amplifier (U5) is also grounded through the third capacitor (C3); and the non-inverting input end of the fifth operational amplifier (U5) is connected to the output end of the fifth operational amplifier (U5) through the fourth resistor (R4).

7. The low-noise high-impedance composite preamplifier circuit according to claim 2, characterized in that: The input offset adjustment module specifically comprises an offset adjustment chip (U1) and a first resistor (R1); the eighth pin of the offset adjustment chip (U1) outputs a positive bias voltage (Vbia+) to between a ninth matching resistor (R3A) and a tenth matching resistor (R3B); the seventh pin of the offset adjustment chip (U1) outputs a negative bias voltage (Vbia-) to between an eleventh matching resistor (R3C) and a twelfth matching resistor (R3D); the first pin of the offset adjustment chip (U1) is connected to a power supply voltage (AVcc) through the first resistor (R1); and the fourth pin and the fifth pin of the offset adjustment chip (U1) are connected to an external controller.

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